Cat. No.

W451-E1-03

SYSMAC CP Series CP1H-X40D@-@, CP1H-XA40D@-@, CP1H-Y20DT-D CP1L-L14D@-@, CP1L-L20D@-@, CP1L-M30D@-@, CP1L-M40D@-@

CP1H/CP1L CPU Unit

PROGRAMMING MANUAL

SYSMAC CP Series
CP1H-X40D@-@, CP1H-XA40D@-@, CP1H-Y20DT-D

CP1H CPU Units

CP1L-L14D@-@, CP1L-L20D@-@, CP1L-M30D@-@, CP1L-M40D@-@

CP1L CPU Units

Programming Manual
Revised April 2007

iv

Notice:
OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury to people or damage to property.

!DANGER
!WARNING

Indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury. Additionally, there may be severe property damage. Indicates a potentially hazardous situation which, if not avoided, could result in death or serious injury. Additionally, there may be severe property damage. Indicates a potentially hazardous situation which, if not avoided, may result in minor or moderate injury, or property damage.

!Caution

OMRON Product References

All OMRON products are capitalized in this manual. The word Unit is also capitalized when it refers to an OMRON product, regardless of whether or not it appears in the proper name of the product. The abbreviation Ch, which appears in some displays and on some OMRON products, often means word and is abbreviated Wd in documentation in this sense. The abbreviation PLC means Programmable Controller. PC is used, however, in some CX-Programmer displays to mean Programmable Controller.

Visual Aids
The following headings appear in the left column of the manual to help you locate different types of information. Note Indicates information of particular interest for efficient and convenient operation of the product. 1,2,3... 1. Indicates lists of one sort or another, such as procedures, checklists, etc.

OMRON, 2005
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or by any means, mechanical, electronic, photocopying, recording, or otherwise, without the prior written permission of OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice. Every precaution has been taken in the preparation of this manual. Nevertheless, OMRON assumes no responsibility for errors or omissions. Neither is any liability assumed for damages resulting from the use of the information contained in this publication.

Unit Versions of CP-series CPU Units

Unit Versions
Notation of Unit Versions on Products A unit version has been introduced to manage CPU Units in the CP Series according to differences in functionality accompanying Unit upgrades. The unit version is given to the right of the lot number on the nameplate of the products for which unit versions are being managed, as shown below.
CP-series CPU Unit Product nameplate CP1H-XA40DR-A CPU UNIT

Lot No. 28705 0000 Ver.1.0 OMRON Corporation MADE IN JAPAN

Lot No.

Unit version (Example for Unit version 1.0)

Confirming Unit Versions with Support Software

The methods used to confirm the unit version for the CP-series CP1H and CP1L CPU Units are somewhat different. CP1H CPU Units CX-Programmer version 6.1 or higher can be used to confirm the unit version using one of the following two methods. (See note.) Using the PLC Information Using the Unit Manufacturing Information

Note CX-Programmer versions lower than version 6.1 cannot be used to confirm unit versions for CP1L CPU Units. CP1L CPU Units CX-Programmer version 7.1 or higher can be used to confirm the unit version using the PLC Information. (See note.) The Unit Manufacturing Information cannot be used. Note CX-Programmer versions lower than version 7.1 cannot be used to confirm unit versions for CP1L CPU Units.

vi

 PLC Information Procedure When the Device Type and CPU Type Are Known 1,2,3... 1. If you know the device type and CPU type, select them in the Change PLC Dialog Box, go online, and select PLC - Edit - Information from the menus. The following Change PLC Dialog Box will be displayed. Example for CP1H

Example for CP1L

vii

2. Click the Settings Button and, when the Device Type Settings Dialog Box is displayed, select the CPU type. Example for CP1H

Example for CP1L

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3. Go online and select PLC - Edit - Information

The PLC Information Dialog Box will be displayed. Example for the CP1H

Unit version

ix

Example for the CP1L

Use the above display to confirm the unit version of the CPU Unit. Procedure When the Device Type and CPU Type Are Not Known This procedure is possible only when connected directly to the CPU Unit with a serial connection. If you don't know the device type and CPU type but are connected directly to the CPU Unit on a serial line, select PLC - Auto Online to go online, and then select PLC - Edit - Information from the menus. The PLC Information Dialog Box will be displayed and can be used to confirm the unit version of the CPU Unit.

Unit version

 Unit Manufacturing Information (CP1H CPU Units Only) 1,2,3... 1. In the IO Table Window, right-click and select Unit Manufacturing information - CPU Unit.

Unit version

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2. The following Unit Manufacturing information Dialog Box will be displayed.

Unit version

Use the above display to confirm the unit version of the CPU Unit connected online. Using the Unit Version Labels The following unit version labels are provided with the CPU Unit.

Ver. Ver.

1.0 1.0

Ver.

Ver.

These Labels can be used to manage differences in the available functions among the Units. Place the appropriate label on the front of the Unit to show what Unit version is actually being used.

These labels can be attached to the front of previous CPU Units to differentiate between CPU Units of different unit versions.

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TABLE OF CONTENTS
PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
1 2 3 4 5 6 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiv xxiv xxiv xxvi xxvii xxx

SECTION 1 Programming Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1 1-2 1-3 1-4 Programming Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introducing Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1
2 33 41 46

SECTION 2 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 2-2 2-3 2-4 Programming with Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CX-Programmer Operations for Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49
50 58 68 75

SECTION 3 Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 Notation and Layout of Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Input Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sequence Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer and Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increment/Decrement Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

77
86 89 113 132 168 209 247 274 320 336 389 436 451 472 525 567 615

3-10 Symbol Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Floating-point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Double-precision Floating-point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Table Data Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Data Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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TABLE OF CONTENTS
3-18 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 Interrupt Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 High-speed Counter/Pulse Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Basic I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Serial Communications Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Network Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Display Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Clock Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 Debugging Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 Failure Diagnosis Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 Block Programming Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 Text String Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 Task Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 Model Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 692 705 751 769 805 844 911 918 932 936 961 975 1008 1040 1047

SECTION 4 Instruction Execution Times and Number of Steps. . . . . . . 1065

4-1 4-2 Instruction Execution Times and Number of Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block Instance Execution Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 1088

Appendices
A B C Instruction Classifications by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List of Instructions by Function Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alphabetical List of Instructions by Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091 1099 1115

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1139

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About this Manual:

This manual describes programming the CP-series Programmable Controllers (PLCs) and includes the sections described below. The CP1H and CP1L are advanced package-type PLCs based on OMRONs advanced control technologies and vast experience in automated control. Please read this manual carefully and be sure you understand the information provided before attempting to install or operate a CP1H or CP1L PLC. Be sure to read the precautions provided in the following section. Definition of the CP Series The CP Series is centered around the CP1H and CP1L CPU Units and is designed with the same basic architecture as the CS and CJ Series. The Special I/O Units and CPU Bus Units of the CJ Series can thus be used with the CP1H CPU Units. CJ-series Basic I/O Units, however, cannot be used. Always use CPM1A Expansion Units or CPM1A Expansion I/O Units when expanding the I/O capacity of CP1H or CP1L PLCs. I/O words are allocated in the same way as the CPM1A/CPM2A PLCs, i.e., using fixed areas for inputs and outputs.
CS/CJ/CP Series

CS Series CS1-H CPU Units CS1H-CPU@@H CS1G-CPU@@H

CJ Series CJ1-H CPU Units CJ1H-CPU@@H CJ1G-CPU@@H CJ1G -CPU@@P (Loop CPU Unit)

CP Series CP1H CPU Units CP1H-X@@@@-@ CP1H-XA@@@@-@ CP1H-Y@@@@-@

CS1 CPU Units CS1H-CPU@@ (-V1) CS1G-CPU@@ (-V1)

CJ1M CPU Unit CJ1M-CPU@@

CP1L CPU Unit CP1L-L14D@-@ CP1L-L20D@-@ CP1L-M30D@-@ CP1L-M40D@-@

CS1D CPU Units

CS1D CPU Units for Duplex-CPU System CS1D-CPU@@ H CS1D CPU Units for Single-CPU System CS1D-CPU @@ S CS1D Process CPU Units

CJ1 CPU Unit CJ1G-CPU@@

CP-series Exapnsion I/O Units

CS1D-CPU@@ P

CP-series Exapnsion Units CS-series Basic I/O Units CS-series Special I/O Units CS-series CPU Bus Units CS-series Power Supply Units
Note: Products specifically for the CS1D Series are required to use CS1D CPU Units.

CJ-series Basic I/O Units CJ-series Special I/O Units CJ-series CPU Bus Units CJ-series Power Supply Units

CPM1A Expansion I/O Units CPM1A Expansion Units CJ-series Special I/O Units (See note.) CJ-series CPU Bus Units (See note.)
Note: Can be used with only a CP1H

CPU Unit.

xv

Precautions provides general precautions for using the Programmable Controller and related devices. Section 1 describes the basic concepts required to program the CP1H. Section 2 describes the operation of tasks and how to use tasks in programming. Section 3 describes each of the instructions that can be used in programming CP-series PLCs. Instructions are described in order of function. Section 4 lists the execution times and number of steps for all instructions supported by the CP1H PLCs, and describes the execution times for function block instances. The Appendices provide lists of the programming instructions in order of function and in order of function number.

xvi

Related Manuals
The following manuals are used for the CP-series CPU Units. Refer to these manuals as required.
Cat. No. Model numbers W451 CP1H-X40D@-@ CP1H-XA40D@-@ CP1H-Y20DT-D CP1L-L14D@-@ CP1L-L20D@-@ CP1L-M30D@-@ CP1L-M40D@-@ Description Provides the following information on the CP Series: Programming instructions Programming methods Tasks File memory Functions Use this manual together with the CP Series CP1H CPU Units Operation Manual (W450) and CP Series CP1L CPU Units Operation Manual (W462) SYSMAC CP Series Provide the following information on the CP Series: CP1H CPU Unit Overview, design, installation, maintenance, and Operation Manual other basic specifications SYSMAC CP Series Features CP1L CPU Unit Oper- System configuration ation Manual Mounting and wiring I/O memory allocation Troubleshooting Use this manual together with the CP1H Programmable Controllers Programming Manual (W451). SYSMAC CP Series Provides basic setup information for CP1L PLCs, CP1L Introduction including the following. Manual Basic configuration and part names Mounting and wiring procedures Programming, program transfer, and debugging with the CX-Programmer Application programming examples using the CP1L SYSMAC CS/CJDescribes commands addressed to CS-series, and series CommunicaCJ-series CPU Units, including C-mode commands tions Commands Ref- and FINS commands. erence Manual Note This manual describes on commands address to CPU Units regardless of the communications path. (CPU Unit serial ports, Serial Communications Unit/Board ports, and Communications Unit ports can be used.) Refer to the relevant operation manuals for information on commands addresses to Special I/O Units and CPU Bus Units. Provides information on installing and operating the CX-Programmer for all functions except for function blocks. Provides specifications and operating procedures for function blocks. Function blocks can be used with CX-Programmer Ver. 6.1 or higher and either a CS1-H/CJ1-H CPU Unit with a unit version of 3.0 or a CP1H CPU Unit. Refer to W446 for operating procedures for functions other than function blocks. Provides an overview of the CX-One FA Integrated Tool and installation procedures. Manual name SYSMAC CP Series CP1H and CP1L CPU Unit Programming Manual (This manual)

W450

W462

CP1H-X40D@-@ CP1H-XA40D@-@ CP1H-Y20DT-D CP1L-L14D@-@ CP1L-L20D@-@ CP1L-M30D@-@ CP1L-M40D@-@

W461

CP1L-L14D@-@ CP1L-L20D@-@ CP1L-M30D@-@ CP1L-M40D@-@

W342

CS1G/H-CPU@@H CS1G/H-CPU@@-V1 CS1D-CPU@@H CS1D-CPU@@S CS1W-SCU21 CS1W-SCB21-V1/41-V1 CJ1G/H-CPU@@H CJ1G-CPU@@P CP1H-CPU@@ CJ1G-CPU@@ CJ1W-SCU21-V1/41-V1 WS02-CXPC1-E-V70

W446

W447

WS02-CXPC1-E-V70

SYSMAC CX-Programmer Ver. 7.0 Operation Manual SYSMAC CX-Programmer Ver. 7.0 Operation Manual Function Blocks

W444

CXONE-AL@@C-E

CX-One FA Integrated Tool Package Setup Manual

xvii

Cat. No. W445

Model numbers CXONE-AL@@C-E

Manual name CX-Integrator Operation Manual

Description Describes CX-Integrator operating procedures and provides information on network configuration (data links, routing tables, Communications Units setup, etc. Provides operating procedures for creating protocol macros (i.e., communications sequences) with the CX-Protocol and other information on protocol macros. The CX-Protocol is required to create protocol macros for user-specific serial communications or to customize the standard system protocols.

W344

WS02-PSTC1-E

CX-Protocol Operation Manual

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Read and Understand this Manual

Please read and understand this manual before using the product. Please consult your OMRON representative if you have any questions or comments.

Warranty and Limitations of Liability

WARRANTY
OMRON's exclusive warranty is that the products are free from defects in materials and workmanship for a period of one year (or other period if specified) from date of sale by OMRON. OMRON MAKES NO WARRANTY OR REPRESENTATION, EXPRESS OR IMPLIED, REGARDING NONINFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR PARTICULAR PURPOSE OF THE PRODUCTS. ANY BUYER OR USER ACKNOWLEDGES THAT THE BUYER OR USER ALONE HAS DETERMINED THAT THE PRODUCTS WILL SUITABLY MEET THE REQUIREMENTS OF THEIR INTENDED USE. OMRON DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED.

LIMITATIONS OF LIABILITY
OMRON SHALL NOT BE RESPONSIBLE FOR SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES, LOSS OF PROFITS OR COMMERCIAL LOSS IN ANY WAY CONNECTED WITH THE PRODUCTS, WHETHER SUCH CLAIM IS BASED ON CONTRACT, WARRANTY, NEGLIGENCE, OR STRICT LIABILITY. In no event shall the responsibility of OMRON for any act exceed the individual price of the product on which liability is asserted. IN NO EVENT SHALL OMRON BE RESPONSIBLE FOR WARRANTY, REPAIR, OR OTHER CLAIMS REGARDING THE PRODUCTS UNLESS OMRON'S ANALYSIS CONFIRMS THAT THE PRODUCTS WERE PROPERLY HANDLED, STORED, INSTALLED, AND MAINTAINED AND NOT SUBJECT TO CONTAMINATION, ABUSE, MISUSE, OR INAPPROPRIATE MODIFICATION OR REPAIR.

xix

Application Considerations
SUITABILITY FOR USE
OMRON shall not be responsible for conformity with any standards, codes, or regulations that apply to the combination of products in the customer's application or use of the products. At the customer's request, OMRON will provide applicable third party certification documents identifying ratings and limitations of use that apply to the products. This information by itself is not sufficient for a complete determination of the suitability of the products in combination with the end product, machine, system, or other application or use. The following are some examples of applications for which particular attention must be given. This is not intended to be an exhaustive list of all possible uses of the products, nor is it intended to imply that the uses listed may be suitable for the products: Outdoor use, uses involving potential chemical contamination or electrical interference, or conditions or uses not described in this manual. Nuclear energy control systems, combustion systems, railroad systems, aviation systems, medical equipment, amusement machines, vehicles, safety equipment, and installations subject to separate industry or government regulations. Systems, machines, and equipment that could present a risk to life or property. Please know and observe all prohibitions of use applicable to the products. NEVER USE THE PRODUCTS FOR AN APPLICATION INVOLVING SERIOUS RISK TO LIFE OR PROPERTY WITHOUT ENSURING THAT THE SYSTEM AS A WHOLE HAS BEEN DESIGNED TO ADDRESS THE RISKS, AND THAT THE OMRON PRODUCTS ARE PROPERLY RATED AND INSTALLED FOR THE INTENDED USE WITHIN THE OVERALL EQUIPMENT OR SYSTEM.

PROGRAMMABLE PRODUCTS
OMRON shall not be responsible for the user's programming of a programmable product, or any consequence thereof.

xx

Disclaimers
CHANGE IN SPECIFICATIONS
Product specifications and accessories may be changed at any time based on improvements and other reasons. It is our practice to change model numbers when published ratings or features are changed, or when significant construction changes are made. However, some specifications of the products may be changed without any notice. When in doubt, special model numbers may be assigned to fix or establish key specifications for your application on your request. Please consult with your OMRON representative at any time to confirm actual specifications of purchased products.

DIMENSIONS AND WEIGHTS

Dimensions and weights are nominal and are not to be used for manufacturing purposes, even when tolerances are shown.

PERFORMANCE DATA
Performance data given in this manual is provided as a guide for the user in determining suitability and does not constitute a warranty. It may represent the result of OMRON's test conditions, and the users must correlate it to actual application requirements. Actual performance is subject to the OMRON Warranty and Limitations of Liability.

ERRORS AND OMISSIONS

The information in this manual has been carefully checked and is believed to be accurate; however, no responsibility is assumed for clerical, typographical, or proofreading errors, or omissions.

xxi

xxii

PRECAUTIONS
This section provides general precautions for using the CP-series Programmable Controllers (PLCs) and related devices. The information contained in this section is important for the safe and reliable application of Programmable Controllers. You must read this section and understand the information contained before attempting to set up or operate a PLC system. 1 2 3 4 5 6 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Environment Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Applicable Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Conformance to EC Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Relay Output Noise Reduction Methods . . . . . . . . . . . . . . . . . . . . . 6-5 Conditions for Meeting EMC Directives when Using CP1, CP-series, or CPM1A Relay Expansion I/O Units . . . . . . . . . . . . . . xxiv xxiv xxiv xxvi xxvii xxx xxx xxx xxx xxxi xxxii

xxiii

Intended Audience

Intended Audience
This manual is intended for the following personnel, who must also have knowledge of electrical systems (an electrical engineer or the equivalent). Personnel in charge of installing FA systems. Personnel in charge of designing FA systems. Personnel in charge of managing FA systems and facilities.

General Precautions
The user must operate the product according to the performance specifications described in the operation manuals. Before using the product under conditions which are not described in the manual or applying the product to nuclear control systems, railroad systems, aviation systems, vehicles, combustion systems, medical equipment, amusement machines, safety equipment, and other systems, machines, and equipment that may have a serious influence on lives and property if used improperly, consult your OMRON representative. Make sure that the ratings and performance characteristics of the product are sufficient for the systems, machines, and equipment, and be sure to provide the systems, machines, and equipment with double safety mechanisms. This manual provides information for programming and operating the Unit. Be sure to read this manual before attempting to use the Unit and keep this manual close at hand for reference during operation.

!WARNING It is extremely important that a PLC and all PLC Units be used for the specified purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PLC System to the above-mentioned applications.

Safety Precautions
!WARNING Do not attempt to take any Unit apart while the power is being supplied. Doing
so may result in electric shock.

!WARNING Do not touch any of the terminals or terminal blocks while the power is being
supplied. Doing so may result in electric shock.

!WARNING Do not attempt to disassemble, repair, or modify any Units. Any attempt to do
so may result in malfunction, fire, or electric shock.

!WARNING Provide safety measures in external circuits (i.e., not in the Programmable
Controller), including the following items, to ensure safety in the system if an abnormality occurs due to malfunction of the PLC or another external factor affecting the PLC operation. Not doing so may result in serious accidents. Emergency stop circuits, interlock circuits, limit circuits, and similar safety measures must be provided in external control circuits.

xxiv

Safety Precautions

3
The PLC will turn OFF all outputs when its self-diagnosis function detects any error or when a severe failure alarm (FALS) instruction is executed. As a countermeasure for such errors, external safety measures must be provided to ensure safety in the system. The PLC or outputs may remain ON or OFF due to deposits on or burning of the output relays, or destruction of the output transistors. As a countermeasure for such problems, external safety measures must be provided to ensure safety in the system. When the 24-V DC output (service power supply to the PLC) is overloaded or short-circuited, the voltage may drop and result in the outputs being turned OFF. As a countermeasure for such problems, external safety measures must be provided to ensure safety in the system.

!WARNING Fail-safe measures must be taken by the customer to ensure safety in the
event of incorrect, missing, or abnormal signals caused by broken signal lines, momentary power interruptions, or other causes. Not doing so may result in serious accidents. !Caution Execute online edit only after confirming that no adverse effects will be caused by extending the cycle time. Otherwise, the input signals may not be readable. !Caution Confirm safety at the destination node before transferring a program to another node or editing the I/O area. Doing either of these without confirming safety may result in injury. !Caution Tighten the screws on the terminal block of the AC Power Supply Unit to the torque specified in this manual. The loose screws may result in burning or malfunction. !Caution Do not touch anywhere near the power supply parts or I/O terminals while the power is ON, and immediately after turning OFF the power. The hot surface may cause burn injury. !Caution Pay careful attention to the polarities (+/-) when wiring the DC power supply. A wrong connection may cause malfunction of the system. !Caution When connecting the PLC to a computer or other peripheral device, either ground the 0 V side of the external power supply or do not ground the external power supply at all. Otherwise the external power supply may be shorted depending on the connection methods of the peripheral device. DO NOT ground the 24 V side of the external power supply, as shown in the following diagram.
Non-insulated DC power supply Twisted-pair cable 0V 0V FG FG CPU Unit FG Peripheral device FG

24 V

0V

xxv

Operating Environment Precautions

!Caution After programming (or reprogramming) using the IOWR instruction, confirm that correct operation is possible with the new ladder program and data before starting actual operation. Any irregularities may cause the product to stop operating, resulting in unexpected operation in machinery or equipment. !Caution The CP-series CPU Units automatically back up the user program and parameter data to flash memory when these are written to the CPU Unit. I/O memory (including the DM Area, Counter present values and Completion Flags, and HR Area), however, is not written to flash memory. The DM Area, Counter present values and Completion Flags, and HR Area can be held during power interruptions with a battery. If there is a battery error, the contents of these areas may not be accurate after a power interruption. If the contents of the DM Area, Counter present values and Completion Flags, and HR Area are used to control external outputs, prevent inappropriate outputs from being made whenever the Battery Error Flag (A402.04) is ON.

Operating Environment Precautions

!Caution Do not operate the control system in the following locations: Locations subject to direct sunlight. Locations subject to temperatures or humidity outside the range specified in the specifications. Locations subject to condensation as the result of severe changes in temperature. Locations subject to corrosive or flammable gases. Locations subject to dust (especially iron dust) or salts. Locations subject to exposure to water, oil, or chemicals. Locations subject to shock or vibration. !Caution Take appropriate and sufficient countermeasures when installing systems in the following locations: Locations subject to static electricity or other forms of noise. Locations subject to strong electromagnetic fields. Locations subject to possible exposure to radioactivity. Locations close to power supplies. !Caution The operating environment of the PLC System can have a large effect on the longevity and reliability of the system. Improper operating environments can lead to malfunction, failure, and other unforeseeable problems with the PLC System. Make sure that the operating environment is within the specified conditions at installation and remains within the specified conditions during the life of the system.

xxvi

Application Precautions

Application Precautions
Observe the following precautions when using the PLC System.

!WARNING Always heed these precautions. Failure to abide by the following precautions
could lead to serious or possibly fatal injury. Always connect to 100 or less when installing the Units. Not connecting to a ground of 100 or less may result in electric shock. Always turn OFF the power supply to the PLC before attempting any of the following. Not turning OFF the power supply may result in malfunction or electric shock. Mounting or dismounting Expansion Units or any other Units Connecting or removing the Memory Cassette or Option Board Setting DIP switches or rotary switches Connecting or wiring the cables Connecting or disconnecting the connectors !Caution Failure to abide by the following precautions could lead to faulty operation of the PLC or the system, or could damage the PLC or PLC Units. Always heed these precautions. Install external breakers and take other safety measures against short-circuiting in external wiring. Insufficient safety measures against short-circuiting may result in burning. Mount the Unit only after checking the connectors and terminal blocks completely. Be sure that all the terminal screws and cable connector screws are tightened to the torque specified in the relevant manuals. Incorrect tightening torque may result in malfunction. Wire all connections correctly according to instructions in this manual. Always use the power supply voltage specified in the operation manuals. An incorrect voltage may result in malfunction or burning. Take appropriate measures to ensure that the specified power with the rated voltage and frequency is supplied. Be particularly careful in places where the power supply is unstable. An incorrect power supply may result in malfunction. Leave the label attached to the Unit when wiring. Removing the label may result in malfunction. Remove the label after the completion of wiring to ensure proper heat dissipation. Leaving the label attached may result in malfunction. Use crimp terminals for wiring. Do not connect bare stranded wires directly to terminals. Connection of bare stranded wires may result in burning. Do not apply voltages to the input terminals in excess of the rated input voltage. Excess voltages may result in burning. Do not apply voltages or connect loads to the output terminals in excess of the maximum switching capacity. Excess voltage or loads may result in burning.

xxvii

Application Precautions

5
Be sure that the terminal blocks, connectors, Option Boards, and other items with locking devices are properly locked into place. Improper locking may result in malfunction. Disconnect the functional ground terminal when performing withstand voltage tests. Not disconnecting the functional ground terminal may result in burning. Wire correctly and double-check all the wiring or the setting switches before turning ON the power supply. Incorrect wiring may result in burning. Check that the DIP switches and data memory (DM) are properly set before starting operation. Check the user program for proper execution before actually running it on the Unit. Not checking the program may result in an unexpected operation. Resume operation only after transferring to the new CPU Unit and/or Special I/O Units the contents of the DM, HR, and CNT Areas required for resuming operation. Not doing so may result in an unexpected operation. Confirm that no adverse effect will occur in the system before attempting any of the following. Not doing so may result in an unexpected operation. Changing the operating mode of the PLC (including the setting of the startup operating mode). Force-setting/force-resetting any bit in memory. Changing the present value of any word or any set value in memory. Do not pull on the cables or bend the cables beyond their natural limit. Doing either of these may break the cables. Do not place objects on top of the cables. Doing so may break the cables. When replacing parts, be sure to confirm that the rating of a new part is correct. Not doing so may result in malfunction or burning. Before touching the Unit, be sure to first touch a grounded metallic object in order to discharge any static buildup. Not doing so may result in malfunction or damage. Do not touch the Expansion I/O Unit Connecting Cable while the power is being supplied in order to prevent malfunction due to static electricity. Do not turn OFF the power supply to the Unit while data is being transferred. When transporting or storing the product, cover the PCBs with electrically conductive materials to prevent LSIs and ICs from being damaged by static electricity, and also keep the product within the specified storage temperature range. Do not touch the mounted parts or the rear surface of PCBs because PCBs have sharp edges such as electrical leads. Double-check the pin numbers when assembling and wiring the connectors. Wire correctly according to specified procedures. Do not connect pin 6 (+5V) on the RS-232C Option Board on the CPU Unit to any external device other than the NT-AL001 or CJ1W-CIF11 Conversion Adapter. The external device and the CPU Unit may be damaged. Use the dedicated connecting cables specified in this manual to connect the Units. Using commercially available RS-232C computer cables may cause failures in external devices or the CPU Unit.

xxviii

Application Precautions

5
Check that data link tables and parameters are properly set before starting operation. Not doing so may result in unexpected operation. Even if the tables and parameters are properly set, confirm that no adverse effects will occur in the system before running or stopping data links. Transfer a routing table to the CPU Unit only after confirming that no adverse effects will be caused by restarting CPU Bus Units, which is automatically done to make the new tables effective. The user program and parameter area data in the CP-series CPU Unit is backed up in the built-in flash memory. The BKUP indicator will light on the front of the CPU Unit when the backup operation is in progress. Do not turn OFF the power supply to the CPU Unit when the BKUP indicator is lit. The data will not be backed up if power is turned OFF. Do not turn OFF the power supply to the PLC while the Memory Cassette is being written. Doing so may corrupt the data in the Memory Cassette. The BKUP indicator will light and the 7-segment display will light to indicate writing progress while data is being written to the Memory Cassette. Wait for the BKUP indicator and 7-segment display to go out before turning OFF the power supply to the PLC. Before replacing the battery, supply power to the CPU Unit for at least 5 minutes and then complete battery replacement within 5 minutes of turn OFF the power supply. Memory data may be corrupted if this precaution is not observed. Always use the following size wire when connecting I/O Units, Special I/O Units, and CPU Bus Units: AWG22 to AWG18 (0.32 to 0.82 mm2). UL standards required that batteries be replaced only by experienced technicians. Do not allow unqualified persons to replace batteries. Also, always follow the replacement procedure provided in the manual. Never short-circuit the positive and negative terminals of a battery or charge, disassemble, heat, or incinerate the battery. Do not subject the battery to strong shocks or deform the barry by applying pressure. Doing any of these may result in leakage, rupture, heat generation, or ignition of the battery. Dispose of any battery that has been dropped on the floor or otherwise subjected to excessive shock. Batteries that have been subjected to shock may leak if they are used. Always construct external circuits so that the power to the PLC it turned ON before the power to the control system is turned ON. If the PLC power supply is turned ON after the control power supply, temporary errors may result in control system signals because the output terminals on DC Output Units and other Units will momentarily turn ON when power is turned ON to the PLC. Fail-safe measures must be taken by the customer to ensure safety in the event that outputs from Output Units remain ON as a result of internal circuit failures, which can occur in relays, transistors, and other elements. If the I/O Hold Bit is turned ON, the outputs from the PLC will not be turned OFF and will maintain their previous status when the PLC is switched from RUN or MONITOR mode to PROGRAM mode. Make sure that the external loads will not produce dangerous conditions when this occurs. (When operation stops for a fatal error, including those produced with the FALS(007) instruction, all outputs from Output Unit will be turned OFF and only the internal output status will be maintained.)

xxix

Conformance to EC Directives

6
Dispose of the product and batteries according to local ordinances as they apply. Have qualified specialists properly dispose of used batteries as industrial waste.

6
6-1

Conformance to EC Directives
Applicable Directives
EMC Directives Low Voltage Directive

6-2

Concepts
EMC Directives OMRON devices that comply with EC Directives also conform to the related EMC standards so that they can be more easily built into other devices or the overall machine. The actual products have been checked for conformity to EMC standards (see the following note). Whether the products conform to the standards in the system used by the customer, however, must be checked by the customer. EMC-related performance of the OMRON devices that comply with EC Directives will vary depending on the configuration, wiring, and other conditions of the equipment or control panel on which the OMRON devices are installed. The customer must, therefore, perform the final check to confirm that devices and the overall machine conform to EMC standards. Note The applicable EMC (Electromagnetic Compatibility) standard is EN61131-2. Low Voltage Directive Always ensure that devices operating at voltages of 50 to 1,000 V AC and 75 to 1,500 V DC meet the required safety standards for the PLC (EN61131-2).

6-3

Conformance to EC Directives
The CP1H/CP1L PLCs comply with EC Directives. To ensure that the machine or device in which the CP1H/CP1L PLC is used complies with EC Directives, the PLC must be installed as follows: 1,2,3... 1. The CP1H/CP1L PLC must be installed within a control panel. 2. You must use reinforced insulation or double insulation for the DC power supplies used for I/O Units and CPU Units requiring DC power. The output holding time must be 10 ms minimum for the DC power supply connected to the power supply terminals on Units requiring DC power. 3. CP1H/CP1L PLCs complying with EC Directives also conform to EN61131-2. Radiated emission characteristics (10-m regulations) may vary depending on the configuration of the control panel used, other devices connected to the control panel, wiring, and other conditions. You must therefore confirm that the overall machine or equipment complies with EC Directives.

xxx

Conformance to EC Directives

6-4

Relay Output Noise Reduction Methods

The CP1H/CP1L PLCs conforms to the Common Emission Standards (EN61131-2) of the EMC Directives. However, noise generated by relay output switching may not satisfy these Standards. In such a case, a noise filter must be connected to the load side or other appropriate countermeasures must be provided external to the PLC. Countermeasures taken to satisfy the standards vary depending on the devices on the load side, wiring, configuration of machines, etc. Following are examples of countermeasures for reducing the generated noise.

Countermeasures
Countermeasures are not required if the frequency of load switching for the whole system with the PLC included is less than 5 times per minute. Countermeasures are required if the frequency of load switching for the whole system with the PLC included is more than 5 times per minute. Note Refer to EN61131-2 for more details.

Countermeasure Examples
When switching an inductive load, connect an surge protector, diodes, etc., in parallel with the load or contact as shown below.
Circuit Current AC DC Yes Yes Characteristic If the load is a relay or solenoid, there is a time lag between the moment the circuit is opened and the moment the load is reset. If the supply voltage is 24 or 48 V, insert the surge protector in parallel with the load. If the supply voltage is 100 to 200 V, insert the surge protector between the contacts. Required element The capacitance of the capacitor must be 1 to 0.5 F per contact current of 1 A and resistance of the resistor must be 0.5 to 1 per contact voltage of 1 V. These values, however, vary with the load and the characteristics of the relay. Decide these values from experiments, and take into consideration that the capacitance suppresses spark discharge when the contacts are separated and the resistance limits the current that flows into the load when the circuit is closed again. The dielectric strength of the capacitor must be 200 to 300 V. If the circuit is an AC circuit, use a capacitor with no polarity.

CR method
Inductive load

C R Power supply

xxxi

Conformance to EC Directives
Circuit Current AC DC No
Inductive load

6
Characteristic The diode connected in parallel with the load changes energy accumulated by the coil into a current, which then flows into the coil so that the current will be converted into Joule heat by the resistance of the inductive load. This time lag, between the moment the circuit is opened and the moment the load is reset, caused by this method is longer than that caused by the CR method. The varistor method prevents the imposition of high voltage between the contacts by using the constant voltage characteristic of the varistor. There is time lag between the moment the circuit is opened and the moment the load is reset. If the supply voltage is 24 or 48 V, insert the varistor in parallel with the load. If the supply voltage is 100 to 200 V, insert the varistor between the contacts. Required element The reversed dielectric strength value of the diode must be at least 10 times as large as the circuit voltage value. The forward current of the diode must be the same as or larger than the load current. The reversed dielectric strength value of the diode may be two to three times larger than the supply voltage if the surge protector is applied to electronic circuits with low circuit voltages. ---

Diode method

Yes

Power supply

Varistor method
Inductive load

Yes

Yes

Power supply

When switching a load with a high inrush current such as an incandescent lamp, suppress the inrush current as shown below.
Countermeasure 1 OUT R COM Providing a dark current of approx. one-third of the rated value through an incandescent lamp COM Providing a limiting resistor Countermeasure 2 R OUT

6-5

Conditions for Meeting EMC Directives when Using CP1, CPseries, or CPM1A Relay Expansion I/O Units
EN 61131-2 immunity testing conditions when using the CP1W-40EDR, CPM1A-40EDR, CP1W-16ER or CPM1A-16ER with an CP1W-CN811 I/O Connecting Cable are given below.

Recommended Ferrite Core

Ferrite Core (Data Line Filter): 0443-164151 manufactured by Nisshin Electric

Minimum impedance: 90 at 25 MHz, 160 at 100 MHz

30

32

33

xxxii

Conformance to EC Directives Recommended Connection Method

1,2,3... 1. Cable Connection Method

2. Connection Method As shown below, connect a ferrite core to each end of the CP1W-CN811 I/O Connecting Cable.
SYSMAC CP1H IN

AC100-240V
BATTERY PERIPHERAL
L1 L2/N COM 00 POWER ERR/ALM BKUP 01 02 03 04 05 06 07 08 09 10 11 00 01 02 03 04 05 06 07 08 09 10 11

EXP

MEMORY
00 COM 100CH 01 COM 02 COM 03 COM 04 05 06 07 00 01 COM 101CH 03 02 1CH COM 04 05 06 07

OUT

NC NC

NC NC

COM 00

01 02 CH

03 04

05 06

07 08

09 10

11 00

01 02 CH

03 04

05 06

07 08

09 10

11

CH

IN
CH CH

00 00

01 01 01 01

02 02 02 02

03 03 03 03

04 04 04 04

05 05 05 05

06 06 06 06

07 07 07 07

08 08

09 09

10 10

11 11

OUT
CH

00 00

40EDR

CH NC NC COM 00 COM 01 COM 02 03 04 COM 05 06 07

CH 00 02 04 05 07 COM 01 03 COM 06

EXP

xxxiii

Conformance to EC Directives

xxxiv

SECTION 1 Programming Concepts

This section describes the basic concepts required to program the CP1H.

1-1

Programming Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1-1 1-1-2 1-1-3 1-1-4 1-1-5 1-1-6 1-1-7 1-1-8 1-1-9 Programs and Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Information on Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Location and Execution Conditions . . . . . . . . . . . . . . . . Addressing I/O Memory Areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Instruction Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Execution Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 2 4 6 7 8 13 17 17 19 20 22 22 27 28 33 33 38 41 41 42 43 45 46 46 47 48

1-1-10 Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1-11 Program Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1-12 Basic Ladder Programming Concepts . . . . . . . . . . . . . . . . . . . . . . . 1-1-13 Inputting Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1-14 Program Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2-1 1-2-2 1-3 1-3-1 1-3-2 1-3-3 1-3-4 1-4 1-4-1 1-4-2 1-4-3 Condition Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Program Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CX-Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Checks with the CX-Programmer . . . . . . . . . . . . . . . . . . . Program Execution Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checking Fatal Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Files Created with CX-Programmer . . . . . . . . . . . . . . . . . . . . . . . . .

Checking Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introducing Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Programming Concepts

Section 1-1

1-1
1-1-1

Programming Concepts
Programs and Tasks
Tasks specify the sequence and interrupt conditions under which individual programs will be executed. They are broadly grouped into the following types: 1,2,3... 1. Tasks executed sequentially that are called cyclic tasks. 2. Tasks executed by interrupt conditions that are called interrupt tasks. Note Interrupt tasks can be executed cyclically in the same way as cyclic tasks. These are called extra cyclic tasks. Programs allocated to cyclic tasks will be executed sequentially by task number and I/O will be refreshed once per cycle after all tasks (more precisely tasks that are in executable status) are executed. If an interrupt condition goes into effect during processing of the cyclic tasks, the cyclic task will be interrupted and the program allocated to the interrupt task will be executed.
Program A

Cyclic task 0

Allocation Interrupt condition goes into effect

Interrupt task 100

Program B

Cyclic task 1

Allocation

Program C Allocation

Cyclic task n Allocation I/O refreshing

Program D

In the above example, programming would be executed in the following order: start of A, B, remainder of A, C, and then D. This assumes that the interrupt condition for interrupt task 100 was established during execution of program A. When execution of program B is completed, the rest of program A would be executed from the place where execution was interrupted. With earlier OMRON PLCs, one continuous program is formed from several continuous parts. The programs allocated to each task are single programs that terminate with an END instruction, just like the single program in earlier PLCs.

Programming Concepts

Section 1-1
One feature of the cyclic tasks is that they can be enabled (executable status) and disabled (standby status) by the task control instructions. This means that several program components can be assembled as a task, and that only specific programs (tasks) can then be executed as needed for the current product model or process being performed (program step switching). Therefore performance (cycle time) is greatly improved because only required programs will be executed as needed.

Earlier system

CP1H Task 1

One continuous subprogram

Allocation

Task 2

Tasks can be put into nonexecuting (standby) status.

Task 3

I/O refreshing I/O refreshing

A task that has been executed will be executed in subsequent cycles, and a task that is on standby will remain on standby in subsequent cycles unless it is executed again from another task. Note Unlike earlier programs that can be compared to reading a scroll, tasks can be compared to reading through a series of individual cards. All cards are read in a preset sequence starting from the lowest number. All cards are designated as either active or inactive, and cards that are inactive will be skipped. (Cards are activated or deactivated by task control instructions.) A card that is activated will remain activated and will be read in subsequent sequences. A card that is deactivated will remain deactivated and will be skipped until it is reactivated by another card.

Programming Concepts
Earlier program: Like a scroll

Section 1-1
CP-series program: Like a series of cards that can be activated or deactivated by other cards.

Activated

Deactivated

1-1-2

Basic Information on Instructions

Programs consist of instructions. The conceptual structure of the inputs to and outputs from an instruction is shown in the following diagram.

Power flow (P.F., execution condition) Instruction condition Flags Instruction

Power flow (P.F., execution condition)*1 Instruction condition*2 Flag *1: Input instructions only. Operands (sources) Operands (destinations) *2: Not output for all instructions.

Memory

Power Flow

The power flow is the execution condition that is used to control the execute and instructions when programs are executing normally. In a ladder program, power flow represents the status of the execution condition. Input Instructions Load instructions indicate a logical start and outputs the execution condition.
Outputs the execution condition.

Intermediate instructions input the power flow as an execution condition and output the power flow to an intermediate or output instruction.
Outputs the execution condition.

= D0 #1215

Programming Concepts
Output Instructions

Section 1-1

Output instructions execute all functions, using the power flow as an execution condition.
LD power flow Power flow for output instruction

Input block

Output block

Instruction Conditions

Instruction conditions are special conditions related to overall instruction execution that are output by the following instructions. Instruction conditions have a higher priority than power flow (P.F.) when it comes to deciding whether or not to execute an instruction. An instruction may become not be executed or may act differently depending on instruction conditions. Instruction conditions are reset (canceled) at the start of each task, i.e., they are reset when the task changes. The following instructions are used in pairs to set and cancel certain instruction conditions. These paired instructions must be in the same task.

Setting instruction An interlock turns OFF part of the program. Special conditions, such as IL(002) turning OFF output bits, resetting timers, and holding counters are in effect. BREAK(514) Ends a FOR(512) - NEXT(513) loop during execution. (Prevents execu- BREAK(514) execution tion of all instructions until to the NEXT(513) instruction.) Executes a JMP0(515) to JME0(516) jump. JMP0(515) Block program Executes a program block from BPRG(096) to BEND(801). BPRG(096) execution

Instruction condition Interlocked

Description

Canceling instruction ILC(003)

NEXT(513) JME0(516) BEND(801)

Flags

In this context, a flag is a bit that serves as an interface between instructions.

Input flags Output flags Differentiation Flags Differentiation Flags Differentiation result flags. The status of these flags Differentiation result flags. The status of these flags are output automatically from the instruction for all differentiated up/down are input automatically to the instruction for all difoutput instructions and the UP(521)/DOWN(522) instruction. ferentiated up/down output instructions and the DIFU(013)/DIFD(014) instructions. Condition Flags Condition Flags include the Always ON/OFF Flags, as well as Carry (CY) Flag flags that are updated by results of instruction execution. In user The Carry Flag is used as an unspecified operand programs, these flags can be specified by labels, such as ER, CY, in data shift instructions and addition/subtraction >, =, A1, A0, rather than by addresses. instructions. Flags for Special Instructions Flags for Special Instructions These include MSG(046) execution completed flags. These include teaching flags for FPD(269) instructions and network communications enabled flags

Operands

Operands specify preset instruction parameters (boxes in ladder diagrams) that are used to specify I/O memory area contents or constants. An instruction can be executed entering an address or constant as the operands. Operands are classified as source, destination, or number operands.
Example #0 D0

S (source) D (destination)

N (number)

Programming Concepts
Operand types Source Specifies the address of the data to be read or a constant. S C Operand symbol Source Operand Control data Description

Section 1-1

Source operand other than control data (C) Compound data in a source operand that has different meanings depending bit status.

Destination (Results) Number

Specifies the address where data D (R) will be written. Specifies a particular number used N in the instruction, such as a jump number or subroutine number.

-----

Note

Operands are also called the first operand, second operand, and so on, starting from the top of the instruction.

#0 D0

First operand Second operand

1-1-3

Instruction Location and Execution Conditions

The following table shows the possible locations for instructions. Instructions are grouped into those that do and those do not require execution conditions.
Instruction type Execution condition Logical start (Load Connected directly Not required. instructions) to the left bus bar or is at the beginning of an instruction block. Intermediate Between a logical Required. instructions start and the output instruction. Possible location Diagram Examples LD, LD TST(350), LD > (and other symbol comparison instructions) AND, OR, AND TEST(350), AND > (and other ADD symbol comparison instructions), UP(521), DOWN(522), NOT(520), etc. Most instructions including OUT and MOV(021). END(001), JME(005), FOR(512), ILC(003), etc.

Input instructions

Output instructions

Connected directly Required. to the right bus bar. Not required.

Note

(1) There is another group of instruction that executes a series of mnemonic instructions based on a single input. These are called block programming instructions. Refer to the CP-series CP1H/CP1L CPU Unit Programming Manual for details on these block programs. (2) If an instruction requiring an execution condition is connected directly to the left bus bar without a logical start instruction, a program error will occur when checking the program on a CX-Programmer.

Programming Concepts

Section 1-1

1-1-4

Addressing I/O Memory Areas

@@@@.@@ Bit number (00 to 15) Word address (Leading zeros are omitted.) Example: The address of bit 03 in word 0001 in the CIO Area would be as shown below. This address is given as CIO 1.03 in this manual. 1.03 Bit number (03) Word address: CIO 1

Bit Addresses

Word 15 CIO 0 CIO 1 CIO 2 14 13 12 11 10 09 08 07 06 05 04 03

Bit address: CIO 1.03 (CIO 1.03)

02

01

00

Bit number

Example: Bit 08 in word H010 in the HR Area is given as shown below.

H10.08 Bit number: 08 Word address: H10

Word Addresses
@@@@

Word address (Leading zeros are omitted.) Example: The address of word 0010 (bits 00 to 15) in the CIO Area is given as shown below. This address is given as CIO 10 in this manual. 10

Word address

Programming Concepts

Section 1-1
Example: The address of word W5 (bits 00 to 15) in the Work Area is given as shown below.

W5

Word address
Example: The address of word D200 (bits 00 to 15) in the DM Area is given as shown below.

D200

Word address

1-1-5

Specifying Instruction Operands

Description The word and bit numbers are specified directly to specify a bit (input bits).
@@@@.@@ Bit number (00 to 15) Word address 1.02 Bit number: 02 Word number: CIO 1

Operand Specifying bit addresses

Notation

Application examples

1.02

Specifying word addresses

Note The same addresses are used to access timer/counter Completion Flags and Present Values. There is also only one address for a Task Flag. The word number is specified directly to spec- 3 ify the 16-bit word.
@@@@ Word address D200 Word number: D200 Word number: 3

MOV(021) 3 D200

Specifying indirect DM addresses in Binary Mode

The offset from the beginning of the area is specified. The contents of the address will be treated as binary data (00000 to 32767) to specify the word address in Data Memory (DM). Add the @ symbol at the front to specify an indirect ad-dress in Binary Mode.
@D@@@@@ Contents D 00000 to 32767 (0000 to 7FFF hex)

@D300 Contents 0100 Hexadecimal 256 Specifies D256. Add the @ symbol.

MOV(021) #1 @D300

Programming Concepts
Operand Specifying indirect DM addresses in BCD Mode Description The offset from the beginning of the area is specified. The contents of the address will be treated as BCD data (0000 to 9999) to specify the word address in Data Memory (DM). Add an asterisk (*) at the front to specify an indirect address in BCD Mode.
*D@@@@@ Contents D 00000 to 9999 (BCD) *D200 0100 BCD: 100 Contents

Section 1-1
Notation Application examples
MOV(021) #1 *D200

Specifies D100. Add an asterisk (*).

Specifying a register directly

An index register (IR) or a data register (DR) is IR0 specified directly by specifying IR@ (@: 0 to 15) or DR@ (@: 0 to 15).

MOVR(560)

1.02 IR0

Stores the PLC memory address for CIO 10 in IR0. IR1

MOVR(560)

10 IR1

Stores the PLC memory address for CIO 10 in IR1. Operand Specifying an indirect address using a register Description Indirect The bit or word with the PLC memory address address contained in IR@ will be speci(No offset) fied. Specify ,IR@ to specify bits and words for instruction operands. Notation ,IR0 Application examples

,IR0
Loads the bit with the PLC memory address in IR0.

,IR1

MOV(021) #1 ,IR1

Stores #0001 in the word with the PLC memory in IR1. Constant offset +5,IR0 The bit or word with the PLC memory address in IR@ + or the constant is specified. Specify +/ constant ,IR@. Constant offsets range from 2048 to +2047 (decimal). The offset is converted to binary +31,IR1 data when the instruction is executed.

+5,IR0
Loads the bit with the PLC memory address in IR0 + 5.
MOV(021) #1 +31 ,IR1

Stores #0001 in the word with the PLC memory address in IR1 + 31

Programming Concepts
Operand Specifying an indirect address using a register DR offset Description Notation

Section 1-1
Application examples

The bit or word with the PLC memory DR0 ,IR0 address in IR@ + the contents of DR@ is specified. Specify DR@ ,IR@. DR (data register) contents are treated as signed-binary data. The contents of IR@ will be given a negative offset if the signed binary value DR0 ,IR1 is negative.

DR0,IR0
Loads the bit with the PLC memory address in IR0 + the value in DR0.
MOV(021) #1 DR0 ,IR1

Stores #0001 in the word with the PLC memory address in IR1 + the value in DR0. Auto Incre- The contents of IR@ is incremented by ment +1 or +2 after referencing the value as an PLC memory address. +1: Specify ,IR@+ +2: Specify ,IR@ + + ,IR0 ++

,IR0 ++
Increments the contents of IR0 by 2 after the bit with the PLC memory address in IR0 is loaded.
MOV(021) #1 ,IR1 +

Note The auto increment operation will not be executed for a CP1L CPU ,IR1 + Unit if a P_ER or P_AER error occurs during instruction execution.

Increments the contents of IR1 by 1 after #0001 is stored in the word with the PLC memory address in IR1. Auto Decrement The contents of IR@ is decremented by 1 or 2 after referencing the value as an PLC memory address. 1: Specify ,IR@ 2: Specify , IR@ Note The auto decrement operation will not be executed for a CP1L CPU Unit if a P_ER or P_AER error occurs during instruction execution. , IR0

,IR
After decrementing the contents of IR0 by 2, the bit with the PLC memory address in IR0 is loaded.
MOV(021) #1 ,IR1

,IR1

After decrementing the contents of IR1 by 1, #0001 is stored in the word with the PLC memory address in IR1.

10

Programming Concepts
Data 16-bit constant Operand Data form All binary data or Unsigned binary a limited range of binary data Symbol # Range #0000 to #FFFF

Section 1-1
Application example
MOV(021) #5A D100

Signed decimal

32768 to +32767

+(400) D200 128 D300

Unsigned decimal

&

&0 to &65535

CMP(020) D400 &999

All BCD data or a BCD limited range of BCD data

#0000 to #9999

B(414) D500 #2000 D600

32-bit constant

All binary data or Unsigned binary a limited range of binary data

#00000000 to #FFFFFFFF

MOVL(498)

#17FFF D100

Signed binary

2147483648 to +2147483647

+L(401) D200 65536 D300

Unsigned decimal

& (See Note.)

&0 to &429467295

CMPL(060)

D400 &99999

All BCD data or a BCD limited range of BCD data

#00000000 to #99999999

BL(415) D500 #1000000 D600

11

Programming Concepts
Data Text string Operand Data form Description Text string data is stored in ASCII --(one byte except for special characters) in order from the leftmost to the rightmost byte and from the rightmost (smallest) to the leftmost word. 00 hex (NUL code) is stored in the rightmost byte of the last word if there is an odd number of characters. 0000 hex (2 NUL codes) is stored in the leftmost and rightmost vacant bytes of the last word + 1 if there is an even number of characters. Symbol Symbol Range Examples
'ABCDE'

Section 1-1
Application example

MOV$(664)

'A' 'C' 'E' 41 43 45

'B' 'D' NUL 42 44 00

D100 D200

D100 D101 D102 D200 D201 D202

41 43 45 41 43 45

42 44 00 42 44 00

'ABCD' 'A' 'C' NUL 41 43 00 'B' 'D' NUL 42 44 00

ASCII characters that can be used in a text string includes alphanumeric characters, Katakana and symbols (except for special characters). The characters are shown in the following table.

ASCII Characters
Bits 0 to 3 Binary Hex 0000 0 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1 2 3 4 5 6 7 8 9 A B C D E F Bits 4 to 7 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Space

! # $ % & ( ) * + , . /

0 1 2 3 4 5 6 7 8 9 : ; < = > ?

@ A B C D E F G H I J K L M N O

P Q R S T U V W X Y Z [ \ ] ^ _

` a b c d e f g h i j k l m n o

p q r s t u v w x y z { | } ~

! # $ % & ( ) * + , . /

0 1 2 3 4 5 6 7 8 9 : ; < = > ?

@ A B C D E F G H I J K L M N O

P Q R S T U V W X Y Z [ \ ] ^ _

12

Programming Concepts

Section 1-1

1-1-6
Data type Unsigned binary

Data Formats
The following table shows the data formats that the CP Series can handle.
Data format
15 14 13 12 11 10 9 8 7 6 26
64

Decimal
5 4 25 24
12 16

3 23
8

2 22
4

0 21 20

0 to 65535

4-digit hexadecimal 0000 to FFFF

Binary Decimal Hex

215 214 213 212 211 210 29

28 27

3276816384 8192 4092 2048 1024 512 256 128

23

22

21 20

23

22 10 9

21 20 23 8 7

22 6
26
64

21 20 5 4
25 24
12 16

23 3
23
8

22 2
22
4

21 20 1 0
21 20
2 1

Signed binary
Binary Decimal Hex

15 14 13

12 11

215 214 213 212 211 210 29

28 27

0 to 32768 0 to +32767

Negative: 8000 to FFFF Positive: 0000 to 7FFF

3276816384 8192 4092 2048 1024 512 256 128

23

22

21 20

23

22

21 20 23

22

21 20

23

22

21 20

Sign bit: 0: Positive, 1: Negative

BCD (binary coded decimal) Binary

Decimal

15 14 13

12 11

10 9

0 to 9999

0000 to 9999

23

22

21 20

23

22

21

20 23

22

21 20

23

22

21

20

0 to 9

0 to 9

0 to 9

0 to 9

13

Programming Concepts
Data type Single-pre31 30 29 23 22 cision floatingpoint decimal Sign of Exponent
mantissa 21

Section 1-1
Data format
20 19 18 17 3 2 1 0

Decimal ---

4-digit hexadecimal ---

Binary

Mantissa

Value = (1)Sign Sign (bit 31) Mantissa

x 1.[Mantissa] x 2Exponent 1: negative or 0: positive The 23 bits from bit 00 to bit 22 contain the mantissa, i.e., the portion below the decimal point in 1.@@@....., in binary. The 8 bits from bit 23 to bit 30 contain the exponent. The exponent is expressed in binary as 127 plus n in 2n.

Exponent

Note This format conforms to IEEE754 standards for single-precision floatingpoint data and is used only with instructions that convert or calculate floating-point data. It can be used to set or monitor from the I/O memory Edit and Monitor Screen on the CX-Programmer. As such, users do not need to know this format although they do need to know that the formatting takes up two words. Doubleprecision floatingpoint decimal
63 62 61 52 51 50 49 48 47 46 3 2 1 0

---

---

Sign of mantissa

Exponent Binary

Mantissa

Value = (1)Sign x 1.[Mantissa] x 2Exponent Sign (bit 63) Mantissa 1: negative or 0: positive The 52 bits from bit 00 to bit 51 contain the mantissa, i.e., the portion below the decimal point in 1.@@@....., in binary. The 11 bits from bit 52 to bit 62 contain the exponent The exponent is expressed in binary as 1023 plus n in 2n.

Exponent

Note This format conforms to IEEE754 standards for double-precision floatingpoint data and is used only with instructions that convert or calculate floating-point data. It can be used to set or monitor from the I/O memory Edit and Monitor Screen on the CX-Programmer. As such, users do not need to know this format although they do need to know that the formatting takes up four words.

Signed Binary Data In signed binary data, the leftmost bit indicates the sign of binary 16-bit data. The value is expressed in 4-digit hexadecimal. Positive Numbers: A value is positive or 0 if the leftmost bit is 0 (OFF). In 4digit hexadecimal, this is expressed as 0000 to 7FFF hex. Negative Numbers: A value is negative if the leftmost bit is 1 (ON). In 4-digit hexadecimal, this is expressed as 8000 to FFFF hex. The absolute of the negative value (decimal) is expressed as a twos complement.

14

Programming Concepts

Section 1-1
Example: To treat 19 in decimal as signed binary, 0013 hex (the absolute value of 19) is subtracted from FFFF hex and then 0001 hex is added to yield FFED hex.
F 1111 True number 0 0000 F 1111 0 0000 F 1111 1 0001 F 1111 3 0011

F 1111 0

F 1111 0 0000

E 1110 0 0000

C 1100 1 0001

+)
Two's complement

0000

F 1111

F 1111

E 1110

D 1101

Complements Generally the complement of base x refers to a number produced when all digits of a given number are subtracted from x 1 and then 1 is added to the rightmost digit. (Example: The tens complement of 7556 is 9999 7556 + 1 = 2444.) A complement is used to express a subtraction and other functions as an addition. Example: With 8954 7556 = 1398, 8954 + (the tens complement of 7556) = 8954 + 2444 = 11398. If we ignore the leftmost bit, we get a subtraction result of 1398. Twos Complements A twos complement is a base-two complement. Here, we subtract all digits from 1 (2 1 = 1) and add one. Example: The twos complement of binary number 1101 is 1111 (F hex) 1101 (D hex) + 1 (1 hex) = 0011 (3 hex). The following shows this value expressed in 4-digit hexadecimal. The twos complement b hex of a hex is FFFF hex a hex + 0001 hex = b hex. To determine the twos complement b hex of a hex, use b hex = 10000 hex a hex. Example: to determine the twos complement of 3039 hex, use 10000 hex 3039 hex = CFC7 hex. Similarly use a hex = 10000 hex b hex to determine the value a hex from the twos complement b hex. Example: To determine the real value from the twos complement CFC7 hex use 10000 hex CFC7 hex = 3039 hex. The CP Series has two instructions: NEG(160)(2S COMPLEMENT) and NEGL(161) (DOUBLE 2S COMPLEMENT) that can be used to determine the twos complement from the true number or to determine the true number from the twos complement.

15

Programming Concepts
Signed BCD Data

Section 1-1

Signed BCD data is a special data format that is used to express negative numbers in BCD. Although this format is found in applications, it is not strictly defined and depends on the specific application. The CP Series supports the following instructions to convert the data formats: SIGNED BCD-TO-BINARY: BINS(470), DOUBLE SIGNED BCD-TO-BINARY: BISL(472), SIGNED BINARY-TO-BCD: BCDS(471), and DOUBLE SIGNED BINARY-TO-BCD: BDSL(473). Refer to the CP-series CPU Unit Programming Manual (W451) for more information.
Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 Decimal +65,535 +65534 . . . +32,769 +32,768 +32,767 +32,766 . . . +2 +1 0 1 2 . . . 32,767 32,768 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 10000 BCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 0001 0010 0011 0100 0101 0110 Signed binary (4-digit hexadecimal) Cannot be expressed.

0001 0001 0001 0001 0001 0001 0001

Unsigned binary (4-digit hexadecimal) FFFF FFFE . . . 8001 8000 7FFF 7FFE . . . 0002 0001 0000 Cannot be expressed.

7FFF 7FFE . . . 0002 0001 0000 FFFF FFFE . . . 8001 8000

16

Programming Concepts

Section 1-1

1-1-7

Instruction Variations
The following variations are available for instructions to differentiate executing conditions and to refresh data when the instruction is executed (immediate refresh).
Variation Differentiation Symbol Description ON @ Instruction that differentiates when the execution condition turns ON. OFF % Instruction that differentiates when the execution condition turns OFF. Immediate refreshing ! Refreshes data in the I/O area specified by the operands or the Special I/O Unit words when the instruction is executed.
@ Instruction (mnemonic) Differentiation variation Immediate refresh variation

1-1-8

Execution Conditions
The CP Series offers the following types of basic and special instructions. Non-differentiated instructions executed every cycle Differentiated instructions executed only once

Non-differentiated Instructions

Output instructions that required execution conditions are executed once every cycle while the execution condition is valid (ON or OFF).
Example
Non-differentiated output instruction

Input instructions that create logical starts and intermediate instructions read bit status, make comparisons, test bits, or perform other types of processing every cycle. If the results are ON, power flow is output (i.e., the execution condition is turned ON).
Example Non-differentiated input instruction

Input-differentiated Instructions
Upwardly Differentiated Instructions (Instruction Preceded by @) Output Instructions: The instruction is executed only during the cycle in which the execution condition turned ON (OFF ON) and are not executed in the following cycles.
Example
1.02
(@) Upwardly-differ entiated instruction

@MOV Executes the MOV instruction once when CIO 1.02 goes OFF ON.

17

Programming Concepts

Section 1-1
Input Instructions (Logical Starts and Intermediate Instructions): The instruction reads bit status, makes comparisons, tests bits, or perform other types of processing every cycle and will output an ON execution condition (power flow) when results switch from OFF to ON. The execution condition will turn OFF the next cycle.
Example Upwardly differentiated input instruction 1.03

ON execution condition created for one cycle only when CIO 1.03 goes from OFF to ON.

Input Instructions (Logical Starts and Intermediate Instructions): The instruction reads bit status, makes comparisons, tests bits, or perform other types of processing every cycle and will output an OFF execution condition (power flow stops) when results switch from OFF to ON. The execution condition will turn ON the next cycle.
Example Upwardly differentiated input instruction 1.03

OFF execution condition created for one cycle only when CIO 1.03 goes from OFF to ON.

Downwardly Differentiated Instructions (Instruction preceded by %)

Output instructions: The instruction is executed only during the cycle in which the execution condition turned OFF (ON OFF) and is not executed in the following cycles.
Example
(%) Downwardly differentiated instruction

1.02

%SET Executes the SET instruction once when CIO 1.02 goes ON to OFF.

Input Instructions (Logical Starts and Intermediate Instructions): The instruction reads bit status, makes comparisons, tests bits, or perform other types of processing every cycle and will output the execution condition (power flow) when results switch from ON to OFF. The execution condition will turn OFF the next cycle.
Downwardly differentiated instruction Example 1.03

Will turn ON when the CIO 1.03 switches from ON to OFF and will turn OFF after one cycle.

Note

Unlike the upwardly differentiated instructions, downward differentiation variation (%) can only be added to LD, AND, OR, SET and RSET instructions. To execute downward differentiation with other instructions, combine the instructions with a DIFD or a DOWN instruction.

18

Programming Concepts

Section 1-1
Input Instructions (Logical Starts and Intermediate Instructions): The instruction reads bit status, makes comparisons, tests bits, or perform other types of processing every cycle and will output an OFF execution condition (power flow stops) when results switch from ON to OFF. The execution condition will turn ON the next cycle.
Example Downwardly differentiated input instruction 1.03

OFF execution condition created for one cycle only when CIO 1.03 goes from ON to OFF.

1-1-9

I/O Instruction Timing

The following timing chart shows different operating timing for individual instructions using a program comprised of only LD and OUT instructions.
Input read

B1

Input read Input read Input read

B2

B3

Input read

B4

!
A B5

Input read Input read

!
A B6

B7 !

Input read Input read

Input read Input read

B8 !

B9 !

Input read

B10 ! B11 ! B12 !

!
A

!
A

CPU processing Instruction I/O refresh executed.

Differentiated Instructions

A differentiated instruction has an internal flag that tells whether the previous value is ON or OFF. At the start of operation, the previous value flags for upwardly differentiated instruction (DIFU and @ instructions) are set to ON and the previous value flags for downwardly differentiated instructions (DIFD and % instructions) are set to OFF. This prevents differentiation outputs from being output unexpectedly at the start of operation.

19

Programming Concepts

Section 1-1
An upwardly differentiated instruction (DIFU or @ instruction) will output ON only when the execution condition is ON and flag for the previous value is OFF. Use in Interlocks (IL - ILC Instructions) In the following example, the previous value flag for the differentiated instruction maintains the previous interlocked value and will not output a differentiated output at point A because the value will not be updated while the interlock is in effect.
0.00 IL

0.01 DIFU 10.00

ILC

0.00

IL is executing

IL is executing

0.01

10.00 A

Use in Jumps (JMP - JME Instructions): Just as for interlocks, the previous value flag for a differentiated instruction is not changed when the instruction is jumped, i.e., the previous value is maintained. Upwardly and downwardly differentiate instructions will output the execution condition only when the input status has changed from the status indicated by the previous value flag. Note (a) Do not use the Always ON Flag or A200.11 (First Cycle Flag) as the input bit for an upwardly differentiated instruction. The instruction will never be executed. (b) Do not use Always OFF Flag as the input bit for a downwardly differentiated instruction. The instruction will never be executed.

1-1-10 Refresh Timing

The following methods are used to refresh external I/O. Cyclic refresh Immediate refresh (! specified instruction, IORF instruction)

Cyclic Refresh

Every program allocated to a ready cyclic task or a task where interrupt condition has been met will execute starting from the beginning program address and will run until the END(001) instruction. After all ready cyclic tasks or tasks where interrupt condition have been met have executed, cyclic refresh will refresh all I/O points at the same time. Note Programs can be executed in multiple tasks. I/O will be refreshed after the final END(001) instruction in the program allocated to the highest number (among all ready cyclic tasks) and will not be refreshed after the END(001) instruction in programs allocated to other cyclic tasks.

20

Programming Concepts

Section 1-1

Top
15 0 0

! LD 1.01 ! OUT 2.09

CIO 1 15 CIO 2

16-bit units

END Top
CIO 3 15 0 15 0

16-bit units

! MOV 3 4 END

CIO 4

Cyclic refresh (batch processing) I/O refresh All real data

Execute IORF(097) for all required words or use instructions with the immediate refresh option prior to the END(001) instruction if I/O refreshing is required in other tasks.

Immediate Refresh
Instructions with Refresh Variation (!) I/O will be refreshed as shown below when an instruction is executing if an real I/O bit in the built-in I/O of the CPU Unit is specified as an operand. When a bit operand is specified for an instruction, I/O will be refreshed for the 16 bits of the word containing the bit. When a word operand is specified for an instruction, I/O will be refreshed for the 16 bits that are specified. Inputs will be refreshed for input or source operand just before an instruction is executed. Outputs will be refreshed for outputs or destination (D) operands just after an instruction is execute. Add an exclamation mark (!) (immediate refresh option) in front of the instruction. Note Immediate refreshing is not supported for real I/O data allocated to CPseries/CPM1A Expansion Units or Expansion I/O Units, but IORF(097) is supported for them. An I/O REFRESH instruction (IORF(097)) that refreshes real I/O data in a specified word range is available as a special instruction for CPseries/CPM1A Expansion Units and Expansion I/O Units. All or just a specified range of real I/O bits can be refreshed during a cycle with this instruction. Note IORF(097) cannot be used for real I/O bits allocated to the built-in I/O of the CPU Unit. Use instructions with the immediate refresh option for this I/O. IORF(097) can also be used to refresh words allocated to CJ-series Special I/O Units.

Units Refreshed for IORF(097)

21

Programming Concepts
DLNK(226) (CP1H CPU Units)

Section 1-1
The CPU BUS UNIT I/O REFRESH instruction (DLNK(226)) can be used to refresh memory allocated to CJ-series CPU Bus Units in the CIO and DM Areas, as well as data link data and other data specific to the CPU Bus Units. The unit number of the CPU Bus Unit is specified when DLNK(226) is executed to refresh all of the following data at the same time. Words allocated to the Unit in CIO Area Words allocated to the Unit in DM Area Special refreshing for the Unit (e.g., data links for Controller Link Units or remote I/O for DeviceNet Units)

1-1-11 Program Capacity

The maximum program capacities of the CP-series CPU Units for all user programs (i.e., the total capacity of all tasks) are given in the following table. All capacities are given as the maximum number of steps. The capacities must not be exceeded, and writing the program will be disabled if an attempt is made to exceed the capacity. Each instruction is from 1 to 7 steps long. Refer to SECTION 4 Instruction Execution Times and Number of Steps for the specific number of steps in each instruction. (The length of each instruction will increase by 1 step if a double-length operand is used.)
Series CPU Unit type CP Series CP1H XA CPU Units X Y CP Series CP1L M CPU Units L Model CP1H-XA40D@-@ CP1H-X40D@-@ CP1H-Y20DT-D CP1L-M40D@-@ CP1L-M30D@-@ CP1L-L20D@-@ CP1L-L14D@-@ Max. program capacity 20K steps

10K steps 5K steps

Note

Memory capacity for CP-series PLCs is measured in steps, whereas memory capacity for previous OMRON PLCs, such as the C200HX/HG/HE and CVseries PLCs, was measured in words. Refer to the information at the end of SECTION 4 Instruction Execution Times and Number of Steps for guidelines on converting program capacities from previous OMRON PLCs.

1-1-12 Basic Ladder Programming Concepts

Instructions are executed in the order listed in memory (mnemonic order). The basic programming concepts as well as the execution order must be correct. General Structure of the Ladder Diagram A ladder diagram consists of left and right bus bars, connecting lines, input bits, output bits, and special instructions. A program consists of one or more program runs. A program rung is a unit that can be partitioned when the bus is split horizontally. In mnemonic form, a rung is all instructions from a LD/LD NOT instruction to the output instruction just before the next LD/LD NOT instructions. A program rung consists of instruction blocks that begin with an LD/LD NOT instruction indicating a logical start.

22

Programming Concepts
Special Output bit Input bit instruction Connecting line Right bus bar Rungs Instruction blocks

Section 1-1

Left bus bar

Mnemonics

A mnemonic program is a series of ladder diagram instructions given in their mnemonic form. It has program addresses, and one program address is equivalent to one instruction.
Example
0.00 0.01 0.02 0.03 102.00

1.00

1.01

Program Address 0 1 2 3 4 5 6 7 8 9

Instruction (Mnemonic) LD AND LD AND NOT LD NOT AND OR LD AND LD OUT END

Operand 0.00 0.01 0.02 0.03 1.00 1.01

102.00

Basic Ladder Program Concepts 1,2,3... 1. When ladder diagrams are executed by PLCs, the signal flow (power flow) is always from left to right. Programming that requires power flow from right to left cannot be used. Thus, flow is different from when circuits are made up of hard-wired control relays. For example, when the circuit a is implemented in a PLC program, power flows as though the diodes in brackets

23

Programming Concepts

Section 1-1
were inserted and coil R2 cannot be driven with contact D included. The actual order of execution is indicated on the right with mnemonics. To achieve operation without these imaginary diodes, the circuit must be rewritten. Also, circuit b power flow cannot be programmed directly and must be rewritten.

Circuit "a"
A (1) Signal flow C (2) ((3)) D (4) ((8)) E (9) R2 ((5)) B (6) R1 (7)

(10)

Order of execution (mnemonic) (1) LD A (6) AND B (2) LD C (7) OUT R1 (3) OUT TR0 (8) LD TR0 (4) AND D (9) AND E (5) OR LD (10) OUT R2

Circuit " b"

A E C D R2 B R1

In circuit a, coil R2 cannot be driven with contact D included. In circuit b, contact E included cannot be written in a ladder diagram. The program must be rewritten. 2. There is no limit to the number of I/O bits, work bits, timers, and other input bits that can be used. Rungs, however, should be kept as clear and simple as possible even if it means using more input bits to make them easier to understand and maintain. 3. There is no limit to the number of input bits that can be connected in series or in parallel in series or parallel rungs. 4. Two or more output bits can be connected in parallel.
0.00 0.05 TIM 0000 #100 102.00

5. Output bits can also be used as input bits.

102.00

102.00

24

Programming Concepts
Restrictions 1,2,3...

Section 1-1

1. A ladder program must be closed so that signals (power flow) will flow from the left bus bar to the right bus bar. A rung error will occur if the program is not closed (but the program can be executed).

2. Output bits, timers, counters and other output instructions cannot be connected directly to the left bus bar. If one is connected directly to the left bus bar, a rung error will occur during the programming check by the CX-Programmer. (The program can be executed, but the OUT and MOV(021) will not be executed.)
Input condition must be provided.

MOV

Insert an unused N.C. work bit or the ON Condition Flag (Always ON Flag) if the input must be kept ON at all times.
Unused work bit

ON (Always ON Flag)
MOV

3. An input bit must always be inserted before and never after an output instruction like an output bit. If it is inserted after an output instruction, then a location error will occur during the CX-Programmer program check.
0.00 0.03 102.01 0.04

0.01

102.01

25

Programming Concepts

Section 1-1
4. The same output bit cannot be programmed in an output instruction more than once. Instructions in a ladder program are executed in order from the top rung in a single cycle, so the result of output instruction in the lower rungs will be ultimately reflected in the output bit and the results of any previous instructions controlling the same bit will be overwritten and not output.
(Output bit) 100.00 (Output bit) 100.00

5. An input bit cannot be used in an OUTPUT instruction (OUT).

(Input bit) 0.00

6. An END(001) instruction must be inserted at the end of the program in each task. If a program without an END(001) instruction starts running, a program error indicating No End Instruction will occur, the ERR/ALM LED on the front of the CPU Unit will light, and the program will not be executed. If a program has more than one END(001) instruction, then the program will only run until the first END(001) instruction. Debugging programs will run much smoother if an END(001) instruction is inserted at various break points between sequence rungs and the END(001) instruction in the middle is deleted after the program is checked.
Task (program) 000000 000001 Task (program) 000000 000001 END END Task (program) 000000 000001 END Task (program) 000000 000001 END END Will not be executed. END Task (program) 000000 000001 Will not be executed.

Task (program) 000000 000001

END

END

26

Programming Concepts

Section 1-1

1-1-13 Inputting Mnemonics

A logical start is accomplished using an LD/LD NOT instruction. The area from the logical start until the instruction just before the next LD/LD NOT instruction is considered a single instruction block. Create a single rung consisting of two instruction blocks using an AND LD instruction to AND the blocks or by using an OR LD instruction to OR the blocks. The following example shows a complex rung that will be used to explain the procedure for inputting mnemonics (rung summary and order). 1,2,3... 1. First separate the rung into small blocks (a) to (f).
0.00 0.01 10.00 10.01 5.00 0.02 0.03 0.04 0.05 0.06 W0.00

(a)

0.00

0.01 (e) 0.04 0.05

(b) 10.00 10.01

(d) 0.02 0.03 (5) (f) 0.06

(1) (c) 5.00 (3) (2)

(4)

27

Programming Concepts

Section 1-1
2. Program the blocks from top to bottom and then from left to right.
(a) 0.00 0.01 (b) 10.00 10.01

(1)
LD 0.00 AND 0.01
OR LD

LD 10.00 AND 10.01

(2)
(c) 5.00 (c) 0.04 0.05

(3)

OR 5.00

LD 0.04 AND 0.05

(5)

(4)
(a) 0.02 0.03 (f) 0.06

AND 0.02 AND NOT 0.03 AND LD

OR 0.06

W0.00

OUT W0.00

Address (a) (b) 200 201 202 203 204 205 206 207 208 209 210 211 212

Instruction Operand LD AND LD AND OR LD OR AND AND NOT LD AND OR AND LD OUT 0.00 0.01 10.00 10.01 --5.00 0.02 0.03 0.04 0.05 0.06 --W0.00

(1)

(2) (3) (5)

(c) (d) (e) (f)

(4)

1-1-14 Program Examples

Parallel/Series Rungs
0.00 0.01 0.02 0.03 102.00 102.00

Instruction Operands LD AND OR AND AND NOT OUT 0.00 0.01 102.00 0.02 0.03 102.00
a

a A block

b B block

Program the parallel instruction in the A block and then the B block.

28

Programming Concepts Series/Parallel Rungs

0.00 0.01 0.02 0.03 102.01

Section 1-1

Instruction Operands LD AND NOT LD AND OR OR AND LD OUT 0.00 0.01 0.02 0.03 102.01 0.04 --102.01 a

102.01 0.04

a A block

B block

Separate the rung into A and B blocks, and program each individually. Connect A and B blocks with an AND LD. Program A block.
Instruction Operands
b1

B1 block 0.00 0.01 0.02 0.03

0.04 102.02

102.02

b2

B2 block
a b

LD NOT AND LD AND NOT LD NOT AND OR LD AND LD OUT

0.00 0.01 0.02 0.03 0.04 102.02 ----102.02

a b1 b2 b1 + b2 ab

A block

B block

Program B1 block and then program B2 block. Connect B1 and B2 blocks with an OR LD and then A and B blocks with an AND LD.

Example of Series Connection in a Series Rung

A1 block B1 block 0.00 0.01 0.04 0.05

0.02 0.03 0.06 0.07

a1

b1

Instruction Operands
102.03

a2

b2

A2 block
a

B2 block
b

A block

B block

LD AND NOT LD NOT AND OR LD LD AND LD AND OR LD AND LD OUT

0.00 0.01 0.02 0.03 --0.04 0.05 0.06 0.07 ----102.03

a1 a2 a1 + a 2 b1 b2 b1 + b 2 ab

Program A1 block, program A2 block, and then connect A1 and A2 blocks with an OR LD. Program B1 and B2 the same way. Connect A block and B block with an AND LD.

29

Programming Concepts
Repeat for as many A to n blocks as are present.

Section 1-1

5.00

A block

B block

C block

n block

Complex Rungs
0.00 0.01 0.02 0.03 0.04 0.06 0.05 0.07 102.04

Instruction Operand LD LD LD AND OR LD AND LD LD AND OR LD LD AND OR LD OUT 0.00 0.01 0.02 0.03 ----0.04 0.05 --0.06 0.07 --102.04

0.00

0.01 0.02 0.03

Z Z The diagram above is based on the diagram below.

0.00 Z

A simpler program can be written by rewriting this as shown below.

0.02 0.01 0.03 0.00

Block
0.00 a 0.01 0.02 d 102.05

Instruction Operand LD LD NOT AND LD AND NOT LD LD AND NOT OR LD AND LD OR LD AND LD OUT 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 --------102.05 a b c d e d+e (d + e) c (d + e) c + b ((d + e) c + b) a

Block
0.03 c 0.04

Block
0.05

Block

0.06

0.07

Block
The above rung can be rewritten as follows:

0.00 0.00 0.00

0.01 0.03 0.03

0.02 0.04 0.04 0.05 0.06 0.07

102.05

30

Programming Concepts
Instruction Operand LD OR OR OR AND NOT OUT TIM AND OUT 0.00 0.01 0.02 H0.00 0.03 H0.00 0001 #100 T1 102.06

Section 1-1

0.00

0.03

H0.00

0.01 0.02 H0.00

Error input

TIM 0001 #100 10 sec

T1

102.06

Error display

If a holding bit is in use, the ON/OFF status would be held in memory even if the power is turned OFF, and the error signal would still be in effect when power is turned back ON.

Rungs Requiring Caution or Rewriting

OR and OL LD Instructions With an OR or OR NOT instruction, an OR is taken with the results of the ladder logic from the LD or LD NOT instruction to the OR or OR NOT instruction, so the rungs can be rewritten so that the OR LD instruction is not required.
0.00 0.01 102.00 102.00 0.01 102.00 102.00

0.00

Example: An OR LD instruction will be needed if the rungs are programmed as shown without modification. A few steps can be eliminated by rewriting the rungs as shown. Output Instruction Branches A TR bit will be needed if there is a branch before an AND or AND NOT instruction. The TR bit will not be needed if the branch comes at a point that is connected directly to output instructions and the AND or AND NOT instruction or the output instructions can be continued as is.
Output instruction 1 0.00
TR0

0.01

102.08

0.00 0.01

102.09 102.08

102.09

Output instruction 2

Example: A temporary storage bit TR0 output instruction and load (LD) instruction are needed at a branch point if the rungs are programmed without modification. A few steps can be eliminated by rewriting the rungs.

31

Programming Concepts
Mnemonic Execution Order

Section 1-1

PLCs execute ladder programs in the order the mnemonics are entered so instructions may not operate as expected, depending on the way rungs are written. Always consider mnemonic execution order when writing ladder diagrams.
0.00 110.00 110.00 102.10 0.00 0.00 110.00 102.10

110.00

Example: CIO 102.10 in the above diagram cannot be output. By rewriting the rung, as shown above, CIO 102.10 can be turned ON for one cycle. Rungs Requiring Rewriting PLCs execute instructions in the order the mnemonics are entered so the signal flow (power flow) is from left to right in the ladder diagram. Power flows from right to left cannot be programmed.
0.00
TR0

0.03 102.11

0.01 0.00

0.02

0.03

102.11

0.01

0.02 0.04 102.12

0.01

0.04

102.12

Example: The program can be written as shown in the diagram at the left where TR0 receives the branch. The same value is obtained, however, by the rungs at the right, which are easier to understand. It is recommended, therefore, that the rungs at the left be rewritten to the rungs at the right. Rewrite the rungs on the left below. They cannot be executed. The arrows show signal flow (power flow) when the rungs consist of control relays.
A A C E B R1 D R2 C A C E E D R2 B R1

32

Precautions

Section 1-2

1-2
1-2-1

Precautions
Condition Flags
Conditions flags are shared by all instructions, and will change during a cycle depending on results of executing individual instructions. Therefore, be sure to use Condition Flags on a branched output with the same execution condition immediately after an instruction to reflect the results of instruction execution. Never connect a Condition Flag directly to the bus bar because this will cause it to reflect execution results for other instructions. Example: Using Instruction A Execution Results
Correct Use Mnemonic Instruction A Instruction Operand a LD Instruction A AND Instruction B =

Using Condition Flags

Condition Flag Example: =

Reflects instruction A execution results. Instruction B

The same execution condition (a) is used for instructions A and B to execute instruction B based on the execution results of instruction A. In this case, instruction B will be executed according to the Condition Flag only if instruction A is executed.
Incorrect Use

Preceding rung

Instruction A Reflects the execution results of the preceding rung if instruction A is not executed. Instruction B

Condition Flag Example: =

If the Condition Flag is connected directly to the left bus bar, instruction B will be executed based on the execution results of a previous rung if instruction A is not executed. Note Condition Flags are used by all instruction within a single program (task) but they are cleared when the task switches. Therefore execution results in the preceding task will not be reflected later tasks. Since conditions flags are shared by all instructions, make absolutely sure that they do not interfere with each other within a single ladder-diagram program. The following is an example.

33

Precautions
Using Execution Results in N.C. and N.C. Inputs

Section 1-2

The Condition Flags will pick up instruction B execution results as shown in the example below even though the N.C. and N.O. input bits are executed from the same output branch.

Instruction A

Incorrect Use Condition Flag Example: =

Reflects instruction A execution results.

Instruction B

Reflects instruction B execution Condition Flag results. Example: =

Make sure each of the results is picked up once by an OUTPUT instruction to ensure that execution results for instruction B will be not be picked up.
Reflects instruction A execution results.

Instruction A

Correct Use

Condition Flag Example: =

Condition Flag Example: =

Reflects instruction A execution results.

Instruction B

34

Precautions

Section 1-2
Example: The following example will move #200 to D200 if D100 contains #10 and move #300 to D300 if D100 does not contain #10.

#10 D100 Incorrect Use Reflects CMP execution results. (1) #200 D200 Reflects MOV execution results. (2) #300 D300

The Equals Flag will turn ON if D100 in the rung above contains #10. #200 will be moved to D200 for instruction (1), but then the Equals Flag will be turned OFF because the #200 source data is not 0000 hex. The MOV instruction at (2) will then be executed and #300 will be moved to D300. A rung will therefore have to be inserted as shown below to prevent execution results for the first MOVE instruction from being picked up.

#10 Correct Use D100

Reflects CMP execution results.

#200 D200

#300 D300

35

Precautions
Using Execution Results from Differentiated Instructions

Section 1-2

With differentiated instructions, execution results for instructions are reflected in Condition Flags only when execution condition is met, and results for a previous rung (rather than execution results for the differentiated instruction) will be reflected in Condition Flags in the next cycle. You must therefore be aware of what Condition Flags will do in the next cycle if execution results for differentiated instructions to be used. In the following for example, instructions A and B will execute only if execution condition C is met, but the following problem will occur when instruction B picks up execution results from instruction A. If execution condition C remains ON in the next cycle after instruction A was executed, then instruction B will unexpectedly execute (by the execution condition) when the Condition Flag goes from OFF to ON because of results reflected from a previous rung.

Previous rung Incorrect Use

Instruction A

Condition Flag Example: =

Reflects execution results for instruction A when execution condition is met. Reflects execution results for a previous rung in the next cycle.
Instruction B

In this case then, instructions A and B are not differentiated instructions, the DIFU (of DIFD) instruction is used instead as shown below and instructions A and B are both upwardly (or downwardly) differentiated and executed for one cycle only.
Previous rung

Correct Use

Instruction A

Reflects instruction A execution results. Condition Flag Example: = Instruction B

Note

The CP1H CPU Units support instructions to save and load the Condition Flag status (CCS(282) and CCL(283)). These can be used to access the status of the Condition Flags at other locations in a task or in a different task.

36

Precautions Main Conditions Turning ON Condition Flags

Error Flag

Section 1-2

The ER Flag will turn ON under special conditions, such as when operand data for an instruction is incorrect. The instruction will not be executed when the ER Flag turns ON. When the ER Flag is ON, the status of other Condition Flags, such as the <, >, OF, and UF Flags, will not change and status of the = and N Flags will vary from instruction to instruction. Refer to the descriptions of individual instructions in the CP-series CP1H CPU Unit Programming Manual (W451) for the conditions that will cause the ER Flag to turn ON. Caution is required because some instructions will turn OFF the ER Flag regardless of conditions. Note The PLC Setup Settings for when an instruction error occurs determines whether operation will stop when the ER Flag turns ON. In the default setting, operation will continue when the ER Flag turns ON. If Stop Operation is specified when the ER Flag turns ON and operation stops (treated as a program error), the program address at the point where operation stopped will be stored at in A298 to A299. At the same time, A295.08 will turn ON. The Equals Flag is a temporary flag for all instructions except when comparison results are equal (=). It is set automatically by the system, and it will change. The Equals Flag can be turned OFF (ON) by an instruction after a previous instruction has turned it ON (OFF). The Equals Flag will turn ON, for example, when MOV or another move instruction moves 0000 hex as source data and will be OFF at all other times. Even if an instruction turns the Equals Flag ON, the move instruction will execute immediately and the Equals Flag will turn ON or OFF depending on whether the source data for the move instruction is 0000 hex or not. The CY Flag is used in shift instructions, addition and subtraction instructions with carry input, addition and subtraction instruction borrows and carries, as well as with Special I/O Unit instructions, PID instructions, and FPD instructions. Note the following precautions. Note (1) The CY Flag can remain ON (OFF) because of execution results for a certain instruction and then be used in other instruction (an addition and subtraction instruction with carry or a shift instruction). Be sure to clear the Carry Flag when necessary. (2) The CY Flag can be turned ON (OFF) by the execution results for a certain instruction and be turned OFF (ON) by another instruction. Be sure the proper results are reflected in the Carry Flag when using it.

Equals Flag

Carry Flag

Less Than and Greater Than Flags

The < and > Flags are used in comparison instruction, as well as in the LMT, BAND, ZONE, PID and other instructions. The < or > Flag can be turned OFF (ON) by another instruction even if it is turned ON (OFF) by execution results for a certain instruction. The N Flag is turned OFF when the leftmost bit of the instruction execution results word is 1 for certain instructions and it is turned OFF unconditionally for other instruction. With the CP-series PLCs, an instruction will be executed as written even if an operand requiring multiple words is specified so that all of the words for the operand are not in the same area. In this case, words will be taken in order of the PLC memory addresses. The Error Flag will not turn ON.

Negative Flag

Specifying Operands for Multiple Words

37

Precautions

Section 1-2
As an example, consider the results of executing a block transfer with XFER(070) if 20 words are specified for transfer beginning with W500. Here, the Work Area, which ends at W511, will be exceeded, but the instruction will be executed without turning ON the Error Flag. In the PLC memory addresses, the present values for timers are held in memory after the Work Area, and thus for the following instruction, W500 to W511 will be transferred to D0 to D11 and the present values for T0 to T7 will be transferred to D12 to D19. Note For specific PLC memory addresses in CP1H CPU Units, refer to Appendix E: Memory Map in the CP Series CP1H CPU Units Operation Manual (W450). For specific PLC memory addresses in CP1L CPU Units, refer to Appendix E: Memory Map in the CP Series CP1L CPU Units Operation Manual (W462).
W500 to &20 Number of words First source word D0 First destination word W511 to Transferred. D0 to D11 D12 to D19 to

T0 to T7

to

to

1-2-2

Special Program Sections

CP-series programs have special program sections that will control instruction conditions. The following special program sections are available.

Program section Subroutine IL - ILC section Step Ladder section FOR-NEXT loop JMP0 - JME0 section

Instructions SBS, SBN and RET instructions IL and ILC instructions STEP S instructions and STEP instructions FOR instructions and NEXT instructions JMP0 instructions and JME0 instructions

Instruction condition Status Subroutine program is The subroutine program section between executed. SBN and RET instructions is executed. Section is interlocked The output bits are turned OFF and timers are reset. Other instructions will not be executed and previous status will be maintained. Break in progress. Looping Jump Block program is executing. The block program listed in mnemonics between the BPRG and BEND instructions is executed.

Block program section BPRG instructions and BEND instructions

Instruction Combinations
Subroutine Subroutine IL - ILC Step ladder section FOR - NEXT loop JMP0 - JME0 Block program section Not possible. OK Not possible. OK OK OK

The following table shows which of the special instructions can be used inside other program sections.
IL - ILC section Not possible. Not possible. OK OK OK OK Step ladder section Not possible. Not possible. Not possible. Not possible. Not possible. OK FOR - NEXT loop Not possible. OK Not possible. OK Not possible. Not possible. JMP0 - JME0 section Not possible. OK OK OK Not possible. OK Block program section Not possible. Not possible. Not possible. Not possible. Not possible. Not possible.

38

Precautions
Note

Section 1-2
Instructions that specify program areas cannot be used for programs in other tasks. Refer to 2-2-2 Task Instruction Limitations for details. Place all the subroutines together just before the END(001) instruction in all programs but after programming other than subroutines. (Therefore, a subroutine cannot be placed in a step ladder, block program, FOR - NEXT, or JMP0 JME0 section.) If a program other than a subroutine program is placed after a subroutine program (SBN to RET), that program will not be executed.
Program

Subroutines

Subroutine

Program

Subroutine

Instructions Not Available in Subroutines

Note

The following instructions cannot be placed in a subroutine.

Function Process Step Control Mnemonic STEP(008) SNXT(009) Instruction Define step ladder section Step through the step ladder

Block Program Sections A subroutine can include a block program section. If, however, the block program is in WAIT status when execution returns from the subroutine to the main program, the block program section will remain in WAIT status the next time it is called.

Instructions Not Available in Step Ladder Program Sections

Function Sequence Control Mnemonic FOR(512), NEXT(513), and BREAK(514) END(001) IL(002) and ILC(003) JMP(004) and JME(005) CJP(510) and CJPN(511) JMP0(515) and JME0(516) Subroutines SBN(092) and RET(093) Instruction FOR, NEXT, and BREAK LOOP END INTERLOCK and INTERLOCK CLEAR JUMP and JUMP END CONDITIONAL JUMP and CONDITIONAL JUMP NOT MULTIPLE JUMP and MULTIPLE JUMP END SUBROUTINE ENTRY and SUBROUTINE RETURN

39

Precautions
Function Block Programs Mnemonic IF(802) (NOT), ELSE(803), and IEND(804) BPRG(096) and BEND(801) EXIT(806) (NOT) LOOP(809) and LEND(810) (NOT) WAIT(805) (NOT) TIMW(813) and TIMWX(816) TMHW(815) and TMHWX(817) CNTW(814) and CNTWX(818) BPPS(811) and BPRS(812)

Section 1-2
Instruction Branching instructions BLOCK PROGRAM BEGIN/END CONDITIONAL BLOCK EXIT (NOT) Loop control ONE CYCLE WAIT (NOT) TIMER WAIT HIGH-SPEED TIMER WAIT COUNTER WAIT BLOCK PROGRAM PAUSE and RESTART

Note

(1) A step ladder program section can be used in an interlock section (between IL and ILC). The step ladder section will be completely reset when the interlock is ON. (2) A step ladder program section can be used between MULTIPLE JUMP (JMP0) and MULTIPLE JUMP END (JME0).

Instructions Not Supported in Block Program Sections

The following instructions cannot be placed in block program sections.

Classification by Function Sequence Control Mnemonic FOR(512), NEXT(513), and BREAK(514) END(001) IL(002) and ILC(003) Instruction

Sequence Input Sequence Output

Timer/Counter

FOR, NEXT, and BREAK LOOP END INTERLOCK and INTERLOCK CLEAR JMP0(515) and JME0(516) MULTIPLE JUMP and MULTIPLE JUMP END UP(521) CONDITION ON DOWN(522) CONDITION OFF DIFU DIFFERENTIATE UP DIFD DIFFERENTIATE DOWN KEEP KEEP OUT OUTPUT OUT NOT OUTPUT NOT TIM and TIMX(550) TIMER TIMH(015) and HIGH-SPEED TIMER TIMHX(551) TMHH(540) and ONE-MS TIMER TMHHX(552) TTIM(087) and ACCUMULATIVE TIMER TTIMX(555) TIML(542) and LONG TIMER TIMLX(553) MTIM(543) and MULTI-OUTPUT TIMER MTIMX(554) CNT and CNTX(546) COUNTER CNTR(012) and REVERSIBLE COUNTER CNTRX(548)

40

Checking Programs
Classification by Function Subroutines Mnemonic SBN(092) and RET(093)

Section 1-3
Instruction SUBROUTINE ENTRY and SUBROUTINE RETURN SHIFT STEP DEFINE and STEP START PID CONTROL BLOCK PROGRAM BEGIN FAILURE POINT DETECTION Instruction with upward differentiation Instruction with downward differentiation

Data Shift Ladder Step Control Data Control Block Program Damage Diagnosis

SFT STEP(008) and SNXT(009) PID BPRG(096) FPD(269)

Instructions with a differen- @XXX tiation option %XXX

Note

(1) Block programs can be used in a step ladder program section. (2) A block program can be used in an interlock section (between IL and ILC). The block program section will not be executed when the interlock is ON. (3) A block program section can be used between MULTIPLE JUMP (JMP0) and MULTIPLE JUMP END (JME0). (4) A JUMP instruction (JMP) and CONDITIONAL JUMP instruction (CJP/CJPN) can be used in a block program section. JUMP (JMP) and JUMP END (JME) instructions, as well as CONDITIONAL JUMP (CJP/CJPN) and JUMP END (JME) instructions cannot be used in the block program section unless they are used in pairs. The program will not execute properly unless these instructions are paired.

1-3

Checking Programs
CP-series programs can be checked at the following stages. Input check during CX-Programmer input and other operations Program check by CX-Programmer Instruction check during execution Fatal error check (program errors) during execution

1-3-1

CX-Programmer
The program will be automatically checked by the CX-Programmer at the following times.
Timing When inputting ladder diagrams When loading files Checked contents Instruction inputs, operand inputs, programming patterns

All operands for all instructions and all programming patterns When downloading files Models supported by the CP Series and all operands for all instructions During online editing Capacity, etc.

The results of checking are output to the text tab of the Output Window. Also, the left bus bar of illegal program sections will be displayed in red in ladder view.

41

Checking Programs

Section 1-3

1-3-2

Program Checks with the CX-Programmer

The errors that are detected by the program check provided by the CX-Programmer are listed in the following table. The CX-Programmer does not check range errors for indirectly addressed operands in instructions. Indirect addressing errors will be detected in the program execution check and the ER Flag will turn ON, as described in the next section. Refer to individual instruction descriptions for details. When the program is checked on the CX-Programmer, the operator can specify program check levels A, B, and C (in order of the seriousness of the error), as well as a custom check level.
Area Illegal data: Ladder diagramming Check Instruction locations I/O lines Connections Instruction and operation completeness Instructions and operands supported by PLC Instruction variations (NOT, !, @, and %) Object code integrity Operand area ranges Operand data types Access check for read-only words Operand range checks, including the following. Constants (#, &, +, ) Control codes Area boundary checks for multi-word operands Size relationship checks for multi-word operands Operand range overlaps Multi-word allocations Double-length operands Area boundary checks for offsets Number of steps Overall capacity Number of tasks Call check for paired instructions ILILC JMPJME, CJP/CJPNJME SBSSBNRET, MCROSBNRET STEPSNXT BPRGBEND IFIEND LOOPLEND Restricted programming locations for BPRGBEND Restricted programming locations for SBNRET Restricted programming locations for STEPSNXT Restricted programming locations for FORNEXT Restricted programming locations for interrupt tasks Illegal nesting END(001) instruction Number consistency Stack overflows

Instruction support by PLC Operand ranges

Program capacity for PLC Syntax

Ladder diagram structure

42

Checking Programs
Area Output duplication (See note.)

Section 1-3
Check Duplicate output check By bit By word Timer/counter instructions Long words (2-word and 4-word) Multiple allocated words Start/end ranges FAL numbers Instructions with multiple output operands Check for tasks set for starting at beginning of operation Task program allocation

Tasks

Note Multi-word Operands

Output duplication is not checked between tasks, only within individual tasks. Memory area boundaries are checked for multi-word operands for the program check as shown in the following table.
Check items The following functionality is provided by the CX-Programmer for multi-word operands that exceed a memory area boundary. The program cannot be transferred to the CPU Unit. The program also cannot be read from the CPU Unit. Compiling errors are generated for the program check. Warnings will appear on-screen during offline programming. Warnings will appear on-screen during online editing in PROGRAM or MONITOR mode.

1-3-3

Program Execution Check

Operand and instruction location checks are performed on instructions during input and during program checks from the CX-Programmer. These are not, however, final checks. The following checks are performed during instruction execution.

Type of error 1. Instruction Processing Error

Flag that turns ON for error ER Flag Note The Instruction Processing Error Flag (A295.08) will also turn ON if Stop Operation is specified when an error occurs. AER Flag Note The Access Error Flag (A295.10) will turn ON if Stop Operation is specified when an error occurs.

Stop/Continue operation A setting in the PLC Setup can be used to specify whether to stop or continue operation for instruction processing errors. The default is to continue operation. A program error will be generated and operation will stop only if Stop Operation is specified. A setting in the PLC Setup can be used to specify whether to stop or continue operation for instruction processing errors. The default is to continue operation. A program error will be generated and operation will stop only if Stop Operation is specified. Fatal (program error)

2. Access Error

3. Illegal Instruction Error 4. UM (User Memory) Overflow Error

Illegal Instruction Error Flag (A295.14) UM Overflow Error Flag (A295.15) Fatal (program error)

Instruction Processing Errors

An instruction processing error will occur if incorrect data was provided when executing an instruction or an attempt was made to execute an instruction outside of a task. Here, data required at the beginning of instruction processing was checked and as a result, the instruction was not executed, the ER Flag (Error Flag) will be turned ON and the EQ and N Flags may be retained or turned OFF depending upon the instruction.

43

Checking Programs

Section 1-3
The ER Flag (error Flag) will turn OFF if the instruction (excluding input instructions) ends normally. Conditions that turn ON the ER Flag will vary with individual instructions. See descriptions of individual instructions in for details. If Instruction Errors are set to Stop Operation in the PLC Setup, then operation will stop (fatal error) and the Instruction Processing Error Flag (A295.08) will turn ON if an instruction processing error occurs and the ER Flag turns ON.

Illegal Access Errors

Illegal access errors indicate that the wrong area was accessed in one of the following ways when the address specifying the instruction operand was accessed. 1. A read or write was executed for a parameter area. 2. A write was executed in a memory area that is not mounted (See note.). 3. A write was executed in a read-only area. 4. The value specified in an indirect DM address in BCD mode was not BCD (e.g., *D1 contains #A000). Note An IR register containing the internal memory address of a bit is used as a word address or an IR containing the internal memory address of a word is used as a bit address.

1,2,3...

Instruction processing will continue and the Error Flag (ER Flag) will not turn ON if an access error occurs, but the Access Error Flag (AER Flag) will turn ON. If Instruction Errors are set to Stop Operation in the PLC Setup, then operation will stop (fatal error) and the Illegal Access Error Flag (A295.10) will turn ON if an illegal access error occurs and the AER Flag turns ON. Note The Access Error Flag (AER Flag) will not be cleared after a task is executed. If Instruction Errors are set to Continue Operation, this Flag can be monitored until just before the END(001) instruction to see if an illegal access error has occurred in the task program. (The status of the final AER Flag after the entire user program has been executed will be monitored if the AER Flag is monitored on the CX-Programmer.)

Other Errors
Illegal Instruction Errors Illegal instruction errors indicate that an attempt was made to execute instruction data other than that defined in the system. This error will normally not occur as long as the program is created on a the CX-Programmer. In the rare even that this error does occur, it will be treated as a program error, operation will stop (fatal error), and the Illegal Instruction Flag (A295.14) will turn ON. UM (User Memory) Overflow Errors UM overflow errors indicate that an attempt was made to execute instruction data stored beyond the last address in the user memory (UM) defined as program storage area. This error will normally not occur as long as the program is created on the CX-Programmer. In the rare even that this error does occur, it will be treated as a program error, operation will stop (fatal error), and the UM Overflow Flag (A295.15) will turn ON.

44

Checking Programs

Section 1-3

1-3-4

Checking Fatal Errors

The following errors are fatal program errors and the CPU Unit will stop running if one of these occurs. When operation is stopped by a program error, the task number where operation stopped will be stored in A294 and the program address will be stored in A298/A299. The cause of the program error can be determined from this information.

Address A294

Description The type of task and the task number at the point where operation stopped will be stored here if operation stops due to a program error.

Stored Data Cyclic task: 0000 to 001F hex (cyclic tasks 0 to 31) Interrupt task: 8000 to 80FF hex (interrupt tasks 0 to 255)

A298/A299

Note FFFF hex will be stored if there are no active cyclic tasks in a cycle, i.e., if there are no cyclic tasks to be executed. The program address at the point where opera- A298: Rightmost portion of program address A299: Leftmost portion of program address tion stopped will be stored here in binary if operation stops due to a program error. Note If the END(001) instruction is missing (A295.11 will be ON), the address where END(001) was expected will be stored. Note If there is a task execution error (A295.12 will be ON), FFFFFFFF hex will be stored in A298/A299.

Note

If the Error Flag or Access Error Flag turns ON, it will be treated as a program error and it can be used to stop the CPU from running. Specify operation for program errors in the PLC Setup.
Description An END instruction is not present in the program. No task is ready in the cycle. No program is allocated to a task. The corresponding interrupt task number is not present even though the execution condition for the interrupt task was met. The wrong data values were provided in the operand when an attempt was made to execute an instruction. Related flags The No END Flag (A295.11) turns ON. The Task Error Flag (295.12) turns ON.

Program error No END Instruction Error During Task Execution

The ER Flag turns ON and the Instruction Processing Error Flag (A295.08) turns ON if Stop Operation set for Instruction Errors in PLC Setup. Illegal Access Error (AER Flag ON) A read or write was executed for a parame- AER Flag turns ON and the Illegal and Stop Operation set for Instruc- ter area. Access Error Flag (A295.10) turns ON tion Errors in PLC Setup if Stop Operation set for Instruction A write was executed in a memory area Errors in PLC Setup that is not mounted. A write was executed in a read-only area. The value specified in an indirect DM address in BCD mode was not BCD. The value specified in an indirect DM address in BCD mode is not BCD.

Instruction Processing Error (ER Flag ON) and Stop Operation set for Instruction Errors in PLC Setup

Indirect DM BCD Error and Stop Operation set for Instruction Errors in PLC Setup Differentiation Address Overflow Error

During online editing, more than 131,072 differentiated instructions have been inserted or deleted.

AER Flag turns ON and the DM Indirect BCD Error Flag (A295.09) turns ON if Stop Operation set for Instruction Errors in PLC Setup The Differentiation Overflow Error Flag (A295.13) turns ON.

45

Introducing Function Blocks

Program error UM (User Memory) Overflow Error

Section 1-4
Description Related flags An attempt was made to execute instrucThe UM (User Memory) Overflow Flag tion data stored beyond the last address in (A295.5) turns ON. user memory (UM) defined as program storage area. An attempt was made to execute an instruction that cannot be executed. The Illegal Instruction Flag (A295.14) turns ON.

Illegal Instruction Error

1-4

Introducing Function Blocks

Function blocks can be used with CP-series CPU Units. Refer to the CX-Programmer Ver. 7.0 Operation Manual Function Blocks (W447) for details on actually using function blocks.

1-4-1

Overview and Features

Function blocks conforming to the IEC 61131-3 standard can be used with CX-Programmer Ver. 5.0 and higher. These function blocks are supported by CS/CJ-series CPU Units with unit version 3.0 or later and by CP-series CPU Units. The following features are supported. User-defined processes can be converted to block format by using function blocks. Function block algorithms can be written in the ladder programming language or in the structured text (ST) language. (See note.) When ladder programming is used, ladder programs created with nonCX-Programmer Ver. 4.0 or earlier can be reused by copying and pasting. When ST language is used, it is easy to program mathematical processes that would be difficult to enter with ladder programming. Note The ST language is an advanced language for industrial control (primarily Programmable Logic Controllers) that is described in IEC 61131-3. The ST language supported by CX-Programmer conforms to the IEC 61131-3 standard.

Function blocks can be created easily because variables do not have to be declared in text. They are registered in variable tables. A variable can be registered automatically when it is entered in a ladder or ST program. Registered variables can also be entered in ladder programs after they have been registered in the variable table. A single function block can be converted to a library function as a single file, making it easy to reuse function blocks for standard processing. A program check can be performed on a single function block to easily confirm the function blocks reliability as a library function. Programs containing function blocks (ladder programming language or structured text (ST) language) can be downloaded or uploaded in the same way as standard programs that do not contain function blocks. Tasks containing function blocks, however, cannot be downloaded in task units (uploading is possible). One-dimensional array variables are supported, so data handling is easier for many applications.

46

Introducing Function Blocks

Note

Section 1-4
The IEC 61131 standard was defined by the International Electrotechnical Commission (IEC) as an international programmable logic controller (PLC) standard. The standard is divided into 7 parts. Specifications related to PLC programming are defined in Part 3 Textual Languages (IEC 61131-3).

A function block (ladder programming language or structured text (ST) language) can be called from another function block (ladder programming language or structured text (ST) language). Function blocks can be nested up to 8 levels and ladder/ST language function blocks can be combined freely.

1-4-2

Function Block Specifications

For specifications that are not listed in the following table, refer to the CX-Programmer Ver. 7.0 Operation Manual Function Blocks (W447).

Item Model number Setup disk Compatible CPU Units

Compatible computers

Computer CPU OS Memory

Hard disk space Monitor CD-ROM drive COM port

Specifications WS02-CXPC1-E-V6 CD-ROM CP-series CPU Units with unit version 1.0 or later CS/CJ-series CS1-H, CJ1-H, and CJ1M CPU Units with unit version 3.0 or later are compatible. Device Type CPU Type CS1G-H CS1G-CPU42H/43H/44H/45H CS1H-H CS1H-CPU63H/64H/65H/66H/67H CJ1G-H CJ1G-CPU42H/43H/44H/45H CJ1H-H CJ1H-CPU65H/66H/67H CJ1M CJ1M-CPU11/12/13/21/22/23 CS/CJ/CP Series Function Restrictions Instructions Not Supported in Function Block Definitions Block Program Instructions (BPRG and BEND), Subroutine Instructions (SBS, GSBS, RET, MCRO, and SBN), Jump Instructions (JMP, CJP, and CJPN), Step Ladder Instructions (STEP and SNXT), Immediate Refresh Instructions (!), I/O REFRESH (IORF), ONE-MS TIMER (TMHH). IBM PC/AT or compatible 133 MHz Pentium or faster with Windows 98, 98SE, or NT 4.0 (with service pack 6 or higher) Microsoft Windows 95, 98, 98SE, Me, 2000, XP, or NT 4.0 (with service pack 6 or higher) 64 Mbytes min. with Windows 98, 98SE, or NT 4.0 (with service pack 6 or higher) Refer to the CX-Programmer Ver. 7.0 Operation Manual (W437) for details. 100 Mbytes min. available disk space SVGA (800 600 pixels) min. Note Use small font for the font size. One CD-ROM drive min. One RS-232C port min.

Note

The structured text (ST language) conforms to the IEC 61131-3 standard, but CX-Programmer Ver. 5.0 supports only assignment statements, selection statements (CASE and IF statements), iteration statements (FOR, WHILE, REPEAT, and EXIT statements), RETURN statements, arithmetic operators, logical operators, comparison functions, numeric functions, and comments.

47

Introducing Function Blocks

Section 1-4

1-4-3

Files Created with CX-Programmer

Projects created using CX-Programmer that contain function block definitions and projects with instances are saved in the same standard project files (*.cxp). The following diagram shows the contents of a project. The function block definitions are created at the same directory level as the program within the relevant PLC directory.
Project file (.cxp) PLC1 Global symbol table I/O table PLC Setup PLC memory table Program (with rung comments) Local symbol table Section 1 (with instances) Section 2 (with instances) END section (with instances) Function block definitions
FunctionBlock1 FunctionBlock2

Project Files (*.cxp)

PLC2

Instances created in program sections.

Each function block can be stored in a separate definition file (.cxf).

Function Block Library Files (*.cxf) Note Project Text Files Containing Function Blocks (*.cxt)

A function block definition created in a project with CX-Programmer can be saved as a file (1 definition = 1 file), enabling definitions to be loaded into other programs and reused. When function blocks are nested, all of the nested (destination) function block definitions are included in this function block library file (.cxf). Data equivalent to that in project files created with CX-Programmer (*.cxp) can be saved as CXT text files (*.cxt).

48

SECTION 2 Tasks
This section describes the operation of tasks and how to use tasks in programming. 2-1 Programming with Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1-1 2-1-2 2-1-3 2-1-4 2-1-5 2-1-6 2-1-7 2-2 2-2-1 2-2-2 2-2-3 2-2-4 2-2-5 2-2-6 2-3 2-3-1 2-3-2 2-3-3 2-4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tasks and Programs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic CPU Unit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Task Execution Conditions and Settings . . . . . . . . . . . . . . . . . . . . . Cyclic Task Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TASK ON and TASK OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Task Instruction Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flags Related to Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples of Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designing Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Subroutine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of Interrupt Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Task Flags and Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 50 52 53 54 56 56 57 58 58 61 62 65 66 68 68 68 73 74 75

Using Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CX-Programmer Operations for Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

49

Programming with Tasks

Section 2-1

2-1
2-1-1

Programming with Tasks

Overview
CP-series CPU Unit control operations can be divided by functions, controlled devices, processes, developers, or any other criteria and each operation can be programmed in a separate unit called a task. Using tasks provides the following advantages: 1,2,3... 1. Programs can be developed simultaneously by several people. Individually designed program parts can be assembled with very little effort into a single user program. 2. Programs can be standardized in modules. More specifically, the following the CX-Programmer functions will be combined to develop programs that are standalone standard modules rather than programs designed for specific systems (machines, devices). This means that programs developed separately by several people can be readily combine. Programming using symbols Global and local designation of symbols Automatic allocation of local symbols to addresses 3. Improved overall response. Overall response is improved because the system is divided into an overall control program as well as individual control programs, and only specific programs will be executed as needed. 4. Easy revision and debugging. Debugging is much more efficient because tasks can be developed separately by several people, and then revised and debugged by individual task. Maintenance is simple because only the task that needs revising will be changed in order to make specification or other changes. Debugging is more efficient because it is easy to determine whether an address is specific or global and addresses between programs only need to be checked once during debugging because symbols are designated globally or locally and local symbols are allocated automatically to addresses through the CX-Programmer. 5. Easy to switch programs. A task control instruction in the program can be used to execute productspecific tasks (programs) when changing operation is necessary. 6. Easily understood user programs. Programs are structured in blocks that make the programs much simpler to understand for sections that would conventionally be handled with instructions like jump.

50

Programming with Tasks

Earlier system CP1H Task 1 One continuous subprogram

Section 2-1

Allocation

Task 2

Tasks can be put into nonexecuting (standby) status.

Program development and debugging is possible by more than one person.

Task 3

I/O refreshing I/O refreshing

Note

Unlike earlier programs that can be compared to reading a scroll, tasks can be compared to reading through a series of individual cards. All cards are read in a preset sequence starting from the lowest number. All cards are designated as either active or inactive, and cards that are inactive will be skipped. (Cards are activated or deactivated by task control instructions.) A card that is activated will remain activated and will be read in subsequent sequences. A card that is deactivated will remain deactivated and will be skipped until it is reactivated by another card.

51

Programming with Tasks

Section 2-1

2-1-2

Tasks and Programs

Up to 288 programs (tasks) can be controlled. Individual programs are allocated 1:1 to tasks. Tasks are broadly grouped into the following types: Cyclic tasks Interrupt tasks Each program allocated to a task is executed independently and must end with an END(001) instruction. I/O refreshing will be executed only after all task programs in a cycle have been executed.
Program A

Cyclic task 0

Allocation Interrupt condition goes into effect

Interrupt task 100

Program B

Cyclic task 1

Allocation

Program C Allocation

Cyclic task n Allocation I/O refreshing

Program D

52

Programming with Tasks

Section 2-1

2-1-3

Basic CPU Unit Operation

The CPU Unit will execute cyclic tasks starting at the task with the lowest number. It will also interrupt cyclic task execution to execute an interrupt task if an interrupt occurs.

Cyclic task 0

Executed in order starting at the lowest number. Cyclic task 1 Interrupt occurs.

Interrupt task 5

Cyclic task n

I/O refresh

Peripheral processing

Note

All Condition Flags (ER, CY, Equals, AER, etc.) and instruction conditions (interlock ON, etc.) will be cleared at the beginning of a task. Therefore Condition Flags cannot be read nor can INTERLOCK/INTERLOCK CLEAR (IL/ILC) instructions, JUMP/JUMP END (JMP/JME) instructions, or SUBROUTINE CALL/SUBROUTINE ENTRY (SBS/SBN) instructions be split between two tasks. Interrupt task can be executed as cyclic tasks by starting them with TKON. These are called extra cyclic tasks. Extra cyclic tasks (interrupt task numbers 0 to 255) are executed starting at the lowest task number after execution of the normal cyclic task (celiac task numbers 0 to 31) has been completed.

53

Programming with Tasks

Section 2-1

Cyclic task 0

Executed in order starting at lowest number of the cyclic tasks.

END

Normal cyclic tasks Cyclic task n

END

Extra cyclic task 0

END

Executed in order starting at lowest number of the extra cyclic tasks. Extra cyclic tasks Extra cyclic task m

END

I/O refresh Peripheral processing

2-1-4

Types of Tasks
Tasks are broadly classified as either cyclic tasks or interrupt tasks. Interrupt tasks are further divided into scheduled, input, high-speed counter, and external interrupt tasks. Interrupt tasks can also be executed as extra cyclic tasks.

Cyclic Tasks

A cyclic task that is READY will be executed once each cycle (from the top of the program until the END(001) instruction) in numerical order starting at the task with the lowest number. The maximum number of cyclic tasks is 32. (Cyclic task numbers: 00 to 31). An interrupt task will be executed if an interrupt occurs even if a cyclic task (including extra cyclic tasks) is currently being executed. The interrupt task will be executed using any time in the cycle, including during user program execution, I/O refreshing, or peripheral servicing, when the execution condition for the interrupt is met. Interrupt tasks can also be executed as extra cyclic tasks.

Interrupt Tasks

54

Programming with Tasks

Input Interrupts (Direct Mode and Counter Mode)

Section 2-1
An interrupt task can be executed each time one of the built-in inputs on the CPU Unit turns ON or OFF (Direct Mode) or when a specified number of inputs has been counted (Count Mode).
CP1H CP1L CPU Unit model X or XA Y M (30 or 40 I/O points) L (20 I/O points) L (14 I/O points) Number of tasks 8 tasks max. 6 tasks max. 6 tasks max. 6 tasks max. 4 tasks max. Interrupt task numbers 140 to 147 140 to 145 140 to 145 140 to 145 140 to 143

Scheduled Interrupt Tasks

A scheduled interrupt task will be executed at a fixed interval based on the internal timer of the CPU Unit. Only one scheduled interrupt tasks can be used (interrupt task number:2). Pulse inputs to a built-in high-speed counter in the CPU Unit can be counted to trigger execution of an interrupt. A user-specified interrupt task (interrupt task numbers 0 to 255) can be executed when an external interrupt occurs. The interrupt task will be executed when requested by a user program running in a CJ-series Special I/O Unit or CJ-series CPU Bus Unit. Up to 256 external interrupt tasks can be used (interrupt task numbers: 0 to 255). If an external interrupt task has the same number as scheduled, input, or high-speed counter interrupt task, the interrupt task will be executed for either condition (the two conditions will operate with OR logic) but basically task numbers should not be duplicated.

High-speed Counter Interrupts External Interrupt Tasks (CP1H CPU Units)

Extra Cyclic Tasks

An interrupt tasks can be executed every cycle, just like the normal cyclic tasks. Extra cyclic tasks (interrupt task numbers 0 to 255) are executed starting at the lowest task number after execution of the normal cyclic task (cyclic task numbers 0 to 31) has been completed. The maximum number of extra cyclic tasks is 256 (Interrupt task numbers: 0 to 255). Cycle interrupt tasks, however, are different from normal cyclic tasks in that they are started with TKON(820), i.e., they cannot be started automatically at startup. If an extra cyclic task has the same number as a scheduled, input, or highspeed counter interrupt task, the interrupt task will be executed for either condition (the two conditions will operate with OR logic). Do not use interrupt tasks both as normal interrupt tasks and as extra cyclic tasks.

Note

(1) Also, TKON(820) and TKOF(821) cannot be used in extra cyclic tasks, meaning that normal cyclic tasks and other extra cyclic tasks cannot be controlled from within an extra cyclic task. (2) The differences between normal cyclic tasks and extra cyclic tasks are listed in the following table.
Item Activating at startup Using TKON(820) and TKOF(821) inside task Task Flags Extra cyclic tasks Not supported. Not supported. Normal cyclic tasks Supported. (Set from CXProgrammer.) Supported.

Not supported.

Supported. (Cyclic task numbers 00 to 31 correspond to Task Flags TK00 to TK31.)

55

Programming with Tasks

Item Extra cyclic tasks

Section 2-1
Normal cyclic tasks Supported.

Initial Task Execution Not supported. Flag (A200.15) and Task Start Flag (A200.14) Index (IR) and data Not defined when task is (DR) register values started (same as normal interrupt tasks). Values at the beginning of each cycle are undefined. Always set values before using them. Values set in the previous cycle cannot be read.

Undefined at the beginning of operation. Values set in the previous cycle can be read.

2-1-5

Task Execution Conditions and Settings

The following table describes task execution conditions, related settings, and status.

Task Cyclic tasks

Execution condition Related Setting Executed once each cycle if READY None (set to start initially or started with the TKON(820)instruction) when the right to execute is obtained. Interrupt Scheduled Interrupt task 2 Executed once every time the preset The scheduled interrupt time is set tasks interrupt task 0 period elapses according to the inter- (0 to 9999) through the SET INTERnal timer of CPU Unit. RUPT MASK instruction (MSKS(690)). Scheduled interrupt unit (10 ms, 1.0 ms, or 0.1 ms) is set in PLC Setup. Masks for designated inputs are Input interrupt Interrupt tasks Executed when the corresponding canceled through the SET INTERtasks 0 to 7 140 to 147 CPU Unit built-in input turns ON or RUPT MASK instruction turns OFF. (MSKS(690)). Interrupt tasks Executed when corresponding target High-speed 0 to 255 or range comparison condition is met counter interfor CPU Unit built-in high-speed rupt tasks counter. External inter- Interrupt tasks Executed when requested by a user None (always enabled) 0 to 255 program in a Special I/O Unit or CPU rupt tasks Bus Unit. (CP1H only) Extra cyclic tasks 0 to 255 Interrupt tasks Executed once each cycle if READY None (always enabled) 0 to 255 (started with the TKON(820) instruction) when the right to execute is obtained.

No. 0 to 31

2-1-6

Cyclic Task Status

This section describes cyclic task status, including extra cyclic tasks. Cyclic tasks always have one of four statuses: Disabled, READY, RUN (executable), and standby (WAIT).

Disabled Status (INI)

A task with Disabled status is not executed. All cyclic tasks have Disabled status in PROGRAM mode. Any cycle task that shifted from this to another status cannot return to this status without returning to PROGRAM mode. A task attribute can be set to control when the task will go to READY status. The attribute can be set to either activate the task using the TASK ON instruction or when RUN operation is started.

READY Status

56

Programming with Tasks

Instruction-activated Tasks Operation-activated Tasks

Section 2-1
A TASK ON instruction (TKON(820)) is used to switch an instruction-activated cyclic task from Disabled status or Standby status to READY status. An operation-activated cyclic task will switch from Disabled status to READY status when the operating mode is changed from PROGRAM to RUN or MONITOR mode. This applies only to normal cyclic tasks. The CX-Programmer can be used to set one or more tasks to go to READY status when operation is started for task numbers 0 through 31. The setting, however, is not possible with extra cyclic tasks. A cyclic task that is READY will switch to RUN status and be executed when the task obtains the right to execute. A TASK OFF (TKOF(821)) instruction can be used to change a cyclic task from Disabled status to Standby status.

Note

RUN Status Standby Status

Note

The task programs for CP-series PLCs can be monitored online from the CXProgrammer to see if they are executing or stopped. The status indications on the CX-Programmer are as follows: Running: The task is in READY or RUN status. (There is no way to tell the difference between these.) Stopped: The task is in INI or WAIT status. (There is no way to tell the difference between these.)

2-1-7

Status Transitions
Activated at the start of operation (See note 1.) or the TKON(820) instruction INI (Disabled) status READY status Executed TKON(820) instruction TKOF(821) instruction (See note 2.) Right to execute obtained. RUN status

Standby status

Note

(1) Activation at the start of operation is possible for normal cyclic tasks only. It is not possible for extra cyclic tasks. (2) A task in RUN status will be put into Standby status by the TKOF(821) instruction even when the TKOF(821) instruction is executed within that task. Standby status functions exactly the same way as a jump (JMP-JME). Output status for the Standby task will be maintained.

Standby status

Jump

57

Using Tasks

Section 2-2
Instructions will not be executed in Standby status, so instruction execution time will not be increased. Programming that does not need to be executed all the time can be made into tasks and assigned Standby status to reduce cycle time.

Conventional program

Reduced cycle time Task

Executes under set conditions

All instructions will be executed unless jumps or other functions are used.

Executes under set conditions

Note

Standby status simply means that a task will be skipped during task execution. Changing to Standby status will not end the program.

2-2
2-2-1

Using Tasks
TASK ON and TASK OFF
The TASK ON (TKON(820)) and TASK OFF (TKOF(821)) instructions switch a cyclic task (including extra cyclic tasks) between READY and Standby status from a program.
N: Task No. A task will go to READY status when the execution condition is ON, and the corresponding Task Flag will turn ON.

N: Task No.

A task will go to Standby status when the execution condition is ON, and the corresponding Task Flag will turn OFF.

The TASK ON and TASK OFF instructions can be used to change any cyclic task (including extra cyclic tasks) between READY and Standby status at any time. A cyclic task that is in READY status will maintain that status in subsequent cycles, and a cyclic task that is in Standby status will maintain that status in subsequent cycles. The TASK ON and TASK OFF instructions can be used only within cyclic tasks and not within interrupt tasks.

58

Using Tasks
Note

Section 2-2
At least one cyclic task must be in READY status in each cycle. If there is not cyclic task in READY status, the Task Error Flag (A295.12) will turn ON, and the CPU Unit will stop running.

Example: Cyclic Task Cyclic task 0 (READY status at the start of operation)

Cyclic task 1

Cyclic task 2

Cyclic task 3

1) Task 0 will be in READY status at the start of operation. Other tasks will remain in Disabled status.

Cyclic task 0

2) Task 1 will go to READY status if A is Cyclic task 0 ON, and tasks 2 and 3 will remain on Disabled status.
Cyclic task 1

3) Task 0 will go to Cyclic task 0 Standby status if D is ON. Other tasks will remain in their current status.
Cyclic task 1

Cyclic task 1

Cyclic task 2

Cyclic task 2

Cyclic task 2

Cyclic task 3

Cyclic task 3

Cyclic task 3

READY status

Standby status/Disabled status

Tasks and the Execution Cycle

A cyclic task (including an extra cyclic task) that is in READY status will maintain that status in subsequent cycles.

Cyclic task 1 TKON(820) Cyclic task 2

READY status at the start of operation READY status

Cyclic task 1

READY status

Cyclic task 2

READY status

59

Using Tasks

Section 2-2
A cyclic task that is in Standby status will maintain that status in subsequent cycles. The task will have to be activated using the TKON(820) instruction in order to switch from Standby to READY status.

Cyclic task 1 TKOF(821) TKON (820) Cyclic task 2

Standby status

Cyclic task 1

Standby status

RUN status

Cyclic task 2

RUN status

If a TKOF(821) instruction is executed for the task it is in, the task will stop being executed where the instruction is executed, and the task will shift to Standby status.
Task 2

Task execution will stop here and the task will shift to Standby status.

Cyclic Task Numbers and the Execution Cycle (Including Extra Cyclic Tasks)

If task m turns ON task n and m > n, task n will go to READY status the next cycle. Example: If task 5 turns ON task 2, task 2 will go to READY status the next cycle. If task m turns ON task n and m < n, task n will go to READY status the same cycle. Example: If task 2 turns ON task 5, task 5 will go to READY status in the same cycle. If task m places task n in Standby status and m > n, will go to Standby status the next cycle. Example: If task 5 places task 2 in Standby status, task 2 will go to Standby status the next cycle. If task m places task n in Standby status and m < n, task n will go to Standby status in the same cycle. Example: If task 2 places task 5 in Standby status, task 5 will go to Standby status in the same cycle.

Relationship of Tasks to I/O Memory

There are two different ways to use Index Registers (IR) and Data Registers (DR): 1) Independently by task or 2) Shared by all task. With independent registers, IR0 used by cyclic task 1 for example is different from IR0 used by cyclic task 2. With shared registers, IR0 used by cyclic task 1 for example is the same as IR0 used by cyclic task 2. The setting that determines if registers are independent or shared is made from the CX-Programmer.

60

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Section 2-2
Other words and bits in I/O Memory are shared by all tasks. CIO 10.00 for example is the same bit for both cyclic task 1 and cyclic task 2. Therefore, be very careful in programming any time I/O memory areas other than the IR and DR Areas are used because values changed with one task will be used by other tasks.
I/O memory Relationship to tasks CIO, Auxiliary, Data Memory and all other Shared with other tasks. memory areas except the IR and DR Areas. Index registers (IR) and data registers (DR) Used separately for each task. (See note.)

Note

IR and DR values are not set when interrupt tasks (including extra cyclic tasks) are started. If IR and DR are used in an interrupt task, these values must be set by the MOVR/MOVRW (MOVE TO REGISTER and MOVE TIMER/COUNTER PV TO REGISTER) instructions within the interrupt task. After the interrupt task has been executed, IR and DR will return to their values prior to the interrupt automatically.

Relationship of Tasks to Timer Operation

Timer present values for TIM, TIMX, TIMH, TIMHX, TMHH, TMHHX, TIMW, TIMWX, TMHW, and TMHWX programmed for timer numbers T0000 to T0015 will be updated even if the task is switched or if the task containing the timer is changed to Standby status or back to READY status. If the task containing TIM goes to Standby status and is the returned to READY status, the Completion Flag will be turned ON if the TIM instruction is executed when the present value is 0. (Completion Flags for timers are updated only when the instruction is executed.) If the TIM instruction is executed when the present value is not yet 0, the present value will continue to be updated just as it was while the task was in READY status. The present values for timers programmed with timer numbers T0016 to T4095 will be maintained when the task is in Standby status.

Relationship of Tasks to Condition Flags

All Condition Flags will be cleared before execution of each task. Therefore Condition Flag status at the end of task 1 cannot be read in task 2. CCS(282) and CCL(283) can be used to read Condition Flag status from another part of the program, e.g., from another task.

2-2-2

Task Instruction Limitations

The following instructions must be placed within the same task. Any attempt to split instructions between two tasks will cause the ER Flag to turn ON and the instructions will not be executed.
Mnemonic JMP/JME CJP/JME CJPN/JME JMP0/JME0 FOR/NEXT IL/ILC SBS/SBN/RET MCRO/SBN/RET BPRG/BEND STEP /SNXT Instruction JUMP/JUMP END CONDITIONAL JUMP/JUMP END CONDITIONAL JUMP NOT/CONDITIONAL JUMP END MULTIPLE JUMP/JUMP END FOR/NEXT INTERLOCK/INTERLOCK CLEAR SUBROUTINE CALL/SUBROUTINE ENTRY/SUBROUTINE RETURN MACRO/SUBROUTINE ENTRY/SUBROUTINE RETURN BLOCK PROGRAM BEGIN/BLOCK PROGRAM END STEP DEFINE

Instructions Required in the Same Task

61

Using Tasks Instructions Not Allowed in Interrupt Tasks

Section 2-2
The following instructions cannot be placed in interrupt tasks. Any attempt to execute one of these instructions in an interrupt task will cause the ER Flag to turn ON and the instruction will not be executed.The following instructions can be used if an interrupt task is being used as an extra task.
Mnemonic TKON(820) TKOF(821) STEP SNXT STUP DI EI Instruction TASK ON TASK OFF STEP DEFINE STEP NEXT CHANGE SERIAL PORT SETUP DISABLE INTERRUPT ENABLE INTERRUPT

The operation of the following instructions is unpredictable in an interrupt task: TIMER: TIM and TIMX(550), HIGH-SPEED TIMER: TIMH(015) and TIMHX(551), ONE-MS TIMER: TMHH(540) and TMHHX(552), ACCUMULATIVE TIMER: TTIM(087) and TTIMX(555), MULTIPLE OUTPUT TIMER: MTIM(543) and MTIMX(554), LONG TIMER: TIML(542) and TIMLX(553), TIMER WAIT: TIMW(813) and TIMWX(816), HIGH-SPEED TIMER WAIT: TMHW(815) and TMHWX(817), PID CONTROL: PID(190), FAILURE POINT DETECTION: FPD(269), and CHANGE SERIAL PORT SETUP: STUP(237).

2-2-3

Flags Related to Tasks

The following flag work only for normal cyclic tasks. They do not work for extra cyclic tasks. A Task Flag is turned ON when a cyclic task in READY status and is turned OFF when the task is in Disabled (INI) or in Standby (WAIT) status. Task numbers 00 to 31 correspond to Task Flags TK00 to TK31.
Task 3 Disabled Cycle READY Cycle READY Cycle Standby

Flags Related to Cyclic Tasks

Task Flags (TK00 to TK31)

Task Flag for task 3

Note

Task Flags are used only with cyclic tasks and not with interrupt tasks. With an interrupt task, A441.15 will turn ON if an interrupt task executes after the start of operation, and the number of the interrupt task that required for maximum processing time will be stored in two-digit hexadecimal in A441.00 to A441.07. The Initial Task Execution Flag will turn ON when cyclic tasks shift from Disabled (INI) to READY status, the tasks obtain the right to execute, and the tasks are executed the first time. It will turn OFF when the first execution of the tasks has been completed.
Ready Task n Initial Task Execution Flag Disabled Disabled Ready

Initial Task Execution Flag (A200.15)

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Using Tasks

Section 2-2
The Initial Task Execution Flag tells whether or not the cyclic tasks are being executed for the first time. This flag can thus be used to perform initialization processing within the tasks.
Initial Task Execution Flag
A200.15

Initializing processing

Note

Even though a Standby cyclic task is shifted back to READY status through the TKON(820) instruction, this is not considered an initial execution and the Initial Task Execution Flag (A200.15) will not turn ON. The Initial Task Execution Flag (A200.15) will also not turn ON if a cyclic task is shifted from Disabled to RUN status or if it is put in Standby status by another task through the TKOF(821) instruction before the right to execute actually is obtained. The Task Start Flag can be used to perform initialization processing each time the task cycle is started. The Task Start Flag turns OF whenever cycle task status changes from Disabled (INI) or Standby (WAIT) status to READY status (whereas the Initial Task Execution Flag turns ON only when status changes from Disabled (INI) to READY).
Ready Task n Disabled Disabled Ready

Task Start Flag (A200.14)

Task Start Flag

The Task Start Flag can be used to perform initialization processing whenever a task goes from Standby to RUN status, i.e., when a task on Standby is enabled using the TRON(820) instruction.
Task Start Flag A200.14 Initialization processing

Flags Related to All Tasks

Task Error Flag (A295.12) The Task Error Flag will turn ON if one of the following task errors occurs. No cyclic tasks (including extra cyclic tasks) are READY during a cycle. The program allocated to a cyclic task (including extra cyclic tasks) does not exist. (This situation will not occur when using the CX-Programmer.) No program is allocated to an activated interrupt task.

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Using Tasks
Task Number when Program Stopped (A294)

Section 2-2
The type of task and the current task number when a task stops execution due to a program error will be stored as follows:
Type A294 Cyclic task 0000 to 001F hex (correspond to task numbers 0 to 31) Interrupt task 8000 to 80FF hex (correspond to interrupt task numbers 0 to 255)

This information makes it easier to determine where the fatal error occurred, and it will be cleared when the fatal error is cleared. The program address where task operation stopped is stored in A298 (rightmost bits of the program address) and in A299 (leftmost bits of the program address).

64

Using Tasks

Section 2-2

2-2-4

Examples of Tasks
An overall control task that is set to go to READY status at the start of operation is generally used to control READY/Standby status for all other cyclic tasks (including extra cyclic tasks). Of course, any cyclic task can control the READY/Standby status of any other cyclic task as required by the application.
From Program Mode to Operating or Monitor Mode. Cyclic task 0 with the startup at the start of operation attribute (overall control task)

Cyclic task 1

Cyclic task 2

Cyclic task 3

Tasks Separated by Function Conveyor task Overall control task Error monitoring task MMI task Communications task Analog processing task

Tasks Separated by Controlled Section A-section control task Overall control task B-section control task C-section control task

Tasks Separated by Product Product A task Overall control task Product B task

Tasks Separated by Developer Developer A task Overall control task

Developer B task Developer C task

Product C task

Tasks Separated by Process

Machining task Overall control task Assembly task Conveyor task

Combinations of the above classifications are also possible, e.g., classification by function and process.

65

Using Tasks

Section 2-2

2-2-5

Designing Tasks
We recommend the following guidelines for designing tasks. 1,2,3... 1. Use the following standards to study separating tasks. a. Summarize specific conditions for execution and non-execution. b. c. Summarize the presence or absence of external I/O. Summarize functions. Keep data exchanged between tasks for sequence control, analog control, man-machine interfacing, error processing and other processes to an absolute minimum in order to maintain a high degree of autonomy. d. Summarize execution in order of priority. Separate processing into cyclic and interrupt tasks.
Breakdown by function Interrupt
Order priority

Input processing

Overall control (may include error processing in some cases)

External I/O

Error processing Sequence control Analog control

Man-machine interfacing

Output processing

Breakdown by execution and non-execution conditions

2. Be sure to break down and design programs in a manner that will ensure autonomy and keep the amount of data exchanged between tasks (programs) to an absolute minimum.
Minimize data exchange

3. Generally, use an overall control task to control the READY/Standby status of the other tasks. 4. Allocate the lowest numbers to tasks with the highest priority. Example: Allocate a lower number to the control task than to processing tasks. 5. Allocate lower numbers to high-priority interrupt tasks. 6. A task in READY status will be executed in subsequent cycles as long as the task itself or another task does not shift it to Standby status. Be sure to insert a TKOF(821) (TASK OFF) instruction for other tasks if processing is to be branched between tasks. 7. Use the Initial Task Execution Flag (A200.15) or the Task Start Flag (A200.14) in the execution condition to execution instructions to initialize tasks. The Initial Task Execution Flag will be ON during the first execution of each task. The Task Start Flag each time a task enters READY status.

66

External outputs

Using Tasks

Section 2-2
8. Assign I/O memory into memory shared by tasks and memory used only for individual tasks, and then group I/O memory used only for individual tasks by task.

Relationship of Tasks to Block Programs

Up to 128 block programs can be created in the tasks. This is the total number for all tasks. The execution of each entire block program is controlled from the ladder diagram, but the instructions within the block program are written using mnemonics. In other words, a block program is formed from a combination of a ladder instruction and mnemonic code. Using a block program makes it easier to write logic flow, such as conditional branching and process stepping, which can be hard to write using ladder diagrams. Block programs are located at the bottom of the program hierarchy, and the larger program units represented by the task can be split into small program units as block programs that operate with the same execution condition (ON condition).
Program
0.00

Block program 000 Task 0 Block program 001 Block program area 000

Block program n
0.01

Task 1

Block program area 001

Task n

67

Interrupt Tasks

Section 2-3

2-2-6

Global Subroutine
A subroutine in one task cannot be called from other tasks. A subroutine called a global subroutine can be created in interrupt task number 0, and this subroutine can be called from cyclic tasks (including extra cyclic tasks). GSBS(750) is used to call a global subroutine. The subroutine number must be between 0 and 255. The global subroutine is defined at the end of interrupt task number 0 (just before END(001)) between GSBN(751) and GRET(752) instructions. Global subroutines can be used to create a library of standard program sections that can be called whenever necessary.
Cyclic task (including extra cyclic task)
GSBS n

Interrupt task 0 Call

GSBN n

n = 0 to 1,023 Global subroutine (shared subroutine used for standard programming)

Execution Return
GRET END

Multiple tasks

Cyclic task (including extra cyclic task) Call

GSBS n

Return

2-3
2-3-1

Interrupt Tasks
Types of Interrupt Tasks
Type Execution condition An interrupt occurs when an interrupt input built into the CPU Unit turns ON or OFF in Direct Mode or when a specified number of ON or OFF signals is detected at the interrupt input in Counter Mode. An interrupt occurs when a condition is met for a target value or range comparison for the present value of a highspeed counter. Setting procedure Use the SET INTERRUPT MASK instruction MSKS(690) to specify which interrupt inputs are enabled. Number of Application interrupts examples 8 points Increasing response speed to specific inputs 6 points 6 points

List of Interrupt Tasks

Task No. CP1H 140 to Input X/XA: 0 to 7 147 Inter- CP1H 140 to rupts Y: 0 to 5 145 140 to CP1L M, or L (20 I/O): 145 0 to 5 CP1L 140 to L (14 I/O): 0 to 3 143 High-speed counter 0 to interrupts 255

4 points Use the COMPARISON TABLE LOADinstruction (CTBL(882)) to specify the execution condition and the interrupt to execute. 256 points Performing positioning operations based on counting encoder pulses

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Interrupt Tasks
Type Scheduled Interrupt 0 2 Task No. Execution condition An interrupt occurs at a scheduled time (fixed intervals). Setting procedure Use the SET INTERRUPT MASK instruction (MSKS(690)) to set the interrupt interval. See Scheduled interrupt interval in PLC Setup. None (always valid) Number of interrupts 1 point

Section 2-3
Application examples Monitoring operating status at fixed intervals

External Interrupts (Not supported by CP1L CPU Units.)

0 to 255

Interrupts are requested by an Special I/O Unit or CPU Bus Unit.

256 points

Performing processing required by CJ-series Special I/O Units

Input Interrupt Tasks

Input interrupt tasks are disabled by default when cyclic task execution is started. To enable input interrupts, execute the SET INTERRUPT MASK instruction (MSKS(690)) in a cyclic task for the interrupt number. Using inputs as interrupt inputs must be enabled in advance in the PLC Setup. Do not enable unneeded input interrupt tasks. If the interrupt input is triggered by noise and there isnt a corresponding interrupt task, a fatal error (task error) will cause the program to stop. Example: The following example shows execution input interrupt task 143 when CIO 0.03 (interrupt input No. 3) turns ON.

Note

Cyclic task
MSKS 113 #0000 MSKS 103 #0000 END

MSKS(690) enables the specified input interrupt (ON, Direct Mode). Input interrupt 3 (ON/OFF designation) ON designation Input interrupt 3 (interrupt designation) Interrupts enabled in Direct Mode.
COM 01 00 02 03 04

CIO 0.03
05 06

Cyclic task

Interrupt

Input interrupt task 143

END

END

CP1H X and XA CPU Units

Interrupt input CIO 0.00 CIO 0.01 CIO 0.02 Input interrupt number 0 1 2 Interrupt task number 140 141 142

69

Interrupt Tasks
Interrupt input CIO 0.03 CIO 1.00 CIO 1.01 CIO 1.02 CIO 1.03 Input interrupt number 3 4 5 6 7 Interrupt task number 143 144 145 146 147

Section 2-3

CP1H Y CPU Units

Interrupt input CIO 0.00 CIO 0.01 CIO 1.00 CIO 1.01 CIO 1.02 CIO 1.03 Input interrupt Interrupt number task number 0 1 2 3 4 5 140 141 142 143 144 145

CP1L M and L (20 I/O-point) CPU Units

Interrupt input CIO 0.04 CIO 0.05 CIO 0.06 CIO 0.07 CIO 0.08 CIO 0.09 Input interrupt number 0 1 2 3 4 5 Interrupt task number 140 141 142 143 144 145

CP1L L (14 I/O-point) CPU Units

Interrupt input CIO 0.04 CIO 0.05 CIO 0.06 CIO 0.07 Input interrupt number 0 1 2 3 Interrupt task number 140 141 142 143

70

Interrupt Tasks High-speed Counter Interrupt Tasks: Tasks 0 to 255

Section 2-3
High-speed counter interrupt tasks are enabled by executing the COMPARISON TABLE LOADinstruction (CTBL(882)) to specify the execution condition and the interrupt to execute. The comparison condition consists of target values or a comparison range. Example The following example illustrates executing high-speed interrupt task 10 when the present value of high-speed counter 0 equals the target value when the present value is incremented.

Cyclic task
CTBL #0000 #0000 D0 END

High-speed counter 0 Register comparison table and start comparison. First word in comparison table One target value D0 0001 D1 2710 Target value: 0000 2710 hex (10,000) D2 0000 Compare when incrementing (bit 15: ON), D3 000A Interrupt task: 10 (0A hex) Target Target value for high-speed counter 0 value 0 0 0 0 2 7 1 0 comparison started with High-speed counter 0 CTBL(82). High-speed counter 0 decrement input Comparison reset input CP1H PV of high-speed counter 0
COM 01 03 05 07 09 00 02 04 06 08

Cyclic task

END

High-speed counter 0 increment input Match High-speed Counter interrupt task 10

END

Scheduled Interrupt Task: Task 2

1,2,3...

Scheduled interrupt tasks are disabled in the default PLC Setup at the start of cyclic task execution. Perform the following steps to enable scheduled interrupt tasks. 1. Execute the SET INTERRUPT MASK instruction MSKS(690) from a cyclic task and set the time (cycle) for the specified scheduled interrupt. 2. Set the Scheduled interrupt interval in PLC Setup.

Note

The interrupt time setting affects the cyclic task in that the shorter the interrupt time, the more frequently the task executes and the longer the cycle time. Example: The following examples shows executed scheduled interrupt task every second.

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Interrupt Tasks

Section 2-3

Cyclic task

Scheduled interrupt 0 (Interrupt No. 14: Reset start) Interrupt internal: 100 x 10 ms
14 &100

Scheduled interrupt time unit in PLC Setup = 10 ms (0.01 s) Every second

Cyclic task

Interrupt

Scheduled interrupt (Interrupt task 2)

Scheduled Interrupt Numbers and Interrupt Task Number

Scheduled interrupt number 0 interrupt task 2

PLC Setup Settings

Set the Scheduled interrupt interval on the Timings Tab Page of the PLC Setup to 0.1, 1.0, or 10 ms.
Name Scheduled interrupt interval Settings 10 ms (default) 1.0 ms 0.1 ms

External Interrupt Tasks: Tasks 0 to 255

External interrupt tasks can be received at any time. External interrupt processing is performed at the CPU Unit in PLCs containing CJ-series Special I/O Units or CPU Bus Units. Settings dont have to be made in the CPU Unit. The specified interrupt task must be programmed in the CPU Unit. If an external interrupt task (0 to 255) has the same number as the scheduled interrupt task (task), an input interrupt task (140 to 147), or a high-speed counter task (0 to 255), the interrupt task will be executed for either interrupt condition (external interrupt or the other interrupt condition). As a rule, task numbers should not be duplicated. All interrupt tasks have the same priority, i.e., once execution of any interrupt task has started, it will be completed through the end of the task even if another interrupt occurs during execution. For example, execution of an input interrupt task will not be interrupted to execute the scheduled interrupt task, i.e., the scheduled interrupt task will be executed only after completing the input interrupt task.

Note

Interrupt Task Priority and Order of Execution

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Interrupt Tasks

Section 2-3
If more than one interrupt occurs at the same time, the interrupt tasks will be executed in the following order: Input interrupt tasks (Direct Mode or Counter Mode), High-speed interrupt tasks, External interrupt tasks, Scheduled interrupt task. If more than one of the same type of interrupt occurs at the same time, the one with the lower task number will be executed first. Keep in mind that the above order of execution means that time may be required to execute a programmed task even after an interrupt has occurred if the user program allows the possibility of more than one interrupt occurring at the same time. For example, the user must give special consideration to the scheduled interrupt, which may not be executed at the expected time if other interrupts occur.

2-3-2

Interrupt Task Flags and Words

The maximum processing time for an interrupt task is stored in binary data in 0.1-ms units and is cleared at the start of operation.

Maximum Interrupt Task Processing Time (A440) Interrupt Task with Maximum Processing Time (A441)

The interrupt task number with maximum processing time is stored in binary data. Here, 8000 to 80FF hex correspond to task numbers 00 to FF hex. A441.15 will turn ON when the first interrupt occurs after the start of operation. The maximum processing time for subsequent interrupt tasks will be stored in the rightmost two digits in hexadecimal and will be cleared at the start of operation. If Interrupt Task Error Detection is turned ON in the PLC Setup, the Interrupt Task Error Flag will turn ON if an interrupt task error occurs.

Interrupt Task Error Flag (Nonfatal Error) (A402.13) Interrupt Task Error Flag (A426.15)/Task Number Generating the Interrupt Task Error (A426.00 to A426.11)

If A402.13 turns ON, then the following data will be stored in A426.15 and A426.00 to A426.11.
A402.13 Interrupt Task Error (If Interrupt Task Error Detection is turned ON in the PLC Setup) Interrupt Task Error A426.15 A426.00 to A426.11 Description The unit number of the When trying to refresh ON CJ-series Special I/O I/O for a large number Unit being refreshed of words using will be stored in 12 bits IORF(097) from an of binary data (unit interrupt task while a number 0 to 95: 000 to CJ-series Special I/O 05F hex). Unit is being refreshed by cyclic I/O refreshing.

Task Number when Program Stopped (A294)

The type of task and the current task number when a program stops due to a program error will be stored in the following locations.
Type Interrupt task Cyclic task A294 8000 to 80FF hex (corresponds to interrupt task 0 to 255) 0000 to 001F hex (corresponds to task 0 to 31)

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Interrupt Tasks

Section 2-3

2-3-3

Application Precautions
If an IORF(097) instruction has to be executed from an interrupt task for a CJseries Special I/O Unit, be sure to turn OFF cyclic refresh for the Special I/O Unit (using the unit number) in the PLC Setup. A interrupt task error will occur if you try to refresh a Special I/O Unit with an IORF(097) instruction from an interrupt task while the Unit is also being refreshed by cyclic I/O refresh or by I/O refresh instructions (IORF(097) or immediate refresh instructions (!)). If Interrupt Task Error Detection is turned ON in the PLC Setup when an interrupt task error occurs, A402.13 (Interrupt Task Error Flag) will turn ON and the unit number of the Special I/O Unit for which I/O refreshing has been duplicated will be stored in A426 (Interrupt Task Error, Task Number). The CPU Unit will continue running.
CJ-series Special I/O Unit CP1H I/O refresh

Executing IORF(097) for a Special I/O Unit

Incorrect Use
Do not executed IORF(097) in an interrupt task if cyclic refreshing is enabled for Special I/O Units in the PLC Setup.

Interrupt task IORF D1 D2 END

Correct Use Disable cyclic refreshing for Special I/O Units in the PLC Setup before executing the IORF(097) instruction in an interrupt task.

PLC Setup Settings

Select or clear the Detect Interrupt Task Error Checkbox in the Execute Process Area on the Settings Tab Page in the PLC Setup.
Name Setting Detect Interrupt Task Cleared Error Selected Description Interrupt task errors not detected. Interrupt Task Error Flag (A402.13) turned ON when an interrupt task error is detected.

Related Auxiliary Area Flags/Words

Name Interrupt Task Error Flag Interrupt Task Error Unit Number Interrupt Task Error Factor Flag Address A402.13 A426 Description Turns ON if you try to refresh a CJ-series Special I/O Unit with IORF(097) from an interrupt task while that Unit is being refreshed by cyclic I/O refresh. Bits 00 to The unit number of the Special I/O Unit undergoing duplicate refreshing will 11 be stored here when A402.13 turns ON. Bit 15 Turns ON to indicate the cause of the error when A402.13 turns ON.

Disabling Interrupts

With a CP-series CPU Unit, the following processing will be interrupted to execute an interrupt task. Instruction execution Refreshing for CPU Unit built-in I/O, CPM1A Expansion Units, CPM1A Expansion I/O Units, or CJ-series Special I/O Units Peripheral servicing

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CX-Programmer Operations for Tasks

Data Concurrency between Cyclic and Interrupt Tasks

Section 2-4

Data may not be concurrent if a cyclic (including extra cyclic tasks) and an interrupt task are reading and writing the same I/O memory addresses. Use the following procedure to disable interrupts during memory access by cyclic task instructions. Immediately prior to reading or writing by a cyclic task instruction, use a DISABLE INTERRUPT (DI(693)) instruction to disable execution of interrupt tasks. Use an ENABLE INTERRUPT instruction (EI(694)) immediately after processing in order to enable interrupt task execution.
Cyclic task

Disabled Interrupt task Reading and writing I/O memory common to interrupt tasks.

Enabled Processing with interrupt task execution enabled

Interrupt task

Problems may occur with data concurrency even if DI(693) and EI(694) are used to disable interrupt tasks during execution of an instruction that requires response reception and processing (such as a network instruction or serial communications instruction).

2-4

CX-Programmer Operations for Tasks

Note Use the CX-Programmer to create cyclic tasks (including extra cyclic tasks). Be sure to use the CX-Programmer to allocate the task types and task numbers. Specify the task type and number as attributes for each program. 1,2,3... 1. Select View/Properties, or click the right button and select Properties from the popup menu, to display the program that will be allocated a task. 2. Click the General Tab, and select the Task Type and Task No. For a cyclic task, select the Operation start Option to start the task at startup if required.

CX-Programmer

75

CX-Programmer Operations for Tasks

Section 2-4

76

SECTION 3 Instructions
This section describes each of the instructions that can be used in programming CP-series PLCs. Instructions are described in order of function. 3-1 3-2 Notation and Layout of Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . Sequence Input Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2-1 3-2-2 3-2-3 3-2-4 3-2-5 3-2-6 3-2-7 3-2-8 3-2-9 LOAD: LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LOAD NOT: LD NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND: AND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND NOT: AND NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR: OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR NOT: OR NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND LOAD: AND LD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR LOAD: OR LD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differentiated and Immediate Refreshing Instructions. . . . . . . . . . . 86 89 89 91 93 95 97 98 100 102 105 106 107 108 109 110 113 113 114 115 119 122 124 127 130 132 132 133 133 136

3-2-10 Operation Timing for I/O Instructions . . . . . . . . . . . . . . . . . . . . . . . 3-2-11 TR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2-12 NOT: NOT(520) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2-13 CONDITION ON/OFF: UP(521) and DOWN(522) . . . . . . . . . . . . 3-2-14 BIT TEST: TST(350) and TSTN(351) . . . . . . . . . . . . . . . . . . . . . . . 3-3 Sequence Output Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3-1 3-3-2 3-3-3 3-3-4 3-3-5 3-3-6 3-3-7 3-3-8 3-4 3-4-1 3-4-2 3-4-3 3-4-4 3-4-5 OUTPUT: OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTPUT NOT: OUT NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KEEP: KEEP(011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014). . . . . . SET and RESET: SET and RSET. . . . . . . . . . . . . . . . . . . . . . . . . . . MULTIPLE BIT SET/RESET: SETA(530)/RSTA(531) . . . . . . . . . SINGLE BIT SET/RESET: SETB(532)/RSTB(533) . . . . . . . . . . . . SINGLE BIT OUTPUT: OUTB(534) . . . . . . . . . . . . . . . . . . . . . . . END: END(001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NO OPERATION: NOP(000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of Interlock Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003) . MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTI-INTERLOCK DIFFERENTIATION RELEASE, and MULTI-INTERLOCK CLEAR: MILH(517), MILR(518), and MILC(519) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JUMP and JUMP END: JMP(004) and JME(005). . . . . . . . . . . . . . CONDITIONAL JUMP: CJP(510)/CJPN(511) . . . . . . . . . . . . . . . . MULTIPLE JUMP and JUMP END: JMP0(515) and JME0(516) . FOR-NEXT LOOPS: FOR(512)/NEXT(513) . . . . . . . . . . . . . . . . .

Sequence Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

140 154 157 161 163 166

3-4-6 3-4-7 3-4-8 3-4-9

3-4-10 BREAK LOOP: BREAK(514) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3-5

Timer and Counter Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5-1 3-5-2 3-5-3 3-5-4 3-5-5 3-5-6 3-5-7 3-5-8 3-5-9 TIMER: TIM/TIMX(550) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HIGH-SPEED TIMER: TIMH(015)/TIMHX(551) . . . . . . . . . . . . . ONE-MS TIMER: TMHH(540)/TMHHX(552). . . . . . . . . . . . . . . . ACCUMULATIVE TIMER: TTIM(087)/TTIMX(555) . . . . . . . . . LONG TIMER: TIML(542)/TIMLX(553). . . . . . . . . . . . . . . . . . . . MULTI-OUTPUT TIMER: MTIM(543)/MTIMX(554) . . . . . . . . . COUNTER: CNT/CNTX(546). . . . . . . . . . . . . . . . . . . . . . . . . . . . . REVERSIBLE COUNTER: CNTR(012)/CNTRX(548) . . . . . . . . . RESET TIMER/COUNTER: CNR(545)/CNRX(547). . . . . . . . . . .

168 170 174 178 181 184 187 193 196 200 203 206 209 209 215 220 222 225 227 230 233 235 238 242 244 247 247 248 250 251 253 255 257 260 262 264 265 267 269 270 272 274 274 276 279

3-5-10 Example Timer and Counter Applications . . . . . . . . . . . . . . . . . . . . 3-5-11 Indirect Addressing of Timer/Counter Numbers . . . . . . . . . . . . . . . 3-6 Comparison Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6-1 3-6-2 3-6-3 3-6-4 3-6-5 3-6-6 3-6-7 3-6-8 3-6-9 Input Comparison Instructions (300 to 328). . . . . . . . . . . . . . . . . . . Time Comparison Instructions (341 to 346). . . . . . . . . . . . . . . . . . . COMPARE: CMP(020) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE COMPARE: CMPL(060) . . . . . . . . . . . . . . . . . . . . . . . . SIGNED BINARY COMPARE: CPS(114) . . . . . . . . . . . . . . . . . . . DOUBLE SIGNED BINARY COMPARE: CPSL(115) . . . . . . . . . MULTIPLE COMPARE: MCMP(019) . . . . . . . . . . . . . . . . . . . . . . TABLE COMPARE: TCMP(085) . . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK COMPARE: BCMP(068) . . . . . . . . . . . . . . . . . . . . . . . . . .

3-6-10 EXPANDED BLOCK COMPARE: BCMP2(502). . . . . . . . . . . . . . 3-6-11 AREA RANGE COMPARE: ZCP(088). . . . . . . . . . . . . . . . . . . . . . 3-6-12 DOUBLE AREA RANGE COMPARE: ZCPL(116) . . . . . . . . . . . . 3-7 Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7-1 3-7-2 3-7-3 3-7-4 3-7-5 3-7-6 3-7-7 3-7-8 3-7-9 MOVE: MOV(021). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVE NOT: MVN(022) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE MOVE: MOVL(498) . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE MOVE NOT: MVNL(499) . . . . . . . . . . . . . . . . . . . . . . . MOVE BIT: MOVB(082) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVE DIGIT: MOVD(083) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MULTIPLE BIT TRANSFER: XFRB(062). . . . . . . . . . . . . . . . . . . BLOCK TRANSFER: XFER(070) . . . . . . . . . . . . . . . . . . . . . . . . . BLOCK SET: BSET(071) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-7-10 DATA EXCHANGE: XCHG(073) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7-11 DOUBLE DATA EXCHANGE: XCGL(562) . . . . . . . . . . . . . . . . . 3-7-12 SINGLE WORD DISTRIBUTE: DIST(080) . . . . . . . . . . . . . . . . . . 3-7-13 DATA COLLECT: COLL(081) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7-14 MOVE TO REGISTER: MOVR(560) . . . . . . . . . . . . . . . . . . . . . . . 3-7-15 MOVE TIMER/COUNTER PV TO REGISTER: MOVRW(561). . 3-8 Data Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8-1 3-8-2 3-8-3 SHIFT REGISTER: SFT(010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REVERSIBLE SHIFT REGISTER: SFTR(084) . . . . . . . . . . . . . . . ASYNCHRONOUS SHIFT REGISTER: ASFT(017). . . . . . . . . . .

78

3-8-4 3-8-5 3-8-6 3-8-7 3-8-8 3-8-9

WORD SHIFT: WSFT(016). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARITHMETIC SHIFT LEFT: ASL(025). . . . . . . . . . . . . . . . . . . . . DOUBLE SHIFT LEFT: ASLL(570). . . . . . . . . . . . . . . . . . . . . . . . ARITHMETIC SHIFT RIGHT: ASR(026) . . . . . . . . . . . . . . . . . . . DOUBLE SHIFT RIGHT: ASRL(571) . . . . . . . . . . . . . . . . . . . . . . ROTATE LEFT: ROL(027). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

281 283 284 286 287 289 290 292 294 295 297 299 300 302 303 305 307 309 311 314 317 320 320 322 324 326 328 330 332 334 336 337 339 341 343 345 346 348 349 351 353 357 359 361

3-8-10 DOUBLE ROTATE LEFT: ROLL(572) . . . . . . . . . . . . . . . . . . . . . . 3-8-11 ROTATE RIGHT: ROR(028) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8-12 DOUBLE ROTATE RIGHT: RORL(573) . . . . . . . . . . . . . . . . . . . . 3-8-13 ROTATE LEFT WITHOUT CARRY: RLNC(574) . . . . . . . . . . . . . 3-8-14 DOUBLE ROTATE LEFT WITHOUT CARRY: RLNL(576). . . . . 3-8-15 ROTATE RIGHT WITHOUT CARRY: RRNC(575) . . . . . . . . . . . . 3-8-16 DOUBLE ROTATE RIGHT WITHOUT CARRY: RRNL(577) . . . 3-8-17 ONE DIGIT SHIFT LEFT: SLD(074) . . . . . . . . . . . . . . . . . . . . . . . 3-8-18 ONE DIGIT SHIFT RIGHT: SRD(075). . . . . . . . . . . . . . . . . . . . . . 3-8-19 SHIFT N-BIT DATA LEFT: NSFL(578) . . . . . . . . . . . . . . . . . . . . . 3-8-20 SHIFT N-BIT DATA RIGHT: NSFR(579). . . . . . . . . . . . . . . . . . . . 3-8-21 SHIFT N-BITS LEFT: NASL(580) . . . . . . . . . . . . . . . . . . . . . . . . . 3-8-22 DOUBLE SHIFT N-BITS LEFT: NSLL(582) . . . . . . . . . . . . . . . . . 3-8-23 SHIFT N-BITS RIGHT: NASR(581) . . . . . . . . . . . . . . . . . . . . . . . . 3-8-24 DOUBLE SHIFT N-BITS RIGHT: NSRL(583) . . . . . . . . . . . . . . . 3-9 Increment/Decrement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9-1 3-9-2 3-9-3 3-9-4 3-9-5 3-9-6 3-9-7 3-9-8 INCREMENT BINARY: ++(590) . . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE INCREMENT BINARY: ++L(591) . . . . . . . . . . . . . . . . DECREMENT BINARY: (592). . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE DECREMENT BINARY: L(593). . . . . . . . . . . . . . . . INCREMENT BCD: ++B(594) . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE INCREMENT BCD: ++BL(595) . . . . . . . . . . . . . . . . . . DECREMENT BCD: B(596) . . . . . . . . . . . . . . . . . . . . . . . . . . . DOUBLE DECREMENT BCD: BL(597). . . . . . . . . . . . . . . . . .

3-10 Symbol Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10-1 SIGNED BINARY ADD WITHOUT CARRY: +(400) . . . . . . . . . . 3-10-2 DOUBLE SIGNED BINARY ADD WITHOUT CARRY: +L(401) 3-10-3 SIGNED BINARY ADD WITH CARRY: +C(402). . . . . . . . . . . . . 3-10-4 DOUBLE SIGNED BINARY ADD WITH CARRY: +CL(403) . . . 3-10-5 BCD ADD WITHOUT CARRY: +B(404) . . . . . . . . . . . . . . . . . . . . 3-10-6 DOUBLE BCD ADD WITHOUT CARRY: +BL(405) . . . . . . . . . . 3-10-7 BCD ADD WITH CARRY: +BC(406) . . . . . . . . . . . . . . . . . . . . . . 3-10-8 DOUBLE BCD ADD WITH CARRY: +BCL(407). . . . . . . . . . . . . 3-10-9 SIGNED BINARY SUBTRACT WITHOUT CARRY: (410) . . . . 3-10-10 DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY: L(411) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10-11 SIGNED BINARY SUBTRACT WITH CARRY: C(412) . . . . . . . 3-10-12 DOUBLE SIGNED BINARY SUBTRACT WITH CARRY: CL(413). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10-13 BCD SUBTRACT WITHOUT CARRY: B(414) . . . . . . . . . . . . . .

79

3-10-14 DOUBLE BCD SUBTRACT WITHOUT CARRY: BL(415) . . . . 3-10-15 BCD SUBTRACT WITH CARRY: BC(416). . . . . . . . . . . . . . . . . 3-10-16 DOUBLE BCD SUBTRACT WITH CARRY: BCL(417) . . . . . . . 3-10-17 SIGNED BINARY MULTIPLY: *(420). . . . . . . . . . . . . . . . . . . . . . 3-10-18 DOUBLE SIGNED BINARY MULTIPLY: *L(421) . . . . . . . . . . . . 3-10-19 UNSIGNED BINARY MULTIPLY: *U(422) . . . . . . . . . . . . . . . . . 3-10-20 DOUBLE UNSIGNED BINARY MULTIPLY: *UL(423). . . . . . . . 3-10-21 BCD MULTIPLY: *B(424). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10-22 DOUBLE BCD MULTIPLY: *BL(425) . . . . . . . . . . . . . . . . . . . . . . 3-10-23 SIGNED BINARY DIVIDE: /(430) . . . . . . . . . . . . . . . . . . . . . . . . . 3-10-24 DOUBLE SIGNED BINARY DIVIDE: /L(431) . . . . . . . . . . . . . . . 3-10-25 UNSIGNED BINARY DIVIDE: /U(432) . . . . . . . . . . . . . . . . . . . . 3-10-26 DOUBLE UNSIGNED BINARY DIVIDE: /UL(433). . . . . . . . . . . 3-10-27 BCD DIVIDE: /B(434). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10-28 DOUBLE BCD DIVIDE: /BL(435) . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Conversion Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-1 BCD-TO-BINARY: BIN(023) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-2 DOUBLE BCD-TO-DOUBLE BINARY: BINL(058) . . . . . . . . . . . 3-11-3 BINARY-TO-BCD: BCD(024). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-4 DOUBLE BINARY-TO-DOUBLE BCD: BCDL(059) . . . . . . . . . . 3-11-5 2S COMPLEMENT: NEG(160) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-6 DOUBLE 2S COMPLEMENT: NEGL(161) . . . . . . . . . . . . . . . . . 3-11-7 16-BIT TO 32-BIT SIGNED BINARY: SIGN(600) . . . . . . . . . . . . 3-11-8 DATA DECODER: MLPX(076) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-9 DATA ENCODER: DMPX(077) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-10 ASCII CONVERT: ASC(086) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-11 ASCII TO HEX: HEX(162) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-12 COLUMN TO LINE: LINE(063). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-13 LINE TO COLUMN: COLM(064) . . . . . . . . . . . . . . . . . . . . . . . . . 3-11-14 SIGNED BCD-TO-BINARY: BINS(470) . . . . . . . . . . . . . . . . . . . . 3-11-15 DOUBLE SIGNED BCD-TO-BINARY: BISL(472) . . . . . . . . . . . . 3-11-16 SIGNED BINARY-TO-BCD: BCDS(471). . . . . . . . . . . . . . . . . . . . 3-11-17 DOUBLE SIGNED BINARY-TO-BCD: BDSL(473) . . . . . . . . . . . 3-11-18 GRAY CODE CONVERT: GRY(474) . . . . . . . . . . . . . . . . . . . . . . . 3-12 Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12-1 LOGICAL AND: ANDW(034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12-2 DOUBLE LOGICAL AND: ANDL(610) . . . . . . . . . . . . . . . . . . . . 3-12-3 LOGICAL OR: ORW(035) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12-4 DOUBLE LOGICAL OR: ORWL(611). . . . . . . . . . . . . . . . . . . . . . 3-12-5 EXCLUSIVE OR: XORW(036). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12-6 DOUBLE EXCLUSIVE OR: XORL(612). . . . . . . . . . . . . . . . . . . . 3-12-7 EXCLUSIVE NOR: XNRW(037) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12-8 DOUBLE EXCLUSIVE NOR: XNRL(613) . . . . . . . . . . . . . . . . . . 3-12-9 COMPLEMENT: COM(029) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12-10 DOUBLE COMPLEMENT: COML(614) . . . . . . . . . . . . . . . . . . . .

363 366 367 369 371 372 374 375 377 378 380 382 384 385 387 389 389 390 392 393 395 397 398 400 404 408 411 415 417 419 422 424 427 430 436 436 437 439 440 442 444 445 447 449 450

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3-13 Special Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13-1 BINARY ROOT: ROTB(620) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13-2 BCD SQUARE ROOT: ROOT(072). . . . . . . . . . . . . . . . . . . . . . . . . 3-13-3 ARITHMETIC PROCESS: APR(069) . . . . . . . . . . . . . . . . . . . . . . . 3-13-4 FLOATING POINT DIVIDE: FDIV(079) . . . . . . . . . . . . . . . . . . . . 3-13-5 BIT COUNTER: BCNT(067). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Floating-point Math Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-1 FLOATING TO 16-BIT: FIX(450). . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-2 FLOATING TO 32-BIT: FIXL(451) . . . . . . . . . . . . . . . . . . . . . . . . 3-14-3 16-BIT TO FLOATING: FLT(452) . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-4 32-BIT TO FLOATING: FLTL(453) . . . . . . . . . . . . . . . . . . . . . . . . 3-14-5 FLOATING-POINT ADD: +F(454). . . . . . . . . . . . . . . . . . . . . . . . . 3-14-6 FLOATING-POINT SUBTRACT: F(455) . . . . . . . . . . . . . . . . . . . 3-14-7 FLOATING-POINT MULTIPLY: *F(456). . . . . . . . . . . . . . . . . . . . 3-14-8 FLOATING-POINT DIVIDE: /F(457) . . . . . . . . . . . . . . . . . . . . . . . 3-14-9 DEGREES TO RADIANS: RAD(458) . . . . . . . . . . . . . . . . . . . . . . 3-14-10 RADIANS TO DEGREES: DEG(459) . . . . . . . . . . . . . . . . . . . . . . 3-14-11 SINE: SIN(460) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-12 COSINE: COS(461) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-13 TANGENT: TAN(462) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-14 ARC SINE: ASIN(463) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-15 ARC COSINE: ACOS(464) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-16 ARC TANGENT: ATAN(465) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-17 SQUARE ROOT: SQRT(466) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-18 EXPONENT: EXP(467) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-19 LOGARITHM: LOG(468) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14-20 EXPONENTIAL POWER: PWR(840) . . . . . . . . . . . . . . . . . . . . . . 3-14-21 Single-precision Floating-point Comparison Instructions . . . . . . . . 3-14-22 FLOATING-POINT TO ASCII: FSTR(448) . . . . . . . . . . . . . . . . . . 3-14-23 ASCII TO FLOATING-POINT: FVAL(449) . . . . . . . . . . . . . . . . . . 3-15 Double-precision Floating-point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 3-15-1 DOUBLE FLOATING TO 16-BIT: FIXD(841). . . . . . . . . . . . . . . . 3-15-2 DOUBLE FLOATING TO 32-BIT: FIXLD(842) . . . . . . . . . . . . . . 3-15-3 16-BIT TO DOUBLE FLOATING: DBL(843) . . . . . . . . . . . . . . . . 3-15-4 32-BIT TO DOUBLE FLOATING: DBLL(844) . . . . . . . . . . . . . . . 3-15-5 DOUBLE FLOATING-POINT ADD: +D(845) . . . . . . . . . . . . . . . . 3-15-6 DOUBLE FLOATING-POINT SUBTRACT: D(846) . . . . . . . . . . 3-15-7 DOUBLE FLOATING-POINT MULTIPLY: *D(847). . . . . . . . . . . 3-15-8 DOUBLE FLOATING-POINT DIVIDE: /D(848) . . . . . . . . . . . . . . 3-15-9 DOUBLE DEGREES TO RADIANS: RADD(849) . . . . . . . . . . . . 3-15-10 DOUBLE RADIANS TO DEGREES: DEGD(850) . . . . . . . . . . . . 3-15-11 DOUBLE SINE: SIND(851) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15-12 DOUBLE COSINE: COSD(852) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15-13 DOUBLE TANGENT: TAND(853) . . . . . . . . . . . . . . . . . . . . . . . . . 3-15-14 DOUBLE ARC SINE: ASIND(854) . . . . . . . . . . . . . . . . . . . . . . . .

451 451 453 456 467 470 472 478 480 481 483 484 486 488 490 492 493 495 496 498 500 502 503 505 507 509 511 512 516 521 525 530 532 533 534 536 538 540 542 544 545 547 548 550 551

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3-15-15 DOUBLE ARC COSINE: ACOSD(855) . . . . . . . . . . . . . . . . . . . . . 3-15-16 DOUBLE ARC TANGENT: ATAND(856) . . . . . . . . . . . . . . . . . . . 3-15-17 DOUBLE SQUARE ROOT: SQRTD(857) . . . . . . . . . . . . . . . . . . . 3-15-18 DOUBLE EXPONENT: EXPD(858) . . . . . . . . . . . . . . . . . . . . . . . . 3-15-19 DOUBLE LOGARITHM: LOGD(859) . . . . . . . . . . . . . . . . . . . . . . 3-15-20 DOUBLE EXPONENTIAL POWER: PWRD(860) . . . . . . . . . . . . 3-15-21 Double-precision Floating-point Input Instructions . . . . . . . . . . . . . 3-16 Table Data Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-1 SET STACK: SSET(630) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-2 PUSH ONTO STACK: PUSH(632) . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-3 FIRST IN FIRST OUT: FIFO(633) . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-4 LAST IN FIRST OUT: LIFO(634) . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-5 DIMENSION RECORD TABLE: DIM(631). . . . . . . . . . . . . . . . . . 3-16-6 SET RECORD LOCATION: SETR(635) . . . . . . . . . . . . . . . . . . . . 3-16-7 GET RECORD NUMBER: GETR(636) . . . . . . . . . . . . . . . . . . . . . 3-16-8 DATA SEARCH: SRCH(181) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-9 SWAP BYTES: SWAP(637). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-10 FIND MAXIMUM: MAX(182) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-11 FIND MINIMUM: MIN(183) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-12 SUM: SUM(184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-13 FRAME CHECKSUM: FCS(180) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-14 STACK SIZE READ: SNUM(638) . . . . . . . . . . . . . . . . . . . . . . . . . 3-16-15 STACK DATA READ: SREAD(639). . . . . . . . . . . . . . . . . . . . . . . . 3-16-16 STACK DATA OVERWRITE: SWRIT(640) . . . . . . . . . . . . . . . . . . 3-16-17 STACK DATA INSERT: SINS(641). . . . . . . . . . . . . . . . . . . . . . . . . 3-16-18 STACK DATA DELETE: SDEL(642) . . . . . . . . . . . . . . . . . . . . . . . 3-17 Data Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17-1 PID CONTROL: PID(190) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17-2 PID CONTROL WITH AUTOTUNING: PIDAT(191) . . . . . . . . . . 3-17-3 LIMIT CONTROL: LMT(680) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17-4 DEAD BAND CONTROL: BAND(681) . . . . . . . . . . . . . . . . . . . . . 3-17-5 DEAD ZONE CONTROL: ZONE(682) . . . . . . . . . . . . . . . . . . . . . 3-17-6 TIME-PROPORTIONAL OUTPUT: TPO(685) . . . . . . . . . . . . . . . 3-17-7 SCALING: SCL(194). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17-8 SCALING 2: SCL2(486) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17-9 SCALING 3: SCL3(487) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17-10 AVERAGE: AVG(195) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18-1 SUBROUTINE CALL: SBS(091) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18-2 MACRO: MCRO(099) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18-3 SUBROUTINE ENTRY: SBN(092). . . . . . . . . . . . . . . . . . . . . . . . . 3-18-4 SUBROUTINE RETURN: RET(093) . . . . . . . . . . . . . . . . . . . . . . . 3-18-5 GLOBAL SUBROUTINE CALL: GSBS(750) . . . . . . . . . . . . . . . . 3-18-6 GLOBAL SUBROUTINE ENTRY: GSBN(751) . . . . . . . . . . . . . . . 3-18-7 GLOBAL SUBROUTINE RETURN: GRET(752) . . . . . . . . . . . . .

553 555 557 558 560 562 563 567 567 570 573 575 578 580 582 584 586 588 591 594 597 600 603 606 609 612 615 615 627 637 639 642 644 652 656 660 664 668 668 674 678 680 681 688 691

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3-19 Interrupt Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19-1 SET INTERRUPT MASK: MSKS(690) . . . . . . . . . . . . . . . . . . . . . 3-19-2 READ INTERRUPT MASK: MSKR(692) . . . . . . . . . . . . . . . . . . . 3-19-3 CLEAR INTERRUPT: CLI(691) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19-4 DISABLE INTERRUPTS: DI(693) . . . . . . . . . . . . . . . . . . . . . . . . . 3-19-5 ENABLE INTERRUPTS: EI(694) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 High-speed Counter/Pulse Output Instructions. . . . . . . . . . . . . . . . . . . . . . . . 3-20-1 MODE CONTROL: INI(880) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20-2 HIGH-SPEED COUNTER PV READ: PRV(881). . . . . . . . . . . . . . 3-20-3 COUNTER FREQUENCY CONVERT: PRV2(883). . . . . . . . . . . . 3-20-4 REGISTER COMPARISON TABLE: CTBL(882) . . . . . . . . . . . . . 3-20-5 SPEED OUTPUT: SPED(885) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20-6 SET PULSES: PULS(886) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20-7 PULSE OUTPUT: PLS2(887) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20-8 ACCELERATION CONTROL: ACC(888) . . . . . . . . . . . . . . . . . . . 3-20-9 ORIGIN SEARCH: ORG(889) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20-10 PULSE WITH VARIABLE DUTY FACTOR: PWM(891) . . . . . . . 3-21 Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21-1 STEP DEFINE and STEP START: STEP(008)/SNXT(009) . . . . . . 3-22 Basic I/O Unit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22-1 I/O REFRESH: IORF(097). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22-2 7-SEGMENT DECODER: SDEC(078) . . . . . . . . . . . . . . . . . . . . . . 3-22-3 DIGITAL SWITCH INPUT DSW(210) . . . . . . . . . . . . . . . . . . . . 3-22-4 TEN KEY INPUT TKY(211) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22-5 HEXADECIMAL KEY INPUT HKY(212) . . . . . . . . . . . . . . . . . 3-22-6 MATRIX INPUT: MTR(213) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22-7 7-SEGMENT DISPLAY OUTPUT 7SEG(214) . . . . . . . . . . . . . . 3-22-8 INTELLIGENT I/O READ: IORD(222) . . . . . . . . . . . . . . . . . . . . . 3-22-9 INTELLIGENT I/O WRITE: IOWR(223) . . . . . . . . . . . . . . . . . . . . 3-22-10 CPU BUS UNIT I/O REFRESH: DLNK(226) . . . . . . . . . . . . . . . . 3-23 Serial Communications Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23-1 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23-2 PROTOCOL MACRO: PMCR(260) . . . . . . . . . . . . . . . . . . . . . . . . 3-23-3 TRANSMIT: TXD(236) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23-4 RECEIVE: RXD(235) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23-5 TRANSMIT VIA SERIAL COMMUNICATIONS UNIT: TXDU(256). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23-6 RECEIVE VIA SERIAL COMMUNICATIONS UNIT: RXDU(255) 3-23-7 CHANGE SERIAL PORT SETUP: STUP(237) . . . . . . . . . . . . . . . 3-24 Network Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24-1 About Network Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24-2 About Explicit Message Instructions (CP1H Only) . . . . . . . . . . . . . 3-24-3 NETWORK SEND: SEND(090) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24-4 NETWORK RECEIVE: RECV(098) . . . . . . . . . . . . . . . . . . . . . . . . 3-24-5 DELIVER COMMAND: CMND(490) . . . . . . . . . . . . . . . . . . . . . .

692 692 696 699 702 703 705 705 709 715 719 723 728 731 739 745 749 751 752 769 769 772 775 779 782 786 790 794 797 800 805 805 806 815 820 825 833 841 844 844 859 864 870 876

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3-24-6 EXPLICIT MESSAGE SEND: EXPLT(720) . . . . . . . . . . . . . . . . . . 3-24-7 EXPLICIT GET ATTRIBUTE: EGATR(721) . . . . . . . . . . . . . . . . . 3-24-8 EXPLICIT SET ATTRIBUTE: ESATR(722) . . . . . . . . . . . . . . . . . . 3-24-9 EXPLICIT WORD READ: ECHRD(723) . . . . . . . . . . . . . . . . . . . . 3-24-10 EXPLICIT WORD WRITE: ECHWR(724) . . . . . . . . . . . . . . . . . . . 3-25 Display Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25-1 DISPLAY MESSAGE: MSG(046) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25-2 SEVEN-SEGMENT LED WORD DATA DISPLAY: SCH(047) . . . 3-25-3 SEVEN-SEGMENT LED CONTROL: SCTRL(048) . . . . . . . . . . . 3-26 Clock Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26-1 CALENDAR ADD: CADD(730) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26-2 CALENDAR SUBTRACT: CSUB(731) . . . . . . . . . . . . . . . . . . . . . 3-26-3 HOURS TO SECONDS: SEC(065) . . . . . . . . . . . . . . . . . . . . . . . . . 3-26-4 SECONDS TO HOURS: HMS(066) . . . . . . . . . . . . . . . . . . . . . . . . 3-26-5 CLOCK ADJUSTMENT: DATE(735) . . . . . . . . . . . . . . . . . . . . . . . 3-27 Debugging Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27-1 Trace Memory Sampling: TRSM(045) . . . . . . . . . . . . . . . . . . . . . . . 3-28 Failure Diagnosis Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28-1 FAILURE ALARM: FAL(006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28-2 SEVERE FAILURE ALARM: FALS(007) . . . . . . . . . . . . . . . . . . . 3-28-3 FAILURE POINT DETECTION: FPD(269) . . . . . . . . . . . . . . . . . . 3-29 Other Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29-1 SET CARRY: STC(040) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29-2 CLEAR CARRY: CLC(041) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29-3 EXTEND MAXIMUM CYCLE TIME: WDT(094) . . . . . . . . . . . . 3-29-4 SAVE CONDITION FLAGS: CCS(282) . . . . . . . . . . . . . . . . . . . . . 3-29-5 LOAD CONDITION FLAGS: CCL(283). . . . . . . . . . . . . . . . . . . . . 3-29-6 CONVERT ADDRESS FROM CV: FRMCV(284) . . . . . . . . . . . . . 3-29-7 CONVERT ADDRESS TO CV: TOCV(285) . . . . . . . . . . . . . . . . . . 3-30 Block Programming Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30-1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30-2 BLOCK PROGRAM BEGIN/END: BPRG(096)/BEND(801) . . . . 3-30-3 BLOCK PROGRAM PAUSE/RESTART: BPPS(811)/BPRS(812) . 3-30-4 Branching: IF(802), ELSE(803), and IEND(804). . . . . . . . . . . . . . . 3-30-5 CONDITIONAL BLOCK EXIT (NOT): EXIT (NOT)(806) . . . . . . 3-30-6 ONE CYCLE AND WAIT (NOT): WAIT(805)/WAIT(805) NOT. . 3-30-7 TIMER WAIT: TIMW(813) and TIMWX(816) . . . . . . . . . . . . . . . . 3-30-8 COUNTER WAIT: CNTW(814) and CNTWX(818) . . . . . . . . . . . . 3-30-9 HIGH-SPEED TIMER WAIT: TMHW(815) and TMHWX(817) . . 3-30-10 Loop Control: LOOP(809)/LEND(810)/LEND(810) NOT . . . . . . . 3-31 Text String Processing Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-1 Text String Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-2 MOV STRING: MOV$(664) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-3 CONCATENATE STRING: +$(656) . . . . . . . . . . . . . . . . . . . . . . . . 3-31-4 GET STRING LEFT: LEFT$(652) . . . . . . . . . . . . . . . . . . . . . . . . . .

883 890 897 903 907 911 911 913 915 918 918 921 924 927 929 932 932 936 936 944 951 961 961 961 962 964 966 967 971 975 975 979 982 984 988 991 995 998 1001 1004 1008 1008 1009 1011 1013

84

3-31-5 GET STRING RIGHT: RGHT$(653) . . . . . . . . . . . . . . . . . . . . . . . . 3-31-6 GET STRING MIDDLE: MID$(654). . . . . . . . . . . . . . . . . . . . . . . . 3-31-7 FIND IN STRING: FIND$(660). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-8 STRING LENGTH: LEN$(650). . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-9 REPLACE IN STRING: RPLC$(661) . . . . . . . . . . . . . . . . . . . . . . . 3-31-10 DELETE STRING: DEL$(658) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-11 EXCHANGE STRING: XCHG$(665) . . . . . . . . . . . . . . . . . . . . . . . 3-31-12 CLEAR STRING: CLR$(666) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31-13 INSERT INTO STRING: INS$(657) . . . . . . . . . . . . . . . . . . . . . . . . 3-31-14 String Comparison Instructions (670 to 675) . . . . . . . . . . . . . . . . . . 3-32 Task Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32-1 TASK ON: TKON(820) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32-2 TASK OFF: TKOF(821) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 Model Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33-1 BLOCK TRANSFER: XFERC(565) . . . . . . . . . . . . . . . . . . . . . . . . 3-33-2 SINGLE WORD DISTRIBUTE: DISTC(566). . . . . . . . . . . . . . . . . 3-33-3 DATA COLLECT: COLLC(567) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33-4 MOVE BIT: MOVBC(568). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33-5 BIT COUNTER: BCNTC(621) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33-6 GET VARIABLE ID: GETID(286) . . . . . . . . . . . . . . . . . . . . . . . . .

1016 1018 1020 1022 1024 1026 1029 1030 1032 1035 1040 1040 1043 1047 1049 1051 1054 1059 1061 1062

85

Notation and Layout of Instruction Descriptions

Section 3-1

3-1

Notation and Layout of Instruction Descriptions

Instructions are described in groups by function. Refer to Appendix C Alphabetical List of Instructions by Mnemonic for a list of instructions by mnemonic that lists the page number in this section for each instruction. The description of each instruction is organized as described in the following table.

Item Name and Mnemonic Purpose Ladder Symbol and Operand Names

Contents The heading of each section consists of the name of the instruction followed by the mnemonic with the function code in parentheses. Example: MOVE BIT: MOVB(082) The basic purpose of the instruction is described after the section heading. The ladder symbol used to represent the instruction on the CX-Programmer is shown, as in the example for the MOVE BIT instruction given below. The name of each operand is also provided with the ladder symbol.

MOVB(082) S C D
Variations Variations

S: Source word or data C: Control word D: Destination word

The variations that can be used to control execution of the instruction under special conditions are given using the mnemonic form. Any variation that is not supported by an instruction is given as Not supported. Executed Each Cycle for ON Condition: The instruction is executed as long as it receives an ON execution condition. Executed Once for Upward Differentiation: The instruction is executed during the next cycle only after the execution condition changes from OFF to ON. Executed Once for Downward Differentiation: The instruction is executed during the next cycle only after the execution condition changes from ON to OFF. Always Executed: The instruction does not require an execution condition and is executed each cycle. Creates ON Condition....: The instruction is executed each cycle to create an execution condition for the next instruction.
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation MOVB(082) @MOVB(082)

Variations

Variations

Executed Once for Downward Differenti- Not supported ation

Immediate Refreshing Specification

Immediate refreshing can be specified for some instructions to refresh I/O when the instruction is executed. If immediate refreshing is supported, the specification is given using the mnemonic form. If immediate refreshing is not support by an instruction Not supported is given.
Immediate Refreshing Specification Not supported.

Applicable Program Areas

The program areas in which the instruction can be used are specified. OK indicates the areas in which the instruction can be used.
Block program areas OK Step program areas OK Subroutines OK Interrupt tasks OK

86

Notation and Layout of Instruction Descriptions

Item Operands Contents

Section 3-1

Where necessary, the meaning of words and bits used in specific operands, such as control words, is given.
15 8 7 0

Source bit: 00 to 0F (0 to 15 decimal) Destination bit: 00 to 0F (0 to 15 decimal)

Operand Specifications

The memory areas addresses that can be used each operand are listed in a table like the following one. The letters used in the column headings on the left are the same as those used in the ladder symbol. --- is used to indicate when an area cannot be specific for an operand.
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 A448 to A959 C D

Description Flags

The function of the instruction and the operands used in the instruction are described. The flags table indicates the status of the condition flags immediately after execution of the instruction. Any flags that are not listed are not affected by the instruction. OFF indicates that a flag is turned OFF immediately after execution of the instruction regardless of the results of executing the instruction.
Name Error Flag Equals Flag Negative Flag ER = N Label Operation ON if control data is within ranges. OFF in all other cases. OFF OFF

Precautions Example

Special precautions required in using the instruction are provided. Be sure to read and follow these precautions. An example of using the instruction with specific operands is provided to further explain the function of the instruction.

Constants

Constants input for operands are given as listed below. Operand Descriptions and Operand Specifications Operands Specifying Bit Strings (Normally Input as Hexadecimal): Only the hexadecimal form is given for operands specifying bit strings, e.g., only #0000 to #FFFF is specified as the S operand for the MOV(021) instruction. On the CX-Programmer, however, bit strings can be input in decimal form by using the & prefix. Operands Specifying Numeric Values (Normally Input as Decimal, Including Jump Numbers): Both the decimal and hexadecimal forms are given for operands specifying numeric values, e.g., #0000 to #FFFF and &0 to &65535 are given for the N operand for the XFER(070) instruction.

87

Notation and Layout of Instruction Descriptions

Section 3-1

Operands Indicating Control Numbers (Except for Jump Numbers): The decimal form is given for control numbers, e.g., 0 to 1023 is given for the N operand for the SBS(091) instruction. Examples In the examples, constants are given using the CX-Programmer notation, e.g., operands specifying numeric values are given in decimal for with an & prefix, as shown in the following example.
XFER &10 D100 D200

The input methods for constants for the CX-Programmer are given in the following table.
Operand Operands specifying bit strings (normally input as hexadecimal) Operands specifying numeric values (normally input as decimal) Operands specifying control numbers (except for jump numbers) CX-Programmer Input as decimal with an & prefix or input as hexadecimal with an # prefix. (See note.) Input as decimal with an # prefix. (See note.)

Note Condition Flags

When operands are input on the CX-Programmer, the input ranges will be displayed along with the appropriate prefixes. Flag names are used for condition flags in this section. With the CX-Programmer, the condition flags are registered in advance as global symbols.
Flag name (Used in this section.) Error Flag Access Error Flag Carry Flag Greater Than Flag Equals Flag Less Than Flag Negative Flag Overflow Flag Underflow Flag Greater Than or Equals Flag Not Equal Flag Less Than or Equals Flag Always ON Flag Always OFF Flag CX-Programmer label P_ER P_AER P_CY P_GT P_EQ P_LT P_N P_OF P_UF P_GE P_NE P_LE P_On P_Off

Precautions for DM Area Addresses in CP1L L CPU Units

The DM Area is smaller in the CP1L L CPU Units, in comparison to the other CP-series CPU Units. The operand specifications listed in this Programming Manual are for CP1H and CP1L M (30 or 40-I/O point) CPU Units, so the entire listed DM Area address ranges may not be usable in the CP1L L (14 or 20 I/O point) CPU Units. When programming with the CX-Programmer, out-of-range DM Area addresses cannot be specified. In addition, if an invalid DM Area is set in the program, an error will occur when the program is transferred to the PLC.

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Section 3-2
The following table shows example DM Area ranges in the CP1L L CPU Units.

CP1H and CP1L M CPU Units

DM Area D00000 to D32767

CP1L L CPU Units

DM Area D00000 to D09999, D32000 to D32767 Indirect DM addresses in @D00000 to @D09999, binary @D30000 to @D32767 Indirect DM addresses in *D00000 to *D09999, BCD *D30000 to *D32767

Indirect DM addresses in @D00000 to @D32767 binary Indirect DM addresses in *D00000 to *D32767 BCD

3-2
3-2-1
Purpose

Sequence Input Instructions

LOAD: LD
Indicates a logical start and creates an ON/OFF execution condition based on the ON/OFF status of the specified operand bit.
Bus bar Starting point of block

Ladder Symbol

Variations
Variations Restarts Logic and Creates ON Each Cycle Operand Bit is ON Restarts Logic and Creates ON Once for Upward Differentiation Restarts Logic and Creates ON Once for Downward Differentiation Immediate Refreshing Specification Combined Refreshes Input Bit, Restarts Logic, and Variations Creates ON Once for Upward Differentiation Refreshes Input Bit, Restarts Logic, and Creates ON Once for Downward Differentiation LD @LD %LD !LD !@LD !%LD

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Task Flag Area Condition Flags Clock Pulses TR Area DM Area LD operand bit CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 T0000 to T4095 C0000 to C4095 TK00 to TK31 ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0 0.0 2s, 0.1 s, 0.2 s, 1 s, 1 min TR0 to TR15 ---

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Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers LD operand bit -----

Section 3-2

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) , ( )IR0 to, ( )IR15

Description

LD is used for the first normally open bit from the bus bar or for the first normally open bit of a logic block. If there is no immediate refreshing specification, the specified bit in I/O memory is read. If there is an immediate refreshing specification, the status of the Basic Input Units input terminal is read and used. LD is used in the following circumstances as an instruction for indicating a logical start. When directly connecting to the bus bar. When logic blocks are connected by AND LD or OR LD, i.e., at the beginning of a logic block. The AND LOAD and OR LOAD instructions are used to connect in series or in parallel logic blocks beginning with LD or LD NOT. At least one LOAD or LOAD NOT instruction is required for the execution condition when output-related instructions cannot be connected directly to the bus bar. If there is no LOAD or LOAD NOT instruction, a programming error will occur with the program check by the CX-Programmer. When logic blocks are connected by AND LOAD or OR LOAD instructions, the total number of AND LOAD/OR LOAD instructions must match the total number of LOAD/LOAD NOT instructions minus 1. If they do not match, a programming error will occur. For details, refer to 3-2-7 AND LOAD: AND LD and 3-2-8 OR LOAD: OR LD.

Flags Precautions

There are no flags affected by this instruction. Differentiate up (@) or differentiate down (%) can be specified for LD. If differentiate up (@) is specified, the execution condition is turned ON for one cycle only after the status of the operand bit goes from OFF to ON. If differentiate down (%) is specified, the execution condition is turned ON for one cycle only after the status of the operand bit goes from ON to OFF. Immediate refreshing (!) can be specified for LD. An immediate refresh instruction updates the status of the input bit for CPU Unit built-in inputs just before the instruction is executed. For LD, it is possible to combine immediate refreshing and up or down differentiation (!@ or !%). If either of these is specified, the built-in input is refreshed from the CPU Unit just before the instruction is executed and the execution condition is turned ON for one cycle only after the status goes from OFF to ON, or from ON to OFF.

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Example
0.00 0.01 0.02 0.04 0.05 0.03 100.00

Section 3-2

Instruction LD LD LD AND OR LD AND LD LD NOT AND OR LD OUT

Operand 0.00 0.01 0.02 0.03 ----0.04 0.05 --100.00

OR LD

AND LD

OR LD

3-2-2
Purpose

LOAD NOT: LD NOT

Indicates a logical start and creates an ON/OFF execution condition based on the reverse of the ON/OFF status of the specified operand bit.
Starting point of block

Ladder Symbol
Bus bar

Variations
Variations Restarts Logic and Creates ON Each Cycle Operand Bit is OFF Restarts Logic and Creates ON Once for Upward Differentiation Restarts Logic and Creates ON Once for Downward Differentiation Immediate Refreshing Specification Combined Refreshes Input Bit, Restarts Logic, and Creates ON Variations Once for Upward Differentiation Refreshes Input Bit, Restarts Logic, and Creates ON Once for Downward Differentiation LD NOT @LD NOT %LD NOT !LD NOT !@LD NOT !%LD NOT

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

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Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Task Flag Area Condition Flags Clock Pulses TR Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers

Section 3-2

LD NOT bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 T0000 to T4095 C0000 to C4095 TK00 to TK31 ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER 0.0 2s, 0.1 s, 0.2 s, 1 s, 1 min --------------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

LD NOT is used for the first normally closed bit from the bus bar, or for the first normally closed bit of a logic block. If there is no immediate refreshing specification, the specified bit in I/O memory is read and reversed. If there is an immediate refreshing specification, the status of the Basic Input Units input terminal is read, reversed, and used. LD NOT is used in the following circumstances as an instruction for indicating a logical start. When directly connecting to the bus bar. When logic blocks are connected by AND LD or OR LD. (Used at the beginning of a logic block.) The AND LOAD and OR LOAD instructions are used to connect in series or in parallel logic blocks beginning with LD or LD NOT. At least one LOAD or LOAD NOT instruction is required for the execution condition when output-related instructions cannot be connected directly to the bus bar. If there is no LOAD or LOAD NOT instruction, a program error will occur with the program check by the CX-Programmer. When logic blocks are connected by AND LOAD or OR LOAD instructions, the total number of AND LOAD/OR LOAD instructions must match the total number of LOAD/LOAD NOT instructions minus1. If they do not match, a programming error will occur.

Flags Precautions

There are no flags affected by this instruction. Immediate refreshing (!) can be specified for LD NOT. An immediate refresh instruction updates the status of the input bit for a CPU Unit built-in input just before the instruction is executed.

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Example
100.00

Section 3-2

0.00

0.01 0.02 0.03

0.04 0.05

Instruction LD LD LD AND OR LD AND LD LD NOT AND OR LD OUT

Operand 0.00 0.01 0.02 0.03 ----0.04 0.05 --100.00

OR LD

AND LD

OR LD

3-2-3
Purpose

AND: AND
Takes a logical AND of the status of the specified operand bit and the current execution condition.

Ladder Symbol

Variations
Variations Creates ON Each Cycle AND Result is ON Creates ON Once for Upward Differentiation Creates ON Once for Downward Differentiation Immediate Refreshing Specification Combined Refreshes Input Bit and Creates ON Once for Variations Upward Differentiation Refreshes Input Bit and Creates ON Once for Downward Differentiation AND @AND %AND !AND !@AND !%AND

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

93

Sequence Input Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Task Flag Area Condition Flags Clock Pulses TR Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers

Section 3-2

AND bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 T0000 to T4095 C0000 to C4095 TK00 to TK31 ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min --------------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

AND is used for a normally open bit connected in series. AND cannot be directly connected to the bus bar, and cannot be used at the beginning of a logic block. If there is no immediate refreshing specification, the specified bit in I/O memory is read. If there is an immediate refreshing specification, the status of the CPU Units input terminal is read. There are no flags affected by this instruction. Differentiate up (@) or differentiate down (%) can be specified for AND. If differentiate up (@) is specified, the execution condition is turned ON for one cycle only after the status of the operand bit goes from OFF to ON. If differentiate down (%) is specified, the execution condition is turned ON for one cycle only after the status of the operand bit goes from ON to OFF. Immediate refreshing (!) can be specified for AND. An immediate refresh instruction updates the status of the input bit for CPU Unit built-in inputs just before the instruction is executed. For AND, it is possible to combine immediate refreshing and up or down differentiation (!@ or !%). If either of these is specified, the input is refreshed from the CPU Unit just before the instruction is executed and the execution condition is turned ON for one cycle only after the status goes from OFF to ON, or from ON to OFF.

Flags Precautions

94

Sequence Input Instructions

Example
0.00 0.01 0.02 0.04 0.03 0.05 100.00

Section 3-2

Instruction LD AND LD AND LD AND NOT OR LD AND LD OUT

Operand 0.00 0.01 0.02 0.03 0.04 0.05 ----100.00

3-2-4
Purpose

AND NOT: AND NOT

Reverses the status of the specified operand bit and takes a logical AND with the current execution condition.

Ladder Symbol

Variations
Creates ON Each Cycle AND NOT Result is ON Creates ON Once for Upward Differentiation Creates ON Once for Downward Differentiation Immediate Refreshing Specification Combined Refreshes Input Bit and Creates ON Once for Variations Upward Differentiation Refreshes Input Bit and Creates ON Once for Downward Differentiation Variations AND NOT @AND NOT %AND NOT !AND NOT !@AND NOT !%AND NOT

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Task Flag Area Condition Flags AND NOT bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 T0000 to T4095 C0000 to C4095 TK00 to TK31 ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER

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Area Clock Pulses TR Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers AND NOT bit operand 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min ---------

Section 3-2

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

AND NOT is used for a normally closed bit connected in series. AND NOT cannot be directly connected to the bus bar, and cannot be used at the beginning of a logic block. If there is no immediate refreshing specification, the specified bit in I/O memory is read. If there is an immediate refreshing specification, the status the CPU Units input terminals is read. There are no flags affected by this instruction. Immediate refreshing (!) can be specified for AND NOT. An immediate refresh instruction updates the status of the input bit for CPU Unit built-in inputs just before the instruction is executed.

Flags Precautions

Example
0.00 0.01 0.02 0.04 0.03 0.05 100.00

Instruction LD AND LD AND LD AND NOT OR LD AND LD OUT 0.00 0.01 0.02 0.03 0.04 0.05 ----100.00

Operand

96

Sequence Input Instructions

Section 3-2

3-2-5
Purpose

OR: OR
Takes a logical OR of the ON/OFF status of the specified operand bit and the current execution condition.
Bus bar

Ladder Symbol

Variations
Creates ON Each Cycle OR Result is ON Creates ON Once for Upward Differentiation Creates ON Once for Downward Differentiation Immediate Refreshing Specification Combined Refreshes Input Bit and Creates ON Once for Variations Upward Differentiation Refreshes Input Bit and Creates ON Once for Downward Differentiation Variations OR @OR %OR !OR !@OR !%OR

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Task Flag Area Condition Flags Clock Pulses DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers OR bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 T0000 to T4095 C0000 to C4095 TK00 to TK31 ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min ------------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

97

Sequence Input Instructions

Description

Section 3-2
OR is used for a normally open bit connected in parallel. A normally open bit is configured to form a logical OR with a logic block beginning with a LOAD or LOAD NOT instruction (connected to the bus bar or at the beginning of the logic block). If there is no immediate refreshing specification, the specified bit in I/O memory is read. If there is an immediate refreshing specification, the status of the CPU Units input terminal is read. There are no flags affected by this instruction. Differentiate up (@) or differentiate down (%) can be specified for OR. If differentiate up (@) is specified, the execution condition is turned ON for one cycle only after the status of the operand bit goes from OFF to ON. If differentiate down (%) is specified, the execution condition is turned ON for one cycle only after the status of the operand bit goes from ON to OFF. Immediate refreshing (!) can be specified for OR. An immediate refresh instruction updates the status of the input bit for a CPU Unit built-in input just before the instruction is executed. For OR, it is possible to combine immediate refreshing and up or down differentiation (!@ or !%). If either of these is specified, the input is refreshed from the CPU Unit just before the instruction is executed and the execution condition is turned ON for one cycle only after the status of the operand bit goes from OFF to ON, or from ON to OFF.

Flags Precautions

Example
0.00 0.03 0.01 0.02 0.04 0.05 0.07 0.06 100.00

Instruction LD AND AND OR AND LD AND OR NOT AND LD OUT 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 --100.00

Operand

3-2-6
Purpose

OR NOT: OR NOT
Reverses the status of the specified bit and takes a logical OR with the current execution condition.
Bus bar

Ladder Symbol

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Sequence Input Instructions

Variations
Variations Creates ON Each Cycle OR NOT Result is ON Creates ON Once for Upward Differentiation Creates ON Once for Downward Differentiation Immediate Refreshing Specification Combined Refreshes Input Bit and Creates ON Once for Variations Upward Differentiation Refreshes Input Bit and Creates ON Once for Downward Differentiation

Section 3-2

OR NOT @OR NOT %OR NOT !OR NOT !@OR NOT !%OR NOT

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Task Flag Area Condition Flags Clock Pulses TR Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers OR NOT bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 T0000 to T4095 C0000 to C4095 TK00 to TK31 ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min --------------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

OR NOT is used for a normally closed bit connected in parallel. A normally closed bit is configured to form a logical OR with a logic block beginning with a LOAD or LOAD NOT instruction (connected to the bus bar or at the beginning of the logic block). If there is no immediate refreshing specification, the specified bit in I/O memory is read. If there is an immediate refreshing specification, the status of the CPU Units input terminal is read. There are no flags affected by this instruction. Immediate refresh (!) can be specified for OR NOT. An immediate refresh instruction updates the status of the input bit from a CPU Unit built-in input just before the instruction is executed.

Flags Precautions

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Sequence Input Instructions

Example
0.00 0.03 0.01 0.02 0.04 0.05 0.07 0.06 100.00

Section 3-2

Instruction LD AND AND OR AND LD AND OR NOT AND LD OUT

Operand 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 --100.00

3-2-7
Purpose

AND LOAD: AND LD

Takes a logical AND between logic blocks.

Ladder Symbol
Logic block Logic block

Variations
Variations Creates ON Each Cycle AND Result is ON Immediate Refreshing Specification AND LD Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Description

AND LD connects in series the logic block just before this instruction with another logic block.
LD
to Logic block A

LD
to Logic block B

AND LD

Serial connection between logic block A and logic block B.

The logic block consists of all the instructions from a LOAD or LOAD NOT instruction until just before the next LOAD or LOAD NOT instruction on the same rungs.

100

Sequence Input Instructions

Section 3-2
In the following diagram, the two logic blocks are indicated by dotted lines. Studying this example shows that an ON execution condition will be produced when either of the execution conditions in the left logic block is ON (i.e., when either CIO 0.00 or CIO 0.01 is ON) and either of the execution conditions in the right logic block is ON (i.e., when either CIO 0.02 is ON or CIO 0.03 is OFF).
0.00 0.01 0.02 0.03 100.00

Flags Precautions

There are no flags affected by this instruction. Three or more logic blocks can be connected in series using this instruction to first connect two of the logic blocks and then to connect the next and subsequent ones in order. It is also possible to continue placing this instruction after three or more logic blocks and connect them together in series. When a logic block is connected by AND LOAD or OR LOAD instructions, the total number of AND LOAD/OR LOAD instructions must match the total number of LOAD/LOAD NOT instructions minus 1. If they do not match, a program error will occur.

Example
0.00 0.01 0.02 0.03 0.04 0.05 100.00

Coding Example (1)

Instruction LD OR NOT LD NOT OR AND LD LD OR AND LD . . OUT Operand 0.00 0.01 0.02 0.03 --0.04 0.05 --. . 100.00

Coding Example (2)

Instruction LD OR NOT LD NOT OR LD OR . . Operand 0.00 0.01 0.02 0.03 0.04 0.05 . .

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Sequence Input Instructions

Instruction AND LD AND LD . . OUT Operand ----. . 100.00

Section 3-2

The AND LOAD instruction can be used repeatedly. In programming method (2) above, however, the number of AND LOAD instructions becomes one less than the number of LOAD and LOAD NOT instructions before that. In method (2), make sure that the total number of LOAD and LOAD NOT instructions before AND LOAD is not more than eight. To use nine or more, program using method (1). If there are nine or more with method (2), then a program error will occur during the program check by the CX-Programmer. Coding
Address 000000 000001 000002 000003 000004 000005 Instruction LD OR LD OR NOT AND LD OUT Operand 0.00 0.01 0.02 0.03 --100.00

Second LD: Used for first bit of next block connected in series to previous block.

3-2-8
Purpose

OR LOAD: OR LD
Takes a logical OR between logic blocks.

Ladder Symbol
Logic block

Logic block

Variations
Variations Creates ON Each Cycle AND Result is ON Immediate Refreshing Specification OR LD Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

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Description

Section 3-2
AND LD connects in parallel the logic block just before this instruction with another logic block.
LD
to Logic block A

LD
to Logic block B

OR LD

Parallel connection between logic block A and logic block B.

The logic block consists of all the instructions from a LOAD or LOAD NOT instruction until just before the next LOAD or LOAD NOT instruction on the same rungs. The following diagram requires an OR LOAD instruction between the top logic block and the bottom logic block. An ON execution condition would be produced either when CIO 0.00 is ON and CIO 0.01 is OFF or when CIO 0.02 and CIO 0.03 are both ON. The operation of and mnemonic code for the OR LOAD instruction is exactly the same as those for a AND LOAD instruction except that the current execution condition is ORed with the last unused execution condition.
0.00 0.02 0.01 0.03 100.00

Flags Precautions

There are no flags affected by this instruction. Three or more logic blocks can be connected in parallel using this instruction to first connect two of the logic blocks and then to connect the next and subsequent ones in order. It is also possible to continue placing this instruction after three or more logic blocks and connect them together in parallel. When a logic block is connected by AND LOAD or OR LOAD instructions, the total number of AND LOAD/OR LOAD instructions must match the total number of LOAD/LOAD NOT instructions minus 1. If they do not match, a programming error will occur.

Example
0.00 0.02 0.01 0.03 100.00

0.04

0.05

Coding Example (1)

Instruction LD AND NOT LD NOT AND NOT OR LD Operand 0.00 0.01 0.02 0.03 ---

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Instruction LD AND OR LD . . OUT 0.04 0.05 --. . 100.00 Operand

Section 3-2

Coding Example (2)

Instruction LD AND NOT LD NOT AND NOT LD AND . . OR LD OR LD . . OUT 0.00 0.01 0.02 0.03 0.04 0.05 . . ----. . 100.00 Operand

The OR LOAD instruction can be used repeatedly. In programming method (2) above, however, the number of OR LOAD instructions becomes one less than the number of LOAD and LOAD NOT instructions before that. In method (2), make sure that the total number of LOAD and LOAD NOT instructions before OR LOAD is not more than eight. To use nine or more, program using method (1). If there are nine or more with method (2), then a program error will occur during the program check by the CX-Programmer. Coding
Address 000100 000101 000102 000103 000104 000105 Instruction LD AND NOT LD AND OR LD OUT Operand 0.00 0.01 0.02 0.03 --100.00

Second LD: Used for first bit of next block connected in series to previous block.

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Section 3-2

3-2-9

Differentiated and Immediate Refreshing Instructions

The LOAD, AND, and OR instructions have differentiated and immediate refreshing variations in addition to their ordinary forms, and there are also two combinations available. The LOAD NOT, AND NOT, OR NOT, OUT, and OUT NOT instructions have immediate refreshing variations in addition to their ordinary forms. The I/O timing for data handled by instructions differs for ordinary and differentiated instructions, immediate refreshing instructions, and immediate refreshing differentiated instructions. Ordinary and differentiated instructions are executed using data input by previous I/O refresh processing, and the results are output with the next I/O processing. Here I/O refreshing means the data exchanged between the CPUs internal memory and CPU Unit built-in I/O, CPM1A Expansion Units, and CPM1A Expansion I/O Units. In addition to the above I/O refreshing, an immediate refresh instruction exchanges data with the I/O Unit for those words that are accessed by the instruction. An immediate refresh instruction refreshes all of the bits in the word containing the specified bit.

Instruction variation Mnemonic Ordinary LD, AND, OR, LD NOT, AND NOT, OR NOT

OUT, OUT NOT

Differentiated up

@LD, @AND, @OR

Differentiated down

%LD, %AND, %OR

Immediate refresh

!LD, !AND, !OR, !LD NOT, !AND NOT, !OR NOT !OUT, !OUT NOT

Differentiated up / immediate refresh

!@LD, !@AND, !@OR

Differentiated down / immediate refresh

!%LD, !%AND, !%OR

Function The ON/OFF status of the specified bit is taken by the CPU with cyclic refreshing, and it is reflected in the next instruction execution. After the instruction is executed, the ON/ OFF status of the specified bit is output with the next cyclic refreshing. The instruction is executed once when the specified bit turns from OFF to ON and the ON state is held for one cycle. The instruction is executed once when the specified bit turns from ON to OFF and the ON state is held for one cycle. The input data for the specified bit is taken by the CPU and the instruction is executed. After the instruction is executed, the data for the specified bit is output. The input data for the specified bit is refreshed by the CPU, and the instruction is executed once when the bit turns from OFF to ON and the ON state is held for one cycle. The input data for the specified bit is refreshed by the CPU, and the instruction is executed once when the bit turns from ON to OFF and the ON state is held for one cycle.

I/O refresh Cyclic refreshing

Before instruction execution After instruction execution Before instruction execution

Note

Immediate refresh instructions (i.e., instructions with !) can be used only for built-in I/O on the CPU Unit. They cannot be used for I/O on CPM1A Expansion Units or CPM1A Expansion I/O Units. Use IORF(097) for I/O on CPM1A Expansion Units or CPM1A Expansion I/O Units.

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Section 3-2

3-2-10 Operation Timing for I/O Instructions

The following chart shows the differences in the timing of instruction operations for a program configured from LD and OUT.
Input received

Input received
! ! ! ! ! ! !

Input received Input received

Input received Input received

Input received

Input received Input received Input received Input received Input received

! ! ! ! ! ! CPU processing

Instruction execution

I/O refreshing

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Section 3-2

3-2-11 TR Bits
TR bits are used to temporarily retain the ON/OFF status of execution conditions in a program when programming in mnemonic code. They are not used when programming directly in ladder program form because the processing is automatically executed by the CX-Programmer. The following diagram shows a simple application using two TR bits.
0.00 0.01 0.02 0.03 0.04 0.05 100.00 100.01 100.02 100.03

Address Instruction Operands 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 LD OUT AND OUT AND OUT LD AND OUT LD AND OUT LD AND NOT OUT 0.00 TR0 0.01 TR1 0.02 100.00 TR1 0.03 100.01 TR0 0.04 100.02 TR0 0.05 100.03

Using TR0 to TR15

TR0 to TR15 are used only with LOAD and OUTPUT instructions. There are no restrictions on the order in which the bit addresses are used. Sometimes it is possible to simplify a program by rewriting it so that TR bits are not required. The following diagram shows one case in which a TR bit is unnecessary and one in which a TR bit is required.

In instruction block (1), the ON/OFF status at point A is the same as for output CIO 100.00, so AND 0.01 and OUT 100.01 can be coded without requiring a TR bit. In instruction block (2), the status of the branching point and that of output CIO 100.02 are not necessarily the same, so a TR bit must be used. In this case, the number of steps in the program could be reduced by using instruction block (1) in place of instruction block (2). TR0 to TR15 Considerations TR bits are used only for retaining (OUT TR0 to TR15) and restoring (LD TR0 to TR15) the ON/OFF status of branching points in programs with many output branches. They are thus different from general bits, and cannot be used with AND or OR instructions, or with instructions that include NOT.

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TR0 to TR15 output Duplication

Section 3-2
A TR bit address cannot be repeated within the same block in a program with many output branches, as shown in the following diagram. It can, however, be used again in a different block.
0.00 0.01 0.02 0.03 0.04 100.00 100.01 100.02

to 0.10 0.11 0.12 0.13 110.00 110.01 110.02 110.03 110.04

0.14 0.15 1.00 1.01

3-2-12 NOT: NOT(520)

Purpose Ladder Symbol
NOT(520)

Reverses the execution condition.

Variations
Variations Reverses the Execution Condition Each Cycle Immediate Refreshing Specification NOT(520) Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Description Flags Precautions Example

NOT(520) is placed between an execution condition and another instruction to invert the execution condition. There are no flags affected by NOT(520) NOT(520) is an intermediate instruction, i.e., it cannot be used as a right-hand instruction. Be sure to program a right-hand instruction after NOT(520). NOT(520) reverses the execution condition in the following example.
0.00 0.01 100.00

0.02

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Section 3-2
The following table shows the operation of this program section.
CIO 0.00 1 1 1 0 1 0 0 0 1 1 0 1 0 1 0 0 Input bit status CIO 0.01 1 0 1 1 0 0 1 0 CIO 0.02 Output bit status CIO 0.03 0 0 1 0 1 1 1 1

3-2-13 CONDITION ON/OFF: UP(521) and DOWN(522)

Purpose UP(521) turns ON the execution condition for the next instruction for one cycle when the execution condition it receives goes from OFF to ON. DOWN(522) turns ON the execution condition for the next instruction for one cycle when the execution condition it receives goes from ON to OFF.

Ladder Symbols
UP(521) DOWN(522)

Variations
Variations Creates ON Once for Upward Differentiation Immediate Refreshing Specification Variations Creates ON Once for Downward Differentiation Immediate Refreshing Specification UP(521) Not supported UP(522) Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Description

UP(521) is placed between an execution condition and another instruction to turn the execution condition into an up-differentiated condition. UP(521) causes the connecting instruction to be executed just once when the execution condition goes from OFF to ON. DOWN(522) is placed between an execution condition and another instruction to turn the execution condition into a down-differentiated condition. DOWN(522) causes the connecting instruction to be executed just once when the execution condition goes from ON to OFF. The DIFU(013) and DIFD(014) instructions can also be used for the same purpose, but they require work bits. UP(521) and DOWN(522) simplify programming by reducing the number of work bits and program addresses needed.

Flags Precautions

There are no flags affected by UP(521) and DOWN(522). UP(521) and DOWN(522) are intermediate instructions, i.e., they cannot be used as right-hand instructions. Be sure to program a right-hand instruction after UP(521) or DOWN(522).

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Section 3-2
The operation of UP(521) and DOWN(522) depends on the execution condition for the instruction as well as the execution condition for the program section when it is programmed in an interlocked program section, a jumped program section, or a subroutine. Refer to 3-4-4 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003), 3-4-6 JUMP and JUMP END: JMP(004) and JME(005), and 3-19 Interrupt Control Instructions for details.

Examples

When CIO 0.00 goes from OFF to ON in the following example, CIO 100.00 is turned ON for just one cycle.
0.00 100.00

0.00

100.00

Cycle time

When CIO 0.00 goes from ON to OFF in the following example, CIO 100.01 is turned ON for just one cycle.
0.00 100.01

0.00 100.01

Cycle time

3-2-14 BIT TEST: TST(350) and TSTN(351)

Purpose LD TST(350), AND TST(350), and OR TST(350) are used in the program like LD, AND, and OR; the execution condition is ON when the specified bit in the specified word is ON, and OFF when the bit is OFF. LD TSTN(351), AND TSTN(351), and OR TSTN(351) are used in the program like LD NOT, AND NOT, and OR NOT; the execution condition is OFF when the specified bit in the specified word is ON, and ON when the bit is OFF. Ladder Symbols
TST(350) S N S: Source word N: Bit number

TSTN(351) S N S: Source word N: Bit number

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Variations
Variations Executed Each Cycle Immediate Refreshing Specification Variations Executed Each Cycle Immediate Refreshing Specification

Section 3-2

TST(350) Not supported TSTN(351) Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

N: Bit number The bit number must be between 0000 and 000F hexadecimal or between &0000 and &0015 decimal. Only the rightmost bit (0 to F hexadecimal) of the contents of the word is valid when a word address is specified.

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to #000F (binary) or &0 to &15 N

DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 , IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

LD TST(350), AND TST(350), and OR TST(350) can be used in the program like LD, AND, and OR; the execution condition is ON when the specified bit in the specified word is ON and OFF when the bit is OFF. Unlike LD, AND, and OR, bits in the DM area can be used as operands in TST(350). LD TSTN(351), AND TSTN(351), and OR TSTN(351) can be used in the program like LD NOT, AND NOT, and OR NOT; the execution condition is OFF when the specified bit in the specified word is ON and ON when the bit is OFF. Unlike LD NOT, AND NOT, and OR NOT, bits in the DM area can be used as operands in TSTN(351).

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF or unchanged OFF or unchanged OFF or unchanged

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Precautions

Section 3-2
TST(350) and TSTN(351) are intermediate instructions, i.e., they cannot be used as right-hand instructions. Be sure to program a right-hand instruction after TST(350) or TSTN(351). LD TST(350) and LD TSTN(351) In the following example, CIO 100.01 is turned ON when bit 3 of D10 is ON.
100.01 D10 &3

Examples

In the following example, CIO 100.02 is turned ON when bit 3 of D10 is OFF.
100.02 D10 &3

AND TST(350) and AND TSTN(351) In the following example, CIO 100.01 is turned ON when CIO 0.00 and bit 3 of D10 are both ON.
0.00 D10 &3 100.01

In the following example, CIO 100.02 is turned ON when CIO 0.01 is ON and bit 3 of D10 is OFF.
0.01 D10 &3 100.02

OR TST(350) and OR TSTN(351) In the following example, CIO 100.01 is turned ON when CIO 0.00 or bit 3 of D10 is ON.
0.00 100.01

D10 &3

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Section 3-3

In the following example, CIO 100.02 is turned ON when CIO 0.01 is ON or bit 3 of D10 is OFF.
0.01 100.02

D10 &3

3-3
3-3-1
Purpose

Sequence Output Instructions

OUTPUT: OUT
Outputs the result (execution condition) of the logical processing to the specified bit.

Ladder Symbol

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification OUT Not supported. Not supported. !OUT

Applicable Program Areas

Block program areas Not allowed Step program areas OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area TR Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers OUT bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A448.00 to A959.15 ----TR0 to TR15 -----------

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Area Index Registers Indirect addressing using Index Registers

Section 3-3
OUT bit operand --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to ,IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

If there is no immediate refreshing specification, the status of the execution condition (power flow) is written to the specified bit in I/O memory. If there is an immediate refreshing specification, the status of the execution condition (power flow) is also written to the CPU Units output terminal in addition to the output bit in I/O memory. There are no flags affected by this instruction. Immediate refreshing (!) can be specified for OUT and OUT NOT. An immediate refresh instruction updates the status of the output terminal on the CPU Unit just after the instruction is executed at the same time as it writes the status of the execution condition (power flow) to the specified output bit in I/O memory.
100.00 100.01

Flags Precautions

Example
0.00

Instruction LD OUT OUT NOT 0.00 100.00 100.01

Operand

3-3-2
Purpose

OUTPUT NOT: OUT NOT

Reverses the result (execution condition) of the logical processing, and outputs it to the specified bit.

Ladder Symbol

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification OUT NOT Not supported. Not supported. !OUT NOT

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

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Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area TR Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers OUT bit operand CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A448.00 to A959.15 ----TR0 to TR15 -------

Section 3-3

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to ,IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

If there is no immediate refreshing specification, the status of the execution condition (power flow) is reversed and written to a specified bit in I/O memory. If there is an immediate refreshing specification, the status of the execution condition (power flow) is reversed and also written to the CPU Units output terminal in addition to the output bit in I/O memory. There are no flags affected by this instruction.
100.00 100.01

Flags Example

0.00

Instruction LD OUT OUT NOT 0.00 0.01 0.02

Operand

3-3-3
Purpose

KEEP: KEEP(011)
Operates as a latching relay.

Ladder Symbol
S (Set) KEEP(011) B R (Reset) B: Bit

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Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-3

KEEP(011) Not supported Not supported !KEEP(011)

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers B CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A448.00 to A959.15 ----------------,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

When S turns ON, the designated bit will go ON and stay ON until reset, regardless of whether S stays ON or goes OFF. When R turns ON, the designated bit will go OFF. The relationship between execution conditions and KEEP(011) bit status is shown below.
Set

Reset

ON

S execution condition OFF

ON

R execution condition OFF

ON

Status of C

OFF

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Section 3-3

If S and R are ON simultaneously, the reset input takes precedence.

Set Reset Status of C

The set input (S) cannot be received while R is ON.

Set Reset Status of C

KEEP(011) has an immediate refreshing variation (!KEEP(011)). When an external output bit has been specified for B in a !KEEP(011) instruction, any changes to B will be refreshed when !KEEP(011) is executed and reflected immediately in the output bit for the CPU Unit built-in output. KEEP(011) operates like the self-maintaining bit, but a self-maintaining bit programmed with KEEP(011) requires one less instruction.
0.02 0.03 100.00

100.00

0.02 100.00 0.03

Self-maintaining bits programmed with KEEP(011) will maintain status even in an interlock program section, unlike the self-maintaining bit programmed without KEEP(011).

Output bit C will maintain its previous status in an interlock.

Output bit C will be turned OFF in an interlock.

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KEEP(011) can be used to create flip-flops as shown below.

Section 3-3

If a holding bit is used for B, the bit status will be retained even during a power interruption. KEEP(011) can thus be used to program bits that will maintain status after restarting the PLC following a power interruption. An example of this that can be used to produce a warning display following a system shutdown for an emergency situation is shown below.
0.02 H0.00 0.03
Indicates emergency situation

0.04

0.05

Reset input

H0.00

100.00 Activates
warning display

The status of I/O Area bits can be retained in the event of a power interruption by turning ON the IOM Hold Bit and setting IOM Hold Bit Hold in the PLC Setup. In this case, I/O Area bits used in KEEP(011) will maintain status after restarting the PLC following a power interruption, just like holding bits. Be sure to restart the PLC after changing the PLC Setup; otherwise the new settings will not be used. Flags Precautions No flags are affected by KEEP(011). Never use an input bit in a normally closed condition on the reset (R) for KEEP(011) when the input device uses an AC power supply. The delay in shutting down the PLCs DC power supply (relative to the AC power supply to the input device) can cause the operand bit of KEEP(011) to be reset. This situation is shown below.
Input Unit A S KEEP 120000 A

NEVER

The operands for KEEP(011) are input in a different order in ladder diagrams and mnemonic code. Ladder diagram order: Set input KEEP(011) Reset input Mnemonic code order: Set input Reset input KEEP(011)

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Example

Section 3-3

When CIO 0.00 goes ON in the following example, CIO 100.00 is turned ON. CIO 100.00 remains ON until CIO 0.01 goes ON. When CIO 0.02 goes ON and CIO 0.03 goes OFF in the following example, CIO 100.01 is turned ON. CIO 100.01 remains ON until CIO 0.04 or CIO 0.05 goes ON.
0.00 100.00 0.01

0.02

0.03 100.01

0.04

0.05

Coding
Address 000100 000101 000102 000103 000104 000105 000106 000107 Instruction LD LD KEEP (011) LD AND NOT LD OR KEEP (011) 0.00 0.01 100.00 0.02 0.03 0.04 0.05 100.01 Operand

Note

KEEP(011) is input in different orders on in ladder and mnemonic form. In ladder form, input the set input, KEEP(011), and then the reset input. In mnemonic form, input the set input, the reset input, and then KEEP(011).

3-3-4
Purpose

DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014)

DIFU(013) turns the designated bit ON for one cycle when the execution condition goes from OFF to ON (rising edge). DIFD(014) turns the designated bit ON for one cycle when the execution condition goes from ON to OFF (falling edge).

Ladder Symbols
DIFU(013) B B: Bit

DIFD(014) B B: Bit

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Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-3

Not supported DIFU(013) Not supported !DIFU(013) Not supported DIFD(014) Not supported !DIFD(014)

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers B CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A448.00 to A959.15 ----------------,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to ,15( ) IR

Description

When the execution condition goes from OFF to ON, DIFU(013) turns B ON. When DIFU(013) is reached in the next cycle, B is turned OFF.
Execution condition

Status of B 1 cycle

When the execution condition goes from ON to OFF, DIFD(014) turns B ON. When DIFD(014) is reached in the next cycle, B is turned OFF.
Execution condition

Status of B 1 cycle

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Section 3-3

DIFU(013) and DIFD(014) have immediate refreshing variations (!DIFU(013) and !DIFD(014)). When an external output bit has been specified for B in one of these instructions, any changes to B will be refreshed when the instruction is executed and reflected immediately in the output bit for the CPU Unit built-in output. UP(521) and DOWN(522) can be used to execute an instruction for just one cycle when the execution condition goes from OFF ON or ON OFF. Refer to 3-2-13 CONDITION ON/OFF: UP(521) and DOWN(522) for details. Flags Precautions No flags are affected by DIFU(013) and DIFD(014). The operation of DIFU(013) or DIFD(014) depends on the execution condition for the instruction itself as well as the execution condition for the program section when it is programmed in an interlocked program section, a jumped program section, or a subroutine. Refer to 3-4-4 INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003), 3-4-6 JUMP and JUMP END: JMP(004) and JME(005), and 3-19 Interrupt Control Instructions for details. If DIFU(013) is used in a FOR-NEXT loop and the loop repeats in a cycle, the controlled bit will be always ON or always OFF within that loop. Examples Operation of DIFU(013) When CIO 0.00 goes from OFF to ON in the following example, CIO 100.00 is turned ON for one cycle.
0.00 100.00

0.00 100.00 1 cycle 1 cycle

Operation of DIFD(014) When CIO 0.00 goes from ON to OFF in the following example, CIO 100.00 is turned ON for one cycle.
0.00 100.00 0.00

100.00 1 cycle 1 cycle

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Section 3-3

3-3-5
Purpose

SET and RESET: SET and RSET

SET turns the operand bit ON when the execution condition is ON. RSET turns the operand bit OFF when the execution condition is ON.

Ladder Symbols
SET B B: Bit

RSET B B: Bit

Variations
Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification Combined Executed Once and Bit Refreshed variations Immediately for Upward Differentiation Executed Once and Bit Refreshed Immediately for Downward Differentiation Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification Combined Immediate Refreshing Once for Upward Variations Differentiation Immediate Refreshing Once for Downward Differentiation Variations Variations SET @SET %SET !SET !@SET !%SET

RSET @RSET %RSET !RSET !@RSET !%RSET

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A448.00 to A959.15 --------------B

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Area Index Registers Indirect addressing using Index Registers

Section 3-3
B --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to ,( ) IR15

Description

SET turns the operand bit ON when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF. Use RSET to turn OFF a bit that has been turned ON with SET.
Execution condition of SET Status of B

RSET turns the operand bit OFF when the execution condition is ON, and does not affect the status of the operand bit when the execution condition is OFF. Use SET to turn ON a bit that has been turned OFF with RSET.
Execution condition of RSET Status of B

SET and RSET have immediate refreshing variations (!SET and !RSET). When an external output bit has been specified for B in one of these instructions, any changes to B will be refreshed when the instruction is executed and reflected immediately in the output bit for the CPU Unit built-in output. The set and reset inputs for a KEEP(011) instruction must be programmed with the instruction, but the SET and RSET instructions can be programmed completely independently. Furthermore, the same bit may be used as the operand in any number of SET or RSET instructions. Flags Precautions No flags are affected by SET and RSET. SET and RSET cannot be used to set and reset timers and counters. When SET or RSET is programmed between IL(002) and ILC(003) or JMP(004) and JME(005), the status of the specified bit will not be changed if the program section is interlocked or jumped.

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Example Differences between OUT/OUT NOT and SET/RSET

Section 3-3

The operation of SET differs from that of OUT because the OUT instruction turns the operand bit OFF when its execution condition is OFF. Likewise, RSET differs from OUT NOT because OUT NOT turns the operand bit ON when its execution condition is OFF.
0.00 100.00 CIO 100.00 is turned ON/OFF when CIO 0.00 goes ON/OFF.

0.01 100.01 0.02 100.01 CIO 100.01 is turned ON when CIO 0.01 goes ON; it remains ON until CIO 0.02 goes ON.

3-3-6
Purpose

MULTIPLE BIT SET/RESET: SETA(530)/RSTA(531)

SETA(530) turns ON the specified number of consecutive bits. RSTA(531) turns OFF the specified number of consecutive bits.

Ladder Symbols
SETA(530) D N1 N2 RSTA(531) D N1 N2 D: Beginning word N1: Beginning bit N2: Number of bits D: Beginning word N1: Beginning bit N2: Number of bits

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SETA(530) @SETA(530) Not supported Not supported RSTA(531) @RSTA(531) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

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Operands D: Beginning Word Specifies the first word in which bits will be turned ON or OFF. N1: Beginning Bit

Section 3-3

Specifies the first bit which will be turned ON or OFF. N1 must be #0000 to #000F (&0 to &15). N2: Number of Bits Specifies the number of bits which will be turned ON or OFF. N2 must be #0000 to #FFFF (&0 to &65535). Note The bits being turned ON or OFF must be in the same data area. (The range of words is roughly D to D+N216.)

D to D: 4,096 words max.

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants D N1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --N2

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

#0000 to #000F #0000 to #FFFF (binary) or &0 to (binary) or &0 to &15 &65535 DR0 to DR15

Description

The operation of SETA(530) and RSTA(531) are described separately below. Operation of SETA(530) SETA(530) turns ON N2 bits, beginning from bit N1 of D, and continuing to the left (more-significant bits). All other bits are left unchanged. (No changes will be made if N2 is set to 0.)

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Section 3-3

Bits turned ON by SETA(530) can be turned OFF by any other instructions, not just RSTA(531).

N2 bits are set to 1 (ON).

SETA(530) can be used to turn ON bits in data areas that are normally accessed by words only, such as the DM area. Operation of RSTA(531) RSTA(531) turns OFF N2 bits, beginning from bit N1 of D, and continuing to the left (more-significant bits). All other bits are left unchanged. (No changes will be made if N2 is set to 0.) Bits turned OFF by RSTA(531) can be turned ON by any other instructions, not just SETA(530).

N2 bits are reset to 0 (OFF).

RSTA(531) can be used to turn OFF bits in data areas that are normally accessed by words only, such as the DM area. Flags
Name Error Flag Label ER Operation ON if N1 is not within the specified range of 0000 to 000F. OFF in all other cases.

Examples

SETA(530) Example When CIO 0.00 is turned ON in the following example, the 20 bits (0014 hexadecimal) beginning with bit 5 of CIO 200 are turned ON.
0.00 N1: Bit 5 200 &5 &20 D: 200 201 N2: 20 bits

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RSTA(531) Example

Section 3-3

When CIO 0.01 is turned ON in the following example, the 20 bits (0014 hexadecimal) beginning with bit 3 of CIO 210 are turned OFF.
0.01 N1: Bit 3 210 &3 &20 D: 210 211 N2: 20 bits

3-3-7
Purpose

SINGLE BIT SET/RESET: SETB(532)/RSTB(533)

SETB(532) turns ON the specified bit. RSTB(533) turns OFF the specified bit.

Ladder Symbols
SETB(532)

D N
RSTB(533)

D: Word address N: Bit number

D N

D: Word address N: Bit number

Variations
Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification Combined Executed Once and Bit Refreshed Variations Immediately for Upward Differentiation Executed Once and Bit Refreshed Immediately for Downward Differentiation Variations Variations SETB(532) @SETB(532) Not supported !SETB(532) !@SETB(532) Not supported

Executed Each Cycle for ON Condition RSTB(533) Executed Once for Upward Differentiation @RSTB(533) Executed Once for Downward Differentiation Not supported !RSTB(533) !@RSTB(533) Not supported

Immediate Refreshing Specification Combined Executed Once and Bit Refreshed Variations Immediately for Upward Differentiation Executed Once and Bit Refreshed Immediately for Downward Differentiation

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

D: Word Address Specifies the word in which the bit will be turned ON or OFF. N: Beginning Bit Specifies the bit which will be turned ON or OFF. N must be #0000 to #000F (&0 to &15).

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Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers D CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 ---

Section 3-3

A0 to A959

#0000 to #000F (binary) or &0 to &15

DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

The functions of SETB(532) and RSTB(533) are described separately below. Operation of SETB(532) SETB(532) turns ON bit N of word D when the execution condition is ON. The status of the bit is not affected when the execution condition is OFF. Unlike SET, SETB(532) can turn ON a bit in the DM area.
15

This bit is turned ON. ON OFF ON OFF

Execution condition

Bit N of word D

Bits turned ON by SETB(532) can be turned OFF by any other instruction, not just RSTB(533).

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Operation of RSTB(533)

Section 3-3

RSTB(533) turns OFF bit N of word D when the execution condition is ON. The status of the bit is not affected when the execution condition is OFF. (Use SETB(532) to turn ON the bit.) Unlike RST, RSTB(533) can turn OFF a bit in the DM area.
15

This bit is turned OFF.

Execution condition ON OFF Bit N of word D ON OFF

Bits turned OFF by RSTB(533) can be turned ON by any other instruction, not just SETB(532). Flags
Name Error Flag Label ER Operation ON if N is not within the specified range of 0000 to 000F (&0 to &15). OFF in all other cases.

Precautions

SETB(532) and RSTB(533) cannot set/reset timers and counters. When SETB(532) or RSTB(533) is programmed between IL(002) and ILC(003) or JMP(004) and JME(005), the status of the specified bit will not be changed if the program section is interlocked or jumped, i.e., when the interlock condition or jump condition is OFF. SETB(532) and RSTB(533) have immediate refreshing variations (!SETB(532) and !RSTB(533)). When an external output bit has been specified in one of these instructions, any changes to the specified bit will be refreshed when the instruction is executed and reflected immediately in the output bit for the CPU Unit built-in output. Differences between SET/RSET and SETB(532)/RSTB(533) The SET and RSET instructions operate somewhat differently from SETB(532) and RSTB(533). 1. The instructions operate in the same way when the specified bit is in the CIO, W, H, or A Area. 2. The SETB(532) and RSTB(533) instructions can control bits in the DM Area, unlike SET and RSET. Differences between OUTB(534) and SETB(532)/RSTB(533) The OUTB(534) instruction operates somewhat differently from SETB(532) and RSTB(533). 1. The SETB(532) and RSTB(533) instructions change the status of the specified bit only when their execution condition is ON. These instructions have no effect on the status of the specified bit when their execution condition is OFF. 2. The OUTB(534) instruction turns ON the specified bit when its execution condition is ON and turns OFF the specified bit when its execution condition is OFF.

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Section 3-3

3. The set and reset inputs for a KEEP(011) instruction must be programmed with the instruction, but the SETB(532) and RSTB(533) instructions can be programmed completely independently. Furthermore, the same bit may be used as the operand in any number of SETB(532) and RSTB(533) instructions.
0.00 SETB D0 &2 0.01 RSTB D2 &2 Bit 02 of D2 is turned OFF when CIO 0.01 is ON. Bit 02 of D0 is turned ON when CIO 0.00 is ON.

3-3-8
Purpose

SINGLE BIT OUTPUT: OUTB(534)

OUTB(534) outputs the status of the instructions execution condition to the specified bit. OUTB(534) can control a bit in the DM Area, unlike OUT.

Ladder Symbols
OUTB(534)

D N

D: Word address N: Bit number

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification OUTB(534) @OUTB(534) Not supported !OUTB(534)

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

Operands

D: Word Address Specifies the word containing the bit to be controlled. N: Beginning Bit Specifies the bit to be controlled. N must be #0000 to #000F (&0 to &15).

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants D CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --N

A0 to A959

#0000 to #000F (binary) or &0 to &15

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Area Data Registers Index Registers Indirect addressing using Index Registers

Section 3-3
D N DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

When the execution condition is ON, OUTB(534) turns ON bit N of word D. When the execution condition is OFF, OUTB(534) turns OFF bit N of word D.
15 D N 0

This bit is turned OFF. ON OFF

Execution condition

Bit N of word D

ON OFF

If the immediate refreshing version is not used, the status of the execution condition (power flow) is written to the specified bit in I/O memory. If the immediate refreshing version is used, the status of the execution condition (power flow) is written to the CPU Units output terminal as well as the output bit in I/O memory. Flags Precautions There are no flags affected by this instruction. Immediate refreshing (!OUTB(534)) can be specified. An immediate refresh instruction updates the status of the output terminal just after the instruction is executed on an output bit allocated to a CPU Unit built-in output, at the same time as it writes the status of the execution condition (power flow) to the specified output bit in I/O memory. When OUTB(534) is programmed between IL(002) and ILC(003), the specified bit will be turned OFF if the program section is interlocked. (This is the same as an OUT instruction in an interlocked program section.) When a word is specified for the bit number (N), only bits 00 to 03 of N are used. For example, if N contains FFFA hex, OUTB(534) will control bit 10 of word D. Example
0.00 OUTB D0 &10 Bit 10 of D0 is turned OFF when CIO 0.00 is OFF.

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Section 3-4

3-4
3-4-1
Purpose

Sequence Control Instructions

END: END(001)
Indicates the end of a program.

Ladder Symbol
END(001)

Variations
Variations Executed Each Cycle for ON Condition Immediate Refreshing Specification END(001) Not supported

Applicable Program Areas

Block program areas Step program areas Not allowed Not allowed Subroutines Not allowed Interrupt tasks OK

Description

END(001) completes the execution of a program for that cycle. No instructions written after END(001) will be executed. Execution proceeds to the program with the next task number. When the program being executed has the highest task number in the program, END(001) marks the end of the overall main program.

Task 1

Program A

To the next task number

Task 2

Program B

To the next task number

Task n

Program Z

End of the main program

I/O refreshing

Precautions

Always place END(001) at the end of each program. A programming error will occur if there is not an END(001) instruction in the program.

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Section 3-4

3-4-2
Purpose

NO OPERATION: NOP(000)
This instruction has no function. (No processing is performed for NOP(000).) There is no ladder symbol associated with NOP(000).

Ladder Symbol Variations

Variations Executed Each Cycle for ON Condition Immediate Refreshing Specification

NOP(000) Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Description

No processing is performed for NOP(000), but this instruction can be used to set aside lines in the program where instructions will be inserted later. When the instructions are inserted later, there will be no change in program addresses. No flags are affected by NOP(000). NOP(000) can only be used with mnemonic displays, not with ladder programs.

Flags Precautions

3-4-3

Overview of Interlock Instructions

The following instruction combinations can be used to interlock outputs in a program section. INTERLOCK and INTERLOCK CLEAR (IL(002) and IL(003)) MULTI-INTERLOCK DIFFERENTIATION HOLD and MULTI-INTERLOCK CLEAR (MILH(517) and MILC(519))* Note MILH(517) holds the status of the Differentiation Flag, so differentiated instructions that were interlocked are executed after the interlock is cleared.

Interlock Instructions

MULTI-INTERLOCK DIFFERENTIATION RELEASE and MULTI-INTERLOCK CLEAR (MILR(518) and MILC(519))* Note MILR(518) does not hold the status of the Differentiation Flag, so differentiated instructions that were interlocked are not executed after the interlock is cleared.

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Differences between Interlocks and Multiple Interlocks

Section 3-4

Regular interlocks (IL(002) and IL(003)) cannot be nested, but multiple interlocks (MILH(517), MILR(518), and MILC(519)) can be nested. Ladder programming can be simplified by nesting multiple interlocks, as shown in the following diagram.
Interlocks with MILH and MILC a MILH Interlocks with IL and ILC

a IL A1

A1 b MILH 1 A2 A2 c MILH 2 A3 A3 MILC 2 MILC 1 MILC 0 a b c a b

ILC

IL

ILC

IL

ILC

Differences between MILH(517) and MILR(518)

Differentiated instructions (DIFU, DIFD, or instructions with a @ or % prefix) operate differently in interlocks created with MILH(517) and MILR(518). The operation of differentiated instructions in an interlock created with MILH(517) is identical to the operation in an interlock created with IL(002). For details, refer to 3-4-5 MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTI-INTERLOCK DIFFERENTIATION RELEASE, and MULTI-INTERLOCK CLEAR: MILH(517), MILR(518), and MILC(519).

Precautions

Do not combine interlocks created with different interlock instructions (IL-ILC, MILH-MILC, and MILR-MILC). The interlocks may not operate properly if different interlock methods are used together. For details on combining instructions, refer to 3-4-5 MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTIINTERLOCK DIFFERENTIATION RELEASE, and MULTI-INTERLOCK CLEAR: MILH(517), MILR(518), and MILC(519).

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Section 3-4

For example, an MILH(517) instruction cannot be inserted between IL(002) and IL(003).
IL
MILH(517) is in an interlocked area between IL(002) and ILC.(003).

MILH

ILC

Note

The different interlocks (IL-ILC, MILH-MILC, and MILR-MILC) can be used together as long as the interlocked program sections do not overlap. For example, all three interlock methods can be used without overlapping, as shown in the following diagram.
IL

ILC MILH

MILC

Different interlock methods can be used as long as the interlocked areas do not overlap.

MILR

MILC

Differences between Interlocks and Jumps

The following table shows the differences between interlocks (created with IL(002)/ILC(003), MILH(517)/MILC(519), or MILR(518)/MILC(519)) and jumps created with JMP(004)/JME(005).
Treatment in IL(002)/ILC(003), MILH(517)/ Treatment in MILC(519), or MILR(518)/MILC(519)) JMP(004)/JME(005) Instructions other than OUT, OUT NOT, No instructions are executed. OUTB(534), and timer instructions are not executed. All outputs retain their previous status. Except for outputs in OUT, OUT NOT, OUTB(534), and timer instructions, all outputs retain their previous status. OFF All outputs retain their previous status. Reset Operating timers (TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552) only) continue timing because the PVs are updated even when the timer instruction is not being executed.

Item Instruction execution

Output status in instructions

Bits in OUT, OUT NOT, OUTB(534) Status of timer instructions (except (TTIM(087), TTIMX(555), MTIM(543), and MTIMX(554))

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Section 3-4

3-4-4
Purpose

INTERLOCK and INTERLOCK CLEAR: IL(002) and ILC(003)

Interlocks all outputs between IL(002) and ILC(003) when the execution condition for IL(002) is OFF. IL(002) and ILC(003) are normally used in pairs.

Ladder Symbols
IL(002)

ILC(003)

Variations
Variations Interlocks when OFF/Does Not interlock when ON IL(002) Immediate Refreshing Specification Not supported Variations Executed Each Cycle for ON Condition Immediate Refreshing Specification ILC(003) Not supported

Applicable Program Areas

Block program areas Step program areas Not allowed Not allowed Subroutines OK Interrupt tasks OK

Description

When the execution condition for IL(002) is OFF, the outputs for all instructions between IL(002) and ILC(003) are interlocked. When the execution condition for IL(002) is ON, the instructions between IL(002) and ILC(003) are executed normally.
Execution condition Execution Execution condition ON condition OFF

Interlocked section of the program

Normal Outputs execution interlocked.

The following table shows the treatment of various outputs in an interlocked section between IL(002) and ILC(003).
Instruction Bits specified in OUT, OUT NOT, or OUTB(534) TIM, TIMX(550), TIMH(015), Completion Flag TIMHX(551), TMHH(540), PV TMHHX(552), TIML(542), and TIMXL(553) Bits/words specified in all other instructions (See note.) Treatment OFF OFF (reset) Time set value (reset) Retain previous status.

Note

Bits and words in all other instructions including TTIM(087), TTIMX(555), MTIM(543), MTIMX(554), SET, RSET, CNT, CNTX(546), CNTR(012), CNTRX(548), SFT, and KEEP(011) retain their previous status. If there are bits which you want to remain ON in an interlocked program section, set these bits to ON with SET just before IL(002).

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Section 3-4

It is often more efficient to switch a program section with IL(002) and ILC(003). When several processes are controlled with the same execution condition, it takes fewer program steps to put these processes between IL(002) and ILC(003).

The following table shows the differences between IL(002)/ILC(003) and JMP(004)/JME(005).
Item Instruction execution Treatment in IL(002)/ILC(003) Instructions other than OUT, OUT NOT, OUTB(534), and timer instructions are not executed. Except for outputs in OUT, OUT NOT, OUTB(534), and timer instructions, all outputs retain their previous status. OFF Reset Treatment in JMP(004)/JME(005) No instructions are executed.

Output status in instructions

All outputs retain their previous status.

Bits in OUT, OUT NOT, OUTB(534) Status of timer instructions (except (TTIM(087), TTIMX(555), MTIM(543), and MTIMX(554))

All outputs retain their previous status. Operating timers (TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552) only) continue timing because the PVs are updated even when the timer instruction is not being executed.

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF OFF or unchanged OFF or unchanged

Precautions

The cycle time is not shortened when a section of the program is interlocked because the interlocked instructions are executed internally. The operation of DIFU(013), DIFD(014), and differentiated instructions is not dependent solely on the status of the execution condition when they are programmed between IL(002) and ILC(003). Changes in the execution condition for DIFU(013), DIFD(014), or a differentiated instruction are not recorded if the DIFU(013) or DIFD(014) is in an interlocked section and the execution condition for the IL(002) is OFF.

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Section 3-4

In general, IL(002) and ILC(003) are used in pairs, although it is possible to use more than one IL(002) with a single ILC(003) as shown in the following diagram. If IL(002) and ILC(003) are not paired, an error message will appear when the program check is performed but the program will be executed properly.

Execution condition a b OFF ON OFF OFF ON OFF ON ON

Program section A B Interlocked Interlocked Interlocked Interlocked Not interlocked Interlocked Not interlocked Not interlocked

IL(002) and ILC(003) cannot be nested, as in the following diagram. (Use MILH(517)/MILR(518) and MILC(519) when it is necessary to nest interlocks.)

Differential Instruction in Interlocks

Differentiated instructions (DIFU(013), DIFD(014), or instructions with a @ or % prefix) written between IL(002) and ILC(003) are executed according to changes in memory status between when the interlock is started and when it is released. If a differentiated condition is met, it will be effected when the interlock is released.

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Section 3-4

For example, if the input condition for DIFU(013) is OFF when an interlock is started and ON when the interlock is released, the operand bit of DIFU(013) will be turned ON when the interlock is released.
0.00 ILC
1. Assume that the input condition for DIFU(013) (CIO 0.01) is OFF when CIO 0.00 turns OFF (i.e., when the interlock is started. 2. Assume that CIO 0.01 turns ON while CIO 0.00 is OFF (i.e., while the interlock is in effect). 3. DIFU(013) will be executed to turn ON CIO 100.00 when CIO 0.00 turns ON (i.e., when the interlock is released) if the input condition for DIFU(013) (CIO 0.01) is still ON.

0.01 DIFU 100.00

ILC

IL(002) affects differentiated operation in the same way as MILH(517). Timing Chart
No interlocked. Interlocked. No interlocked.

ON
CIO 0.00

OFF
Differentiation condition

ON
CIO 0.01

OFF

OFF
DIFU(013) executed.

CIO 10.00

ON OFF
1 cycle

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Examples

Section 3-4

When CIO 0.00 is OFF in the following example, all outputs between IL(002) and ILC(003) are interlocked. When CIO 0.00 is ON in the following example, the instructions between IL(002) and ILC(003) are executed normally.

0.00

CIO 0.00 ON

CIO 0.00 OFF

0.01

100.00 OFF

0.02

H0.00 OFF Normal execution Reset Outputs interlocked

Retained 100.03

Retained

3-4-5

MULTI-INTERLOCK DIFFERENTIATION HOLD, MULTI-INTERLOCK DIFFERENTIATION RELEASE, and MULTI-INTERLOCK CLEAR: MILH(517), MILR(518), and MILC(519)
Interlocks all outputs between MILH(517) (or MILR(518)) and MILC(519) when the execution condition for MILH(517) (or MILR(518)) is OFF. MILH(517) (or MILR(518)) and MILC(519) are normally used in pairs. Unlike the IL(002)/ILC(003) interlocks, the MILH(517)/MILC(519) and MILR(518)/MILC(519) interlocks can be nested. The operation of differentiated instructions is different for interlocks created with MILH(517) and MILR(518).

Purpose

Ladder Symbols
MILH(517) N D MILR(518) N D N: Interlock Number D: Interlock Status Bit N: Interlock Number D: Interlock Status Bit

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MILC(519) N N: Interlock Number

Section 3-4

Operands

N: Interlock Number The interlock number must be between 0 and 15. Match the interlock number of the MILH(517) (or MILR(518)) instruction with the same number in the corresponding MILC(519) instruction. The interlock numbers can be used in any order. D: Interlock Status Bit ON when the program section is not interlocked. OFF when the program section is interlocked. When the interlock is engaged, the Interlock Status Bit can be force-set to release the interlock. Conversely, when the interlock is not engaged, the Interlock Status Bit can be force-reset to engage the interlock.

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers N ------------------0 to 15 ------D CIO 0.00 to CIO 6143.15 W0.00 to W511.15 H0.00 to H511.15 A0.00 to A959.15 ----------------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

Variations
Variations Interlocks when OFF/Does Not interlock when ON MILH(517) and MILR(518) Immediate Refreshing Specification Not supported Variations Executed Each Cycle for ON Condition Immediate Refreshing Specification MILC(519) Not supported

Applicable Program Areas

The following table shows the applicable program areas for MILH(517), MILR(518), and MILC(519).
Block program areas Step program areas Not allowed Not allowed Subroutines OK Interrupt tasks OK

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Description

Section 3-4

When the execution condition for MILH(517) (or MILR(518)) with interlock number N is OFF, the outputs for all instructions between that MILH(517)/ MILR(518) instruction and the next MILC(519) with interlock number N are interlocked. When the execution condition for MILH(517) (or MILR(518)) with interlock number N is ON, the instructions between that MILH(517)/MILR(518) instruction and the next MILC(519) with interlock number N are executed normally. Interlock Status The following table shows the treatment of various outputs in an interlocked section between MILH(517)/MILR(518) instruction and the next MILC(519).
Instruction Bits specified in OUT, OUT NOT, or OUTB(534) TIM, TIMX(550), TIMH(015), Completion Flag TIMHX(551), TMHH(540), PV TMHHX(552), TIML(542), and TIMXL(553) Bits/words specified in all other instructions (See note.) Treatment OFF OFF (reset) Time set value (reset) Retain previous status.

Note

Bits and words in all other instructions including TTIM(087), TTIMX(555), MTIM(543), MTIMX(554), SET, RSET, CNT, CNTX(546), CNTR(012), CNTRX(548), SFT, and KEEP(011) retain their previous status. The MILH(517)/MILR(518) instruction turns OFF the Interlock Status Bit (operand D) when the interlock is in engaged and turns ON the bit when the interlock is not engaged. Consequently, the Interlock Status Bit can be monitored to check whether or not the interlock for a given interlock number is engaged.
Input condition ON (Normal operation) Input condition OFF MILH Input condition n d Normal operation Interlock Status Bit (d) ON Outputs interlocked. (Outputs OFF, timers reset, etc.) Interlock Status Bit (d) OFF

Interlocked program section

MILC n

Nesting Interlocks are nested when an interlocked program section (MILH(517)/ MILR(518) and MILC(519) combination) is placed within another interlocked program section (MILH(517)/MILR(518) and MILC(519) combination). Interlocks can be nested up to 16 levels. Nesting can be used for the following kinds of applications.

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Example 1

Section 3-4

Interlocking the entire program with one condition and interlocking a part of the program with another condition (1 nesting level)
Global interlock (Emergency stop) A1 (Peripheral processing) Partial interlock (Conveyor RUN) A2 (Conveyor operation)

A1 and A2 are interlocked when the Emergency Stop Button is ON. A2 is interlocked when Conveyor RUN is OFF.
Global interlock (Emergency stop)

MILH 0

A1 (Peripheral processing)
Partial interlock (Conveyor RUN)

When the Emergency Stop is ON (input condition OFF), both A1 and A2 are interlocked. When the Emergency Stop is OFF (input condition ON), A1 is executed normally and A2 is controlled by the Conveyor RUN switch as described below.

MILH 1

When the Conveyor RUN switch is OFF (input condition OFF), A2 is interlocked. When the Conveyor RUN switch is ON (input condition ON), A2 is executed normally.

A2 (Conveyor operation) MILC 1 MILC 0

Example 2 Interlocking the entire program with one condition and interlocking two overlapping parts of the program with other conditions (2 nesting levels)
Global interlock (Emergency stop)

A1 (Peripheral processing)
Partial interlock (Conveyor RUN)

A2 (Conveyor operation)
Partial interlock (Arm RUN)

A3 (Arm operation)

A1, A2, and A3 are interlocked when the Emergency Stop Button is ON. A2 and A3 are interlocked when Conveyor RUN is OFF.

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Sequence Control Instructions

A3 is interlocked when Arm RUN is OFF.
Global interlock (Emergency stop)

Section 3-4

MILH 0

A1 (Peripheral processing)
Partial interlock (Conveyor RUN)

When the Emergency Stop is ON (input condition OFF), A1, A2, and A3 are interlocked. When the Emergency Stop is OFF (input condition ON), A1 is executed normally and A2 and A3 are controlled by the Conveyor RUN and Arm RUN switches as described below.

MILH 1

A2 (Conveyor operation)
Partial interlock (Arm RUN)

When the Conveyor RUN switch is OFF (input condition OFF), both A2 and A3 are interlocked. When the Conveyor RUN switch is ON (input condition ON), A2 is executed normally and A3 is controlled by the Arm RUN switch as described below.

MILH 2

When the Arm RUN switch is OFF (input condition OFF), A3 is interlocked. When the Arm RUN switch is ON (input condition ON), A3 is executed normally.

A3 (Arm operation) MILC 2 MILC 1 MILC 0

Differences between MILH(517) and MILR(518) Differentiated instructions (DIFU(013), DIFD(014), or instructions with a @ or % prefix) operate differently in interlocks created with MILH(517) and MILR(518). When a program section is interlocked with MILR(518), a differentiated instruction will not be executed when the interlock is cleared even if the differentiation condition was activated during the interlock (comparing the status of the execution condition when the interlock started to its status when the interlock was cleared). When a program section is interlocked with MILH(517), a differentiated instruction will be executed when the interlock is cleared if the differentiation condition was activated during the interlock (comparing the status of the execution condition when the interlock started to its status when the interlock was cleared).

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Section 3-4

Instruction Operation of Differentiated Instructions MILH(517) A differentiated instruction (DIFU, DIFD, or MULTI-INTERLOCK DIFFER- instruction with a @ or % prefix) will be executed after the interlock is cleared if the differENTIATION HOLD

entiation condition of the instruction was established while the instruction was interlocked. (The status of the execution condition when the interlock started is compared to its status when the interlock was cleared.) MILR(518) A differentiated instruction (DIFU, DIFD, or MULTI-INTERLOCK DIFFER- instruction with a @ or % prefix) will not be executed after the interlock is cleared even if ENTIATION RELEASE the differentiation condition of the instruction was established while the instruction was interlocked. Operation of Differentiated Instructions in an MILH(517) Interlock If there is a differentiated instruction (DIFU, DIFD, or instruction with a @ or % prefix) between MILH(517) and the corresponding MILC(519), that instruction will be executed after the interlock is cleared if the differentiation condition of the instruction was established. (The system compares the execution conditions status when the interlock started to its status when the interlock was cleared.) In the same way, a differentiated instruction will be executed if its execution condition is established at the same time that the interlock is started or cleared. Many other conditions in the program may cause the differentiation condition to be reset even if it was established during the interlock. In this case, the differentiation instruction will not be executed when the interlock is cleared. Example When a DIFFERENTIATE UP (DIFU(013)) instruction is being used and the input condition is OFF when the interlock starts and ON when the interlock is cleared, DIFU(013) will be executed when the interlock is cleared. (Differentiated instructions operate the same in the MILH(517) interlock as they would in an IL(002) interlock.)
0.00 MILH 0

1. When CIO 0.00 is OFF (interlock starts), the DIFU's CIO 0.01 input condition is OFF. 2. The DIFU's CIO 0.01 input condition goes from OFF to ON while CIO 0.00 is OFF (DIFU interlocked), 3. When CIO 0.00 goes from OFF to ON (interlock cleared), DIFU is executed if CIO 0.01 is still ON.

0.01 DIFU 100.00 MILC 0

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Timing Chart
Not interlocked ON 0.00 OFF Status (OFF) at start of interlock ON 0.01 OFF OFF MILH(517) interlock ON Interlocked

Section 3-4

Not interlocked

Differentiation condition established

Status (ON) when interlock is cleared DIFU(013) is executed.

ON 100.00 OFF 1 cycle

Operation of Differentiated Instructions in an MILR(518) Interlock If there is a differentiated instruction (DIFU, DIFD, or instruction with a @ or % prefix) between MILR(518) and the corresponding MILC(519), that instruction will not be executed after the interlock is cleared even if the differentiation condition of the instruction was established. (The system compares the execution conditions status in the cycle when the interlock started to its status in the cycle when the interlock was cleared.) In the same way, a differentiated instruction will not be executed if its execution condition is established at the same time that the interlock is started or cleared. Example When a DIFFERENTIATE UP (DIFU(013)) instruction is being used and the input condition is OFF when the interlock starts and ON when the interlock is cleared, DIFU(013) will not be executed when the interlock is cleared.
0.00 MILR 0

1. When CIO 0.00 is OFF (interlock starts), the DIFU's CIO 0.01 input condition is OFF. 2. The DIFU's CIO 0.01 input condition goes from OFF to ON while CIO 0.00 is OFF (DIFU interlocked), 3. When CIO 0.00 goes from OFF to ON (interlock cleared), DIFU is not executed even though CIO 0.01 is still ON.

0.01 DIFU 100.00 MILC 0

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Timing Chart
Not interlocked ON 0.00 OFF ON Interlocked

Section 3-4

Not interlocked

ON 0.01 OFF OFF

ON 100.00 OFF

MILR(518) interlock DIFU(013) is not executed.

Controlling Interlock Status from the CX-Programmer An interlock can be engaged or released manually by force-resetting or forcesetting the Interlock Status Bit (specified with operand D of MILH(517) and MILR(518)) from the CX-Programmer. The forced status of the Interlock Status Bit has priority and overrides the interlock status calculated by program execution. Force-set: Releases the interlock.
OFF MILH n 100.00 Program section controlled by interlock CIO 100.00 is OFF when the interlock is engaged.

If CIO 100.00 is force-set (ON), the interlock is released.

MILC n

Force-reset: Engages the interlock.

ON MILH n 100.00 Program section controlled by interlock CIO 100.00 is ON when the interlock is not engaged.

If CIO 100.00 is force-reset (OFF), the interlock is engaged.

MILC n

Note

Program operation can be switched more efficiently by using interlocks with MILH(517) or MILR(518).

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Section 3-4

Instead of switching processing with compound conditions, insert an MILH(517) or MILR(518) instruction before each process and an MILC(519) instruction after each process.
a a

A1

MILH 0

A2
b

A1

MILH 1

A2 MILC 1 MILC 0

Unlike the IL(002) interlocks, MILH(517) and MILR(518) interlocks can be nested, so the operation of similar programs will be different if MILH(517) or MILR(518) is used instead of ILC(002). Program with MILH(517)/MILC(519) Interlocks
a

MILH 0 100.00 A1
b

MILH 1 100.01 A2 MILC 1 A3 MILC 0

Execution condition a b OFF ON OFF ON OFF ON ON

A1 Interlocked Not interlocked Not interlocked

Program section A2 A3 Interlocked Interlocked Interlocked Not interlocked Not interlocked Not interlocked

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Sequence Control Instructions

Program with IL(002)/ILC(003) Interlocks
a

Section 3-4

IL

A1
b

IL

A2

ILC This program section is not controlled by the interlock. ILC This ILC(003) instruction is ignored so ...

A3

Execution condition a b A1 OFF ON Interlocked OFF ON OFF Not interlocked ON ON Not interlocked

Program section A2 A3 Interlocked Not interlocked (Not controlled by the IL(002)/ Interlocked ILC(003) interlock.) Not interlocked

If there are bits which you want to remain ON in a program section interlocked by MILH(517) or MILR(518), set these bits to ON with SET just before the MILH(517) or MILR(518) instruction. Flags
Name Error Flag Label ER Operation OFF

Precautions

The cycle time is not shortened when a section of the program is interlocked by MILH(517) or MILR(518) because the interlocked instructions are executed internally.

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Section 3-4

When nesting interlocks, assign interlock numbers so that the nested program section does not exceed the outer program section.
a

MILH 0

A1
b

MILH 1

A2 MILC 0 A3 MILC 1
The nested program section must not go beyond the outer program section.

Other instructions can be input between the MILC(519) instructions, as shown in the following diagram.
a

MILH 0 100.00 A1
b

MILH 1 100.01 A2 MILC 1 A3 MILC 0

Other instructions can be inserted between two MILC(519) instructions. In this case, sections A1 and A3 operate together. (They are interlocked when "a" is OFF, regardless of the ON/OFF status of "b".)

If there is an ILC(003) instruction between an MILH(517) and MILC(519) pair, the program section between MILH(517) and ILC(003) will be interlocked.

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a

Section 3-4

MILH 0

When input condition "a" is OFF, only program section A1 is interlocked.

A1 ILC A2 MILC 0
The MILC(519) instruction is ignored. If there is an ILC(003) instruction, the interlock is cleared at that point.

If there is an ILC(003) instruction between an MILR(518) and MILC(519) pair, the ILC(003) instruction will be ignored and the full program section between MILR(518) and MILC(519) will be interlocked.
a

MILR 0

When input condition "a" is OFF, program sections A1 and A2 are interlocked.

A1 ILC A2 MILC 0
The ILC(003) instruction is ignored.

If there is another MILH(517) or MILR(518) instruction with the same interlock number between an MILH(517) and MILC(519) pair and the first MILH(517) instructions interlock is engaged, the second MILH(517)/MILR(518) will not operate. If there is another MILH(517) or MILR(518) instruction with the same interlock number between an MILH(517) and MILC(519) pair and the first MILH(517) instructions interlock is not engaged, the second MILH(517)/MILR(518) will operate normally.
a

MILH 0

When input condition "a" is OFF, program sections A1 and A2 are both interlocked, even if input condition "b" is ON.

A1
b

MILH 0

When input condition "a" is ON and "b" is OFF, only program section A2 is interlocked.

A2 MILC 0

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Note

Section 3-4

The MILR(518) interlocks operate in the same way if there is another MILH(517) or MILR(518) instruction with the same interlock number between an MILR(518) and MILC(519) pair. If there is an MILC(519) instruction with a different interlock number between an MILH(517)/MILR(518) and MILC(519) pair, that MILC(519) instruction will be ignored.
a

MILH 0

When input condition "a" is OFF, program sections A1 and A2 are both interlocked.

A1 MILC 1 A2 MILC 0
This MILC(519) instruction is ignored.

If there is an MILH(517) instruction between an IL(002) and ILC(003) pair and the IL(002) interlock is engaged, the MILH(517) instruction has no effect. In this case, the program section between IL(002) and ILC(003) will be interlocked. If the IL(002) interlock is not engaged and the MILH(517) instructions execution condition (b in this case) is OFF, the program section between MILH(517) and ILC(003) will be interlocked.
a

IL A1
b

When input condition "a" is OFF, program sections A1 and A2 are both interlocked.

MILH 0

If the program section is not interlocked by IL(002) and "b" is OFF, program section A2 is interlocked.

A2 ILC

If there is an MILC(519) instruction between an IL(002) and ILC(003) pair, that MILC(519) instruction will be ignored and the entire program section between IL(002) and ILC(003) will be interlocked.

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a

Section 3-4

IL A1 MILC 0 A2 ILC

When input condition "a" is OFF, program sections A1 and A2 are both interlocked.

The MILC(519) instruction is ignored.

Examples

When W0.00 and W0.01 are both ON, the instructions between MILH(517) with interlock number 0 and MILC(519) with interlock number 0 are executed normally. When W0.00 is OFF, the instructions between MILH(517) with interlock number 0 and MILC(519) with interlock number 0 are interlocked. When W0.00 is ON and W0.01 are OFF, the instructions between MILH(517) with interlock number 1 and MILC(519) with interlock number 1 are interlocked. The other instructions are executed normally.

W0.00 MILH 0 100.00 0.01 200.00

W0.00 and W0.01 both ON

W0.00 OFF

W0.00 ON and W0.01 OFF

Executed normally. OFF

W0.01 MILH 1 100.01 0.02 H0.00 Executed normally.

OFF Outputs interlocked. Outputs interlocked.

SET 110.03 MILC 1 CNT 1 #10

Held

Held

Executed normally.

MILC 0

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Section 3-4

3-4-6
Purpose

JUMP and JUMP END: JMP(004) and JME(005)

When the execution condition for JMP(004) is OFF, program execution jumps directly to the first JME(005) in the program with the same jump number. JMP(004) and JME(005) are used in pairs.

Ladder Symbols
JMP(004) N N: Jump number

JME(005) N N: Jump number

Variations
Variations Jumps when OFF/Does Not Jump when ON Immediate Refreshing Specification Variations Executed Each Cycle for ON Condition JMP(004) Not supported JME(005) Not supported

Immediate Refreshing Specification

Applicable Program Areas

Block program areas Step program areas OK Not allowed Subroutines OK Interrupt tasks OK

Operands Operand Specifications

N: Jump Number The jump number must be 0000 to 00FF (&0 to &255 decimal).

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers JMP(004) CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #00FF (binary) or &0 to &255 DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15

N JME(005) ------------------#0000 to #00FF (binary) or &0 to &255 -------

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Sequence Control Instructions

Description

Section 3-4

When the execution condition for JMP(004) is ON, no jump is made and the program is executed consecutively as written. When the execution condition for JMP(004) is OFF, program execution jumps directly to the first JME(005) in the program with the same jump number. The instructions between JMP(004) and JME(005) are not executed, so the status of outputs between JMP(004) and JME(005) is maintained. In block programs, the instructions between JMP(004) and JME(005) are skipped regardless of the status of the execution condition.
Execution condition Instructions jumped Instructions in this section are not executed and output status is maintained. The instruction execution time for these instructions is eliminated.

Instructions executed

Because all of instructions between JMP(004) and JME(005) are skipped when the execution condition for JMP(004) is OFF, the cycle time is reduced by the total execution time of the skipped instructions. In contrast, NOP(000) processing is performed for instructions between JMP0(515) and JME0(516), so the cycle time is not reduced as much with those jump instructions. The following table compares the various jump instructions.
Item Execution condition for jump Number allowed Instruction processing when jumped Instruction execution time when jumped Status of outputs (bits and words) when jumped Status of operating timers when jumped Processing in block programs JMP(004) JME(005) OFF 256 total Not executed. None CJP(510) JME(005) ON CJPN(511) JME(005) OFF JMP0(515) JME0(516) OFF No limit NOP(000) processing Same as NOP(000) instructions

Bits and words maintain their previous status. Operating timers continue timing. Always jump. Jump when ON. Jump when OFF. Not allowed.

Flags (JMP)
Name Error Flag Label ER Operation ON if N is not within the specified range of 0 to 255 (0000 to 00FF hex). ON if there is a JMP(004) in the program without a JME(005) with the same jump number. ON if there is a JMP(004) in the task without a JME(005) with the same jump number in the task. OFF in all other cases.

Precautions

All of the outputs (bits and words) in jumped instructions retain their previous status. Operating timers (TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), and TMHHX(552)) continue timing because the PVs are updated even when the timer instruction is not being executed. When there are two or more JME(005) instructions with the same jump number, only the instruction with the lower address will be valid. The JME(005) with the higher program address will be ignored.

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Section 3-4

When JME(005) precedes JMP(004) in the program, the instructions between JME(005) and JMP(004) will be executed repeatedly as long as the execution condition for JMP(004) is OFF. A Cycle Time Too Long error will occur if the execution condition is not turned ON or END(001) is not executed within the maximum cycle time.

Program section A is executed repeatedly as long as execution condition a is OFF.

In block programs, the instructions between JMP(004) and JME(005) are always skipped regardless of the status of the execution condition for JMP(004).

Block program section JMP &1 to JME &1

JMP(004) and JME(005) pairs must be in the same task because jumps between tasks are not allowed. An error will occur if a JME(005) instruction is not programmed in the same task as its corresponding JMP(004) instruction. The operation of DIFU(013), DIFD(014), and differentiated instructions is not dependent solely on the status of the execution condition when they are programmed between JMP(004) and JME(005). When DIFU(013), DIFD(014), or a differentiated instruction is executed in an jumped section immediately after the execution condition for the JMP(004) has gone ON, the execution condition for the DIFU(013), DIFD(014), or differentiated instruction will be compared to the execution condition that existed before the jump became effective (i.e., before the execution condition for JMP(004) went OFF).

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Examples Basic Operation

Section 3-4

When CIO 0.00 is OFF in the following example, the instructions between JMP(004) and JME(005) are not executed and the outputs maintain their previous status. When CIO 0.00 is ON in the following example, the instructions between JMP(004) and JME(005) are executed normally.
0.00 &1

CIO 0.00 ON

CIO 0.00 OFF

Normal Instructions execution not executed. (Outputs remain unchanged.)

&1

3-4-7
Purpose

CONDITIONAL JUMP: CJP(510)/CJPN(511)

The operation of CJP(510) is the basically the opposite of JMP(004). When the execution condition for CJP(510) is ON, program execution jumps directly to the first JME(005) in the program with the same jump number. CJP(510) and JME(005) are used in pairs. The operation of CJPN(511) is almost identical to JMP(004). When the execution condition for CJP(004) is OFF, program execution jumps directly to the first JME(005) in the program with the same jump number. CJPN(511) and JME(005) are used in pairs.

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Ladder Symbols
CJP(510) N CJPN(511) N N: Jump number N: Jump number

Section 3-4

Variations
Variations Jumps when ON/Does Not Jump when OFF Immediate Refreshing Specification Variations Jumps when OFF/Does Not Jump when ON Immediate Refreshing Specification Variations Executed Each Cycle for ON Condition Immediate Refreshing Specification CJP(510) Not supported CJPN(511) Not supported JME(005) Not supported

Applicable Program Areas

Block program areas Step program areas OK Not allowed Subroutines OK Interrupt tasks OK

Operands Operand Specifications

N: Jump Number The jump number must be 0000 to 00FF (0 to 255 decimal).

Area CJP(510) CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767

N CJPN(511) -------------------

JME(005)

CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM *D0 to *D32767 addresses in BCD Constants #0000 to #00FF (binary) or &0 to &255

Data Registers Index Registers Indirect addressing using Index Registers

DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15

#0000 to #00FF (binary) or &0 to &255 -------

Description

The operation of CJP(510) and CJPN(511) differs only in the execution condition. CJP(510) jumps to the first JME(005) when the execution condition is ON and CJPN(511) jumps to the first JME(005) when the execution condition is OFF.

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Section 3-4

Because the jumped instructions are not executed, the cycle time is reduced by the total execution time of the jumped instructions. Operation of CJP(510) When the execution condition for CJP(510) is OFF, no jump is made and the program is executed consecutively as written. When the execution condition for CJP(510) is ON, program execution jumps directly to the first JME(005) in the program with the same jump number.
Execution condition OFF Execution condition ON Instructions jumped Instructions in this section are not executed and output status is maintained. The instruction execution time for these instructions is eliminated.

Instructions executed

Operation of CJPN(511) When the execution condition for CJPN(511) is ON, no jump is made and the program is executed consecutively as written. When the execution condition for CJPN(511) is OFF, program execution jumps directly to the first JME(005) in the program with the same jump number.
Execution condition ON Execution condition OFF Instructions jumped Instructions in this section are not executed and output status is maintained. The instruction execution time for these instructions is eliminated.

Instructions executed

Flags

The following table shows the flags affected by CJP(510) and CJPN(511).
Name Error Flag Label ER Operation ON if there is not a JME(005) with the same jump number as CJP(510) or CJPN(511). ON if N is not within the specified range of 0 to 255 (0000 to 00FF hex). ON if there is a CJP(510) or CJPN(511) instruction in a task without a JME(005) with the same jump number. OFF in all other cases.

Precautions

All of the outputs (bits and words) in jumped instructions retain their previous status. Operating timers (TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), and TMHHX(552)) continue timing be-cause the PVs are updated even when the timer instruction is not being executed. When there are two or more JME(005) instructions with the same jump number, only the instruction with the lower address will be valid. The JME(005) with the higher program address will be ignored.

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Section 3-4

When JME(005) precedes the CJP(510) or CJPN(511) instruction in the program, the instructions in-between will be executed repeatedly as long as the execution condition remains OFF (CJP(510)) or ON (CJPN(511)). A Cycle Time Too Long error will occur if the jump is not completed by changing the execution condition executing END(001) within the maximum cycle time. The CJP(510) or CJPN(511) instructions will operate normally in block programs. When the execution condition for the CJP(510) is ON or the execution condition for CJPN(511) is OFF, program execution will jump directly to the JME instruction without executing instructions between CJP(510)/CJPN(511) and JME. No execution time will be required for these instructions and the cycle time will thus be reduced. When the execution condition for the JMP0 is OFF, NOP processing is executed between the JMP0 and JME0, requiring execution time. Therefore, the cycle time will not be reduced. When a CJP(510) or CJPN(511) instruction is programmed in a task, there must be a JME(005) with the same jump number because jumps between tasks are not allowed. An error will occur if a corresponding JME(005) instruction is not programmed in the same task. The operation of DIFU(013), DIFD(014), and differentiated instructions is not dependent solely on the status of the execution condition when they are programmed in a jumped program section. When DIFU(013), DIFD(014), or a differentiated instruction is executed in an jumped section immediately after the execution condition for the CJP(510) has gone OFF (ON for CJPN(511)), the execution condition for the DIFU(013), DIFD(014), or differentiated instruction will be compared to the execution condition that existed before the jump became effective.

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Example

Section 3-4

When CIO 0.00 is ON in the following example, the instructions between CJP(510) and JME(005) are not executed and the outputs maintain their previous status. When CIO 0.00 is OFF in the following example, the instructions between CJP(510) and JME(005) are executed normally.
0.00 &1

CIO 0.00 ON

CIO 0.00 OFF

Instructions not executed. (Outputs remain unchanged.)

Normal execution

&1

Note

For CJPN(511), the ON/OFF status of CIO 0.00 would be reversed.

3-4-8
Purpose

MULTIPLE JUMP and JUMP END: JMP0(515) and JME0(516)

When the execution condition for JMP0(515) is OFF, all instructions from JMP0(515) to the next JME0(516) in the program are processed as NOP(000). Use JMP0(515) and JME0(516) in pairs. There is no limit on the number of pairs that can be used in the program.

Ladder Symbols
JMP0(515) JME0(516)

Variations
Variations Jumps when OFF/Does Not Jump when ON Immediate Refreshing Specification JMP0(515) Not supported

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Variations Executed Each Cycle for ON Condition Immediate Refreshing Specification

Section 3-4
JME0(516) Not supported

Applicable Program Areas

Block program areas Step program areas Not allowed Not allowed Subroutines OK Interrupt tasks OK

Description

When the execution condition for JMP0(515) is ON, no jump is made and the program executed consecutively as written. When the execution condition for JMP0(515) is OFF, all instructions from JMP0(515) to the next JME0(516) in the program are processed as NOP(000). Unlike JMP(004), CJP(510), and CJPN(511), JMP0(515) does not use jump numbers, so these instructions can be placed anywhere in the program.
Execution condition a ON Execution condition a OFF Instructions jumped

Instructions executed Jumped instructions are processed as NOP(000). Instruction execution times Execution are the same as NOP(000). Execution condition b ON condition b OFF

Instructions executed

Instructions jumped

Unlike JMP(004), CJP(510), and CJPN(511) which jump directly to the first JME(005) instruction in the program, all of the instructions between JMP0(515) and JME0(516) are executed as NOP(000). The execution time of the jumped instructions will be reduced, but not eliminated. The jumped instructions themselves are not executed and their outputs (bits and words) maintain their previous status. Precautions Multiple pairs of JMP0(515) and JME0(516) instructions can be used in the program, but the pairs cannot be nested. JMP0(515) and JME0(516) cannot be used in block programs. JMP0(515) and JME0(516) pairs must be in the same tasks because jumps between tasks are not allowed. The operation of DIFU(013), DIFD(014), and differentiated instructions is not dependent solely on the status of the execution condition when they are programmed between JMP0(515) and JME0(516). When DIFU(013), DIFD(014), or a differentiated instruction is executed in an jumped section immediately after the execution condition for the JMP0(515) has gone ON, the execution condition for the DIFU(013), DIFD(014), or differentiated instruction will be compared to the execution condition that existed before the jump became effective (i.e., before the execution condition for JMP0(515) went OFF).

162

Sequence Control Instructions

Example

Section 3-4

When CIO 0.00 is OFF in the following example, the instructions between JMP0(515) and JME0(516) are processed as NOP(000) instructions and the outputs maintain their previous status. When CIO 0.00 is ON in the following example, the instructions between JMP0(515) and JME0(516) are executed normally.
0.00

CIO 0.00 ON

CIO 0.00 OFF

Instructions Normal execution processed as NOP(000). (Outputs remain unchanged.)

3-4-9
Purpose

FOR-NEXT LOOPS: FOR(512)/NEXT(513)

The instructions between FOR(512) and NEXT(513) are repeated a specified number of times. FOR(512) and NEXT(513) are used in pairs.

Ladder Symbols
FOR(512) N N: Number of loops

NEXT(513)

Variations
Variations Executed Each Cycle for ON Condition Executed Each Cycle for ON Condition Immediate Refreshing Specification FOR(512) NEXT(513) Not supported

163

Sequence Control Instructions

Applicable Program Areas
Block program areas Step program areas Not allowed OK Subroutines OK

Section 3-4

Interrupt tasks OK

Operands Operand Specifications

N: Number of Loops The number of loops must be 0000 to FFFF (0 to 65,535 decimal).

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

#0000 to #FFFF (binary) or &0 to &65,535 DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

The instructions between FOR(512) and NEXT(513) are executed N times and then program execution continues with the instruction after NEXT(513). The BREAK(514) instruction can be used to cancel the loop. If N is set to 0, the instructions between FOR(512) and NEXT(513) are processed as NOP(000) instructions. Loops can be used to process tables of data with a minimum amount of programming.
Repeated N times

Repeated program section

164

Sequence Control Instructions

Section 3-4

FOR-NEXT loops can be nested up to 15 levels. In the example below, program sections A, B, and C are executed as follows: A B B C, A B B C, and A B B C

&3

&2

Use BREAK(514) to escape from a FOR-NEXT loop. Several BREAK(514) instructions (the number of levels nested) are required to escape from nested loops. The remaining instructions in the loop after BREAK(514) are processed as NOP(000) instructions.

&3

Escapes from loop when condition a is ON. Remaining instructions are processed as 1 2 NOP(000).

&3

&2 Breaks FOR-NEXT loop 2.

Breaks FOR-NEXT loop 1.

Alternative Looping Methods There are two ways to repeat a program section until a given execution condition is input. 1,2,3... 1. FOR-NEXT Loop with BREAK Start a FOR-NEXT loop with a maximum of N repetitions. Program BREAK(514) within the loop with the desired execution condition. The loop will end before N repetitions if the execution condition is input.

165

Sequence Control Instructions

2. JME(005)-JMP(004) Loop

Section 3-4

Program a loop with JME(005) before JMP(004). The instructions between JME(005) and JMP(004) will be executed repeatedly as long as the execution condition for JMP(004) is OFF. (A Cycle Time Too Long error will occur if the execution condition is not turned ON or END(001) is not executed within the maximum cycle time.) Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation ON if more than 15 loops are nested. OFF in all other cases. OFF OFF

Precautions

Program FOR(512) and NEXT(513) in the same task. Execution will not be repeated if these instructions are not in the same task. A jump instruction such as JMP(004) may be executed within a FOR-NEXT loop, but do not jump beyond the FOR-NEXT loop. The following instructions cannot be used within FOR-NEXT loops: Block programming instructions MULTIPLE JUMP and JUMP END: JMP(515) and JME(516) STEP DEFINE and STEP START: STEP(008)/SNXT(009) Note If a loop repeats in one cycle and a differentiated bit is used in the FOR-NEXT loop, that bit will be always ON or always OFF within that loop. In the following example, the looped program section transfers the content of D100 to the address indicated in D200 and then increments the content of D200 by 1.

Example

&3

Repeated 3 times.

D100 @D200

D100 D200

D0 D1 D2

D200

#0000

3-4-10 BREAK LOOP: BREAK(514)

Purpose Programmed in a FOR-NEXT loop to cancel the execution of the loop for a given execution condition. The remaining instructions in the loop are processed as NOP(000) instructions.

Ladder Symbol
BREAK(514)

166

Sequence Control Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-4

BREAK(514) Not supported Not supported Not supported

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

Description

Program BREAK(514) between FOR(512) and NEXT(513) to cancel the FOR-NEXT loop when BREAK(514) is executed. When BREAK(514) is executed, the rest of the instructions up to NEXT(513) are processed as NOP(000).
N repetitions Condition a ON

Repetitions forced to end.

Processed as NOP(000).

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF OFF OFF

Precautions

A BREAK(514) instruction cancels only one loop, so several BREAK(514) instructions (the number of levels nested) are required to escape from nested loops. BREAK(514) can be used only in a FOR-NEXT loop.

167

Timer and Counter Instructions

Section 3-5

3-5

Timer and Counter Instructions

This section describes instructions used to define and handle timers and counters.
Instruction TIMER HIGH-SPEED TIMER ONE-MS TIMER ACCUMULATIVE TIMER LONG TIMER MULTI-OUTPUT TIMER COUNTER REVERSIBLE COUNTER RESET TIMER/COUNTER Mnemonic TIM/TIMX TIMH/TIMHX TMHH/TIMHHX TTIM/TTIMX TIML/TIMLX MTIM/MTIMX CNT/CNTX CNTR/CNTRX CNR/CNRX Function code ---/550 015/551 540/552 087/555 542/553 543/554 ---/546 012/548 545/547 Page 170 174 178 181 184 187 193 196 200

Refresh Methods for Timer/Counter PV

Overview The refresh method for present values timer and counter instructions can be set to either BCD or binary for CP-series CPU Units. Using binary data instead of BCD allows the SV range for timers and counter to be increased from 0 to 9999 to 0 to 65535. It also enables using binary data calculated with other instructions directly as a timer/counter SV. The refresh method is valid even when setting an SV indirectly (i.e., using the contents of memory word). (That is, the contents of the addressed word is taken as either BCD or binary data according to the refresh method that is set.) Refer to the CP Series CP1H Operation Manual for details on refresh methods.

Applicable Instructions
Classification Timer/counter instructions Instruction TIMER HIGH-SPEED TIMER ONE-MS TIMER ACCUMULATIVE TIMER LONG TIMER MULTI-OUTPUT TIMER COUNTER REVERSIBLE COUNTER RESET TIMER/COUNTER TIMER WAIT HIGH-SPEED TIMER WAIT COUNTER WAIT Mnemonic BCD Binary TIM TIMX(550) TIMH(015) TIMHX(551) TMHH(540) TMHHX(552) TTIM(087) TTIMX(555) TIML(542) TIMLX(553) MTIM(543) MTIMX(554) CNT CNTX(546) CNTR(012) CNTRX(548) CNR(545) CNRX(547) TIMW(813) TIMWX(816) TMHW(815) TMHWX(817) CNTW(814) CNTWX(818)

Block programming instructions

168

Timer and Counter Instructions Basic Timer Specifications

Item Timing method Timing units Max. SV TIM/TIMX(550) Decrementing 0.1 s TIM: 999.9 s TIMX: 6,553.5 s 1 Used At execution See note 1. OFF SV

Section 3-5

The following table shows the basic specifications of the timers.

TIMH(015)/ TIMHX(551) Decrementing 0.01 s TIMH: 99.99 s TIMHX: 655.35 s 1 Used At execution See note 2. OFF SV TMHH(540)/ TMHHX(552) Decrementing 0.001 s TMHH: 9.999 s TMHHX: 65.535 s 1 Used By interrupt every 1 ms Every 1 ms OFF SV TTIM(087)/ TTIMX(555) Incrementing 0.1 s TTIM: 999.9 s TTIMX: 6,553.5 s 1 Used At execution At execution OFF 0 TIML(542)/ TIMLX(553) Decrementing 0.1 s TIML: 115 days TIMLX: 49,710 days 1 Not used At execution At execution OFF SV MTIM(543)/ MTIMX(554) Incrementing 0.1 s MTIM: 999.9 s MTIMX: 6,553.5 s 8 Not used At execution At execution OFF 0

Outputs/ instruction Timer numbers Comp. flag refreshing Timer PV refreshing Value Comp. after flags reset PVs

Note

(1) TIM PVs are refreshed at execution for all times and also every 100 ms for T0000 to T0015. (2) TIMH(015)/TIMHX(551) PVs are refreshed at execution for all times and also every 10 ms for T0000 to T0015.

Timer Operation
Item

The following table shows the effects of operating and programming conditions on the operation of the timers.
MTIM(543)/ MTIMX(554) ----Not applicable

TIM/ TIMH(015)/ TMHH(540)/ TTIM(087)/ TIML(542)/ TIMX(550) TIMHX(551) TMHHX(552) TTIMX(555) TIMLX(553) Operating mode change PV = 0 --Completion Flag = OFF Power interrupt/reset PV = 0 --Completion Flag = OFF Execution of CNR(545)/ Binary: PV = FFFF, Completion Flag = OFF Not applicable CNRX(547) BCD: PV = FFFF or 9999, Completion Flag = OFF Operation in jumped pro- Operating timers continue timing. Timer status is maintained. gram section (JMP(004)-JME(005)) Timer status PV = SV Operation in interlocked PV = SV Completion Flag = OFF maintained. Comp. flag = program section OFF (IL(002)-ILC(003)) Forced Comp. flags ON --set PVs Set to 0. --Forced Comp. flags OFF --reset PVs Reset to SV. Set to 0. ---

Timer status maintained. ---------

169

Timer and Counter Instructions

Section 3-5

3-5-1
Purpose

TIMER: TIM/TIMX(550)
TIM or TIMX(550) operates a decrementing timer with units of 0.1-s. The setting range for the set value (SV) is 0 to 999.9 s for TIM and 0 to 6,553.5 s for TIMX(550). The timer accuracy is 0 to 0.01 s.

Ladder Symbol
PV refresh method BCD Symbol Operands

TIM N S
Binary

N: 0000 to 4095 (decimal) S: #0000 to #9999 (BCD)

N: Timer number S: Set value

N: 00000 to 4095 (decimal) S: &0 to &65535 (decimal) #0000 to #FFFF (hex)

TIMX(550) N S N: Timer number S: Set value

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification TIM/TIMX(550) Not supported. Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks Not allowed

Operands

N: Timer Number The timer number must be between 0000 and 4095 (decimal). S: Set Value The set value must be between #0000 and 9999 (BCD). (If the set value is set to #0000, the Completion Flag will be turned ON when TIM/TIMX(550) is executed.)

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD N --------0000 to 4095 (decimal) --------S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

170

Timer and Counter Instructions

Area Constants N ---

Section 3-5
S BCD: #0000 to 9999 (BCD) & cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) DR0 to DR15 ---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

Description

When the timer input is OFF, the timer specified by N is reset, i.e., the timers PV is reset to the SV and its Completion Flag is turned OFF. When the timer input goes from OFF to ON, TIM/TIMX(550) starts decrementing the PV. The PV will continue timing down as long as the timer input remains ON and the timers Completion Flag will be turned ON when the PV reaches 0000. The status of the timers PV and Completion Flag will be maintained after the timer times out. To restart the timer, the timer input must be turned OFF and then ON again or the timers PV must be changed to a non-zero value (by MOV(021), for example).
Timer input Timer PV Completion Flag SV

The following timing chart shows the behavior of the timers PV and Completion Flag when the timer input is turned OFF before the timer times out.
Timer input Timer PV Completion Flag SV

Flags
Name Error Flag Label ER Operation ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer. ON if in BCD mode and S does not contain BCD data. OFF in all other cases. OFF or unchanged OFF or unchanged

Equals Flag Negative Flag

= N

171

Timer and Counter Instructions

Precautions

Section 3-5

Timer numbers are shared by the TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817) instructions. If two timers share the same timer number, but are not used simultaneously, a duplication error will be generated when the program is checked, but the timers will operate normally. Timers which share the same timer number will not operate properly if they are used simultaneously. Timers created with timer numbers 16 to 4095 will not operate properly when the CPU Unit cycle time exceeds 100 ms. Use timer numbers 0 to 15 when the cycle time is longer than 100 ms. The present value of timers programmed with timer numbers 0 to 15 will be updated even when the timer is on standby. The present value of timers programmed with timer numbers 16 to 4095 will be held when the timer is on standby. Timers will be reset or paused in the following cases. (When a timer is reset, its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition Operating mode changed from RUN or 0000 MONITOR mode to PROGRAM mode or vice versa.1 0000 Power supply interrupted and reset2 Execution of CNR(545)/CNRX(547), the RESET TIMER/COUNTER instructions3 Operation in interlocked program section (IL(002)ILC(003)) Operation in jumped program section (JMP(004)JME(005)) PV Completion Flag OFF

OFF OFF

BCD: 9999 Binary: FFFF Reset to SV.

OFF

PV continues decrementing.

Retains previous status.

Note

(1) If the IOM Hold Bit (A500.12) has been turned ON, the status of timer Completion Flags and PVs will be maintained when the operating mode is changed. (2) If the IOM Hold Bit (A500.12) has been turned ON and the status of the IOM Hold Bit itself is protected in the PLC Setup, the status of timer Completion Flags and PVs will be maintained even when the power is interrupted. (3) The PV will be set to the SV when TIM/TIMX(550) is executed. When TIM/TIMX(550) is in a program section between IL(002) and ILC(003) and the program section is interlocked, the PV will be reset to the SV and the Completion Flag will be turned OFF. When an operating TIM/TIMX(550) timer created with a timer number between 0 and 15 is in a jumped program section (JMP(004), CJMP(510), CJPN(511), JME(005)), the timers PV will continue timing. The jumped TIM/ TIMX(550) instruction will not be executed, but the PV will be refreshed each cycle after all tasks have been executed. When a TIM/TIMX(550) timer is forced set, its Completion Flag will be turned ON and its PV will be set to 0. When a TIM/TIMX(550) timer is forced reset, its Completion Flag will be turned OFF and its PV will be reset to the SV. The operation of the = Flag and N Flag depends on the model of the CPU Unit. Refer to Flags, above, for details.

172

Timer and Counter Instructions

Section 3-5

The timers Completion Flag is refreshed only when TIM/TIMX(550) is executed, so a delay of up to one cycle may be required for the Completion Flag to be turned ON after the timer times out. If online editing is used to convert a timer to another kind of timer with the same timer number (such as TIM/TIMX(550) TIMH(015)/TIMHX(551) or TIM/TIMX(550) TMHH(540)/TMHHX(552)), be sure to reset the Completion Flag. The timer will not operate properly unless the Completion Flag is reset. A TIM/TIMX(550) instructions PV and Completion Flag can be refreshed in the following ways depending on the timer number that is used. Timers Created with Timer Numbers 0000 to 2047
Execution of TIM/ TIMX(550) The PV is updated every time that TIM/TIMX(550) is executed. The Completion Flag is turned ON if the PV is 0000. The Completion Flag is turned OFF if the PV is not 0000. 100-ms interval refreshing If the cycle time exceeds 100 ms, the timers PV is updated every 100 ms.

Timers Created with Timer Numbers T0016 to T4095

Execution of TIM The PV is updated every time that TIM is executed. The Completion Flag is turned ON if the PV is 0. The Completion Flag is turned OFF if the PV is not 0.

Timers are reset (PV = SV, Completion Flag OFF) by power interruptions unless the IOM Hold Bit (A500.12) is ON and the bit is protected in the PLC Setup. It is also possible use a clock pulse bit and a counter instruction to program a timer that will retain its PV in the event of a power interruption, as shown in the following diagram.
Execution condition 1-s clock pulse bit Count input Reset input

173

Timer and Counter Instructions

Example

Section 3-5

When timer input CIO 0.00 goes from OFF to ON in the following example, the timer PV will begin counting down from the SV. Timer Completion Flag T0000 will be turned ON when the PV reaches 0000. When CIO 0.00 goes OFF, the timer PV will be reset to the SV and the Completion Flag will be turned OFF.
0.00

#100

Timer input CIO 0.00 Timer PV T0000 Timer Completion Flag T0000

3-5-2
Purpose

HIGH-SPEED TIMER: TIMH(015)/TIMHX(551)

TIMH(015)/TIMHX(551) operates a decrementing timer with units of 10-ms. The setting range for the set value (SV) is 0 to 99.99 s for TIMH(015) and 0 to 655.35 s for TIMHX(551). The timer accuracy is 0 to 0.01 s.

Ladder Symbol
PV refresh method BCD Symbol Operands

TIMH(015) N S
Binary

N: 0000 to 4095 (decimal) S: #0000 to #9999 (BCD)

N: Timer number S: Set value

N: 00000 to 4095 (decimal) S: &0 to &65535 (decimal) #0000 to #FFFF (hex)

TIMHX(551) N S N: Timer number S: Set value

Variations
Variations TIMH(015)/ TIMHX(551) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks Not allowed

174

Timer and Counter Instructions

Operands N: Timer Number The timer number must be between 0000 and 4095 (decimal). S: Set Value The set value must be between #0000 and 9999 in BCD mode. Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants N --------0000 to 4095 (decimal) -----------

Section 3-5

S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 BCD: #0000 to 9999 (BCD) & cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) DR0 to DR15 ---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

Description

When the timer input is OFF, the timer specified by N is reset, i.e., the timers PV is reset to the SV and its Completion Flag is turned OFF. When the timer input goes from OFF to ON, TIMH(015)/TIMHX(551) starts decrementing the PV. The PV will continue timing down as long as the timer input remains ON and the timers Completion Flag will be turned ON when the PV reaches 0000. The status of the timers PV and Completion Flag will be maintained after the timer times out. To restart the timer, the timer input must be turned OFF and then ON again or the timers PV must be changed to a non-zero value (by MOV(021), for example).
Timer input Timer PV Completion Flag SV

175

Timer and Counter Instructions

Section 3-5

The following timing chart shows the behavior of the timers PV and Completion Flag when the timer input is turned OFF before the timer times out.
Timer input Timer PV Completion Flag SV

Flags
Name Error Flag Label ER Operation ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer. ON if in BCD mode and S does not contain BCD data. OFF in all other cases. OFF or unchanged OFF or unchanged

Equals Flag Negative Flag

= N

Precautions

Timer numbers are shared by the TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817) instructions. If two timers share the same timer number, but are not used simultaneously, a duplication error will be generated when the program is checked, but the timers will operate normally. Timers which share the same timer number will not operate properly if they are used simultaneously. Timers created with timer numbers 16 to 4095 will not operate properly when the CPU Unit cycle time exceeds 100 ms. Use timer numbers 0 to 15 when the cycle time is longer than 100 ms. TIMH(015)/TIMHX(551) timers created with timer numbers 0 to 15 are refreshed every 10 ms. Use these timer numbers when the PV is being referenced in the user program. The present value of timers programmed with timer numbers 0 to 15 will be updated even when the timer is on standby. The present value of timers programmed with timer numbers 16 to 4095 will be held when the timer is on standby. The operation of the = Flag and N Flag depends on the model of the CPU Unit. Refer to Flags, above, for details. Timers will be reset or paused in the following cases. (When a timer is reset, its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition Operating mode changed from RUN or MONITOR mode to PROGRAM mode or vice versa.1 Power supply interrupted and reset2 Execution of CNR(545)/CNRX(547), the RESET TIMER/COUNTER instructions3 Operation in interlocked program section (IL(002)ILC(003)) Operation in jumped program section (JMP(004)JME(005)) PV 0000 Completion Flag OFF

0000 BCD: 9999 Binary: FFFF Reset to SV.

OFF OFF OFF

PV continues Retains previous status. decrementing.

176

Timer and Counter Instructions

Note

Section 3-5

(1) If the IOM Hold Bit (A500.12) has been turned ON, the status of timer Completion Flags and PVs will be maintained when the operating mode is changed. (2) If the IOM Hold Bit (A500.12) has been turned ON and the status of the IOM Hold Bit itself is protected in the PLC Setup, the status of timer Completion Flags and PVs will be maintained even when the power is interrupted. (3) The PV will be set to the SV when TIMH(015)/TIMHX(551) is executed. When an operating TIMH(015)/TIMHX(551) timer created with a timer number between 0 and 15 is in a jumped program section (JMP(004), CJMP(510), CJPN(511), JME(005)), the timers PV will continue timing. (The jumped TIMH(015)/TIMHX(551) instruction will not be executed, but the PV will be refreshed every 10 ms and each cycle after all tasks have been executed.) When TIMH(015)/TIMHX(551) is in a program section between IL(002) and ILC(003) and the program section is interlocked, the PV will be reset to the SV and the Completion Flag will be turned OFF. When a TIMH(015)/TIMHX(551) timer is forced set, its Completion Flag will be turned ON and its PV will be set to 0. When a TIMH(015)/TIMHX(551) timer is forced reset, its Completion Flag will be turned OFF and its PV will be reset to the SV. The operation of the = Flag and N Flag depends or the model of CPU Unit. Refer to Flags for details. The timers Completion Flag is refreshed only when TIMH(015)/TIMHX(551) is executed, so a delay of up to one cycle may be required for the Completion Flag to be turned ON after the timer times out. If online editing is used to convert a timer to another kind of timer with the same timer number (such as TIMH(015)/TIMHX(551) TIM/TIMX(550) or TIMH(015)/TIMHX(551) TMHH(540)/TMHHX(552)), be sure to reset the Completion Flag. The timer will not operate properly unless the Completion Flag is reset. A TIMH(015)/TIMHX(551) instructions PV and Completion Flag can be refreshed in the following ways depending on the timer number that is used. Timers Created with Timer Numbers T0000 to T0015
Execution of TIMH(015)/ TIMHX(551) 10-ms interval refreshing The Completion Flag is turned ON if the PV is 0000. The Completion Flag is turned OFF if the PV is not 0000. The timers PV is updated every 10 ms.

Timers Created with Timer Numbers T0016 to T4095

Execution of TIMH(015)/ TIMHX(551) The PV is updated every time that TIMH(015) is executed. The Completion Flag is turned ON if the PV is 0. The Completion Flag is turned OFF if the PV is not 0.

177

Timer and Counter Instructions

Example

Section 3-5

When timer input CIO 0.00 goes from OFF to ON in the following example, the timer PV will begin counting down from the SV (#0064 = 100 = 1.00 s). The Timer Completion Flag, T0000, will be turned ON when the PV reaches 0000. When CIO 0.00 goes OFF, the timer PV will be reset to the SV and the Completion Flag will be turned OFF.
0.00

Timer input CIO 0.00 Timer PV T0000 #0100 (1.00 s)

Timer Completion Flag T0000

3-5-3
Purpose

ONE-MS TIMER: TMHH(540)/TMHHX(552)

TMHH(540)/TMHHX(552) operates a decrementing timer with units of 1-ms. The setting range for the set value (SV) is 0 to 9.999 s for TMHH(540) and 0 to 65.535 for TMHHX(552). The timer accuracy is 0.001 to 0 s.

Ladder Symbol
PV refresh method BCD Symbol Operands

TMHH(540) N S
Binary

N: 0000 to 15 (decimal) S: #0000 to #9999 (BCD)

N: Timer number S: Set value

N: 00000 to 15 (decimal) S: &0 to &65535 (decimal) #0000 to #FFFF (hex)

TMHHX(552) N S N: Timer number S: Set value

Variations
Variations TMHH(540)/ TMHHX(552) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks Not allowed

Operands

N: Timer Number The timer number must be between 0000 and 0015 (decimal). S: Set Value The set value must be between #0000 and 9999 (BCD).

178

Timer and Counter Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants N --------0000 to 0015 (decimal) -----------

Section 3-5

S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 BCD: #0000 to 9999 (BCD) & cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) DR0 to DR15 ---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

Description

When the timer input is OFF, the timer specified by N is reset, i.e., the timers PV is reset to the SV and its Completion Flag is turned OFF. When the timer input goes from OFF to ON, TMHH(540)/TMHHX(552) starts decrementing the PV. The PV will continue timing down as long as the timer input remains ON and the timers Completion Flag will be turned ON when the PV reaches 0000. The status of the timers PV and Completion Flag will be maintained after the timer times out. To restart the timer, the timer input must be turned OFF and then ON again or the timers PV must be changed to a non-zero value (by MOV(021), for example).

Flags
Name Error Flag Label ER Operation ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer. ON if in BCD mode and S does not contain BCD data. OFF in all other cases. OFF or unchanged OFF or unchanged

Equals Flag Negative Flag

= N

Precautions

Timer numbers are shared by the TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817) instructions. If two timers share the same timer number, but are not used simultaneously, a duplication error will be generated when the program is checked, but the timers will operate normally. Timers which share the same timer number will not operate properly if they are used simultaneously.

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The Completion Flag is updated only when TMHH(540)/TMHHX(552) is executed. The Completion Flag can thus be delayed by up to one cycle time from the actual set value. The present value of timers programmed with timer numbers 0000 to 2047 will be updated even when the timer is on standby. The present value of timers programmed with timer numbers 2048 to 4095 will be held when the timer is on standby. Timers will be reset or paused in the following cases. (When a timer is reset, its PV is reset to the SV and its Completion Flag is turned OFF.)
Condition Operating mode changed from RUN or MONITOR mode to PROGRAM mode or vice versa.1 Power supply interrupted and reset2 Execution of CNR(545)/CNRX(547), the RESET TIMER/COUNTER instructions3 Operation in interlocked program section (IL(002)ILC(003)) Operation in jumped program section (JMP(004)JME(005)) PV 0000 Completion Flag OFF

0000

OFF

BCD: 9999 OFF Binary: FFFF Reset to SV. OFF

PV continues Retains previous status. decrementing.

Note

(1) If the IOM Hold Bit (A500.12) has been turned ON, the status of timer Completion Flags and PVs will be maintained when the operating mode is changed. (2) If the IOM Hold Bit (A500.12) has been turned ON and the status of the IOM Hold Bit itself is protected in the PLC Setup, the status of timer Completion Flags and PVs will be maintained even when the power is interrupted. (3) The PV will be set to the SV when TMHH(540)/TMHHX(552) is executed. When an operating TMHH(540)/TMHHX(552) timer is in a jumped program section (JMP(004), CJMP(510), CJPN(511), JME(005)), the timers PV will continue timing. (The jumped TMHH(540)/TMHHX(552) instruction will not be executed, but the PV will be refreshed every 1 ms.) When TMHH(540)/TMHHX(552) is in a program section between IL(002) and ILC(003) and the program section is interlocked, the PV will be reset to the SV and the Completion Flag will be turned OFF. When a TMHH(540)/TMHHX(552) timer is forced set, its Completion Flag will be turned ON and its PV will be set to 0000. When a TMHH(540)/ TMHHX(552) timer is forced reset, its Completion Flag will be turned OFF and its PV will be reset to the SV. The operation of the = Flag and N Flag depends on the model of the CPU Unit. Refer to Flags, above, for details. If online editing is used to convert a timer to another kind of timer with the same timer number (such as TMHH(540)/TMHHX(552) TIM/TIMX(550) or TMHH(540)/TMHHX(552) TIMH(015)/TIMHX(551)), be sure to reset the Completion Flag. The timer will not operate properly unless the Completion Flag is reset.

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Section 3-5

A TMHH(540)/TMHHX(552) instructions PV and Completion Flag are refreshed as shown in the following table.
Execution of TMHH(540)/ TMHHX(552) 1-ms interval refreshing The Completion Flag is turned ON if the PV is 0000. The Completion Flag is turned OFF if the PV is not 0000. The timers PV is updated every 1 ms.

3-5-4
Purpose

ACCUMULATIVE TIMER: TTIM(087)/TTIMX(555)

TTIM(087)/TTIMX(555) operates an incrementing timer with units of 0.1-s. The setting range for the set value (SV) is 0 to 999.9 s for TTIM(087) and 0 to 6,553.5 s for TTIMX(555). The timer accuracy is 0.01 to 0 s.

Ladder Symbol
PV refresh method BCD Symbol Operands

Timer input

TTIM(087) N S

N: 0000 to 15 (decimal) S: #0000 to #9999 N: Timer number (BCD)

S: Set value

Reset input
Binary

Timer input

TTIMX(555) N S

N: 00000 to 15 (decimal) S: &0 to &65535 N: Timer number (decimal) #0000 to #FFFF S: Set value (hex)

Reset input

Variations
Variations TTIM(087)/ TTIMX(555) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks Not allowed

Operands

N: Timer Number The timer number must be between 0000 to 4095 (decimal). S: Set Value The set value must be between #0000 and 9999 (BCD).

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area N --------0000 to 4095 (decimal) S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095

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Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants N -----------

Section 3-5
S C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 BCD: #0000 to 9999 (BCD) & cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) DR0 to DR15 ---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

Description

When the timer input is ON, TTIM(087)/TTIMX(555) increments the PV. When the timer input goes OFF, the timer will stop incrementing the PV, but the PV will retain its value. The PV will resume timing when the timer input goes ON again. The timers Completion Flag will be turned ON when the PV reaches the SV. The status of the timers PV and Completion Flag will be maintained after the timer times out. There are three ways to restart the timer: the timers PV can be changed to a non-zero value (by MOV(021), for example), the reset input can be turned ON, or CNR(545)/CNRX(547) can be executed.
Timer input Timer PV SV Timing resumes. PV maintained. Completion Flag Reset input

Flags
Name Error Flag Label ER Operation ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer. ON if in BCD mode and S does not contain BCD data. OFF in all other cases.

Precautions

Timer numbers are shared by the TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817) instructions. If two timers share the same timer number, but are not used simultaneously, a duplication error will be generated when the program is checked, but the timers will operate normally. Timers which share the same timer number will not operate properly if they are used simultaneously.

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Timers will be reset or paused in the following cases. (When a TTIM(087)/ TTIMX(555) timer is reset, its PV is reset to 0000 and its Completion Flag is turned OFF.)
Condition PV Operating mode changed from RUN or 0000 MONITOR mode to PROGRAM mode or vice versa.1 0000 Power supply interrupted and reset2 Execution of CNR(545)/CNRX(547), the RESET TIMER/COUNTER instructions3 Operation in interlocked program section (IL(002)ILC(003)) Operation in jumped program section (JMP(004)JME(005)) Completion Flag OFF

OFF

BCD: 9999 OFF Binary: FFFF Retains previ- Retains previous status. ous status. Retains previ- Retains previous status. ous status.

Note

(1) If the IOM Hold Bit (A500.12) has been turned ON, the status of timer Completion Flags and PVs will be maintained when the operating mode is changed. (2) If the IOM Hold Bit (A500.12) has been turned ON and the status of the IOM Hold Bit itself is protected in the PLC Setup, the status of timer Completion Flags and PVs will be maintained even when the power is interrupted. (3) The PV will be set to the SV when TTIM(087)/TTIMX(555) is executed. When TTIM(087)/TTIMX(555) is in a program section between IL(002) and ILC(003) and the program section is interlocked, the PV will retain its previous value (it will not be reset). Be sure to take this fact into account when TTIM(087)/TTIMX(555) is programmed between IL(002) and ILC(003). When an operating TTIM(087)/TTIMX(555) timer is in a program section between JMP(004) and JME(005) and the program section is jumped, the PV will retain its previous value. Be sure to take this fact into account when TTIM(087)/TTIMX(555) is programmed between JMP(004) and JME(005). When a TTIM(087)/TTIMX(555) timer is forced set, its Completion Flag will be turned ON and its PV will be reset to 0000. When a TTIM(087)/TTIMX(555) timer is forced reset, its Completion Flag will be turned OFF and its PV will be reset to 0000. The forced set and forced reset operations take priority over the status of the timer and reset inputs. The timers PV is refreshed only when TTIM(087)/TTIMX(555) is executed, so the timer will not operate properly when the cycle time exceeds 100 ms because the timer increments in 100-ms units. The timers Completion Flag is refreshed only when TTIM(087)/TTIMX(555) is executed, so a delay of up to one cycle may be required for the Completion Flag to be turned ON after the timer times out. Typical timers such as TIM/TIMX(550) are decrementing counters and the PV shows the time remaining until the timer times out. The PV of TTIM(087)/ TTIMX(555) shows how much time has elapsed, so the PV can be used unchanged in many calculations and display outputs.

Example

When timer input CIO 0.00 is ON in the following example, the timer PV will begin counting up from 0. Timer Completion Flag T0001 will be turned ON when the PV reaches the SV. If the reset input is turned ON, the timer PV will be reset to 0000 and the Completion Flag (T0001) will be turned OFF. (Usually the reset input is turned ON to reset the timer and then the timer input is turned ON to start timing.)

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Section 3-5

If the timer input is turned OFF before the SV is reached, the timer will stop timing but the PV will be maintained. The timer will resume from its previous PV when the timer input is turned ON again.
0.00

0.01

#100

Timer input CIO 0.00 Timer PV T0001

Timing resumes. PV maintained.

Timer Completion Flag T0001 Reset input CIO 0.01

3-5-5
Purpose

LONG TIMER: TIML(542)/TIMLX(553)

TIML(542)/TIMLX(553) operates a decrementing timer with units of 0.1 s that can time up to 115 days for TIML(542) and 4,971 days for TIMLX(543). The timer accuracy is 0 to 0.01 s. BCD
TIML(542) D1 D2 S D1: Completion Flag D2: PV word S: SV word

Ladder Symbol

Binary
TIMLX(543) D1 D2 S D1: Completion Flag D2: PV word S: SV word

Variations
Variations TIML(542)/ TIMLX(553) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

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Applicable Program Areas
Block program areas Step program areas Not allowed OK Subroutines OK

Section 3-5

Interrupt tasks Not allowed

Operands

D1: Completion Flag Bit 0 of D1 acts as the Completion Flag for TIML(542)/TIMLX(553).
15 D1 Do not use. Completion Flag 0

D2: PV Word D2+1 and D2 contain the 8-digit binary or BCD PV. (D2 and D2+1 must be in the same data area.) The PV can range from #00000000 to #99999999 for TIML(542) and &00000000 to &4294967295 (decimal) or #00000000 to #FFFFFFFF (hexadecimal) for TIMLX(553).
D2 D2+1 D2

S: SV Word S+1 and S contain the 8-digit binary or BCD SV. (S and S+1 must be in the same data area.) The SV must be between #00000000 to #99999999 for TIML(542) and &00000000 to &4294967294 (decimal) or #00000000 to #FFFFFFFF (hexadecimal) for TIMLX(553).
S S+1 S

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants D1 D2 S CIO 0 to CIO 0 to CIO 6142 CIO 6143 W0 to W511 W0 to W510 H0 to H511 H0 to H510 A448 to A959 A448 to A958 A0 to A958 ----T0000 to T4094 ----C0000 to C4094 D0 to D32767 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 --BCD: #00000000 to 99999999 (BCD) & cannot be used. Binary: &00000000 to &4294967295 (decimal) or #00000000 to #FFFFFFFF (hex)

Data Registers

---

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Timer and Counter Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-5
D1 D2 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 S

Description

TIML(542)/TIMLX(553) is a decrementing ON-delay timer with units of 0.1-s that uses an 8-digit SV and an 8-digit PV. When the timer input is OFF, the timer is reset, i.e., the timers PV is reset to the SV and its Completion Flag is turned OFF. When the timer input goes from OFF to ON, TIML(542)/TIMLX(553) starts decrementing the PV in D2+1 and D2. The PV will continue timing down as long as the timer input remains ON and the timers Completion Flag will be turned ON when the PV reaches 0000 0000. The status of the timers PV and Completion Flag will be maintained after the timer times out. To restart the timer, the timer input must be turned OFF and then ON again or the timers PV must be changed to a non-zero value (by MOV(021), for example).
Timer input

Timer PV

SV

Completion Flag (Bit 00 of D1)

Flags
Name Error Flag Label ER Operation ON if BCD was specified and the PV contained in D2+1 and D2 is not BCD. ON if the SV contained in S+1 and S is not BCD. OFF in all other cases.

Precautions

Unlike most timers, TIML(542)/TIMLX(553) does not use a timer number. (Timer area PV refreshing is not performed for TIML(542)/TIMLX(553).) Since the Completion Flag for TIML(542)/TIMLX(553) is in a data area it can be forced set or forced reset like other bits, but the PV will not change. The timers PV is refreshed only when TIML(542)/TIMLX(553) is executed, so the timer will not operate properly when the cycle time exceeds 100 ms because the timer increments in 100-ms units. The timers Completion Flag is refreshed only when TIML(542)/TIMLX(553) is executed, so a delay of up to one cycle may be required for the Completion Flag to be turned ON after the timer times out. When TIML(542)/TIMLX(553) is in a program section between IL(002) and ILC(003) and the program section is interlocked, the PV will be reset to the SV and the Completion Flag will be turned OFF. When an operating TIML(542)/TIMLX(553) timer is in a program section between JMP(004) and JME(005) and the program section is jumped, the PV will retain its previous value. Be sure to take this fact into account when TIML(542)/TIMLX(553) is programmed between JMP(004) and JME(005).

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Be sure that the words specified for the Completion Flag and PV (D1, D2, and D2+1) are not used in other instructions. If these words are affected by other instructions, the timer might not time out properly. Example When timer input CIO 0.00 is ON in the following example, the timer PV (in D101 and D100) will be set to the SV (in D201 and D200) and the PV will begin counting down. The timer Completion Flag (CIO 200.00) will be turned ON when the PV reaches 0000 0000. When CIO 0.00 goes OFF, the timer PV will be reset to the SV and the Completion Flag will be turned OFF.
0.00 200 D100 D200

Timer input CIO 0.00 Timer PV (D101 and D100) Timer SV: (D201 and D200)

Timer Completion Flag (CIO 200.00) D1: 200 Timer Completion Flag (CIO 200.00) D2: D100 D101 Timer's PV (LSB) Timer's PV (MSB)

S: D200 D201

0 1

Timer SV: (100,000 decimal= 10,000 s)

3-5-6
Purpose

MULTI-OUTPUT TIMER: MTIM(543)/MTIMX(554)

MTIM(543)/MTIMX(554) operates a 0.1-s incrementing timer with eight independent SVs and Completion Flags. The set value is 0 to 999.9 s for MTIM(543) and 0 to 6,553.5 s for MTIMX(554), and the timer accuracy is 0 to 0.01 s. BCD
MTIM(543) D1 D2 S D1: Completion Flags D2: PV word S: First SV word

Ladder Symbol

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Timer and Counter Instructions

Binary
MTIMX(554) D1 D2 S D1: Completion Flags D2: PV word S: First SV word

Section 3-5

Variations
Variations MTIM(543)/ MTIMX(554) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks Not allowed

Operands

D1: Completion Flags D1 contains the eight Completion Flags as well as the pause and reset bits.
15 D1 Do not use. Completion Flags Reset bit Pause bit 9 87 65 4 3 2 1 0

D2: PV Word D2 contains the 4-digit binary or BCD PV.

Data BCD Binary Range #0000 to #9999 &0 to &65535 (decimal) #0000 to #FFFF (hex)

S: First SV Word S through S+7 contain the eight independent SVs. Each SV must be as follows:
Data BCD Binary Range #0000 to #9999 &0 to &65535 (decimal) #0000 to #FFFF (hex)
Corresponding bit (Completion Flag) in D1

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Timer and Counter Instructions

Data BCD Binary Range One word for each of 8 timer SV: #0000 to #9999 One word for each of 8 timer SV: &0 to &65535 (decimal) #0000 to #FFFF (hex)

Section 3-5

Note Operand Specifications

S through S+7 must be in the same data area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers

D1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767

D2

S CIO 0 to CIO 6136 W0 to W504 H0 to H504 A0 to A952 T0000 to T4088 C0000 to C4088 D0 to D32760

*D0 to *D32767 ----DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

When the execution condition for MTIM(543)/MTIMX(554) is ON and the reset and timer bits are both OFF, MTIM(543)/MTIMX(554) increments the PV in D2. If the pause bit is turned ON, the timer will stop incrementing the PV, but the PV will retain its value. MTIM(543)/MTIMX(554) will resume timing when the pause bit goes OFF again. The PV (content of D2) is compared to the eight SVs in S through S+7 each time that MTIM(543)/MTIMX(554) is executed, and if any of the SVs is less than or equal to the PV, the corresponding Completion Flag (D1 bits 00 through 07) is turned ON. When the PV reaches 9999, the PV will be reset to 0000 and all of the Completion Flags will be turned OFF. If the reset bit is turned ON while the timer is operating or paused, the PV will be reset to 0000 and all of the Completion Flags will be turned OFF.

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Timer PV

Section 3-5

Timer SVs 0

to

to

Timer input SV 7 SV 2 Timer PV (D2) SV 1 SV 0 0 Bit 7 Completion flags (D1) Bit 2 Bit 1 Bit 0

The following table shows the operation of MTIM(543)/MTIMX(554) for the four possible combinations of the reset and pause bits.
Reset bit (Bit 08) OFF Pause bit Operation (Bit 09) OFF The PV will be updated and the corresponding Completion Flag will be turned ON when SV PV. ON The PV will not be updated and MTIM(543)/MTIMX(554) will be treated as NOP(000). OFF The PV will be reset to 0000 and the Completion Flags will be turned OFF. The PV will not be updated. ON

ON

The reset and pause bits are effective only when the execution condition for MTIM(543)/MTIMX(554) is ON. Flags
Name Error Flag Label ER Operation ON if the PV contained in D2 is not BCD. OFF in all other cases.

Precautions

Unlike most timers, MTIM(543)/MTIMX(554) does not use a timer number. (Timer area PV refreshing is not performed for MTIM(543)/MTIMX(554).) When the PV reaches 9999, the PV will be reset to 0000 and all of the Completion Flags will be turned OFF. If in BCD mode and an SV in S through S+7 does not contain BCD data, that SV will be ignored. An error will not occur and the Error Flag will not be turned ON. Since the Completion Flag for MTIM(543)/MTIMX(554) is in a data area it can be forced set or forced reset like other bits, but the PV will not change.

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When eight or fewer SVs are required, set the word after the last SV to 0000. MTIM(543)/MTIMX(554) will ignore the SV that is set to 0000 and all of the remaining SVs.

to

to These SVs are ignored.

The timers PV is refreshed only when MTIM(543)/MTIMX(554) is executed, so the timer will not operate properly when the cycle time exceeds 100 ms because the timer increments in 100-ms units. To ensure precise timing and prevent problems caused by long cycle times, input the same MTIM(543)/ MTIMX(554) instruction at several points in the program. The timers Completion Flag is refreshed only when MTIM(543)/MTIMX(554) is executed, so a delay of up to one cycle may be required for the Completion Flag to be turned ON after the timer times out. When MTIM(543)/MTIMX(554) is in a program section between IL(002) and ILC(003) and the program section is interlocked, the PV will retain its previous value (it will not be reset). Be sure to take this fact into account when MTIM(543)/MTIMX(554) is programmed between IL(002) and ILC(003). When an operating MTIM(543)/MTIMX(554) timer is in a program section between JMP(004) and JME(005) and the program section is jumped, the PV will retain its previous value. Be sure to take this fact into account when MTIM(543)/MTIMX(554) is programmed between JMP(004) and JME(005). Be sure that the words specified for the Completion Flags and PV (D1 and D2) are not used in other instructions. If these words are affected by other instructions, the timer might not time out properly. If a word in the CIO area is specified for D1, the SET and RSET instructions can be used to control the pause and reset bits. Example When CIO 0.00 is ON and the pause bit (CIO 200.09) is OFF in the following example, the timer will start operating when the reset bit (CIO 200.08) is turned from ON to OFF. The timers PV will begin timing up from 0000. The eight SVs in D200 through D207 are compared to the PV and the corresponding Completion Flags (CIO 200.00 through CIO 200.07) are turned ON when the SV PV.

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Timer and Counter Instructions

0.00 200 D100 D200

Section 3-5

D1: 200 Completion Flags Reset bit Pause bit

Timer PV D2: D100 Timer SVs S: D200 S+1: D201 S+2: D202 S+3: D203 S+4: D204 S+5: D205 S+6: D206 S+7: D207 Timer input CIO 0.00 Reset bit CIO 200.08 Pause bit CIO 200.09 Max. PV = 9999 Timer SVs SV 7 SV 1 SV 0 Timing resumes.

(Incrementing) Corresponding completion flag ON when SV PV.

Timer input must remain ON while the timer is timing.

PV maintained.

Completion Flags
200.00

200.01

200.07

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Section 3-5

3-5-7
Purpose

COUNTER: CNT/CNTX(546)
CNT/CNTX(546) operates a decrementing counter. The setting range 0 to 9,999 for CNT and 0 to 65,535 for CNTX(546). BCD
Count input CNT N S Reset input N: Counter number S: Set value

Ladder Symbol

Binary
Count input CNTX(546) N S Reset input N: Counter number S: Set value

Variations
Variations CNT/ CNTX(546) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

Operands

N: Counter Number The counter number must be between 0000 and 4095 (decimal). S: Set Value
Data BCD Binary Range #0000 to #9999 &0 to &65535 (decimal) #0000 to #FFFF (hex)

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary N ----------0000 to 4095 (decimal) ----S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767

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Timer and Counter Instructions

Area Indirect DM addresses in BCD Constants N ---

Section 3-5
S *D0 to *D32767

---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

BCD: #0000 to 9999 (BCD) & cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) DR0 to DR15 ---

Description

The counter PV is decremented by 1 every time that the count input goes from OFF to ON. The Completion Flag is turned ON when the PV reaches 0. Once the Completion Flag is turned ON, reset the counter by turning the reset input ON or by using the CNR(545)/CNRX(547) instruction. Otherwise, the counter cannot be restarted. The counter is reset and the count input is ignored when the reset input is ON. (When a counter is reset, its PV is reset to the SV and the Completion Flag is turned OFF.)
Count input

Reset input Counter PV SV

Completion Flag

Flags
Name Error Flag Label ER Operation ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a counter. ON if in BCD mode and S does not contain BCD data. OFF in all other cases. OFF or unchanged OFF or unchanged

Equals Flag Negative Flag

= N

Precautions

Counter numbers are shared by the CNT, CNTX(546), CNTR(012), CNTRX(548), CNTW(814), and CNTWX(818) instructions. If two counters share the same counter number but are not used simultaneously, a duplication error will be generated when the program is checked but the counters will operate normally. Counters which share the same counter number will not operate properly if they are used simultaneously. A counters PV is refreshed when the count input goes from OFF to ON and the Completion Flag is refreshed each time that CNT/CNTX(546) is executed. The Completion Flag is turned ON if the PV is 0 and it is turned OFF if the PV is not 0.

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Section 3-5

When a CNT/CNTX(546) counter is forced set, its Completion Flag will be turned ON and its PV will be reset to 0000. When a CNT/CNTX(546) counter is forced reset, its Completion Flag will be turned OFF and its PV will be set to the SV. Be sure to reset the counter by turning the reset input from OFF ON OFF before beginning counting with the count input, as shown in the following diagram. The count input will not be received if the reset input is ON.
Reset input Count input SV Counter PV

Completion Flag Ready to start counting

The reset input will take precedence and the counter will be reset if the reset input and count input are both ON at the same time. (The PV will be reset to the SV and the Completion Flag will be turned OFF.)
Reset input Count input SV Counter PV Completion Flag Count input Reset input Count input can be re- takes pre- can be received. cedence. ceived.

The operation of the = Flag and N Flag depends on the model of the CPU Unit. Refer to Flags, above, for details. Note If online editing is used to add a counter, the counter must be reset before it will work properly. If the counter is not reset, the previous value will be used as the counters present value (PV), and the counter may not operate properly after it is written.

195

Timer and Counter Instructions

Section 3-5

Counter PVs are retained even through a power interruption. If you want to restart counting from the SV instead of resuming the count from the retained PV, add the First Cycle Flag (A200.11) as a reset input to the counter.

First Cycle Flag (A200.11)

3-5-8
Purpose

REVERSIBLE COUNTER: CNTR(012)/CNTRX(548)

CNTR(012)/CNTRX(548) operates a reversible counter. BCD
Increment input CNTR(012) N S Decrement input Reset input N: Counter number S: Set value

Ladder Symbol

Binary
Increment input CNTRX(548) N S Decrement input Reset input N: Counter number S: Set value

Variations
Variations CNTR(012)/ CNTRX(548) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas Not allowed OK Subroutines OK Interrupt tasks OK

Operands

N: Counter Number The counter number must be between 0000 and 4095 (decimal). S: Set Value
Data BCD Binary Range #0000 to #9999 &0 to &65535 (decimal) #0000 to #FFFF (hex)

196

Timer and Counter Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants N ----------0000 to 4095 (decimal) -----

Section 3-5

S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767

---

*D0 to *D32767

---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

BCD: #0000 to 9999 (BCD) & cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) DR0 to DR15 ---

Description

The counter PV is incremented by 1 every time that the increment input goes from OFF to ON and it is decremented by 1 every time that the decrement input goes from OFF to ON. The PV can fluctuate between 0 and the SV.

Increment input Decrement input

Counter PV

When incrementing, the Completion Flag will be turned ON when the PV is incremented from the SV back to 0 and it will be turned OFF again when the PV is incremented from 0 to 1.
Counter PV SV +1

Completion Flag

197

Timer and Counter Instructions

Section 3-5

When decrementing, the Completion Flag will be turned ON when the PV is decremented from 0 up to the SV and it will be turned OFF again when the PV is decremented from the SV to SV1.
SV Counter PV 1

Completion Flag

Flags
Name Error Flag Label ER Operation ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a counter. ON if in BCD mode and S does not contain BCD data. OFF in all other cases.

Precautions

Counter numbers are shared by the CNT, CNTX(546), CNTR(012), CNTRX(548), CNTW(814), and CNTWX(818) instructions. If two counters share the same counter number but are not used simultaneously, a duplication error will be generated when the program is checked but the counters will operate normally. Counters which share the same counter number will not operate properly if they are used simultaneously. The PV will not be changed if the increment and decrement inputs both go from OFF to ON at the same time. When the reset input is ON, the PV will be reset to 0 and both count inputs will be ignored. The Completion Flag will be ON only when the PV has been incremented from the SV to 0 or decremented from 0 to the SV; it will be OFF in all other cases. When inputting the CNTR(012)/CNTRX(548) instruction with mnemonics, first enter the increment input (II), then the decrement input (DI), the reset input (R), and finally the CNTR(012)/CNTRX(548) instruction. When entering with the ladder diagrams, first input the increment input (II), then the CNTR(012)/ CNTRX(548) instruction, the decrement input (DI), and finally the reset input (R).

198

Timer and Counter Instructions

Examples Basic Operation of CNTR(012)/CNTRX(548)

Section 3-5

The counter PV is reset to 0 by turning the reset input (CIO 0.02) ON and OFF. The PV is incremented by 1 each time that the increment input (CIO 0.00) goes from OFF to ON. When the PV is incremented from the SV (3), it is automatically reset to 0 and the Completion Flag is turned ON. Likewise, the PV is decremented by 1 each time that the decrement input (CIO 0.01) goes from OFF to ON. When the PV is decremented from 0, it is automatically set to the SV (3) and the Completion Flag is turned ON.
0.00 Increment input

Decrement 0.01 input

0.02

#3

Reset input

Increment input CIO 0.00 Decrement input CIO 0.01 Reset input CIO 0.02 SV

Counter PV C0001

Completion Flag C0001

199

Timer and Counter Instructions

Specifying the SV in a Word

Section 3-5

In the following example, the SV for CNTR(012) 0007 is determined by the content of CIO 1. The content of CIO 1 can be controlled by an external switch so that the set value can be changed manually from the switch.
0.00 0.01

Fixed SV: 5000

0.02

200.07

0.03 0.04 0.05 200.08

SV: CIO 1

Increment input

Decrement input Completion Flag Roll-over Roll-back

3-5-9
Purpose

RESET TIMER/COUNTER: CNR(545)/CNRX(547)

Resets the timers or counters within the specified range of timer or counter numbers. BCD
CNR(545) N1 N2 N1: First number in range N2: Last number in range

Ladder Symbol

Binary
CNRX(547) N1 N2 N1: First number in range N2: Last number in range

200

Timer and Counter Instructions

Variations
Variations

Section 3-5

CNR(545)/ CNRX(547) Executed Once for Upward Differentiation @CNR(545)/ CNRX(547) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported.

Executed Each Cycle for ON Condition

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

N1: First Number in Range N1 must be a timer number between T0000 and T4095 or a counter number between C0000 and C4095. N2: Last Number in Range N2 must be a timer number between T0000 and T4095 or a counter number between C0000 and C4095. Note N1 and N2 must be in the same data area, i.e., N1 and N2 must be timer numbers or counter numbers.

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers N1 --------C0000 to C4095 T0000 to T4095 ------N2 --------C0000 to C4095 T0000 to T4095 -------

------------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

CNR(545)/CNRX(547) resets the Completion Flags of all timers or counters from N1 to N2. At the same time, the PVs will all be set to the maximum value (9999 for BCD and FFFF for binary). (The PV will be set to the SV the next time that the timer or counter instruction is executed.)

201

Timer and Counter Instructions

Timers Reset by CNR(545)/CNRX(547)

Section 3-5

The following timers will be reset if their timer numbers fall within the specified range: TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817). When a timer is reset, its Completion Flag is turned OFF and its PV is set to the maximum value of 9999. Note The TIML(542), TIMLX(553), MTIM(543), and MTIMX(554) timers are not reset by CNR(545)/CNRX(547) because these timers do not use timer numbers. Counters Reset by CNR(545)/CNRX(547) The following counters will be reset if their counter numbers fall within the specified range: CNT, CNTX(546), CNTR(012), CNTRX(548), CNTW(814), and CNTWX(818). When a counter is reset, its Completion Flag is turned OFF and its PV is set to the maximum value of 9999. Flags
Name Error Flag Label ER Operation ON if N1 is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer or counter. ON if N2 is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer or counter. ON if N1 and N2 are not in the same data area. OFF in all other cases.

Precautions

CNR(545)/CNRX(547) does not reset the timer/counter instructions themselves, it resets the PVs and Completion Flags allocated to those instructions. In most cases, the effect of CNR(545)/CNRX(547) is different from directly resetting the instructions. For example, when a TIM/TIMX(550) instruction is reset directly its PV is set to the SV, but when that timer is reset by CNR(545)/ CNRX(547) its PV is set to the maximum value of 9999. When N1 and N2 are specified with N1>N2, only the Completion Flag for the timer/counter number will be reset.

Example

When CIO 0.00 is ON in the following example, the Completion Flags for timers T0002 to T0005 are turned OFF and the timers PVs are set to the maximum value of 9999. When CIO 0.01 is ON, the Completion Flags for counters C0003 to C0007 are turned OFF and the counters PVs are set to the maximum value of 9999.
0.00

0.01

202

Timer and Counter Instructions

Section 3-5

3-5-10 Example Timer and Counter Applications

The following examples show various applications of timer and counter instructions including long-term timers, a two-stage counter, ON/OFF delay, one-shot bit, and flicker bit. Example 1: Long-term Timers The following program examples show three ways to create long-term timers with standard TIM and CNT instructions. Two TIM Instructions In this example, two TIM instructions are combined to make a 30-minute timer.
0.00

Address Instruction Operands 000000 000001 LD TIM LD TIM LD OUT 0.00 0001 #9000 T0001 0002 #9000 T0002 200.00

T0001

000002 000003
T0002

200.00

000004 000005

TIM and CNT Instructions In this example, a TIM instruction and a CNT instruction are combined to make a 500-second timer. TIM 0001 generates a pulse every 5 s and CNT 0002 counts these pulses. The set value for this combination is the timer interval counter SV. In this case, the timer SV would be 5 s 100 = 500 s. With this combination, the long-term timers PV is actually the PV of a counter, which is maintained through power interruptions.
100.00

Address Instruction Operands 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 000010 LD LD CNT LD AND NOT AND NOT TIM LD OUT LD OUT 100.00 0.01 0002 #100 0.00 100.00 C0002 0001 #50 T0001 100.00 C0002 201.01

0.01 0.00 Start 100.00 Count up

#100

#50 100.00

200.01

203

Timer and Counter Instructions

Clock Pulse and CNT Instruction

Section 3-5

In this example, a CNT instruction counts the pulses from the 1-s clock pulse to make a 700-second timer. If the First Cycle Flag (A200.11) is ORed with the counters reset input (CIO 0.01), the counters PV will be reset to the SV (0700) when program execution begins rather than resuming the count from the previous PV.
0.00 P_1 s (1-s clock)

Address Instruction Operands 000000 000001 000002 000003 000004 000005 000006 LD AND LD NOT OR CNT LD OUT 0.00 1s 0.01 A200.11 0001 #700 C0001 200.02

0.01

#700

A200.11 200.02

C0001

Example 2: Two-stage Counter

When an SV higher than 9999 is required, two counters can be combined as shown in the following example. In this case, two CNT instructions are combined to make a BCD counter with an SV of 20,000.
0.00 0.01

Address Instruction Operands 000000 000001 000002 000003 000004 000005 000006 000007 000008 LD AND LD NOT OR OR CNT LD LD NOT CNT LD OUT 0.00 0.01 0.02 C0001 C0002 0001 #100 C0001 0.02 0002 #200 C0002 200.03

0.02

#100

0.02 #200 200.03

000009 000010

204

Timer and Counter Instructions

Example 3: ON/OFF Delay

Section 3-5

In this example two TIM timers are combined with KEEP(011) to make an ON delay and an OFF delay. CIO 100.00 will be turned ON 5.0 seconds after CIO 0.00 goes ON and it will be turned OFF 3.0 seconds after CIO 0.00 goes OFF.
0.00

Address 000000 000001 000002 000003 000004 000005 000006 000007

Instruction Operands LD TIM LD AND NOT TIM LD LD KEEP(011) 0.00 0001 #50 100.00 0.00 0002 #30 T0001 T0002 100.00

#50 100.00 0.00

#30

100.00

CIO 0.00

CIO 100.00 5.0 s 3.0 s

Example 4: One-shot Bit

A TIM timer can be combined with OUT or OUT NOT to control how long a particular bit is ON or OFF. In this example, CIO 100.00 will be ON for 1.5 seconds (the SV of T0001) after CIO 0.00 goes ON.
0.00 W0.00 W0.01 W0.00

Address 000000 000001 000002 000003 000004 000005 000006 000007 000008 000009 000010 000011

Instruction Operands LD LD AND NOT OR LD OUT LD TIM LD OUT LD AND NOT OUT 0.00 W0.00 W0.01 --W0.00 W0.00 0001 #15 T0001 W0.01 W0.00 W0.01 100.00

W0.00

#15 W0.01

W0.00

W0.01

100.00

CIO 0.00

CIO 100.00 1.5 s 1.5 s

205

Timer and Counter Instructions

Example 5: Flicker Bit

Section 3-5

The following program examples show two ways to create flicker bits. The second example just mimics a clock pulse. Two TIM Instructions Two TIM timers can be combined to make a bit turn ON and OFF at regular intervals while the execution condition is ON. In this example, CIO 200.00 will be OFF for 1.0 second and then ON for 1.5 seconds as long as CIO 0.00 is ON.
0.00

Address 000000 000001 000002 000003 000004

#15 200.00

Instruction Operands LD AND TIM LD TIM LD OUT 0.00 T0002 0001 #10 200.00 0002 #15 T0001 200.00

#10 200.00

000005 000006

CIO 0.00 CIO 200.00

1.0 s 1.5 s 1.0 s 1.5 s

Clock Pulse The desired execution condition can be combined with a clock pulse to mimic the clock pulse (0.1 s, 0.2 s, or 1.0 s).
0.00 P_1 s 1-s clock pulse 0.00 100.00

Address Instruction Operands 000000 000001 000002 LD AND OUT 0.00 1s 100.00

1-s clock pulse

100.00

3-5-11 Indirect Addressing of Timer/Counter Numbers

Timer and counter numbers can be indirectly addressed using Index Registers. When Index Registers will be used for indirect addressing, use MOVRW(561) (MOVE TIMER/COUNTER PV TO REGISTER) to set the PLC memory address of the desired timer or counters PV to the desired Index Register. The following timers and counters can be indirectly addressed using Index Registers: TIM, TIMX(550), TIMH(015), TIMHX(551), TTIM(087), TTIMX(555), TMHH(540), TMHHX(552), TIMW(813), TIMWX(816), TMHW(815), TMHWX(817), CNT, CNTX(546), CNTR(012), CNTRX(548), CNTW(814), and CNTWX(818). (These are the timers and counters that use timer and counter numbers.)

206

Timer and Counter Instructions

Section 3-5

The timer or counter instruction will not be executed if the PLC memory address in the specified Index Register is not the address of a timer or counter PV. Using Index Registers to indirectly address timers and counters can reduce the size of the program and increase flexibility. For example, common subroutines can be created. Example The following example shows a program section that uses indirect addressing to define and start 100 timers with SVs contained in D100 through D199. IR0 contains the PLC memory address of the timer PV and IR1 contains the PLC memory address of the timer Completion Flag.
DM address D100 D101 D102 . . . D199
P_On 1 (Always ON Flag)

Content 0010 0100 0050 . . . 0999

Function SV for T0000 SV for T0001 SV for T0002 . . . SV for T0099

3
2000.00

&100 D0

FOR &100

5
@D0

P_On ++ (Always ON Flag)

D0

NEXT

1,2,3...

1. MOVRW(561) moves the PLC memory address of the PV for timer T0000 to IR0. Afterwards IR0 can be used in place of the timer number.

207

Timer and Counter Instructions

Section 3-5

2. MOVR(560) moves the PLC memory address of the Completion Flag for timer T0000 to IR1. 3. MOVR(560) moves the PLC memory address of CIO 2000.00 into IR2. 4. MOV(021) moves &100 into D0 for indirect addressing of the timer SVs. 5. The content of IR0, IR1, IR2, and D0 are incremented by 1 each time as this loop is executed 100 times, starting timers T0 through T99. The loop in the program above has 4 input parameters which are used to start all 100 timers with this common subroutine. IR0 IR1 IR2 D0
2000.00

The PLC memory address of the timers PV The PLC memory address of the timers Completion Flag The PLC memory address of the timers execution condition The DM address of the word containing the timers SV

The subroutine above is equivalent to the 400 instructions below.

D100 T0000 2000.00

2000.01

D101 T0001 2000.01

2006.02

D199 T0099 2006.02

208

Comparison Instructions

Section 3-6

3-6

Comparison Instructions
This section describes instructions used to compare data of various lengths and in various ways.
Instruction Input Comparison Instructions Time Comparison Instructions COMPARE DOUBLE COMPARE SIGNED BINARY COMPARE DOUBLE SIGNED BINARY COMPARE MULTIPLE COMPARE TABLE COMPARE Mnemonic =, <>, <, <=, >, >= (S, L) (LD, AND, OR) =DT, <>DT, <DT, <=DT, >DT, >=DT (LD, AND, OR) CMP CMPL CPS CPSL MCMP TCMP Function code 300 to 328 341 to 346 020 060 114 115 019 085 068 502 Page 209 215 220 222 225 227 230 233 235 238

BLOCK COMPARE BCMP EXPANDED BLOCK COMPARE BCMP2

3-6-1
Purpose

Input Comparison Instructions (300 to 328)

Input comparison instructions compare two values (constants and/or the contents of specified words) and create an ON execution condition when the comparison condition is true. Input comparison instructions are available to compare signed or unsigned data of one-word or double length data. Note Refer to 3-14-21 Single-precision Floating-point Comparison Instructions for details on single-precision floating-point input comparison instructions and 315-21 Double-precision Floating-point Input Instructions for details on doubleprecision floating-point input comparison instructions.

Ladder Symbol
Symbol & options S1 S2 S1: Comparison data 1 S2: Comparison data 2

Variations
Variations Creates ON Each Cycle Comparison is True Input comparison instruction Not supported

Immediate Refreshing Specification

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications for Instructions for One-word Data

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area S1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 S2

209

Comparison Instructions
Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S1 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-6
S2

#0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Operand Specifications for Instructions for Double-length Data

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) &0 to &4294967295 (unsigned decimal) --IR0 to IR15 (for unsigned data only) ,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 S2

Description

The input comparison instruction compares S1 and S2 as signed or unsigned values and creates an ON execution condition when the comparison condition is true. Unlike instructions such as CMP(020) and CMPL(060), the result of an input comparison instruction is reflected directly as an execution condition, so it is not necessary to access the result of the comparison through an Arithmetic Flag and the program is simpler and faster.

210

Comparison Instructions
Inputting the Instructions

Section 3-6

The input comparison instructions are treated just like the LD, AND, and OR instructions to control the execution of subsequent instructions.
Input type LD AND OR
LD connection <

Operation The instruction can be connected directly to the left bus bar. The instruction cannot be connected directly to the left bus bar. The instruction can be connected directly to the left bus bar.
ON execution condition when comparison result is true.

AND connection <

ON execution condition when comparison result is true.

OR connection

< ON execution condition when comparison result is true.

Options The input comparison instructions can compare signed or unsigned data and they can compare one-word or double values. If no options are specified, the comparison will be for one-word unsigned data. With the three input types and two options, there are 72 different input comparison instructions.
= <> < <= > >= Symbol (Equal) (Not equal) (Less than) (Less than or equal) (Greater than) (Greater than or equal) Option (data format) None: Unsigned data S: Signed data Option (data length) None: One-word data L: Double-length data

Unsigned input comparison instructions (i.e., instructions without the S option) can handle unsigned binary or BCD data. Signed input comparison instructions (i.e., instructions with the S option) handle signed binary data.

211

Comparison Instructions
Summary of Input Comparison Instructions

Section 3-6

The following table shows the function codes, mnemonics, names, and functions of the 72 input comparison instructions. (For one-word comparisons C1=S1 and C2=S2; for double comparisons C1=S1+1, S1 and C2=S2+1, S2.)
Code Mnemonic 300 LD= AND= OR= 301 LD=L AND=L OR=L 302 LD=S AND=S OR=S 303 LD=SL AND=SL OR=SL 305 LD<> AND<> OR<> 306 LD<>L AND<>L OR<>L 307 LD<>S AND<>S OR<>S 308 LD<>SL AND<>SL OR<>SL 310 LD< AND< OR< 311 LD<L AND<L OR<L 312 LD<S AND<S OR<S 313 LD<SL AND<SL OR<SL Name LOAD EQUAL AND EQUAL OR EQUAL LOAD DOUBLE EQUAL AND DOUBLE EQUAL OR DOUBLE EQUAL LOAD SIGNED EQUAL AND SIGNED EQUAL OR SIGNED EQUAL LOAD DOUBLE SIGNED EQUAL AND DOUBLE SIGNED EQUAL OR DOUBLE SIGNED EQUAL LOAD NOT EQUAL AND NOT EQUAL OR NOT EQUAL LOAD DOUBLE NOT EQUAL AND DOUBLE NOT EQUAL OR DOUBLE NOT EQUAL LOAD SIGNED NOT EQUAL AND SIGNED NOT EQUAL OR SIGNED NOT EQUAL LOAD DOUBLE SIGNED NOT EQUAL AND DOUBLE SIGNED NOT EQUAL OR DOUBLE SIGNED NOT EQUAL LOAD LESS THAN AND LESS THAN OR LESS THAN LOAD DOUBLE LESS THAN AND DOUBLE LESS THAN OR DOUBLE LESS THAN LOAD SIGNED LESS THAN AND SIGNED LESS THAN OR SIGNED LESS THAN LOAD DOUBLE SIGNED LESS THAN AND DOUBLE SIGNED LESS THAN OR DOUBLE SIGNED LESS THAN Function True if C1 = C2

True if C1 C2

True if C1 < C2

212

Comparison Instructions
Code Mnemonic 315 LD<= AND<= OR<= 316 LD<=L AND<=L OR<=L 317 LD<=S AND<=S OR<=S 318 LD<=SL AND<=SL OR<=SL 320 LD> AND> OR> 321 LD>L AND>L OR>L 322 LD>S AND>S OR>S 323 LD>SL AND>SL OR>SL 325 LD>= AND>= OR>= 326 LD>=L AND>=L OR>=L 327 LD>=S AND>=S OR>=S 328 LD>=SL AND>=SL OR>=SL

Section 3-6
Name LOAD LESS THAN OR EQUAL AND LESS THAN OR EQUAL OR LESS THAN OR EQUAL LOAD DOUBLE LESS THAN OR EQUAL AND DOUBLE LESS THAN OR EQUAL OR DOUBLE LESS THAN OR EQUAL LOAD SIGNED LESS THAN OR EQUAL AND SIGNED LESS THAN OR EQUAL OR SIGNED LESS THAN OR EQUAL LOAD DOUBLE SIGNED LESS THAN OR EQUAL AND DOUBLE SIGNED LESS THAN OR EQUAL OR DOUBLE SIGNED LESS THAN OR EQUAL LOAD GREATER THAN AND GREATER THAN OR GREATER THAN LOAD DOUBLE GREATER THAN AND DOUBLE GREATER THAN OR DOUBLE GREATER THAN LOAD SIGNED GREATER THAN AND SIGNED GREATER THAN OR SIGNED GREATER THAN LOAD DOUBLE SIGNED GREATER THAN AND DOUBLE SIGNED GREATER THAN OR DOUBLE SIGNED GREATER THAN LOAD GREATER THAN OR EQUAL AND GREATER THAN OR EQUAL OR GREATER THAN OR EQUAL LOAD DOUBLE GREATER THAN OR EQUAL AND DOUBLE GREATER THAN OR EQUAL OR DOUBLE GREATER THAN OR EQUAL LOAD SIGNED GREATER THAN OR EQUAL AND SIGNED GREATER THAN OR EQUAL OR SIGNED GREATER THAN OR EQUAL LOAD DBL SIGNED GREATER THAN OR EQUAL AND DBL SIGNED GREATER THAN OR EQUAL OR DBL SIGNED GREATER THAN OR EQUAL Function True if C1 C2

True if C1 C2 True if C1 > C2

True if C1 C2

Flags
Name Greater Than Flag Label > Operation ON if S1 > S2 with one-word data. ON if S1+1, S1 > S2+1, S2 with double-length data. OFF in all other cases. ON if S1 S2 with one-word data. ON if S1+1, S1 S2+1, S2 with double-length data. OFF in all other cases. ON if S1 = S2 with one-word data. ON if S1+1, S1 = S2+1, S2 with double-length data. OFF in all other cases.

Greater Than or > = Equal Flag

Equal Flag

213

Comparison Instructions
Name Not Equal Flag Label = Operation ON if S1 S2 with one-word data.

Section 3-6

ON if S1+1, S1 S2+1, S2 with double-length data. Less Than Flag < OFF in all other cases. ON if S1 < S2 with one-word data. ON if S1+1, S1 < S2+1, S2 with double-length data. Less Than or Equal Flag <= OFF in all other cases. ON if S1 S2 with one-word data. ON if S1+1, S1 S2+1, S2 with double-length data. OFF in all other cases.

Precautions Examples

Input comparison instructions cannot be used as right-hand instructions, i.e., another instruction must be used between them and the right bus bar. AND LESS THAN: AND<(310) When CIO 0.00 is ON in the following example, the contents of D100 and D200 are compared in as unsigned binary data. If the content of D100 is less than that of D200, CIO 100.00 is turned ON and execution proceeds to the next line. If the content of D100 is not less than that of D200, the remainder of the instruction line is skipped and execution moves to the next instruction line.

0.00 <
D100 D200

100.00 Unsigned LESS THAN Comparison S1: D100 8714 Decimal: 34,580 S2: D200 3A1C Decimal: 14,876

0.01 <S
D110 D210

100.01

34,580 > 14,876 (Will not proceed to next line.)

AND SIGNED LESS THAN: AND<S(312) When CIO 0.01 is ON in the following example, the contents of D110 and D210 are compared as signed binary data. If the content of D110 is less than that of D210, CIO 100.01 is turned ON and execution proceeds to the next line. If the content of D110 is not less than that of D210, the remainder of the instruction line is skipped and execution moves to the next instruction line.
0.00 D100 D200 0.01 D110 D210 100.01 100.00

Signed LESS THAN Comparison

S1: D110 8714

S2: D210 3A1C Decimal: 14,876

Decimal: 30,956

30,956 < 14,876 (Will proceed to next line.)

214

Comparison Instructions

Section 3-6

3-6-2
Purpose

Time Comparison Instructions (341 to 346)

Time comparison instructions compare two BCD time values and create an ON execution condition when the comparison condition is true. The time comparison instructions are treated just like the LD, AND, and OR instructions to control the execution of subsequent instructions.

Ladder Symbol
LD

Symbol C S1 S2 C: Control word S1: First word of present time S2: First word of comparison time

AND

Symbol C S1 S2
OR

C: Control word S1: First word of present time S2: First word of comparison time

Symbol C S1 S2 C: Control word S1: First word of present time S2: First word of comparison time

Variations
Variations Creates ON Each Cycle Comparison is True Time comparison instruction Not supported

Immediate Refreshing Specification

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

C: Control Word Bits 00 to 05 of C specify whether or not the time data will be masked for the comparison. Bits 00 to 05 mask the seconds, minutes, hours, day, month, and year, respectively. If all 6 values are masked, the instruction will not be executed, the execution condition will be OFF, and the Error Flag will be turned ON.
15 8 7 6 5 4 3 2 1 0

C 0 0 0 0 0 0 0 0 0 0
Masks seconds data when ON. Masks minutes data when ON. Masks hours data when ON. Masks day data when ON. Masks month data when ON. Masks year data when ON.

215

Comparison Instructions

Section 3-6
S1 through S1+2: Present Time Data S1 through S1+2 contain the present time data. S1 through S1+2 must be in the same data area.
15 8 7 0

S1

Seconds: 00 to 59 (BCD) Minutes: 00 to 59 (BCD)

15 8 7 0

S1+1

Hour: 00 to 23 (BCD) Day: 01 to 31 (BCD)

15 8 7 0

S1+2

Month: 01 to 12 (BCD) Year: 00 to 99 (BCD)

Note

When using the CPU Units internal clock data for the comparison, set S1 to A351 to specify the CPU Units internal clock data (A351 to A353). S2 through S2+2: Comparison Time Data S2 through S2+2 contain the comparison time data. S2 through S2+2 must be in the same data area.
15 8 7 0

S2

Seconds: 00 to 59 (BCD) Minutes: 00 to 59 (BCD)

15 8 7 0

S2+1

Hour: 00 to 23 (BCD) Day: 01 to 31 (BCD)

15 8 7 0

S2+2

Month: 01 to 12 (BCD) Year: 00 to 99 (BCD)

216

Comparison Instructions
Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 ----S1 CIO 0 to CIO 6141 W0 to W509 H0 to H509 A0 to A957 T0000 to T4093 C0000 to C4093 D0 to D32765 @ D0 to @ D32767 *D0 to *D32767

Section 3-6

S2 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

See previous page. See previous page. ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The time comparison instruction compares the unmasked values (corresponding bit of C set to 0) of the present time data in S1 to S1+2 with the comparison time data in S2 to S2+2 and creates an ON execution condition when the comparison condition is true. At the same time, the result of a time comparison instruction is reflected in the arithmetic flags (=, <>, <, <=, >, >=). There are 18 possible combinations of time comparison instructions. Any time values that are masked in the control word (C) are not included in the comparison. The following table shows the ON/OFF status of each flag for each comparison result.
Result = S1 = S2 S1 > S2 S1 < S2
S1

ON OFF OFF
Comparison

<> OFF ON ON

Flag status < <= OFF ON OFF ON OFF ON

> OFF ON OFF

>= ON ON OFF

S2
Conditions Flags (=, <>, <, <=, >, >=)

Result

Masking Time Values Time values can be masked individually and excluded from the comparison operation. To mask a time value, set the corresponding bit in the control word (C) to 1. Bits 00 to 05 of C mask the seconds, minutes, hours, day, month, and year, respectively.

217

Comparison Instructions

Section 3-6
Example: When C = 39 hex, the rightmost 6 bits are 111001 (year=1, month=1, day=1, hours=0, minutes=0, and seconds=1) so only the hours and minutes are compared. This mask setting can be used to perform a particular operation at a given time (hour and minute) each day.
Present time data
15 S1 S1+1 S1+2 08 07 00 S2 Minute (00 to Second (00 to 59, BCD) 59, BCD)
Day of month Hour (00 to (01 to 31, BCD) 23, BCD)

Comparison time data

15 08 07 00 Minute (00 to 59, BCD) Second (00 to 59, BCD) Hour (00 to Month (01 to 12, BCD)

S2+1 Day of month Year (00 to S2+2 99, BCD)

(01 to 31, BCD) 23, BCD)

Year (00 to 99, BCD)

Month (01 to 12, BCD)

Compares only hours and minutes data.

Year, month, day, and seconds data is masked.

Previous data comparison instructions compared data in 16-bit units. The time comparison instructions are limited to comparing 8-bit time values. The following table shows the structure of the CPU Units internal Calendar/ Clock Area.
Addresses A351.00 to A351.07 A351.08 to A351.15 A352.00 to A352.07 A352.08 to A352.15 A353.00 to A353.07 A353.08 to A353.15 Contents Second (00 to 59, BCD) Minute (00 to 59, BCD) Hour (00 to 23, BCD) Day of month (01 to 31, BCD) Month (01 to 12, BCD) Year (00 to 99, BCD)

The Calendar/Clock Area can be set with the CX-Programmer, DATE(735) instruction, or CLOCK WRITE FINS command (0702 hex). Summary of Time Comparison Instructions The following table shows the function codes, mnemonics, names, and functions of the 18 time comparison instructions.
Code Mnemonic 341 LD= DT AND=DT OR=DT 342 LD<>DT AND<>DT OR<>DT 343 LD<DT AND<DT 344 OR<DT LD<=DT AND<=DT OR<=DT LD>DT AND>DT OR>DT Name LOAD EQUAL AND EQUAL OR EQUAL LOAD NOT EQUAL AND NOT EQUAL OR NOT EQUAL LOAD LESS THAN AND LESS THAN OR LESS THAN LOAD LESS THAN OR EQUAL AND LESS THAN OR EQUAL OR LESS THAN OR EQUAL LOAD GREATER THAN AND GREATER THAN OR GREATER THAN Function True if S1 = S2 True if S1 S2 True if S1 < S2 True if S1 S2 True if S1 > S2

345

218

Comparison Instructions
Code Mnemonic Name 346 LD>=DT LOAD GREATER THAN OR EQUAL AND>=DT AND GREATER THAN OR EQUAL OR>=DT OR GREATER THAN OR EQUAL

Section 3-6
Function True if S1 S2

Flags
Name Error Flag Greater Than Flag Label ER > Operation ON if all 6 of the mask bits (C bits 00 to 05) are ON. OFF in all other cases. ON if S1 > S2. OFF in all other cases. ON if S1 S2. OFF in all other cases. ON if S1 = S2. OFF in all other cases. ON if S1 S2. OFF in all other cases. ON if S1 < S2. OFF in all other cases. ON if S1 S2. OFF in all other cases.

Greater Than or > = Equal Flag Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag = = < <=

Precautions Example

Time comparison instructions cannot be used as right-hand instructions, i.e., another instruction must be used between them and the right bus bar. When CIO 0.00 is ON and the time is 13:00:00, CIO 100.00 is turned ON. The contents of A351 to A353 (the CPU Units internal calendar/clock data) are used as the present time data and the contents of D100 to D102 are used as the comparison time data. The year, month, and day values are masked, so only the hour, minute, and second data are compared.
0.00 =DT C S1 S2 7 D0 6 5 1 D0 A351 D100 4 1 3 1 2 0 1 0 0 0
Seconds compared. Minutes compared. Hours compared. Day masked. Month masked. Year masked.

100.00

D0 set to 0038 hex

Shaded data is compared.

15 A351 8 7 0 15 S2: D100 00 8 7 00 13 0

Minute Year

Second Hour Month

A352 Day of month A353

S2+1: D101 S2+2: D102

Conditions Flags set as soon as execution condition is turned ON.

219

Comparison Instructions

Section 3-6

3-6-3
Purpose

COMPARE: CMP(020)
Compares two unsigned binary values (constants and/or the contents of specified words) and outputs the result to the Arithmetic Flags in the Auxiliary Area.

Ladder Symbol
CMP(020) S1 S2 S1: Comparison data 1 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification CMP(020) Not supported Not supported !CMP(020)

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 S2

#0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) Data Registers DR0 to DR15 Index Registers --Indirect addressing using ,IR0 to ,IR15 Index Registers 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

CMP(020) compares the unsigned binary data in S1 and S2 and outputs the result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area.
Unsigned binary comparison

Arithmetic Flags (>, >=, =, <=, <, <>)

220

Comparison Instructions
Condition Flag Status

Section 3-6

The following table shows the status of the Arithmetic Flags after execution of CMP(020). (A status of --- indicates that the Flag may be ON or OFF.)
CMP(020) Result S1 > S2 S1 = S2 S1 < S2 ON OFF OFF > ON ON OFF >= Flag status = <= OFF OFF ON OFF ON ON < OFF OFF ON ON OFF ON <>

Using CMP(020) Results in the Program When CMP(020) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls CMP(020), as shown in the following diagram. In this case, the Equals Flag and output A will be turned ON when S1 = S 2.

Correct Use of CMP(020)

CMP S1 S2 Arithmetic Flag (Example: Equal Flag) A

Using CMP(020) Results in the Program Do not program another instruction between CMP(020) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of CMP(020).

Incorrect Use of CMP(020)

CMP S1 S2

Instruction B Arithmetic Flag (Example: Equal Flag)

A

The immediate-refreshing variation (!CMP(020)) can be used with words allocated to external inputs specified in S1 and/or S2. When !CMP(020) is executed, input refreshing will be performed for the external input word specified in S1 and/or S2 and that refreshed value will be compared.

221

Comparison Instructions
Flags
Name Greater Than Flag CX-Programmer label P_GT

Section 3-6

Operation ON if S1 > S2. OFF in all other cases. ON if S1 S2. OFF in all other cases. ON if S1 = S2. OFF in all other cases. ON if S1 S2. OFF in all other cases. ON if S1 < S2. OFF in all other cases. ON if S1 S2. OFF in all other cases.

Greater Than or Equal Flag P_GE Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag P_EQ P_NE P_LT P_LE

Precautions

Do not program another instruction between CMP(020) and an input condition that accesses the result of CMP(020) because the other instruction might change the status of the Arithmetic Flags.

3-6-4
Purpose

DOUBLE COMPARE: CMPL(060)

Compares two double unsigned binary values (constants and/or the contents of specified words) and outputs the result to the Arithmetic Flags in the Auxiliary Area.

Ladder Symbol
CMPL(060) S1 S2 S1: Comparison data 1 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification CMPL(060) Not supported Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area S1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 S2

222

Comparison Instructions
Area S1

Section 3-6
S2

Indirect DM addresses in @ D0 to @ D32767 binary Indirect DM addresses in *D0 to *D32767 BCD Constants #00000000 to #FFFFFFFF (binary) &0 to &4294967295 (unsigned decimal) Data Registers --Index Registers IR0 to IR15 Indirect addressing using ,IR0 to ,IR15 Index Registers 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

CMPL(060) compares the unsigned binary data in S1 +1, S1 and S2+1, S2 and outputs the result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area.
Unsigned binary comparison
S2+1

Arithmetic Flags (>, >=, =, <=, <, <>)

Arithmetic Flag Status The following table shows the status of the Arithmetic Flags after execution of CMPL(060). (A status of --- indicates that the Flag may be ON or OFF.)
CMPL(060)Result > S1 +1, S1 > S2+1, S2 ON S1+1, S1 = S2+1, S2 S1+1, S1 < S2+1, S2 OFF OFF >= ON ON OFF Flag status = <= OFF OFF ON OFF ON ON < OFF OFF ON <> ON OFF ON

Using CMPL(060) Results in the Program When CMPL(060) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls CMPL(060), as shown in the following diagram. Here, the Equals Flag and output A will be turned ON when S1 +1, S1 = S2+1, S2.

Correct Use of CMPL(060)

CMPL S1 S2 Arithmetic Flag (Example: Equal Flag) A

223

Comparison Instructions
Using CMPL(060) Results in the Program

Section 3-6

Do not program another instruction between CMPL(060) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of CMPL(060).

Incorrect Use of CMPL(060)

CMPL S1 S2

Instruction B Arithmetic Flag (Example: Equals Flag)

Flags
Name Greater Than Flag Greater Than or Equal Flag Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag CX-Programmer label P_GT P_GE P_EQ P_NE P_LT P_LE Operation ON if S1 +1, S1 > S2+1, S2. OFF in all other cases. ON if S1 +1, S1 S2+1, S2. OFF in all other cases. ON if S1 +1, S1 = S2+1, S2. OFF in all other cases. ON if S1 +1, S1 S2+1, S2. OFF in all other cases. ON if S1 +1, S1 < S2+1, S2. OFF in all other cases. ON if S1 +1, S1 S2+1, S2. OFF in all other cases.

Precautions

Do not program another instruction between CMPL(060) and an input condition that accesses the result of CMPL(060) because the other instruction might change the status of the Arithmetic Flags.

224

Comparison Instructions
Example

Section 3-6
When CIO 0.00 is ON in the following example, the eight-digit unsigned binary data in CIO 1001 and CIO 1000 is compared to the eight-digit unsigned binary data in CIO 1501 and CIO 1500 and the result is output to the Arithmetic Flags. The results recorded in the Greater Than, Equals, and Less Than Flags are immediately saved to CIO 100.00 (Greater Than), CIO 100.01 (Equals), and CIO 100.02 (Less Than).

0.00 1000 1500 100.00

S1+1 = CIO 1001

S1 = CIO 1000

Flag status Result > = < (0) (0) (1)

Comparison
S2+1 = CIO 1501 S2 = CIO 1500

100.01

100.02

3-6-5
Purpose

SIGNED BINARY COMPARE: CPS(114)

Compares two signed binary values (constants and/or the contents of specified words) and outputs the result to the Arithmetic Flags in the Auxiliary Area.

Ladder Symbol
CPS(114) S1 S2 S1: Comparison data 1 S2: Comparison data 2

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification CPS(114) Not supported Not supported !CPS(114)

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD S1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 S2

225

Comparison Instructions
Area Constants S1

Section 3-6
S2

#0000 to #FFFF (binary) 32768 to 0 to 32767 (signed decimal) Data Registers DR0 to DR15 Index Registers --Indirect addressing using ,IR0 to ,IR15 Index Registers 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

CPS(114) compares the signed binary data in S1 and S2 and outputs the result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area.
Signed binary comparison

Arithmetic Flags (>, >=, =, <=, <, <>)

Note

CPS(114) treats the data in S1 and S2 as signed binary data which ranges from 8000 to 7FFF (32,768 to 32,767 decimal). Arithmetic Flag Status The following table shows the status of the Arithmetic Flags after execution of CPS(114). (A status of --- indicates that the Flag may be ON or OFF.)
CPS(114) Result S1 > S2 S1 = S2 S1 < S2 ON OFF OFF > ON ON OFF >= Flag status = <= OFF OFF ON OFF ON ON < OFF OFF ON ON OFF ON <>

Using CPS(114) Results in the Program When CPS(114) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls CPS(114), as shown in the following diagram. In this case, the Equals Flag and output A will be turned ON when S1 = S 2.

Correct Use of CPS(114)

CPS S1 S2 Arithmetic Flag (Example: Equal Flag) A

226

Comparison Instructions
Using CPS(114) Results in the Program

Section 3-6

Do not program another instruction between CPS(114) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of CPS(114).

Incorrect Use of CPS(114)

CPS S1 S2

Instruction B Arithmetic Flag (Example: Equal Flag)

A

The immediate-refreshing variation (!CPS(114)) can be used with words allocated to external inputs specified in S1 and/or S2. When !CPS(114) is executed, input refreshing will be performed for the external input word specified in S1 and/or S2 and that refreshed value will be compared. Flags
Name Greater Than Flag Greater Than or Equal Flag Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag Label > >= = <> < <= Operation ON if S1 > S2. OFF in all other cases. ON if S1 S2. OFF in all other cases. ON if S1 = S2. OFF in all other cases. ON if S1 S2. OFF in all other cases. ON if S1 < S2. OFF in all other cases. ON if S1 S2. OFF in all other cases.

Precautions

Do not program another instruction between CPS(114) and an input condition that accesses the result of CPS(114) because the other instruction might change the status of the Arithmetic Flags.

3-6-6
Purpose

DOUBLE SIGNED BINARY COMPARE: CPSL(115)

Compares two double signed binary values (constants and/or the contents of specified words) and outputs the result to the Arithmetic Flags in the Auxiliary Area.

Ladder Symbol
CPSL(115) S1 S2 S1: Comparison data 1 S2: Comparison data 2

227

Comparison Instructions
Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-6

CPSL(115) Not supported Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 S2

#00000000 to #FFFFFFFF (binary) 2147483648 to 0 to 2147483647 (signed decimal) Data Registers --Index Registers --Indirect addressing using ,IR0 to ,IR15 Index Registers 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

CPSL(115) compares the double signed binary data in S1 +1, S1 and S2+1, S2 and outputs the result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area.
Signed binary comparison S2+1 Arithmetic Flags (>, >=, =, <=, <, <>)

Note

CPSL(115) treats the data in S1 and S2 as double signed binary data which ranges from 8000 0000 to 7FFF FFFF (2,147,483,648 to 2,147,483,647 decimal).

228

Comparison Instructions
Arithmetic Flag Status

Section 3-6

The following table shows the status of the Arithmetic Flags after execution of CPSL(115). (A status of --- indicates that the Flag may be ON or OFF.)
CPSL(115)Result > S1 +1, S1 > S2+1, S2 S1+1, S1 = S2+1, S2 S1+1, S1 < S2+1, S2 ON OFF OFF >= ON ON OFF Flag status = <= OFF OFF ON OFF ON ON < OFF OFF ON <> ON OFF ON

Using CPSL(115) Results in the Program When CPSL(115) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls CPSL(115), as shown in the following diagram. Here, the Equals Flag and output A will be turned ON when S1 +1, S1 = S2+1, S2.

Correct Use of CPSL(115)

CPSL S1 S2 Arithmetic Flag (Example: Equal Flag) A

Using CPSL(115) Results in the Program Do not program another instruction between CPSL(115) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of CPSL(115).

Incorrect Use of CPSL(115)

CPSL S1 S2

Instruction B Arithmetic Flag (Example: Equal Flag)

A

Flags
Name Greater Than Flag Greater Than or Equal Flag Label > >= Operation ON if S1 +1, S1 > S2+1, S2. OFF in all other cases. ON if S1 +1, S1 S2+1, S2. OFF in all other cases.

229

Comparison Instructions
Name Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag Label = = < <= Operation ON if S1 +1, S1 = S2+1, S2. OFF in all other cases. ON if S1 +1, S1 S2+1, S2. OFF in all other cases. ON if S1 +1, S1 < S2+1, S2. OFF in all other cases. ON if S1 +1, S1 S2+1, S2. OFF in all other cases.

Section 3-6

Precautions

Do not program another instruction between CPSL(115) and an input condition that accesses the result of CPSL(115) because the other instruction might change the status of the Arithmetic Flags. When CIO 0.00 is ON in the following example, the eight-digit signed binary data in D2 and D1 is compared to the eight-digit signed binary data in D6 and D5 and the result is output to the Arithmetic Flags. If the content of D2 and D1 is greater than that of D6 and D5, the Greater Than Flag will be turned ON, causing CIO 100.00 to be turned ON. If the content of D2 and D1 is equal to that of D6 and D5, the Equals Flag will be turned ON, causing CIO 100.01 to be turned ON. If the content of D2 and D1 is less than that of D6 and D5, the Less Than Flag will be turned ON, causing CIO 100.02 to be turned ON.

Example

0.00
D1 D5

D2
1234

D1
5678

D6
ABCD

Comparison D5
EF12

Flag status > (1) (0) = <

(0)

100.00

100.01

100.02

3-6-7
Purpose

MULTIPLE COMPARE: MCMP(019)

Compares 16 consecutive words with another 16 consecutive words and turns ON the corresponding bit in the result word where the contents of the words are not equal.

Ladder Symbol
MCMP(019) S1 S2 R S1: First word of set 1 S2: First word of set 2 R: Result word

230

Comparison Instructions
Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-6

MCMP(019) @MCMP(019) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S1: First word of set 1 Specifies the beginning of the first 16-word range. S1 and S1+15 must be in the same data area. S2: First word of set 2 Specifies the beginning of the second 16-word range. S2 and S2+15 must be in the same data area. R: Result word Each bit of R contains the result of a comparison between two words in the 16-word sets. Bit n of R (n = 00 to 15) contains the result of the comparison between words S1+n and S2+n.
15 14 1 0

R
Comparison result for S1 and S2 Comparison result for S1+1 and S2+1 Comparison result for S1+14 and S2+14 Comparison result for S1+15 and S2+15

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S1 CIO 0 to CIO 6128 W0 to W496 H0 to H496 A0 to A944 T0000 to T4080 C0000 to C4080 D0 to D32752 @ D0 to @ D32767 *D0 to *D32767 ----DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 S2 R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

231

Comparison Instructions
Description

Section 3-6
MCMP(019) compares the contents of the 16 words S1 through S1+15 to the contents of the 16 words S2 through S2+15, and turns ON the corresponding bit in word R when the contents are not equal. The content of S1 is compared to the content of S2, the content of S1+1 to the content of S2+1, ..., and the content of S1+15 to the content of S2+15. Bit n of R is turned OFF if the content of S1+n is equal to the content of S2+n; bit n of R is turned ON if the contents are not equal. If the contents of all 16 pairs of words are the same, the Equals Flag will turn ON after the instruction has been executed.
Comparison

R
0: Words are equal. 1: Words aren't equal.

Flags
Name Error Flag Equals Flag Label ER = Operation OFF ON if the result word is 0000. (The two 16-word sets contain the same data.) OFF in all other cases.

Example

When CIO 0.00 is ON in the following example, MCMP(019) compares words D100 through D115 in order to words D200 through D215 and turns ON the corresponding bits in D300 when the words are not equal.
0.00 D100 D200 D300

R: D300
S1: D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 S2: D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215

232

Comparison Instructions

Section 3-6

3-6-8
Purpose

TABLE COMPARE: TCMP(085)

Compares the source data to the contents of 16 consecutive words and turns ON the corresponding bit in the result word when the contents of the words are equal.

Ladder Symbol
TCMP(085) S T R S: Source data T: First word of table R: Result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification TCMP(085) @TCMP(085) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

T: First word of table Specifies the beginning of the 16-word table. T and T+15 must be in the same data area. R: Result word Each bit of R contains the result of a comparison between S and a word in the 16-word table. Bit n of R (n = 00 to 15) contains the result of the comparison between S and T+n.
Comparison data 0 Comparison data 1

to

to Comparison data 15
15 14 1 0

R
Comparison result for S and T Comparison result for S and T+1 Comparison result for S and T+14 Comparison result for S and T+15

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 T CIO 0 to CIO 6128 W0 to W496 H0 to H496 A0 to A944 T0000 to T4080 C0000 to C4080 D0 to D32752 R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

233

Comparison Instructions
Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S @ D0 to @ D32767 *D0 to *D32767 T

Section 3-6
R

Data Registers Index Registers Indirect addressing using Index Registers

--#0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) 32768 to 0 to 32767 (signed decimal) DR0 to DR15 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

TCMP(085) compares the source data (S) to each of the 16 words T through T+15 and turns ON the corresponding bit in word R when the data are equal. Bit n of R is turned ON if the content of T+n is equal to S and it is turned OFF if they are not equal. S is compared to the content of T and bit 00 of R is turned ON if they are equal or OFF if they are not equal, S is compared to the content of T+1 and bit 01 of R is turned ON if they are equal or OFF if they are not equal, ..., and S is compared to the content of T+15 and bit 15 of R is turned ON if they are equal or OFF if they are not equal.
Comparison R 1: Data are equal. 0: Data aren't equal.

Flags
Name Error Flag Equals Flag Label ER = Operation OFF ON if the result word is 0000. (None of the 16 words in the table equals S.) OFF in all other cases.

Example

When CIO 0.00 is ON in the following example, TCMP(085) compares the content of D100 with the contents of words D200 through D215 and turns ON the corresponding bits in D300 when the contents are equal or OFF when the contents are not equal.

234

Comparison Instructions
0.00 S: D100 D100 D200 D300 T: D200 D201 D202 D203 D204 D205 D206 D207 D208 D209 D210 D211 D212 D213 D214 D215

Section 3-6
R: D300

3-6-9
Purpose

BLOCK COMPARE: BCMP(068)

Compares the source data to 16 ranges (defined by 16 lower limits and 16 upper limits) and turns ON the corresponding bit in the result word when the source data is within a range.

Ladder Symbol
BCMP(068) S B R S: Source data B: First word of block R: Result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BCMP(068) @BCMP(068) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

B: First word of block Specifies the beginning of a 32-word block (16 lower/upper limit pairs). B and B+31 must be in the same data area.

235

Comparison Instructions
R: Result word

Section 3-6

Each bit of R contains the result of a comparison between S and one of the 16 ranges defined the 32-word block. Bit n of R (n = 00 to 15) contains the result of the comparison between S and the nth pair of words.
15 14 R Comparison result for S and range B B+1 Comparison result for S and range B+2 B+3 1 0

Comparison result for S and range B+28 B+29 Comparison result for S and range B+30 B+31

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S CIO 0 to CIO 6143 W0 to W511 H0 to H511 B CIO 0 to CIO 6112 W0 to W480 H0 to H480 R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

A0 to A959 A0 to A928 T0000 to T4095 T0000 to T4064 C0000 to C4095 C0000 to C4064 D0 to D32767 D0 to D32736 @ D0 to @ D32767 *D0 to *D32767

Data Registers Index Registers Indirect addressing using Index Registers

#0000 to #FFFF --(binary) &0 to &65535 (unsigned decimal) 32768 to 0 to 32767 (signed decimal) DR0 to DR15 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

BCMP(068) compares the source data (S) to the 16 ranges defined by pairs of lower and upper limit values in B through B+31. The first word in each pair (B+2n) provides the lower limit and the second word (B+2n+1) provides the upper limit of range n (n = 0 to 15). If S is within any of these ranges (inclusive of the upper and lower limits), the corresponding bit in R is turned ON. The rest of the bits in R will be turned OFF. B B+2 B+4 B+6 B+8 B+10 S S S S S S B+1 B+3 B+5 B+7 B+9 B+11 Bit 00 of R Bit 01 of R Bit 02 of R Bit 03 of R Bit 04 of R Bit 05 of R

236

Comparison Instructions
B+12 B+14 B+16 B+18 B+20 B+22 B+24 B+26 B+28 B+30 S S S S S S S S S S B+13 B+15 B+17 B+19 B+21 B+23 B+25 B+27 B+29 B+31 Bit 06 of R Bit 07 of R Bit 08 of R Bit 09 of R Bit 10 of R Bit 11 of R Bit 12 of R Bit 13 of R Bit 14 of R Bit 15 of R

Section 3-6

For example, bit 00 of R is turned ON if S is within the first range (B S B+1), bit 01 of R is turned ON if S is within the second range (B+2 S B+3), ..., and bit 15 of R is turned ON if S is within the fifteenth range (B+30 S B+31). All other bits in R are turned OFF. Flags
Name Error Flag Equals Flag Label ER = Operation OFF ON if the result word is 0000. (S is not within any of the 16 ranges.) OFF in all other cases.

Precautions Example

An error will not occur if the lower limit is greater than the upper limit, but 0 (not within the range) will be output to the corresponding bit of R. When CIO 0.00 is ON in the following example, BCMP(068) compares the content of D100 with the 16 ranges defined in D200 to D231 (i.e., D200 and D201, D202 and D203, etc.) and turns ON the corresponding bits in D300 when S is within the range or OFF when S is not within the range.

0.00 D100 D200 D300

R: D300
D200 D202 D204 D206 D208 D210 D212 D214 D216 D218 D220 D222 D224 D226 D228 D230

S: D100

to D201 to D203 to D205 to D207 to D209 to D211 to D213 to D215 to D217 to D219 to D221 to D223 to D225 to D227 to D229 to D231

237

Comparison Instructions

Section 3-6

3-6-10 EXPANDED BLOCK COMPARE: BCMP2(502)

Purpose Compares the source data to up to 256 ranges (defined by 256 lower limits and 256 upper limits) and turns ON the corresponding bit in the result word when the source data is within a range.

Ladder Symbol
BCMP2(502) S B R S: Source data B: First word of block R: First result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BCMP2(502) @BCMP2(502) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

B: First word of block Specifies the beginning of a comparison block containing up to 513 words including up to 256 lower/upper limit pairs). All words must be in the same data area.
Word 15 B Range 0 B+1 B+2 Range 1 B+3 B+4 Range 2 B+5 B+6 Comparison block 8 7 00 hex
Last range "N"

0
N: 00 to FF hex (0 to 255)

Range 0 value A Range 0 value B Range 1 value A Range 1 value B Range 2 value A Range 2 value B

Range data

Range 15

B+31 B+32

Range 15 value A Range 15 value B Range 16 value A Range 16 value B Range 17 value A Range 17 value B Range 18 value A Range 18 value B

Range 16

B+33 B+34

Range 17

B+35 B+36

Range 18

B+37 B+38

Range N B+2N+1 B+2(N+1)

Range N value A Range N value B

238

Comparison Instructions
R: First result word

Section 3-6

Each bit of each R word contains the result of a comparison between S and one of the ranges defined the comparison block. The maximum number of result words is 16, i.e., m equals 0 to 15.
15 14 R+m
Comparison result for S and range 16m Comparison result for S and range 16m + n

Comparison result for S and range 16m + 14 Comparison result for S and range 16m + 15

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) 32768 to 0 32767 (signed decimal) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 B R

A448 to A959

Data Registers Index Registers Indirect addressing using Index Registers

239

Comparison Instructions
Description

Section 3-6
BCMP2(502) compares the source data (S) to the ranges defined by pairs of lower and upper limit values in the comparison block. If S is within any of these ranges (inclusive of the upper and lower limits), the corresponding bits in the result words (R to R+15 max.) are turned ON. The rest of the bits in R will be turned OFF. The number of ranges is determined by the value N set in the lower byte of B. N can be between 0 and 255. The upper byte of B must be 00 hex.
Comparison block
15 87 0 Last range N: 00 to FF hex (0 to 255) "N"

B 00 hex

Comparison ranges B+1 B+3 Source data S B+5

Range 0 value A Range 0 value B Range 1 value A Range 1 value B Range 2 value A Range 2 value B

Result words R Bit B+2 0 B+4 B+6 : 15 R+1 Bit 0 1 2 : B+2N+2 In range: ON Not in range: OFF 1 2

: B+31 Range 15 value A Range 15 value B B+32

B+33 Range 16 value A Range 16 value B B+34 B+35 Range 17 value A Range 17 value B B+36 B+37 Range 18 value A Range 18 value B B+38 : B+2N+1
Range N value A Range N value B

Ranges

Number of Ranges The number of ranges in the comparison block is set in the first word of the block. Up to 256 ranges can be set. Setting Ranges The values A and B for each range will determine how the comparison operates depending on which value is larger, as shown below.
If Value A Value B Then, Value A Comparison range Value B

Comparison range

Value A

Value B

If Value A > Value B Then, Comparison range Value B and Value A Comparison range Comparison range Comparison range

Value B

Value A

Example When B+1 B+2 If B+1 S B+2, then bit 0 of R will turn ON, If B+3 S B+4, then bit 1 of R will turn ON, If S < B+5 and B+6 < S, then bit 2 of R will turn OFF, and If S < B+7 and B+8 < S, then bit 3 of R will turn OFF.

240

Comparison Instructions
When B+1 > B+2 If S B+2 and B+1 S, then bit 0 of R will turn ON, If S B+4 and B+3 S, then bit 1 of R will turn ON, If B+6 < S < B+5, then bit 2 of R will turn OFF, and If B+8 < S < B+7, then bit 3 of R will turn OFF. Results Storage Location

Section 3-6

The results are output to corresponding bits in word R. If there are more than 16 comparison ranges, consecutive words following R will be used.The maximum number of result words is 16, i.e., m equals 0 to 15.
15 14 R+m
Comparison result for S and range 16m Comparison result for S and range 16m + n

Comparison result for S and range 16m + 14 Comparison result for S and range 16m + 15

Flags
Name Error Flag Label ER Operation OFF

Example

When CIO 0.00 is ON in the following example, BCMP2(502) compares the content of CIO 1000 with the 24 ranges defined in D200 through D247 (N = 17 hex = 23 decimal, i.e., 24 ranges) and turns ON the corresponding bits in CIO 2000 and CIO 2001 when S is within the range and OFF when S is not within the range. For example, if the source data in CIO 1000 is in the range defined by D201 and D202, then bit 00 of CIO 2000 is turned ON and if it in not in the range, then bit 00 of CIO 2000 is turned OFF. Likewise, the source data in CIO 1000 is compared to the ranges defined by D203 and D204, D247 and D248, and the other words in the comparison block, and bit 1 in CIO 2000, bit 7 in CIO 2001, and the other bits in the result words are manipulated according to the results of comparison.
T: D200 BCMP2 1000 D200 2000 S: CIO 1000 0 1 7 5 D201 D203 D205 0 0 0 0 0 1 0 8 6 0 0 0 0 0 0 1 1 2 0 8 6 0 0 0 D202 D204 D206 0 0 1 7 R: CIO 2000 Bit

0.00

D231

D232 R: CIO 2001

D233 D235 D237

1 1 1

5 9 8

0 0 0

0 0 0

0 0 0

5 1 2

0 0 0

0 0 0

D234 D236 D238

D247

D248

241

Comparison Instructions

Section 3-6

3-6-11 AREA RANGE COMPARE: ZCP(088)

Purpose Compares a 16-bit unsigned binary value (CD) with the range defined by lower limit LL and upper limit UL. The results are output to the Arithmetic Flags.

Ladder Symbol
ZCP(088)

CD LL UL

CD: Comparison Data LL: Lower limit of range UL: Upper limit of range

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ZCP(088) Not supported Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants CD CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 LL UL

#0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) Data Registers DR0 to DR15 Index Registers --Indirect addressing using ,IR0 to ,IR15 Index Registers 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ZCP(088) compares the 16-bit signed binary data in CD with the range defined by LL and UL and outputs the result to the Greater Than, Equals, and Less Than Flags in the Auxiliary Area. (The Less Than or Equal, Greater Than or Equal, and Not Equal Flags are left unchanged.)

242

Comparison Instructions
Arithmetic Flag Status

Section 3-6

The following table shows the status of the Arithmetic Flags after execution of ZCP(088).
ZCP(088)Result > CD > UL CD = UL LL < CD < UL CD = LL CD < LL ON OFF Flag status = < OFF OFF ON

OFF

ON

Using ZCP(088) Results in the Program When ZCP(088) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls ZCP(088), as shown in the following diagram. In this case, the Equals Flag and output A will be turned ON when LL CD UL.

Correct Use of ZCP(088)

ZCP CD LL UL

Arithmetic Flag (Example: Equal Flag)

Do not program another instruction between ZCP(088) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of ZCP(088).

Incorrect Use of ZCP(088)

ZCPL CD LL UL

Instruction B
A

Arithmetic Flag (Example: Equal Flag)

Flags
Name Error Flag Greater Than Flag Greater Than or Equal Flag Label ER > >= Operation ON if LL > UL. ON if CD > UL. OFF in all other cases. Left unchanged.

243

Comparison Instructions
Name Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag Negative Flag Label = <> < <= N Operation ON if LL CD UL. OFF in all other cases. Left unchanged. ON if CD < LL. OFF in all other cases. Left unchanged. Left unchanged.

Section 3-6

Precautions

Do not program another instruction between ZCP(088) and an input condition that accesses the result of ZCP(088) because the other instruction might change the status of the Arithmetic Flags. When CIO 0.00 is ON in the following example, the 16-bit unsigned binary data in D0 is compared to the range 0005 to 001F hex (5 to 31 decimal) and the result is output to the Arithmetic Flags. CIO 100.00 is turned ON if 0005 hex content of D0 001F hex. CIO 100.01 is turned ON if the content of D0 > 001F hex. CIO 100.02 is turned ON if the content of D0 < 0005 hex.
LL ZCP CD LL UL D0 #5 #1F D0 > 001F hex 100.00 = 100.01 > 100.02 < D0 0005 hex > < ON > ON 0005 hex CD D0 001F hex UL

Example

0.00

Arithmetic Flags
= ON

3-6-12 DOUBLE AREA RANGE COMPARE: ZCPL(116)

Purpose Compares a 32-bit unsigned binary value (CD+1, CD) with the range defined by lower limit (LL+1, LL) and upper limit (UL+1, UL). The results are output to the Arithmetic Flags.

Ladder Symbol
ZCPL(116)

CD LL UL

CD: First word of Comparison Data LL: First word of Lower Limit UL: First word of Upper Limit

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ZCPL(116) Not supported Not supported Not supported

244

Comparison Instructions
Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-6

Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants CD CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 LL UL

#0000 0000 to #FFFF FFFF (binary) &0 to &4294967295 (unsigned decimal) Data Registers --Index Registers IR0 to IR15 Indirect addressing using ,IR0 to ,IR15 Index Registers 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ZCPL(116) compares the 32-bit signed binary data in CD+1, CD with the range defined by LL+1, LL and UL+1, UL and outputs the result to the Greater Than, Equals, and Less Than Flags in the Auxiliary Area. (The Less Than or Equal, Greater Than or Equal, and Not Equal Flags are left unchanged.) Arithmetic Flag Status The following table shows the status of the Arithmetic Flags after execution of ZCPL(116).
ZCPL(116)Result > CD+1, CD > UL+1, UL ON CD+1, CD = UL+1, UL OFF LL+1, LL < CD+1, CD < UL+1, UL CD+1, CD = LL+1, LL CD+1, CD < LL+1, LL Flag status = < OFF OFF ON

OFF

ON

Using ZCPL(116) Results in the Program When ZCPL(116) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls ZCPL(116). Do not program another instruction between ZCPL(116) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag.

245

Comparison Instructions

Section 3-6
The operation of ZCPL(116) is almost identical to that of ZCP(088) except that ZCPL(116) compares 32-bit values instead of 16-bit values. Refer to 3-6-11 AREA RANGE COMPARE: ZCP(088) for diagrams showing how to use results in the program and an example program section.

Flags
Name Error Flag Greater Than Flag Greater Than or Equal Flag Equal Flag Not Equal Flag Less Than Flag Less Than or Equal Flag Negative Flag Label ER > >= = <> < <= N Operation ON if LL+1, LL > UL+1, UL. ON if CD > UL+1, UL. OFF in all other cases. Left unchanged. ON if LL+1, LL CD+1, CD UL+1, UL. OFF in all other cases. Left unchanged. ON if CD+1, CD < LL+1, LL. OFF in all other cases. Left unchanged. Left unchanged.

Precautions

Do not program another instruction between ZCPL(116) and an input condition that accesses the result of ZCPL(116) because the other instruction might change the status of the Arithmetic Flags.

246

Data Movement Instructions

Section 3-7

3-7

Data Movement Instructions

This section describes instructions used to move data in various ways.
Instruction MOVE MOVE NOT DOUBLE MOVE DOUBLE MOVE NOT MOVE BIT MOVE DIGIT MULTIPLE BIT TRANSFER BLOCK TRANSFER BLOCK SET DATA EXCHANGE DOUBLE DATA EXCHANGE SINGLE WORD DISTRIBUTE DATA COLLECT MOVE TO REGISTER MOVE TIMER/COUNTER PV TO REGISTER MOV MVN MOVL MVNL MOVB MOVD XFRB XFER BSET XCHG XCGL DIST COLL MOVR MOVRW Mnemonic Function code 021 022 498 499 082 083 062 070 071 073 562 080 081 560 561 Page 247 248 250 251 253 255 257 260 262 264 265 267 269 270 272

3-7-1
Purpose

MOVE: MOV(021)
Transfers a word of data to the specified word.

Ladder Symbol
MOV(021) S D S: Source D: Destination

Variations
Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification Combined Executed Once and Destination Refreshed Variations Immediately for Upward Differentiation Variations MOV(021) @MOV(021) Not supported !MOV(021) !@MOV(021)

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 D

A448 to A959

247

Data Movement Instructions

Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S @ D0 to @ D32767 *D0 to *D32767

Section 3-7
D

#0000 to #FFFF (binary) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

Transfers S to D. If S is a constant, the value can be used for a data setting.

Source word Bit status not changed. Destination word

MOV(021) has an immediate refreshing variation (!MOV(021)). External input bits can be specified for S and external output bits can be specified for D. Input bits used for S will refreshed just before, and output bits used for D will be refreshed just after execution. Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if the data being transferred is 0000. OFF in all other cases. ON if the leftmost bit of the data being transferred is 1. OFF in all other cases.

Example

When CIO 0.00 is ON in the following example, the content of CIO 1000 is copied to D100.
0.00 1000 D100

CIO 1000

D100

3-7-2
Purpose

MOVE NOT: MVN(022)

Transfers the complement of a word of data to the specified word.

Ladder Symbol
MVN(022) S D S: Source D: Destination

248

Data Movement Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-7

MVN(022) @MVN(022) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) DR0 to DR15 ----D

A448 to A959

,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

MVN(022) inverts the bits in S and transfers the result to D. The content of S is left unchanged.
Source word Bit status inverted. Destination word

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if the content of D is 0000 after execution. OFF in all other cases. ON if the leftmost bit of D is 1 after execution. OFF in all other cases.

249

Data Movement Instructions

Example

Section 3-7
When CIO 0.00 is ON in the following example, the status of the bits in CIO 200 is inverted and the result is copied to D100.
0.00 200 D100

CIO 200

D100

3-7-3
Purpose

DOUBLE MOVE: MOVL(498)

Transfers two words of data to the specified words.

Ladder Symbol
MOVL(498) S D S: First source word D: First destination word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification MOVL(498) @MOVL(498) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ----D

A448 to A958

250

Data Movement Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-7
S D IR0 to IR15 ,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, 1( ) IR5

Description
S

MOVL(498) transfers S+1 and S to D+1 and D. If S+1 and S are constants, the value can be used for a data setting.
S+1 D D+1

Bit status not changed.

Flags
Name Error Flag Equals Flag Label ER = Operation OFF ON if the contents of D+1 and D are 0000 0000 after execution. OFF in all other cases. ON if the leftmost bit of D+1 is 1 after execution. OFF in all other cases.

Negative Flag

Example

When CIO 0.01 is ON in the following example, the content of D1001 and D1000 are copied to D2001 and D2000.
0.01 D1000 D2000

D1001 D1000

D2001 D2000

3-7-4
Purpose

DOUBLE MOVE NOT: MVNL(499)

Transfers the complement of two words of data to the specified words.

Ladder Symbol
MVNL(499) S D S: First source word D: First destination word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification MVNL(499) @MVNL(499) Not supported Not supported

251

Data Movement Instructions

Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-7

Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15 D

A448 to A958

Description
S

MVNL(499) inverts the bits in S+1 and S and transfers the result to D+1 and D. The contents of S+1 and S are left unchanged.
S+1 D D+1

Bit status inverted.

Flags
Name Error Flag Equals Flag Label ER = Operation OFF ON if the contents of D+1 and D are 0000 0000 after execution. OFF in all other cases. ON if the leftmost bit of D+1 is 1 after execution. OFF in all other cases.

Negative Flag

252

Data Movement Instructions

Examples

Section 3-7
When CIO 0.01 is ON in the following example, the status of the bits in D1001 and D1000 are inverted and the result is copied to D2001 and D2000. (The original contents of D1001 and D1000 are left unchanged.)
0.01 D1000 D2000

D1001 D1000

D2001 D2000

3-7-5
Purpose

MOVE BIT: MOVB(082)

Transfers the specified bit.

Ladder Symbol
MOVB(082) S C D S: Source word or data C: Control word D: Destination word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification MOVB(082) @MOVB(082) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

C: Control Word The rightmost two digits of C indicate which bit of S is the source bit and the leftmost two digits of C indicate which bit of D is the destination bit.
15 8 7 0

n Source bit: 00 to 0F (0 to 15 decimal) Destination bit: 00 to 0F (0 to 15 decimal)

Operand Specifications
Area CIO Area Work Area Holding Bit Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 C D

253

Data Movement Instructions

Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 C

Section 3-7
D A448 to A959

#0000 to #FFFF Specified values --(binary) only DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

MOVB(082) copies the specified bit (n) from S to the specified bit (m) in D. The other bits in the destination word are left unchanged.

Note Flags

The same word can be specified for both S and D to copy a bit within a word.

Name Error Flag

Label ER

Operation ON if the rightmost and leftmost two digits of C are not within the specified range of 00 to 0F. OFF in all other cases.

Examples

When CIO 0.00 is ON in the following example, the 5th bit of the source word (D0) is copied to the 12th bit of the destination word (D1000) in accordance with the control words value of 0C05.
0.00 D0 D200 D1000 C: D200 0C 0 5

S: D0

D: D1000

254

Data Movement Instructions

Section 3-7

3-7-6
Purpose

MOVE DIGIT: MOVD(083)

Transfers the specified digit or digits. (Each digit is made up of 4 bits.)

Ladder Symbol
MOVD(083) S C D S: Source word or data C: Control word D: Destination word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification MOVD(083) @MOVD(083) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: Source Word The source digits are read from right to left, wrapping back to the rightmost digit (digit 0) if necessary.
15 12 11 8 7 4 3 0

Digit 3

Digit 2

Digit 1

Digit 0

C: Control Word The first three digits of C indicate the first source digit (m), the number of digits to transfer (n), and the first destination digit (l), as shown in the following diagram.
15 12 11 8 7 4 3 0

First digit in S (m): 0 to 3 Number of digits (n): 0 to 3 0: 1 digit First digit in D (l): 0 to 3 1: 2 digits 2: 3 digits 3: 4 digits Always 0.

D: Destination Word The destination digits are written from right to left, wrapping back to the rightmost digit (digit 0) if necessary.
15 12 11 8 7 4 3 0

Digit 3

Digit 2

Digit 1

Digit 0

Operand Specifications
Area CIO Area Work Area Holding Bit Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 C D

255

Data Movement Instructions

Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 C

Section 3-7
D A448 to A959

#0000 to #FFFF Specified values --(binary) only DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

MOVD(083) copies the content of n digits from S (beginning at digit m) to D (beginning at digit l). Only the specified digits are changed; the rest are left unchanged. If the number of digits being read or written exceeds the leftmost digit of S or D, MOVD(083) will wrap to the rightmost digit of the same word.

Note Flags

The same word can be specified for both S and D to copy a bit within a word.

Name Error Flag

Label ER

Operation ON if one of the first three digits of C is not within the specified range of 0 to 3. OFF in all other cases.

256

Data Movement Instructions

Examples Four-digit Transfer

Section 3-7

When CIO 0.00 is ON in the following example, four digits of data are copied from CIO 200 to CIO 300. The transfer begins with the digit 1 of CIO 200 and digit 0 or CIO 300, in accordance with the control words value of 0031.
0.00

D300

C: D300 First digit in S: Digit 1

Digit no. S: 200

Number of digits: 3 (4 digits) Digit no. D: 300 First digit in D: Digit 0

Note

After reading the leftmost digit of S (digit 3), MOVD(083) wraps to the rightmost digit (digit 0). Examples of C The following diagram shows examples of data transfers for various values of C.

Digit 0 Digit 1 Digit 2 Digit 3

Digit 0 Digit 1 Digit 2 Digit 3

Digit 0 Digit 1 Digit 2 Digit 3

Digit 0

Digit 0 Digit 1 Digit 2 Digit 3

Digit 0 Digit 1 Digit 2 Digit 3

Digit 0 Digit 1 Digit 2 Digit 3

Digit 0 Digit 1 Digit 2 Digit 3

Digit 1
Digit 2 Digit 3

3-7-7
Purpose

MULTIPLE BIT TRANSFER: XFRB(062)

Transfers the specified number of consecutive bits.

Ladder Symbol
XFRB(062) C S D C: Control word S: First source word D: First destination word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification XFRB(062) @XFRB(062) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

257

Data Movement Instructions

Operands C: Control Word

Section 3-7

The first three digits of C indicate the first source digit (m), the number of digits to transfer (n), and the first destination digit (l), as shown in the following diagram.
15 8 7 4 3 0

First bit in S (l): 0 to F First bit in D (m): 0 to 3 Number of digits (n): 00 to FF (0 to 255)

S: First Source Word Specifies the first source word. Bits are read from right to left, continuing with consecutive words (up to S+16) when necessary.
15 0

to S+15 max.

to

D: First Destination Word Specifies the first destination word. Bits are written from right to left, continuing with consecutive words (up to D+16) when necessary.
15 0

to D+15 max.

to

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 Specified values ----only DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to 5+(++) ,( ) IR0 to, ( ) IR15 S D

A448 to A959

258

Data Movement Instructions

Description

Section 3-7
XFRB(062) transfers up to 255 consecutive bits from the source words (beginning with bit l of S) to the destination words (beginning with bit m of D). Bits in the destination words that are not overwritten by the source bits are left unchanged. The beginning bits and number of bits are specified in C, as shown in the following diagram.

It is possible for the source words and destination words to overlap. By transferring data overlapping several words, the data can be packed more efficiently in the data area. (This is particularly useful when handling position data for position control.) Since the source words and destination words can overlap, XFRB(062) can be combined with ANDW(034) to shift m bits by n spaces. Flags
Name Error Flag Label ER Operation OFF

Precautions

Up to 255 bits of data can be transferred per execution of XFRB(062). Be sure that the source words and destination words do not exceed the end of the data area.

Examples
0.00
D100

When CIO 0.00 is ON in the following example, the 20 bits beginning with CIO 200.06 are copied to the 20 bits beginning with CIO 300.00.

C: D100 20 bits

259

Data Movement Instructions

Section 3-7

3-7-8
Purpose

BLOCK TRANSFER: XFER(070)

Transfers the specified number of consecutive words.

Ladder Symbol
XFER(070) N S D N: Number of words S: First source word D: First destination word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification XFER(070) @XFER(070) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

N: Number of Words Specifies the number of words to be transferred. The possible range for N is 0000 to FFFF (0 to 65,535 decimal). S: First Source Word Specifies the first source word.
15 0

to S+(N1)

to

D: First Destination Word Specifies the first destination word.

15 0

to D+(N1)

to

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary N CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 S D

A448 to A959

260

Data Movement Instructions

Area Indirect DM addresses in BCD Constants N *D0 to *D32767 S

Section 3-7
D

Data Registers Index Registers Indirect addressing using Index Registers

----#0000 to #FFFF (binary) or &0 to &65535 DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

XFER(070) copies N words beginning with S (S to S+(N1)) to the N words beginning with D (D to D+(N1)).

to S+(N1)

N words D+ (N1)

to

It is possible for the source words and destination words to overlap, so XFER(070) can perform word-shift operations.
D100 &10 D100 D102 D109 D111 D102

Flags
Name Error Flag Label ER Operation OFF

Precautions

Be sure that the source words (S to S+N1) and destination words (D to D+N1) do not exceed the end of the data area. Some time will be required to complete XFER(070) when a large number of words is being transferred. In this case, the XFER(070) transfer might not be completed if a power interruption occurs during execution of the instruction.

Example

When CIO 0.00 is ON in the following example, the 10 words D100 through D109 are copied to D200 through D209.
0.00 &10 D100 D200 D100 D101 D102 D200 D201 D202

10 words

D109

D209

261

Data Movement Instructions

Section 3-7

3-7-9
Purpose

BLOCK SET: BSET(071)

Copies the same word to a range of consecutive words.

Ladder Symbol
BSET(071) S St E S: Source word St: Starting word E: End word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BSET(071) @BSET(071) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: Source Word Specifies the source data or the word containing the source data. St: Starting Word Specifies the first word in the destination range. E: End Word Specifies the last word in the destination range.
St to E Source data Destination range St

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area

S St CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 A448 to A959 T0000 to T4095 C0000 to C4095

262

Data Movement Instructions

Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 St

Section 3-7
E

#0000 to #FFFF --(binary) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, 15( ) IR

Description

BSET(071) copies the same source word (S) to all of the destination words in the range St to E.
Source word Destination words St

Flags
Name Error Flag Label ER Operation ON if St is greater than E. OFF in all other cases.

Precautions

Be sure that the starting word (St) and end word (E) are in the same data area and that St E. Some time will be required to complete BSET(071) when the source data is being transferred to a large number of words. In this case, the BSET(071) transfer might not be completed if a power interruption occurs during execution of the instruction.

Example
0.00
S St E

When CIO 0.00 is ON in the following example, the source data in D100 is copied to D200 through D209.

D100 D200 D209

S: D100

St: D200 D201 D202 D203 D204 D205 D206 D207 D208 E: D209

263

Data Movement Instructions

Section 3-7

3-7-10 DATA EXCHANGE: XCHG(073)

Purpose Ladder Symbol
XCHG(073) E1 E2 E1: First exchange word E2: Second exchange word

Exchanges the contents of the two specified words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification XCHG(073) @XCHG(073) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers E1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15 E2

Description

XCHG(073) exchanges the contents of E1 and E2.

E1 E2

Flags

There are no flags affected by this instruction.

264

Data Movement Instructions

Example

Section 3-7
When CIO 0.00 is ON in the following example, the content of D100 is exchanged with the content of D200.
0.00 D100 D200

D100

D200

D100

D200

3-7-11 DOUBLE DATA EXCHANGE: XCGL(562)

Purpose Ladder Symbol
XCGL(562) E1 E2 E1: First exchange word E2: Second exchange word

Exchanges the contents of a pair of consecutive words with another pair of consecutive words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification XCGL(562) @XCGL(562) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers E1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------E2

265

Data Movement Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-7
E1 E2 IR0 to IR15 ,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15

Description

XCHG(073) exchanges the contents of E1+1 and E1 with the contents of E2+1 and E2.
E1 E1+1 E2 E2+1

To exchange 3 or more words, use XFER(070) to transfer the words to a third set of words (a buffer) as shown in the following diagram.
E1 1st XFER(070) operation Buffer 2nd XFER(070) operation E2 3rd XFER(070) operation

Flags Example

There are no flags affected by this instruction. When CIO 0.01 is ON in the following example, the contents of D100 and D101 are exchanged with the contents of D200 and D201.
0.01 D100 D200

D100 D101

D200 D201

D100 D101

D200 D201

266

Data Movement Instructions

Section 3-7

3-7-12 SINGLE WORD DISTRIBUTE: DIST(080)

Purpose Ladder Symbol
DIST(080) S Bs Of S: Source word Bs: Destination base address Of: Offset

Transfers the source word to a destination word calculated by adding an offset value to the base address.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification DIST(080) @DIST(080) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

Bs: Destination Base Address Specifies the destination base address. The offset is added to this address to calculate the destination word. Of: Offset This value is added to the base address to calculate the destination word. The offset can be any value from 0000 to FFFF (0 to 65,535 decimal), but Bs and Bs+Of must be in the same data area.
15 0

Bs
to to

Bs+Of

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S Bs CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) DR0 to DR15 --#0000 to #FFFF (binary) or &0 to &65535 DR0 to DR15 Of

A0 to A959

Data Registers

---

267

Data Movement Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-7
S Bs --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15 Of

Description

DIST(080) copies S to the destination word calculated by adding Of to Bs. The same DIST(080) instruction can be used to distribute the source word to various words in the data area by changing the value of Of.
S Bs Of

Bs+n

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if the source data is 0000. OFF in all other cases. ON if the leftmost bit of the source data is 1. OFF in all other cases.

Precautions Example

Be sure that the offset does not exceed the end of the data area, i.e., Bs and Bs+Of are in the same data area. When CIO 0.00 is ON in the following example, the contents of D100 will be copied to D210 (D200 + 10) if the contents of D300 is 10 (0A hexadecimal). The contents of D100 can be copied to other words by changing the offset in D300.

0.00 S Bs Of D100 D200 D300

S: D100 Copied by DIST(080). Bs: D200 D201 Offset +10 words D210 Of: D300
0 0 0 A

4-digit hexadecimal

268

Data Movement Instructions

Section 3-7

3-7-13 DATA COLLECT: COLL(081)

Purpose Ladder Symbol
COLL(081) Bs Of D Bs: Source base address Of: Offset D: Destination word

Transfers the source word (calculated by adding an offset value to the base address) to the destination word.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification COLL(081) @COLL(081) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

Bs: Source Base Address Specifies the source base address. The offset is added to this address to calculate the source word. Of: Offset This value is added to the base address to calculate the source word. The offset can be any value from 0000 to FFFF (0 to 65,535 decimal), but Bs and Bs+Of must be in the same data area.
15 0

Bs to Of to

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Bs CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to #FFFF (binary) or &0 to &65535 DR0 to DR15 --Of D

A448 to A959

Data Registers

---

269

Data Movement Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-7
Bs Of --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( ) IR0 to, ( ) IR15 D

Description

COLL(081) copies the source word (calculated by adding Of to Bs) to the destination word. The same COLL(081) instruction can be used to collect data from various source words in the data area by changing the value of Of.
Bs
Of

Bs+n

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if the source data is 0000. OFF in all other cases. ON if the leftmost bit of the source data is 1. OFF in all other cases.

Precautions Example

Be sure that the offset does not exceed the end of the data area, i.e., Bs and Bs+Of are in the same data area. When CIO 0.00 is ON in the following example, the contents of D110 (D100 + 10) will be copied to D300 if the content of D200 is 10 (0A hexadecimal). The contents of other words can be copied to D300 by changing the offset in D200.
0.00 Bs Of D D100 D200 D300 Bs: D100 D101 Offset +10 words D110 Copied by COLL(081). D300 D200 0 0 0 A

4-digit hexadecimal

3-7-14 MOVE TO REGISTER: MOVR(560)

Purpose Sets the PLC memory address of the specified word, bit, or timer/counter Completion Flag in the specified Index Register. (Use MOVRW(561) to set the PLC memory address of a timer/counter PV in an Index Register.)

Ladder Symbol
MOVR(560) S D S: Source (desired word or bit) D: Destination (Index Register)

270

Data Movement Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-7

MOVR(560) @MOVR(560) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Operand Specifications

D: Destination The destination must be an Index Register (IR0 to IR15).

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area

S CIO 0 to CIO 6143 CIO 0.00 to CIO 6143.15 W0 to W511 W0.00 to W511.15 H0 to H511 H0.00 to H511.15 A0 to A447 A448 to A959 A0.00 to A447.15 A448.00 to A959.15 T0000 to T4095 (Completion Flag) C0000 to C4095 (Completion Flag) TK00 to TK31 D0 to D32767 -------------

D ---------

Timer Area Counter Area Task Flag DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers

---------

IR0 to IR15

Description

MOVR(560) finds the PLC memory address (absolute address) of S and writes that address in D (an Index Register).
Internal I/O memory address of S

Index Register

If a timer or counter is specified in S, MOVR(560) will write the PLC memory address of the timer/counter Completion Flag in D. Use MOVRW(561) to write the PLC memory address of the timer/counter PV in D.

271

Data Movement Instructions

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF or unchanged OFF or unchanged OFF or unchanged

Section 3-7

Precautions

MOVR(560) cannot set the PLC memory addresses of timer/counter PVs. Use MOVRW(561) to set the PLC memory addresses of timer/counter PVs. The contents of an index register in an interrupt task is not predictable until it is set. Be sure to set a register using MOVR(560) in an interrupt task before using the register. Any changes to the contents of an IR or DR made in an interrupt task will not affect the contents of the register in a cyclic task.

Example

When CIO 0.00 is ON in the following example, MOVR(560) writes the PLC memory address of CIO 200 to IR0.
0.00 S: 200 200 Internal I/O memory address of CIO 200 D: IR0
14

Internal I/O memory address

14

3-7-15 MOVE TIMER/COUNTER PV TO REGISTER: MOVRW(561)

Purpose Sets the PLC memory address of the specified timer or counters PV in the specified Index Register. (Use MOVR(560) to set the PLC memory address of a word, bit, or timer/counter Completion Flag in an Index Register.)

Ladder Symbol
MOVRW(561) S D S: Source (desired TC number) D: Destination (Index Register)

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification MOVR(561) @MOVR(561) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Operand Specifications

D: Destination The destination must be an Index Register (IR0 to IR15).

Area CIO Area Work Area Holding Bit Area

S -------

272

Data Movement Instructions

Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S --T0000 to T4095 (present value) C0000 to C4095 (present value) ---------------

Section 3-7
D -----

IR0 to IR15

Description

MOVRW(561) finds the PLC memory address for the PV of the timer or counter specified in S and writes that address in D (an Index Register).
Internal I/O memory address of S

Timer/counter PV only Index Register

MOVRW(561) will set the PLC memory address of the timer or counters PV in D. Use MOVR(560) to set the PLC memory address of the timer or counter Completion Flag. Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF or unchanged OFF or unchanged OFF or unchanged

Precautions

MOVRW(561) cannot set the PLC memory addresses of data area words, bits, or timer/counter Completion Flags. Use MOVR(560) to set these PLC memory addresses. When CIO 0.01 is ON in the following example, MOVRW(561) writes the PLC memory address for the PV of timer T0 to IR1.
0.01 S: T0 T0 Internal I/O memory address

Example

273

Data Shift Instructions

Section 3-8

3-8

Data Shift Instructions

This section describes instructions used to shift data within or between words, but in differing amounts and directions.
Instruction SHIFT REGISTER REVERSIBLE SHIFT REGISTER ASYNCHRONOUS SHIFT REGISTER WORD SHIFT ARITHMETIC SHIFT LEFT DOUBLE SHIFT LEFT ARITHMETIC SHIFT RIGHT DOUBLE SHIFT RIGHT ROTATE LEFT DOUBLE ROTATE LEFT ROTATE LEFT WITHOUT CARRY DOUBLE ROTATE LEFT WITHOUT CARRY ROTATE RIGHT DOUBLE ROTATE RIGHT ROTATE RIGHT WITHOUT CARRY DOUBLE ROTATE RIGHT WITHOUT CARRY ONE DIGIT SHIFT LEFT ONE DIGIT SHIFT RIGHT SHIFT N-BIT DATA LEFT SHIFT N-BIT DATA RIGHT SHIFT N-BITS LEFT DOUBLE SHIFT N-BITS LEFT SHIFT N-BITS RIGHT DOUBLE SHIFT N-BITS RIGHT Mnemonic SFT SFTR ASFT WSFT ASL ASLL ASR ASRL ROL ROLL RLNC RLNL ROR RORL RRNC RRNL SLD SRD NSFL NSFR NASL NSLL NASR NSRL Function code 010 084 017 016 025 570 026 571 027 572 574 576 028 573 575 577 074 075 578 579 580 582 581 583 Page 274 276 279 281 283 284 286 287 289 290 295 297 292 294 299 300 302 303 305 307 309 311 314 317

3-8-1
Purpose

SHIFT REGISTER: SFT(010)

Operates a shift register.

Ladder Symbol
Data input Shift input Reset input

SFT(010) St E St: Starting word E: End word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SFT(010) Not supported Not supported Not supported

274

Data Shift Instructions

Applicable Program Areas
Block program areas Step program areas Not allowed OK Subroutines OK

Section 3-8

Interrupt tasks OK

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers

St CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 -----------

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15

Description

When the execution condition on the shift input changes from OFF to ON, all the data from St to E is shifted to the left by one bit (from the rightmost bit to the leftmost bit), and the ON/OFF status of the data input is placed in the rightmost bit.
E St+1, St+2, ... St

Lost

Status of data input for each shift input

Flags
Name Error Flag Label ER Operation ON if the indirect IR address for St and E is not in the CIO, AR, HR, or WR data areas. OFF in all other cases.

Precautions

The bit data shifted out of the shift register is discarded. When the reset input turns ON, all bits in the shift register from the rightmost designated word (St) to the leftmost designated word (E) will be reset (i.e., set to 0). The reset input takes priority over other inputs. St must be less than or equal to E, but even when St is set to greater than E an error will not occur and one word of data in St will be shifted. When St and E are designated indirectly using index registers and the actual addresses in I/O memory are not within memory areas for data, an error will occur and the Error Flag will turn ON.

275

Data Shift Instructions

Examples Shift Register Exceeding 16 Bits

Section 3-8

The following example shows a 48-bit shift register using words CIO 1000 to CIO 1002. A 1-s clock pulse is used so that the execution condition produced by CIO 0.05 is shifted into a 3-word register between CIO 1000.00 and CIO 1002.15 every second.
0.05 P_1s
(1-s clock) Data input

Shift input Reset

1000 1002

E: CIO 1002 Lost

St+1: CIO 1001

St: CIO 1000

Contents of CIO 0.05

0.06

3-8-2
Purpose

REVERSIBLE SHIFT REGISTER: SFTR(084)

Creates a shift register that shifts data to either the right or the left.

Ladder Symbol
SFTR(084) C St E C: Control word St: Starting word E: End word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SFTR(084) @SFTR(084) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

C: Control Word

15 14 13 12
Shift direction 1 (ON): Left 0 (OFF): Right Data input Shift input Reset

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area

C CIO 0 to CIO 6143 W0 to W511

St

276

Data Shift Instructions

Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C St H0 to H511 A0 to A959 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-8
E

--DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

When the execution condition of the shift input bit (bit 14 of C) changes to ON, all the data from St to E is moved in the designated shift direction (designated by bit 12 of C) by 1 bit, and the ON/OFF status of the data input is placed in the rightmost or leftmost bit. The bit data shifted out of the shift register is placed in the Carry Flag (CY).

St

Data input

Data input

St

Shift direction

Flags
Name Error Flag Carry Flag Label ER CY Operation ON when St is greater than E. OFF in all other cases. ON when 1 is shifted into it. OFF when 0 is shifted into it. OFF when reset is set to 1.

Precautions

The above shift operations are applicable when the reset bit (bit 15 of C) is set to OFF. When reset (bit 15 of C) turns ON all bits in the shift register, from St to E will be reset (i.e., set to 0). When St is greater than E, an error will be generated and the Error Flag will turn ON.

277

Data Shift Instructions

Examples Shifting Data

Section 3-8

If shift input H0.14 goes ON when CIO 0.00 is ON and the reset bit H0.15 is OFF, words D100 through D102 will shift one bit in the direction designated by H0.12 (e.g., 1: right) and the contents of input bit H0.13 will be shifted into the rightmost bit of D100. The contents of bit 15 of D102 will be shifted to the Carry Flag (CY).
0.00 C St E H0 D100 D200 C: H0 Shift direction Shift input: 1 Reset input: 0

D102

D101

D100

Data input: H0.13

Resetting Data If H0.14 is ON when CIO 0.00 is ON, and the reset bit, H0.15, is ON, words D100 through D102 and the Carry Flag will be reset to OFF. Controlling Data Resetting Data All bits from St to E and the Carry Flag are set to 0 and no other data can be received when the reset input bit (bit 15 of C) is ON.

Shifting Data Left (from Rightmost to Leftmost Bit) When the shift input bit (bit 14 of C) is ON, the contents of the input bit (bit 13 of C) is shifted to bit 00 of the starting word, and each bit thereafter is shifted one bit to the left. The status of bit 15 of the end word is shifted to the Carry Flag.
Data input

Shifting Data Right (from Leftmost to Rightmost Bit When the shift input bit (bit 14 of C) is ON, the contents of the input bit (bit 13 of C) (I/O) is shifted to bit 15 on the end word, and each bit thereafter is shifted one bit to the right. The status of bit 00 of the starting word is shifted to the Carry Flag.
Data input

278

Data Shift Instructions

Section 3-8

3-8-3
Purpose

ASYNCHRONOUS SHIFT REGISTER: ASFT(017)

Shifts all non-zero word data within the specified word range either towards St or toward E, replacing 0000 hex word data.

Ladder Symbol
ASFT(017) C St E C: Control word St: Starting word E: End word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASFT(017) @ASFT(017) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

C: Control Word
15 14 13 12
Shift direction 0: Non-zero data shifted toward E 1: Non-zero data shifted toward St Shift Enable Bit 0: Shift disabled 1: Shift enabled Clear Bit 0: Data not reset 1: All data from St to E is reset

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers

C St CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15

---

279

Data Shift Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-8
C St --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 E

Description

When the Shift Enable Bit (bit 14 of C) is ON, all of the words with non-zero content within the range of words between St and E will be shifted one word in the direction determined by the Shift Direction Bit (bit 13 of C) whenever the word in the shift direction contains all zeros. If ASFT(017) is repeated sufficient times, all all-zero words will be replaced by non-zero words. This will result in all the data between St and E being divided into zero and non-zero data.

St ... Convert Convert E

Shift direction Shift enabled Clear

St Non-zero data ... Zero data E

Flags
Name Error Flag Label ER Operation ON when St is greater than E. ON if the Communications Port Enabled Flag for the communications port number specified as the Com Port number for Background Execution is OFF when background processing is specified (CP1H only). OFF in all other cases.

Precautions

When the Clear Flag (bit 15 of C) goes ON, all bits in the shift register, from St to E, will be reset (i.e., set to 0). The Clear Flag has priority over the Shift Enable Bit (bit 14 of C). When St is greater than E an error will be generated and the Error Flag will turn ON.

280

Data Shift Instructions

Examples Shifting Data:

Section 3-8

If the Shift Enable Bit, H0.14, goes ON when CIO 0.00 is ON, all words with non-zero data content from D100 through D109 will be shifted in the direction designated by the Shift Direction Bit, H0.13 (e.g., 1: Toward St) if the word to the left of the non-zero data is all zeros.
0.00 C St E H0 D100 D109 C: H0 Shift direction 1: Non-zero data shifted toward E Shift Enable Bit: 1 Clear Before ASFT(017) is executed St: D100 Non-zero data is shifted toward St D101 D102 D103 D104 D105 D106 D107 D108 E: D109 9 A B C 5 6 7 8 9 A B C 1 2 3 4 After one execution 1 5 2 6 3 7 4 8 After two executions 1 5 9 2 6 A 3 7 B 4 8 C

3-8-4
Purpose

WORD SHIFT: WSFT(016)

Shifts data between St and E in word units.

Ladder Symbol
WSFT(016) S St E S: Source word St: Starting word E: End word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification WSFT(016) @WSFT(016) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area

S CIO 0 to CIO 6143 W0 to W511

St

281

Data Shift Instructions

Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S St H0 to H511 A0 to A959 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-8
E

#0000 to #FFFF --(binary) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

WSFT(016) shifts data from St to E in word units and the data from the source word S is places into St. The contents of E is lost.
E Lost St

Flags
Name Error Flag Label ER Operation ON when St is greater than E. OFF in all other cases.

Precautions Note

When St is greater than E, an error will be generated and the Error Flag will turn ON. When large amounts of data are shifted, the instruction execution time is quite long. Be sure that the power is not cut while WSFT(016) is being executed, causing the shift operation to stop halfway through. When CIO 0.00 is ON, data from D100 through D102 will be shifted one word toward E. The contents of H0 will be stored in D100 and the contents of D102 will be lost.
0.00 H0

Examples

St E

D100 D102
E: D102 St: D101 St: D100 S: H0

Lost

282

Data Shift Instructions

Section 3-8

3-8-5
Purpose

ARITHMETIC SHIFT LEFT: ASL(025)

Shifts the contents of Wd one bit to the left.

Ladder Symbol
ASL(025) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASL(025) @ASL(025) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

Description

ASL(025) shifts the contents of Wd one bit to the left (from rightmost bit to leftmost bit). 0 is placed in the rightmost bit and the data from the leftmost bit is shifted into the Carry Flag (CY).

15

283

Data Shift Instructions

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N

Section 3-8

Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When ASL(025) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd is zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON, D100 will be shifted one bit to the left. 0 will be placed in bit 00 of D100 and the contents of bit 15 of D100 will be shifted to the Carry Flag (CY).
0.00 Wd D100

Wd: D100

3-8-6
Purpose

DOUBLE SHIFT LEFT: ASLL(570)

Shifts the contents of Wd and Wd +1 one bit to the left.

Ladder Symbol
ASLL(570) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASLL(570) @ASLL(570) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Wd CIO 0 to CIO 6142 W0 to W510 H0 to H510

284

Data Shift Instructions

Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Wd A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767

Section 3-8

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ASLL(570) shifts the contents of Wd and Wd +1 one bit to the left (from rightmost bit to leftmost bit). 0 is placed in the rightmost bit of Wd and the contents of the leftmost bit of Wd and Wd +1 are shifted into the Carry Flag (CY).
Wd+1 Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When ASLL(570) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd +1 is 1, the Negative Flag will turn ON.

285

Data Shift Instructions

Examples

Section 3-8
When CIO 0.01 is ON, word CIO 1000 and CIO 1001 will shift one bit to the left. 0 is placed into CIO 1000.00 and the contents of CIO 1001.15 will be shifted to the Carry Flag (CY).
0.01 Wd 1000

Wd+1: CIO 1001

Wd: CIO 1000

3-8-7
Purpose

ARITHMETIC SHIFT RIGHT: ASR(026)

Shifts the contents of Wd one bit to the right.

Ladder Symbol
ASR(026) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASR(026) @ASR(026) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

286

Data Shift Instructions

Description

Section 3-8
ASR(026) shifts the contents of Wd one bit to the right (from leftmost bit to rightmost bit). 0 will be placed in the leftmost bit and the contents of the rightmost bit will be shifted into the Carry Flag (CY).

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. OFF

Precautions

When ASR(026) is executed, the Error Flag and the Negative Flag will turn OFF. If as a result of the shift the contents of Wd is zero, the Equals Flag will turn ON.

Examples

When CIO 0.00 is ON, word CIO 1000 will shift one bit to the right. 0 will be placed in CIO 1000.15 and the contents of CIO 1000.00 will be shifted to the Carry Flag (CY).
0.00 Wd 1000

Wd: CIO 1000

3-8-8
Purpose

DOUBLE SHIFT RIGHT: ASRL(571)

Shifts the contents of Wd and Wd +1 one bit to the right.

Ladder Symbol
ASRL(571) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASRL(571) @ASRL(571) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

287

Data Shift Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Wd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767

Section 3-8

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ASRL(571) shifts the contents of Wd and Wd +1 one bit to the right (from leftmost bit to rightmost bit). 0 will be placed in the leftmost bit of Wd +1 and the contents of the rightmost bit of Wd will be shifted into the Carry Flag (CY).
Wd+1 Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. OFF

Precautions

When ASRL (571) is executed, the Error Flag and the Negative Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON.

288

Data Shift Instructions

Examples

Section 3-8
When CIO 0.01 is ON, word CIO 2000 and CIO 2001 will shift one bit to the right. 0 will be placed into CIO 2001.15 and the contents of CIO 2000.00 will be shifted to the Carry Flag (CY).
0.01 Wd 2000

Wd+1: CIO 2001

Wd: CIO 2000

3-8-9
Purpose

ROTATE LEFT: ROL(027)

Shifts all Wd bits one bit to the left including the Carry Flag (CY).

Ladder Symbol
ROL(027) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ROL(027) @ROL(027) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

289

Data Shift Instructions

Description

Section 3-8
ROL(027) shifts all bits of Wd including the Carry Flag (CY) to the left (from rightmost bit to leftmost bit).

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When ROL(027) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd is zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd is 1, the Negative Flag will turn ON. Note It is possible to set the Carry Flag contents to 1 or 0 immediately before executing this instruction, by using the Set Carry (STC(040)) or Clear Carry (CLC(041)) instructions. When CIO 0.00 is ON, word CIO 1000 and the Carry Flag (CY) will shift one bit to the left. The contents of CIO 1000.15 will be shifted to the Carry Flag (CY) and the Carry Flag contents will be shifted to CIO 1000.00.
0.00 Wd 1000

Examples

Wd: CIO 1000

Instruction executed once

3-8-10 DOUBLE ROTATE LEFT: ROLL(572)

Purpose Ladder Symbol
ROLL(572) Wd Wd: Word

Shifts all Wd and Wd +1 bits one bit to the left including the Carry Flag (CY).

290

Data Shift Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-8

ROLL(572) @ROLL(572) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Wd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ROLL(572) shifts all bits of Wd and Wd +1 including the Carry Flag (CY) to the left (from rightmost bit to leftmost bit).
Wd+1 Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When ROLL(572) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON.

291

Data Shift Instructions

Section 3-8
If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Negative Flag will turn ON.

Note

It is possible to set the Carry Flag contents to 1 or 0 immediately before executing this instruction, by using the Set Carry (STC(040)) or Clear Carry (CLC(041)) instructions. When CIO 0.01 is ON, word CIO 2000, CIO 2001 and the Carry Flag (CY) will shift one bit to the left. The contents of CIO 2001.15 will be shifted to the Carry Flag (CY) and the Carry Flag contents will be shifted to CIO 2000.00.
0.01 Wd 2000

Examples

Wd+1: CIO 2001

Wd: CIO 2000

Instruction executed once

3-8-11 ROTATE RIGHT: ROR(028)

Purpose Ladder Symbol
ROR(028) Wd Wd: Word

Shifts all Wd bits one bit to the right including the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ROR(028) @ROR(028) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --Wd

292

Data Shift Instructions

Area Data Registers Index Registers Indirect addressing using Index Registers

Section 3-8
Wd DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ROR(028) shifts all bits of Wd including the Carry Flag (CY) to the right (from leftmost bit to rightmost bit).

Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When ROR(028) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd is zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd is 1, the Negative Flag will turn ON. Note It is possible to set the Carry Flag contents to 1 or 0 immediately before executing this instruction, by using the Set Carry (STC(040)) or Clear Carry (CLC(041)) instructions. When CIO 0.00 is ON, word CIO 1000 and the Carry Flag (CY) will shift one bit to the right. The contents of CIO 1000.00 will be shifted to the Carry Flag (CY) and the Carry Flag contents will be shifted to CIO 1000.15.
0.00 Wd 1000

Examples

Wd: CIO 1000

Instruction executed once

293

Data Shift Instructions

Section 3-8

3-8-12 DOUBLE ROTATE RIGHT: RORL(573)

Purpose Ladder Symbol
RORL(573) Wd Wd: Word

Shifts all Wd and Wd +1 bits one bit to the right including the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification RORL(573) @RORL(573) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

Description

RORL(573) shifts all bits of Wd and Wd +1 including the Carry Flag (CY) to the right (from leftmost bit to rightmost bit).
Wd+1 Wd

Flags
Name Error Flag Equals Flag Label ER = Operation OFF ON when the shift result is 0. OFF in all other cases.

294

Data Shift Instructions

Name Carry Flag Negative Flag Label CY N

Section 3-8
Operation ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When RORL(573) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Negative Flag will turn ON. Note It is possible to set the Carry Flag contents to 1 or 0 immediately before executing this instruction, by using the Set Carry (STC(040)) or Clear Carry (CLC(041)) instructions. When CIO 0.01 is ON, word CIO 2000, CIO 2001 and the Carry Flag (CY) will shift one bit to the right. The contents of CIO 2000.00 will be shifted to the Carry Flag (CY) and the Carry Flag contents will be shifted to CIO 2001.15.
0.01 Wd 2000

Examples

Wd+1: CIO 2001

Wd: CIO 2000

Instruction executed once

3-8-13 ROTATE LEFT WITHOUT CARRY: RLNC(574)

Purpose Ladder Symbol
RLNC(574) Wd Wd: Word

Shifts all Wd bits one bit to the left not including the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification RLNC(574) @RLNC(574) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Wd CIO 0 to CIO 6143 W0 to W511 H0 to H511

295

Data Shift Instructions

Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Wd A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-8

--DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

RLNC(574) shifts all bits of Wd to the left (from rightmost bit to leftmost bit). The contents of the leftmost bit of Wd shifts to the rightmost bit and to the Carry Flag (CY).
Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When RLNC(574) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd is zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd is 1, the Negative Flag will turn ON.

296

Data Shift Instructions

Examples

Section 3-8
When CIO 0.00 is ON, word CIO 1000 will shift one bit to the left (excluding the Carry Flag (CY)). The contents of CIO 1000.15 will be shifted to CIO 1000.00.
0.00 Wd 1000

Wd: CIO 1000

Instruction executed once

1

3-8-14 DOUBLE ROTATE LEFT WITHOUT CARRY: RLNL(576)

Purpose Ladder Symbol
RLNL(576) Wd Wd: Word

Shifts all Wd and Wd +1 bits one bit to the left not including the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification RLNL(576) @RLNL(576) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ----Wd

297

Data Shift Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-8
Wd --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

RLNL(576) shifts all bits of Wd and Wd +1 to the left (from rightmost bit to leftmost bit). The contents of the leftmost bit of Wd +1 is shifted to the rightmost bit of Wd, and to the Carry Flag (CY).
Wd+1 Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When RLNL(576) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.01 is ON, word CIO 1100 and CIO 1101 will shift one bit to the left (excluding the Carry Flag (CY)). The contents of CIO 1101.15 will be shifted to CIO 1100.00.
0.01 Wd 1100

Wd+1: CIO 1101

Wd: CIO 1100

Instruction executed once

1

298

Data Shift Instructions

Section 3-8

3-8-15 ROTATE RIGHT WITHOUT CARRY: RRNC(575)

Purpose Shifts all Wd bits one bit to the right not including the Carry Flag (CY). The contents of the rightmost bit of Wd shifts to the leftmost bit and to the Carry Flag (CY).

Ladder Symbol
RRNC(575) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification RRNC(575) @RRNC(575) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

Description

RRNC(575) shifts all bits of Wd to the right (from leftmost bit to rightmost bit) not including the Carry Flag (CY).

Wd

299

Data Shift Instructions

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N

Section 3-8

Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When RRNC(575) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd is zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON, word CIO 1000 will shift one bit to the right (excluding the Carry Flag (CY)). The contents of CIO 1000.00 will be shifted to CIO 1000.15.
0.00

Wd

1000

Wd: CIO 1000

Instruction executed once

CY

3-8-16 DOUBLE ROTATE RIGHT WITHOUT CARRY: RRNL(577)

Purpose Shifts all Wd and Wd +1 bits one bit to the right not including the Carry Flag (CY). The contents of the rightmost bit of Wd +1 is shifted to the leftmost bit of Wd, and to the Carry Flag (CY).

Ladder Symbol
RRNL(577) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification RRNL(577) @RRNL(577) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

300

Data Shift Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Wd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767

Section 3-8

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

RRNL(577) shifts all bits of Wd and Wd +1 to the right (from leftmost bit to rightmost bit) not including the Carry Flag (CY).
Wd+1 Wd

Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

When RRNL(577) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Negative Flag will turn ON. Note It is possible to set the Carry Flag contents to 1 or 0 immediately before executing this instruction, by using the Set Carry (STC(040)) or Clear Carry (CLC(041)) instructions.

301

Data Shift Instructions

Examples

Section 3-8
When CIO 0.01 is ON, words CIO 2000 and CIO 2001 will shift one bit to the right, (excluding the Carry Flag (CY)). The contents of CIO 2001.00 will be shifted to CIO 2000.15.
0.01 Wd 2000

Wd+1: CIO 2001

Wd: CIO 2000

Instruction executed once

3-8-17 ONE DIGIT SHIFT LEFT: SLD(074)

Purpose Ladder Symbol
SLD(074) St E St: Starting word E: End word

Shifts data by one digit (4 bits) to the left.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SLD(074) @SLD(074) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers

St CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 -----

302

Data Shift Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-8
St E --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

SLD(074) shifts data between St and E by one digit (4 bits) to the left. 0 is placed in the rightmost digit (bits 3 to 0 of St), and the content of the leftmost digit (bits 15 to 12 of E) is lost.
E Lost S t
0 Hex

Flags
Name Error Flag Label ER Operation ON when St is greater than E. OFF in all other cases.

Precautions Note

When St is greater than E, an error will be generated and the Error Flag will turn ON. When large amounts of data are shifted, the instruction execution time is quite long. Be sure that the power is not cut while SLD(074) is being executed, causing the shift operation to stop halfway through. When CIO 0.00 is ON, words CIO 1000 through CIO 1002 will shift by one digit (4 bits) to the left. A zero will be placed in bits 0 to 3 of word CIO 1000 and the contents of bits 12 to 15 of CIO 1002 will be lost.
0.00 St E 1000 1002 Lost E: CIO 1002 St+1: CIO 1001 St: CIO 1000

Examples

3-8-18 ONE DIGIT SHIFT RIGHT: SRD(075)

Purpose Ladder Symbol
SRD(075) St E St: Starting word E: End word

Shifts data by one digit (4 bits) to the right.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SRD(075) @SRD(075) Not supported Not supported

303

Data Shift Instructions

Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-8

Interrupt tasks OK

Note Operand Specifications

St and E must be in the same data area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers

St CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

SRD(075) shifts data between St and E by one digit (4 bits) to the right. 0 is placed in the leftmost digit (bits 15 to 12 of E), and the content of the rightmost digit (bits 3 to 0 of St) is lost.
E S t Lost

Flags
Name Error Flag Label ER Operation ON when St is greater than E. OFF in all other cases.

Precautions

When St is greater than E, an error will be generated and the Error Flag will turn ON. When SRD(075) is executed, the Equals Flag and Negative Flag will turn OFF. Note When large amounts of data are shifted, the instruction execution time is quite long. Always take care that the power is not cut while SRD(075) is being executed, causing the shift operation to stop halfway through.

304

Data Shift Instructions

Examples

Section 3-8
When CIO 0.00 is ON, words CIO 1000 through CIO 1002 will shift by one digit (4 bits) to the right. A zero will be placed in bits 12 to 15 of CIO 1002 and the contents of bits 0 to 3 of word CIO 1000 will be lost.
0.00 St E 1000 1002 E: CIO 1002 St+1: CIO 1001 St: CIO 1000 Lost

3-8-19 SHIFT N-BIT DATA LEFT: NSFL(578)

Purpose Ladder Symbol
NSFL(578) D C N D: Beginning word for shift C: Beginning bit N: Shift data length

Shifts the specified number of bits to the left.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NSFL(578) @NSFL(578) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Note Operand Specifications

C: 0000 to 000F hex (0 to 15) N: 0000 to FFFF hex (0 to 65535) All words in the shift register must be in the same area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants

D C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to #000F (binary) or &0 to &15 DR0 to DR15

#0000 to #FFFF (binary) or &0 to &65535

Data Registers

---

305

Data Shift Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-8
D C --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 N

Description

NSFL(578) shifts the specified number of bits by the shift data length (N) from the beginning bit (C) in the rightmost word, as designated by D one bit to the left (towards the leftmost word and the leftmost bit). 0 is place into the beginning bit and the contents of the leftmost bit in the shift area are shifted to the Carry Flag (CY).

N1 bit

Shifts one bit to the left

N1 bit

Flags
Name Error Flag Carry Flag Label ER CY Operation ON when C data is not between 0000 and 000F hex. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases.

Precautions

When the shift data length (N) is 0, the contents of the beginning bit will be copied to the Carry Flag (CY), and its contents will not be changed. Only the bits shifted into rightmost word in the shift area (i.e. leftmost word data) will be changed.

Examples

When CIO 0.00 is ON, all bits from the beginning bit 3 to the shift data length (B hex) will be shifted one bit to the left (from the rightmost bit to the leftmost bit). 0 will be placed into bit 3 of CIO 100. The contents of the leftmost bit in the shift area (bit 13 of CIO 100) are copied into the Carry Flag (CY).
0.00
D C N &3 &11

N: 11 bits D: CIO 100

C: Starting from bit 3

D: CIO 100

306

Data Shift Instructions

Section 3-8

3-8-20 SHIFT N-BIT DATA RIGHT: NSFR(579)

Purpose Ladder Symbol
NSFR(579) D C N D: Beginning word for shift C: Beginning bit N: Shift data length

Shifts the specified number of bits to the right.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NSFR(579) @NSFR(579) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Note Operand Specifications

C: 0000 to 000F hex (0 to 15) N: 0000 to FFFF hex (0 to 65535) All words in the shift register must be in the same area.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants

D C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to #000F (binary) or &0 to &15 DR0 to DR15

#0000 to #FFFF (binary) or &0 to &65535

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

307

Data Shift Instructions

Description

Section 3-8
NSFR(579) shifts the specified number of bits by the shift data length (N) from the beginning bit (C) in the rightmost word as designated by D one bit to the right (towards the rightmost word and the rightmost bit). 0 will be placed into the beginning bit and the contents of the rightmost bit in the shift area will be shifted to the Carry Flag (CY).

Shifts one bit to the right N-1 bit

N-1 bit

Flags
Name Error Flag Carry Flag Label ER CY Operation ON when C data is not between 0000 and 000F hex. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases.

Precautions

When the shift data length (N) is 0, the contents of the beginning bit will be copied to the Carry Flag (CY), and its contents will not be changed. Only the bits shifted into rightmost word in the shift area (i.e. leftmost word data) will be changed.

Examples

When CIO 0.00 is ON, all bits from the beginning bit 2 to end of the shift data length 11 bits (B hex), will be shifted one bit to the right , (from the leftmost bit to the rightmost bit). 0 is shifted into bit 12 of CIO 1000. The contents of the rightmost bit in the shift area (bit 2 of CIO 1000) are copied into the Carry Flag (CY).
0.00 1000
&2 &11

N: 11 bits D: CIO 1000

C: Starting from bit 2

D: CIO 1000 0

308

Data Shift Instructions

Section 3-8

3-8-21 SHIFT N-BITS LEFT: NASL(580)

Purpose Ladder Symbol
NASL(580) D C D: Shift word C: Control word

Shifts the specified 16 bits of word data to the left by the specified number of bits.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NASL(580) @NASL(580) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

C: Control Word
15 12 11 8 7 0

No. of bits to shift: 00 to 10 Hex

Always 0. Data shifted into register 0 Hex: 0 shifted in 8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers D CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 Specified values only C

A0 to A959

309

Data Shift Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-8
D C --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

NASL(580) shifts D (the shift word) by the specified number of binary bits (specified in C) to the left (from the rightmost bit to the leftmost bit). Either zeros or the value of the rightmost bit will be placed into the specified number of bits of the shift word starting from the rightmost bit.

Shift n-bits

Contents of "a" or "0" shifted in Lost N bits

Flags
Name Error Flag Label ER Operation ON when the control word C (the number of bits to shift) is not within range. OFF in all other cases. ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Equals Flag Carry Flag Negative Flag

= CY N

Precautions

For any bits which are shifted outside the specified word, the contents of the last bit is shifted to the Carry Flag (CY), and all other data is lost. When the number of bits to shift (specified in C) is 0, the data will not be shifted. The appropriate flags will turn ON and OFF, however, according to data in the specified word. When the contents of the control word C is out of range, an error will be generated and the Error Flag will turn ON. If as a result of the shift the contents of D is 0000 hex, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of D is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON, The contents of CIO 1000 is shifted 10 bits to the left (from the rightmost bit to the leftmost bit). The number of bits to shift is specified in bits 0 to 7 of word CIO 2000 (control data). The contents of bit 0 of CIO 1000 is copied into bits from which data was shifted and the contents of the rightmost bit which was shifted out of range is shifted into the Carry Flag (CY). All other data is lost.

310

Data Shift Instructions

0.00 1000 2000

Section 3-8

15

12 11

8 7

4 3

C: CIO 2000

No. of bits to shift: 10 bits (0A Hex)

Always 0. Data shifted into register 8 Hex: Contents of rightmost bit shifted in Lost CIO 1000 Rightmost bit

CIO 1000

No. of bits to shift: 10 bits (Contents of the rightmost bit is inserted.)

3-8-22 DOUBLE SHIFT N-BITS LEFT: NSLL(582)

Purpose Ladder Symbol
NSLL(582) D C D: Shift word C: Control word

Shifts the specified 32 bits of word data to the left by the specified number of bits.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NSLL(582) @NSLL(582) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

311

Data Shift Instructions

Operands C: Control Word

Section 3-8

15

12 11

8 7

No. of bits to shift: 00 to 20 Hex

Always 0. Data shifted into register 0 Hex: 0 shifted in 8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers D CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 --Specified values only --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

Description

NSLL(582) shifts D and D+1 (the shift words) by the specified number of binary bits (specified in C) to the left (from the rightmost bit to the leftmost bit). Either zeros or the value of the rightmost bit will be placed into the specified number of bits of the shift word starting from the rightmost bit.

Shift n-bits Contents of "a" or "0" shifted in Lost N bits

312

Data Shift Instructions

Flags
Name Error Flag Label ER

Section 3-8

Equals Flag Carry Flag Negative Flag

= CY N

Operation ON when the control word C (the number of bits to shift) is not within range. OFF in all other cases. ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

For any bits which are shifted outside the specified word, the contents of the last bit is shifted to the Carry Flag (CY), and all other data is lost. When the number of bits to shift (specified in C) is 0, the data will not be shifted. The appropriate flags will turn ON and OFF, however, according to data in the specified word. When the contents of the control word C are out of range, an error will be generated and the Error Flag will turn ON. If as a result of the shift the contents of D is 0000, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of D, D+1 is 1, the Negative Flag will turn ON.

313

Data Shift Instructions

Examples

Section 3-8
When CIO 0.00 is ON, CIO 1000 and CIO 1001 will be shifted to the left (from the rightmost bit to the leftmost bit) by 10 bits. The number of bits to shift is specified in bits 0 to 7 of word D300 (control data). The contents of bit 0 of CIO 1000 is copied into bits from which data was shifted and the contents of the rightmost bit which was shifted out of range is shifted into the Carry Flag (CY). All other data is lost.
0.00 1000 D300

15

12 11

8 7

4 3

C: D300

No. of bits to shift: 10 bits (0A Hex)

Always 0. Data shifted into register 8 Hex: Contents of rightmost bit shifted in

Lost CIO 1001 CIO 1000

Rightmost bit a

CIO 1001

CIO 1000 No. of bits to shift: 10 bits (Contents of the rightmost bit is shifted in)

3-8-23 SHIFT N-BITS RIGHT: NASR(581)

Purpose Ladder Symbol
NASR(581) D C D: Shift word C: Control word

Shifts the specified 16 bits of word data to the right by the specified number of bits.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NASR(581) @NASR(581) Not supported Not supported

314

Data Shift Instructions

Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-8

Interrupt tasks OK

Operands

C: Control Word
15 12 11 8 7 0

No. of bits to shift: 00 to 10 Hex

Always 0. Data shifted into register 0 Hex: 0 shifted in 8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers D CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --Specified values only DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 C

A0 to A447 A448 to A959

Description

NASR(581) shifts D (the shift word) by the specified number of binary bits (specified in C) to the right (from the rightmost bit to the leftmost bit). Either zeros or the value of the rightmost bit will be placed into the specified number of bits of the shift word starting from the rightmost bit.

Contents of "a" or "0" shifted in Lost N bits

315

Data Shift Instructions

Flags
Name Error Flag Label ER

Section 3-8

Equals Flag Carry Flag Negative Flag

= CY N

Operation ON when the control word C (the number of bits to shift) is not within range. OFF in all other cases. ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Precautions

For any bits which are shifted outside the specified word, the contents of the last bit is shifted to the Carry Flag (CY), and all other data is discarded. When the number of bits to shift (specified in C) is 0, the data will not be shifted. The appropriate flags will turn ON and OFF, however, according to data in the specified word. When the contents of the control word C are out of range, an error will be generated and the Error Flag will turn ON. If as a result of the shift the contents of D is 0000 hex, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of D is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON, CIO 1000 will be shifted 10 bits to the right (from the leftmost bit to the rightmost bit). The number of bits to shift is specified in bits 0 to 7 of word D300. The contents of bit 15 of CIO 1000 is copied into the bits from which data was shifted and the contents of the leftmost bit of data which was shifted out of range, is shifted into the Carry Flag (CY). All other data is lost.
0.00 1000 D300

15

12 11

8 7

4 3

C: D300

No. of bits to shift: 10 bits (0A Hex)

Always 0. Data shifted into register 8 Hex: Contents of leftmost bit shifted in

316

Data Shift Instructions

Leftmost bit Lost

Section 3-8

CIO 1000

CIO 1001 No. of bits to shift: 10 bits (Contents of the leftmost bit is inserted.)

3-8-24 DOUBLE SHIFT N-BITS RIGHT: NSRL(583)

Purpose Ladder Symbol
NSRL(583) D C D: Shift word C: Control word

Shifts the specified 32 bits of word data to the right by the specified number of bits.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NSRL(583) @NSRL(583) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

C: Control Word
15 12 11 8 7 0

No. of bits to shift: 00 to 20 Hex

Always 0. Data shifted into register 0 Hex: 0 shifted in 8 Hex: Contents of rightmost bit shifted in

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area D CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

317

Data Shift Instructions

Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers D @ D0 to @ D32767 *D0 to *D32767

Section 3-8
C

--Specified values only --DR0 to DR15 --,IR0 to ,IR15 -2048 to +2047 ,IR0 to -2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

NSRL(583) shifts D and D+1 (the shift words) by the specified number of binary bits (specified in C) to the right (from the leftmost bit to the rightmost bit). Either zeros or the value of the rightmost bit will be placed into the specified number of bits of the shift word starting from the rightmost bit.

Shift n-bits

Contents of "a" or "0" shifted in

Lost

Flags
Name Error Flag Label ER Operation ON when the control word C (the number of bits to shift) is not within range. OFF in all other cases. ON when the shift result is 0. OFF in all other cases. ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. ON when the leftmost bit is 1 as a result of the shift. OFF in all other cases.

Equals Flag Carry Flag Negative Flag

= CY N

Precautions

For any bits which are shifted outside the specified word, the contents of the last bit is shifted to the Carry Flag (CY), and all other data is lost. When the number of bits to shift (specified in C) is 0, the data will not be shifted. The appropriate flags will turn ON or OFF, however, according to data in the specified word. When the contents of the control word C are out of range, an error will be generated and the Error Flag will turn ON. If as a result of the shift the contents of D +1 is 00000000 hex, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of D +1 is 1, the Negative Flag will turn ON.

318

Data Shift Instructions

Examples

Section 3-8
When CIO 0.00 is ON, CIO 1000 and CIO 1001 will be shifted 10 bits to the right (from the leftmost bit to the rightmost bit). The number of bits to shift is specified in bits 0 to 7 of word D300 (control data). The contents of bit 15 of CIO 1001 will be copied into the bits from which data was shifted and the contents of the leftmost bit of data which was shifted out of range will be shifted into the Carry Flag (CY). All other data is lost.
0.00 1000 D300

15

12 11

8 7

4 3

C: D300

No. of bits to shift: 10 bits (0A hex)

Always 0. Data shifted into register 8 Hex: Contents of leftmost bit shifted in Leftmost bit CIO 1001
CIO 1000

Lost

CIO 1001 No. of bits to shift: 10 bits (Contents of the leftmost bit is inserted.)

CIO 1000

CY

319

Increment/Decrement Instructions

Section 3-9

3-9

Increment/Decrement Instructions
This section describes instructions used to increment data.
Instruction INCREMENT BINARY DOUBLE INCREMENT BINARY DECREMENT BINARY DOUBLE DECREMENT BINARY INCREMENT BCD DOUBLE INCREMENT BCD DECREMENT BCD DOUBLE DECREMENT BCD ++ ++L L ++B ++BL B BL Mnemonic Function code 590 591 592 593 594 595 596 597 Page 320 322 324 326 328 330 332 334

3-9-1
Purpose

INCREMENT BINARY: ++(590)

Increments the 4-digit hexadecimal content of the specified word by 1.

Ladder Symbol
++(590) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ++(590) @++(590) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Wd CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15

320

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The ++(590) instruction adds 1 to the binary content of Wd. The specified word will be incremented by 1 every cycle as long as the execution condition of ++(590) is ON. When the up-differentiated variation of this instruction (@++(590)) is used, the specified word is incremented only when the execution condition has gone from OFF to ON.
Wd Wd

The Equals Flag will be turned ON if the result is 0000, the Carry Flag will be turned ON when a digit changes from F to 0, and the Negative Flag will be turned ON when bit 15 of Wd is ON in the result. Both the Equals Flag and the Carry Flag will be turned ON when the content of Wd changes from FFFF to 0000. Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label Operation ER OFF = ON if the content of Wd is 0000 after execution. OFF in all other cases. CY ON if a digit in Wd went from F to 0 during execution. OFF in all other cases. N ON if bit 15 of Wd is ON after execution. OFF in all other cases.

Examples

Operation of ++(590) In the following example, the content of D100 will be incremented by 1 every cycle as long as CIO 0.00 is ON.
0.00

D100

Incremented every cycle while CIO 0.00 is ON. Wd: D100

0 0 1 9

Wd: D100
0 0 1 A

: Execution of ++(590)

CIO 0.00

Increment Increment

Increment Increment

321

Increment/Decrement Instructions
Operation of @++(590)

Section 3-9

The up-differentiated variation is used in the following example, so the content of D100 will be incremented by 1 only when CIO 0.00 has gone from OFF to ON.
0.00

@++ D100 Wd: D100

0 0 1 9

Incremented only for up-differentiation. Wd: D100

0 0 1 A

: Execution of @++(590)

CIO 0.00

Increment

Increment

3-9-2
Purpose

DOUBLE INCREMENT BINARY: ++L(591)

Increments the 8-digit hexadecimal content of the specified words by 1.

Ladder Symbol
++L(591) Wd Wd: First word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ++L(591) @++L(591) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Wd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 -----

322

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd IR0 to IR15 ,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The ++L(591) instruction adds 1 to the 8-digit hexadecimal content of Wd+1 and Wd. The content of the specified words will be incremented by 1 every cycle as long as the execution condition of ++L(591) is ON. When the up-differentiated variation of this instruction (@++L(591)) is used, the content of the specified words is incremented only when the execution condition has gone from OFF to ON.
Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000, the Carry Flag will be turned ON when a digit changes from F to 0, and the Negative Flag will be turned ON if bit 15 of Wd+1 is ON in the result. Both the Equals Flag and the Carry Flag will be turned ON when the content of changes from FFFF FFFF to 0000 0000. Flags
Name Error Flag Equals Flag Carry Flag Label ER = CY Operation OFF ON if the result is 0000 0000 after execution. OFF in all other cases. ON if a digit in Wd+1 or Wd went from F to 0 during execution. OFF in all other cases. ON if bit 15 of Wd+1 is ON after execution. OFF in all other cases.

Negative Flag

Examples

Operation of ++L(591) In the following example, the 8-digit hexadecimal content of D101 and D100 will be incremented by 1 every cycle as long as CIO 0.00 is ON.
0.00

Incremented every cycle while CIO 0.00 is ON. D100 Wd+1: D101 Wd: D100 Wd+1: D101 Wd: D100

: Execution of ++L(591)

CIO 0.00

Increment

Increment

Increment Increment

323

Increment/Decrement Instructions
Operation of @++L(591)

Section 3-9

The up-differentiated variation is used in the following example, so the content of D101 and D100 will be incremented by 1 only when CIO 0.00 has gone from OFF to ON.
0.00

@++L D100 Wd+1: D101

Incremented only for up-differentiation. Wd: D100 Wd+1: D101 Wd: D100

: Execution of @++L(591)

CIO 0.00

Increment

Increment

3-9-3
Purpose

DECREMENT BINARY: (592)

Decrements the 4-digit hexadecimal content of the specified word by 1.

Ladder Symbol
(592)

Wd

Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification (592) @ (592) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Wd CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15

324

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The (592) instruction subtracts 1 from the binary content of Wd. The specified word will be decremented by 1 every cycle as long as the execution condition of (592) is ON. When the up-differentiated variation of this instruction (@ (592)) is used, the specified word is decremented only when the execution condition has gone from OFF to ON.
Wd Wd

The Equals Flag will be turned ON if the result is 0000, the Carry Flag will be turned ON when a digit changes from 0 to F, and the Negative Flag will be turned ON if bit 15 of Wd is ON in the result. Both the Carry Flag and the Negative Flag will be turned ON when the content of Wd changes from 0000 to FFFF. Flags
Name Error Flag Equals Flag Carry Flag Negative Flag Label ER = CY N Operation OFF ON if the content of Wd is 0000 after execution. OFF in all other cases. ON if a digit in Wd went from 0 to F during execution. OFF in all other cases. ON if bit 15 of Wd is ON after execution. OFF in all other cases.

Examples

Operation of (592) In the following example, the content of D100 will be decremented by 1 every cycle as long as CIO 0.00 is ON.
0.00 D100

Decremented every cycle while CIO 0.00 is ON. Wd: D100 1 Wd: D100

: Execution of (592)

CIO 0.00

Decrement Decrement Decrement Decrement

325

Increment/Decrement Instructions
Operation of @ (592)

Section 3-9

The up-differentiated variation is used in the following example, so the content of D100 will be decremented by 1 only when CIO 0.00 has gone from OFF to ON.
0.00

@
D100

Decremented only for up-differentiation. Wd: D100 1 Wd: D100

: Execution of @ (592)

CIO 0.00

Decrement

Decrement

3-9-4
Purpose

DOUBLE DECREMENT BINARY: L(593)

Decrements the 8-digit hexadecimal content of the specified words by 1.

Ladder Symbol
L(593)

Wd

Wd: First word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification L(593) @ L(593) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Wd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 -----

326

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The L(593) instruction subtracts 1 from the 8-digit hexadecimal content of Wd+1 and Wd. The content of the specified words will be decremented by 1 every cycle as long as the execution condition of L(593) is ON. When the up-differentiated variation of this instruction (@ L(593)) is used, the content of the specified words is decremented only when the execution condition has gone from OFF to ON.
Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000, the Carry Flag will be turned ON when a digit changes from 0 to F, and the Negative Flag will be turned ON if bit 15 of Wd+1 is ON in the result. Both the Carry Flag and the Negative Flag will be turned ON when the content changes from 0000 0000 to FFFF FFFF. Flags
Name Error Flag Equals Flag Carry Flag Label ER = CY Operation OFF ON if the result is 0000 0000 after execution. OFF in all other cases. ON if a digit in Wd+1 or Wd went from 0 to F during execution. OFF in all other cases. ON if bit 15 of Wd+1 is ON after execution. OFF in all other cases.

Negative Flag

Examples

Operation of L(593) In the following example, the 8-digit hexadecimal content of D201 and D200 will be decremented by 1 every cycle as long as CIO 0.01 is ON.
0.01 D200

Decremented every cycle while CIO 0.01 is ON. Wd+1: D201 Wd: D200 1 : Execution of L(593) Wd+1: D201 Wd: D200

0.01

Decrement Decrement Decrement Decrement

327

Increment/Decrement Instructions
Operation of @ L(593)

Section 3-9

The up-differentiated variation is used in the following example, so the content of D201 and D200 will be decremented by 1 only when CIO 0.01 has gone from OFF to ON.
0.01

Decremented only for up-differentiation. @ L D200 Wd+1: D201 Wd: D200 1 : Execution of @ L(593) Wd+1: D201 Wd: D200

0.01

Decrement

Decrement

3-9-5
Purpose

INCREMENT BCD: ++B(594)

Increments the 4-digit BCD content of the specified word by 1.

Ladder Symbol
++B(594) Wd Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ++B(594) @++B(594) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in BCD Indirect DM addresses in BCD Constants Data Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 Wd

328

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The ++B(594) instruction adds 1 to the BCD content of Wd. The specified word will be incremented by 1 every cycle as long as the execution condition of ++B(594) is ON. When the up-differentiated variation of this instruction (@++B(594)) is used, the specified word is incremented only when the execution condition has gone from OFF to ON.
Wd Wd

The Equals Flag will be turned ON if the result is 0000 and the Carry Flag will be turned ON when a digit changes from 9 to 0. Both the Equals Flag and the Carry Flag will be turned ON when the content of Wd changes from 9999 to 0000. Flags
Name Error Flag Equals Flag Carry Flag Label ER = CY Operation ON if the content of Wd is not BCD. OFF in all other cases. ON if the content of Wd is 0000 after execution. OFF in all other cases. ON if a digit in Wd went from 9 to 0 during execution. OFF in all other cases.

Precautions Examples

The content of Wd must be BCD. If it is not BCD, an error will occur and the Error Flag will be turned ON. Operation of ++B(594) In the following example, the BCD content of D100 will be incremented by 1 every cycle as long as CIO 0.00 is ON.
0.00 D100

Incremented every cycle while CIO 0.00 is ON. Wd: D100 Wd: D100

: Execution of ++B(594)

CIO 0.00

Increment Increment

Increment Increment

329

Increment/Decrement Instructions
Operation of @++B(594)

Section 3-9

The up-differentiated variation is used in the following example, so the content of D100 will be incremented by 1 only when CIO 0.00 has gone from OFF to ON.
0.00

@++B D100

Incremented only for up-differentiation. Wd: D100 Wd: D100

: Execution of @++B(594)

CIO 0.00

Increment

Increment

3-9-6
Purpose

DOUBLE INCREMENT BCD: ++BL(595)

Increments the 8-digit BCD content of the specified words by 1.

Ladder Symbol
++BL(595) Wd Wd: First word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ++BL(595) @++BL(595) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in BCD Indirect DM addresses in BCD Constants Data Registers CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ----Wd

330

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The ++BL(595) instruction adds 1 to the 8-digit BCD content of Wd+1 and Wd. The content of the specified words will be incremented by 1 every cycle as long as the execution condition of ++BL(595) is ON. When the up-differentiated variation of this instruction (@++BL(595)) is used, the content of the specified words is incremented only when the execution condition has gone from OFF to ON.
Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000 and the Carry Flag will be turned ON when a digit changes from 9 to 0. Both the Equals Flag and the Carry Flag will be turned ON when the content of changes from 9999 9999 to 0000 0000. Flags
Name Error Flag Equals Flag Carry Flag Label ER = CY Operation ON if the content of Wd+1 and Wd is not BCD. OFF in all other cases. ON if the result is 0000 0000 after execution. OFF in all other cases. ON if a digit in Wd+1 or Wd went from 9 to 0 during execution. OFF in all other cases.

Precautions Examples

The content of Wd+1 and Wd must be BCD. If it is not BCD, an error will occur and the Error Flag will be turned ON. Operation of ++BL(595) In the following example, the 8-digit BCD content of D201 and D200 will be incremented by 1 every cycle as long as CIO 0.01 is ON.
0.01 D200

Incremented every cycle while CIO 0.01 is ON. Wd+1: D201 Wd: D200 Wd+1: D201 Wd: D200

: Execution of ++BL(595)

CIO 0.01

Increment Increment

Increment Increment

331

Increment/Decrement Instructions
Operation of @++BL(595)

Section 3-9

The up-differentiated variation is used in the following example, so the BCD content of D201 and D200 will be incremented by 1 only when CIO 0.01 has gone from OFF to ON.
0.01

@++BL D200

Incremented only for up-differentiation. Wd+1: D201 Wd: D200 Wd+1: D201 Wd: D200

: Execution of @++BL(595)

CIO 0.01

Increment

Increment

3-9-7
Purpose

DECREMENT BCD: B(596)

Decrements the 4-digit BCD content of the specified word by 1.

Ladder Symbol
B(596)

Wd

Wd: Word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification B(596) @ B(596) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in BCD Indirect DM addresses in BCD Constants Data Registers Wd CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15

332

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The B(596) instruction subtracts 1 from the BCD content of Wd. The specified word will be decremented by 1 every cycle as long as the execution condition of B(596) is ON. When the up-differentiated variation of this instruction (@ B(596)) is used, the specified word is decremented only when the execution condition has gone from OFF to ON.
Wd 1 Wd

The Equals Flag will be turned ON if the result is 0000 and the Carry Flag will be turned ON when a digit changes from 0 to 9. Flags
Name Error Flag Equals Flag Carry Flag Label ER = CY Operation ON if the content of Wd is not BCD. OFF in all other cases. ON if the content of Wd is 0000 after execution. OFF in all other cases. ON if a digit in Wd went from 0 to 9 during execution. OFF in all other cases.

Precautions Examples

The content of Wd must be BCD. If it is not BCD, an error will occur and the Error Flag will be turned ON. Operation of B(596) In the following example, the BCD content of D1000 will be decremented by 1 every cycle as long as CIO 0.00 is ON.
0.00 D1000

Decremented every cycle while CIO 0.00 is ON. Wd: D1000 1 : Execution of B(596) Wd: D1000

CIO 0.00

Decrement Decrement Decrement Decrement

333

Increment/Decrement Instructions
Operation of @ B(596)

Section 3-9

The up-differentiated variation is used in the following example, so the BCD content of D1000 will be decremented by 1 only when CIO 0.00 has gone from OFF to ON.
0.00

@ B
D1000

Decremented only for up-differentiation. Wd: D1000 Wd: D1000 1

: Execution of @ B(596)

CIO 0.00

Decrement

Decrement

3-9-8
Purpose

DOUBLE DECREMENT BCD: BL(597)

Decrements the 8-digit BCD content of the specified words by 1.

Ladder Symbol
BL(597)

Wd

Wd: First word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BL(597) @ BL(597) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in BCD Indirect DM addresses in BCD Constants Data Registers CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ----Wd

334

Increment/Decrement Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-9
Wd --,IR0 to ,IR15 2048 to +2047, IR0 to 2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

The BL(597) instruction subtracts 1 from the 8-digit BCD content of Wd+1 and Wd. The content of the specified words will be decremented by 1 every cycle as long as the execution condition of BL(597) is ON. When the updifferentiated variation of this instruction (@ BL(597)) is used, the content of the specified words is decremented only when the execution condition has gone from OFF to ON.
Wd+1 Wd Wd+1 Wd

The Equals Flag will be turned ON if the result is 0000 0000 and the Carry Flag will be turned ON when a digit changes from 0 to 9. Flags
Name Error Flag Equals Flag Carry Flag Label ER = CY Operation ON if the content of Wd+1 and Wd is not BCD. OFF in all other cases. ON if the result is 0000 0000 after execution. OFF in all other cases. ON if a digit in Wd+1 or Wd went from 0 to 9 during execution. OFF in all other cases.

Precautions Examples

The content of Wd+1 and Wd must be BCD. If it is not BCD, an error will occur and the Error Flag will be turned ON. Operation of BL(597) In the following example, the 8-digit BCD content of D2001 and D2000 will be decremented by 1 every cycle as long as CIO 0.01 is ON.
0.01 D2000

Decremented every cycle while CIO 0.01 is ON. Wd+1: D2001 Wd: D2000
0 0 0 0

Wd+1: D2001 1
0 0 0 0

Wd: D2000

: Execution of BL(597)

CIO 0.01

Decrement Decrement

Decrement Decrement

335

Symbol Math Instructions

Operation of @ BL(597)

Section 3-10

The up-differentiated variation is used in the following example, so the BCD content of D2001 and D2000 will be decremented by 1 only when CIO 0.01 has gone from OFF to ON.
0.01

Decremented only for up-differentiation. @ BL D2000 Wd+1: D2001 Wd: D2000 1 : Execution of @ BL(597) Wd+1: D2001 Wd: D2000

CIO 0.01

Decrement

Decrement

3-10 Symbol Math Instructions

This section describes the Symbol Math Instructions, which perform arithmetic operations on BCD or binary data.
Instruction SIGNED BINARY ADD WITHOUT CARRY DOUBLE SIGNED BINARY ADD WITHOUT CARRY SIGNED BINARY ADD WITH CARRY DOUBLE SIGNED BINARY ADD WITH CARRY BCD ADD WITHOUT CARRY DOUBLE BCD ADD WITHOUT CARRY BCD ADD WITH CARRY DOUBLE BCD ADD WITH CARRY SIGNED BINARY SUBTRACT WITHOUT CARRY DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY SIGNED BINARY SUBTRACT WITH CARRY DOUBLE SIGNED BINARY SUBTRACT WITH CARRY BCD SUBTRACT WITHOUT CARRY DOUBLE BCD SUBTRACT WITHOUT CARRY BCD SUBTRACT WITH CARRY DOUBLE BCD SUBTRACT WITH CARRY SIGNED BINARY MULTIPLY Mnemonic + +L +C +CL +B +BL +BC +BCL L C CL B BL BC BCL * Function code 400 401 402 403 404 405 406 407 410 411 412 413 414 415 416 417 420 Page 337 339 341 343 345 346 348 349 351 353 357 359 361 363 366 367 369

336

Symbol Math Instructions

Instruction DOUBLE SIGNED BINARY MULTIPLY UNSIGNED BINARY MULTIPLY DOUBLE UNSIGNED BINARY MULTIPLY BCD MULTIPLY DOUBLE BCD MULTIPLY SIGNED BINARY DIVIDE DOUBLE SIGNED BINARY DIVIDE UNSIGNED BINARY DIVIDE DOUBLE UNSIGNED BINARY DIVIDE BCD DIVIDE DOUBLE BCD DIVIDE Mnemonic *L *U *UL *B *BL / /L /U /UL /B /BL

Section 3-10
Function code 421 422 423 424 425 430 431 432 433 434 435 Page 371 372 374 375 377 378 380 382 384 385 387

3-10-1 SIGNED BINARY ADD WITHOUT CARRY: +(400)

Purpose Ladder Symbol
+(400) Au Ad R Au: Augend word Ad: Addend word R: Result word

Adds 4-digit (single-word) hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +(400) @+(400) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Au CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 Ad R

A448 to A959

337

Symbol Math Instructions

Area Constants

Section 3-10
Au Ad #0000 to #FFFF (binary) --&0 to &65535 (unsigned decimal) 32768 to 0 to 32767 (signed decimal) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Data Registers Index Registers Indirect addressing using Index Registers

Description

+(400) adds the binary values in Au and Ad and outputs the result to R.
Au + CY will turn ON when there is a carry. CY Ad R (Signed binary) (Signed binary)

(Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases. ON when the result of adding two positive numbers is in the range 8000 to FFFF hex. OFF in all other cases. ON when the result of adding two negative numbers is in the range 0000 to 7FFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When +(400) is executed, the Error Flag will turn OFF. If as a result of the addition, the content of R is 0000 hex, the Equals Flag will turn ON. If the addition results in a carry, the Carry Flag will turn ON. If the result of adding two positive numbers is negative (in the range 8000 to FFFF hex), the Overflow Flag will turn ON. If the result of adding two negative numbers is positive (in the range 0000 to 7FFF hex), the Underflow Flag will turn ON. If as a result of the addition, the content of the leftmost bit of R is 1, the Negative Flag will turn ON.

338

Symbol Math Instructions

Examples

Section 3-10
When CIO 0.00 is ON in the following example, D100 and D110 will be added as 4-digit signed binary values and the result will be output to D120.
0.00 D100 D110 D120

3-10-2 DOUBLE SIGNED BINARY ADD WITHOUT CARRY: +L(401)

Purpose Ladder Symbol
+L(401) Au Ad R Au: 1st augend word Ad: 1st addend word R: 1st result word

Adds 8-digit (double-word) hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +L(401) @+L(401) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Au CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) &0 to &4294967295 (unsigned decimal) 2147483648 to 2147483647 (signed decimal) ----Ad R

A448 to A958

Data Registers

339

Symbol Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-10
Au Ad IR0 to IR15 ,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

+L(401) adds the binary values in Au and Au+1 and Ad and Ad+1 and outputs the result to R.
Au+1 Au Ad R (Signed binary) (Signed binary)

+
CY will turn ON when there is a carry. CY

Ad+1 R+1

(Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases. ON when the result of adding two positive numbers is in the range 00000000 to 7FFFFFFF hex. OFF in all other cases. ON when the result of adding two negative numbers is in the range 00000000 to 7FFFFFFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When +L(401) is executed, the Error Flag will turn OFF. If as a result of the addition, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If the addition results in a carry, the Carry Flag will turn ON. If the result of adding two positive numbers is negative (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will turn ON. If the result of adding two negative numbers is positive (in the range 00000000 to 7FFFFFFF hex), the Underflow Flag will turn ON. If as a result of the addition, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.01 is ON, D200 and D201 and D211 and D210 will be added as 8-digit signed binary values and the result will be output to D221 and D220.
0.01 D200 D210 D220

340

Symbol Math Instructions

Section 3-10

3-10-3 SIGNED BINARY ADD WITH CARRY: +C(402)

Purpose Ladder Symbol
+C(402) Au Ad R Au: Augend word Ad: Addend word R: Result word

Adds 4-digit (single-word) hexadecimal data and/or constants with the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +C(402) @+C(402) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Au CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) --&0 to &65535 (unsigned decimal) 32768 to 0 to 32767 (signed decimal) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Ad R

A448 to A959

Data Registers Index Registers Indirect addressing using Index Registers

341

Symbol Math Instructions

Description

Section 3-10
+C(402) adds the binary values in Au, Ad, and CY and outputs the result to R.
Au Ad + CY will turn ON when there is a carry. CY R CY (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the addition result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases. ON when the addition result of adding two positive numbers and CY is in the range 8000 to FFFF hex. OFF in all other cases. ON when the addition result of adding two negative numbers and CY is in the range 0000 to 7FFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When +C(402) is executed, the Error Flag will turn OFF. If as a result of the addition, the content of R is 0000 hex, the Equals Flag will turn ON. If the addition results in a carry, the Carry Flag will turn ON. If the result of adding two positive numbers and CY is negative (in the range 8000 to FFFF hex), the Overflow Flag will turn ON. If the result of adding two negative numbers and CY is positive (in the range 0000 to 7FFF hex), the Underflow Flag will turn ON. If as a result of the addition, the content of the leftmost bit of R is 1, the Negative Flag will turn ON. Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.00 is ON, D200, D210, and CY will be added as 4-digit signed binary values and the result will be output to D220.
0.00 D200 D210 D220

Examples

342

Symbol Math Instructions

Section 3-10

3-10-4 DOUBLE SIGNED BINARY ADD WITH CARRY: +CL(403)

Purpose Ladder Symbol
+CL(403) Au Ad R Au: 1st augend word Ad: 1st addend word R: 1st result word

Adds 8-digit (double-word) hexadecimal data and/or constants with the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +CL(403) @+CL(403) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Au CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) --&0 to &4294967295 (unsigned decimal) 2147483648 to 2147483647 (signed decimal) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Ad R

A448 to A958

Data Registers Index Registers Indirect addressing using Index Registers

343

Symbol Math Instructions

Description

Section 3-10
+CL(403) adds the binary values in Au and Au+1, Ad and Ad+1, and CY and outputs the result to R.
Au+1 Ad+1 + CY will turn ON when there is a carry. CY R+1 R Au Ad CY (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the result is 0. OFF in all other cases. ON when the results in a carry. OFF in all other cases. ON when the result of adding two positive numbers and CY is in the range 80000000 to FFFFFFFF hex. OFF in all other cases. ON when the result of adding two negative numbers and CY is in the range 00000000 to 7FFFFFFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When +CL(403) is executed, the Error Flag will turn OFF. If as a result of the addition, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If the addition results in a carry, the Carry Flag will turn ON. If the result of adding two positive numbers and CY is negative (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will turn ON. If the result of adding two negative numbers and CY is positive (in the range 00000000 to 7FFFFFFF hex), the Underflow Flag will turn ON. If as a result of the addition, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON. Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.01 is ON, D1001, D1000, D1011, D1010, and CY will be added as 8-digit signed binary values, and the result will be output to D2001 and D2000.
0.01 D1000 D1010 D2000

Examples

344

Symbol Math Instructions

Section 3-10

3-10-5 BCD ADD WITHOUT CARRY: +B(404)

Purpose Ladder Symbol
+B(404) Au Ad R Au: Augend word Ad: Addend word R: Result word

Adds 4-digit (single-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +B(404) @+B(404) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Au CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 0000 to 9999 (BCD) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Ad R

A448 to A959

Description

+B(404) adds the BCD values in Au and Ad and outputs the result to R.
Au + CY will turn ON when there is a carry. CY Ad R (BCD) (BCD)

(BCD)

345

Symbol Math Instructions

Flags
Name Error Flag Label ER Operation ON when Au is not BCD. ON when Ad is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases.

Section 3-10

Equals Flag Carry Flag

= CY

Precautions

If Au or Ad is not BCD, an error is generated and the Error Flag will turn ON. If as a result of the addition, the content of R is 0000 hex, the Equals Flag will turn ON. If an addition results in a carry, the Carry Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D100 and D110 will be added as 4-digit BCD values, and the result will be output to D120.
0.00 D100 D110 D120

3-10-6 DOUBLE BCD ADD WITHOUT CARRY: +BL(405)

Purpose Ladder Symbol
+BL(405) Au Ad R Au: 1st augend word Ad: 1st addend word R: 1st result word

Adds 8-digit (double-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +BL(405) @+BL(405) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area Au CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 Ad R

A448 to A958

346

Symbol Math Instructions

Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Au D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 Ad

Section 3-10
R

#00000000 to #99999999 (BCD) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

+BL(405) adds the BCD values in Au and Au+1 and Ad and Ad+1 and outputs the result to R, R+1.
Au+1 Au Ad R (BCD) (BCD) (BCD)

+
CY will turn ON when there is a carry. CY

Ad+1 R+1

Flags
Name Error Flag Label ER Operation ON when Au, Au +1 is not BCD. ON when Ad, Ad +1 is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases.

Equals Flag Carry Flag

= CY

Precautions

If Au, Au +1 or Ad, Ad +1 are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the addition, the content of R, R +1 is 00000000 hex, the Equals Flag will turn ON. If an addition results in a carry, the Carry Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D1001 and D1000 and D1101 and D1100 will be added as 8-digit BCD values, and the result will be output to D1201 and D1200.
0.01 D1000 D1100 D1200

347

Symbol Math Instructions

Section 3-10

3-10-7 BCD ADD WITH CARRY: +BC(406)

Purpose Ladder Symbol
+BC(406) Au Ad R Au: Augend word Ad: Addend word R: Result word

Adds 4-digit (single-word) BCD data and/or constants with the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +BC(406) @+BC(406) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Au CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to 9999 (BCD) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Ad R

A448 to A959

Description

+BC(406) adds BCD values in Au, Ad, and CY and outputs the result to R.
Au Ad + CY will turn ON when there is a carry. CY R CY (BCD) (BCD) (BCD)

348

Symbol Math Instructions

Flags
Name Error Flag Label ER Operation ON when Au is not BCD. ON when Ad is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases.

Section 3-10

Equals Flag Carry Flag

= CY

Precautions

If Au or Ad is not BCD, an error is generated and the Error Flag will turn ON. If as a result of the addition, the content of R is 0000 hex, the Equals Flag will turn ON. If an addition results in a carry, the Carry Flag will turn ON. Note To clear the Carry Flay (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.00 is ON in the following example, D100, D200, and CY will be added as 4-digit BCD values, and the result will be output to D300.
0.00 D100 D200 D300

Examples

3-10-8 DOUBLE BCD ADD WITH CARRY: +BCL(407)

Purpose Ladder Symbol
+BCL(407) Au Ad R Au: 1st augend word Ad: 1st addend word R: 1st result word

Adds 8-digit (double-word) BCD data and/or constants with the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +BCL(407) @+BCL(407) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Au CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 Ad R

A448 to A958

349

Symbol Math Instructions

Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Au T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 Ad

Section 3-10
R

#00000000 to #99999999 (BCD) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

+BCL(407) adds the BCD values in Au and Au+1, Ad and Ad+1, and CY and outputs the result to R, R+1.
Au+1 Ad+1 + CY will turn ON when there is a carry. CY R+1 R Au Ad CY (BCD) (BCD) (BCD)

Flags
Name Error Flag Label ER Operation ON when Au, Au +1 is not BCD. ON when Ad, Ad +1 is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the addition results in a carry. OFF in all other cases.

Equals Flag Carry Flag

= CY

Precautions

If Au, Au +1 or Ad, Ad +1 are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the addition, the content of R, R +1 is 00000000 hex, the Equals Flag will turn ON. If an addition results in a carry, the Carry Flag will turn ON. Note To clear the Carry Flay (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.01 is ON in the following example, D1001, D1000, D1101, D1100, and CY will be added as 8-digit BCD values, and the result will be output to D1201 and D1200.
0.01 D1000 D1100 D1200

Examples

350

Symbol Math Instructions

Section 3-10

3-10-9 SIGNED BINARY SUBTRACT WITHOUT CARRY: (410)

Purpose Ladder Symbol
(410)

Subtracts 4-digit (single-word) hexadecimal data and/or constants.

Mi Su R

Mi: Minuend word Su: Subtrahend word R: Result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification (410) @(410) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Mi CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D4095 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) --&0 to &65535 (unsigned decimal) 32768 to 32767 (signed decimal) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Su R

A448 to A959

Data Registers Index Registers Indirect addressing using Index Registers

351

Symbol Math Instructions

Description

Section 3-10
(400) subtracts the binary values in Su from Mi and outputs the result to R. When the result is negative, it is output to R as a 2s complement. (Refer to 310-10 DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY: L(411) for an example of handling 2s complements.)
Mi CY will turn ON when there is a borrow. CY Su R (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases. ON when the result of subtracting a negative number from a positive number is in the range 8000 to FFFF hex. OFF in all other cases. ON when the result of subtracting a negative number from a positive number is in the range 0000 to 7FFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When (410) is executed, the Error Flag will turn OFF. If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag will turn ON. If the subtraction results in a borrow, the Carry Flag will turn ON. If the result of subtracting a negative number from a positive number is negative (in the range 8000 to FFFF hex), the Overflow Flag will turn ON. If the result of subtracting a positive number from a negative number is positive (in the range 0000 to 7FFF hex), the Underflow Flag will turn ON. If as a result of the subtraction, the content of the leftmost bit of R is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D200 will be subtracted from D100 as 4-digit signed binary values and the result will be output to D300.
0.00

D100 D200 D300

352

Symbol Math Instructions

Section 3-10

3-10-10 DOUBLE SIGNED BINARY SUBTRACT WITHOUT CARRY: L(411)

Purpose Ladder Symbol
L(411)

Subtracts 8-digit (double-word) hexadecimal data and/or constants.

Mi Su R

Mi: Minuend word Su: Subtrahend word R: Result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification L(411) @L(411) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Mi CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) --&0 to &4294967295 (unsigned decimal) 2147483648 to 2147483647 (signed decimal) --IR0 to IR15 ,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Su R

A448 to A958

Data Registers Index Registers Indirect addressing using Index Registers

353

Symbol Math Instructions

Description

Section 3-10
L(411) subtracts the binary values in Su and Su+1 from Mi and Mi+1 and outputs the result to R, R+1. When the result is negative, it is output to R and R+1 as a 2s complement.
Mi+1 CY will turn ON when there is a borrow. CY Su+1 R+1 Mi Su R (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases. ON when the result of subtracting a negative number from a positive number is in the range 80000000 to FFFFFFFF hex. OFF in all other cases. ON when the result of subtracting a positive number from a negative number is in the range 00000000 to 7FFFFFFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When L(411) is executed, the Error Flag will turn OFF. If as a result of the subtraction, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If the subtraction results in a borrow, the Carry Flag will turn ON. If the result of subtracting a negative number from a positive number is negative (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will turn ON. If the result of subtracting a positive number from a negative number is positive (in the range 00000000 to 7FFFFFFF hex), the Underflow Flag will turn ON. If as a result of the subtraction, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D1201 and D1200 will be subtracted from D1001 and D1000 as 8-digit signed binary values and the result will be output to D1501 and D1500.
0.01

L D1000 D1200 D1500

354

Symbol Math Instructions

Examples

Section 3-10
If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi <Su+1, Su), the result is output as the 2s complement and the Carry Flag (CY) will turn ON to indicate that the result of the subtraction is negative. To convert the 2s complement to the true number, an instruction which subtracts the result from 0 is necessary using the Carry Flag (CY) as an execution condition.

Note

2s Complement A 2s complement is the value obtained by subtracting each binary digit from 1 and adding one to the result. For example, the 2s complement for 1101 is calculated as follows: 1111 (F hexadecimal) 1101 (D hexadecimal) + 1 (1 hexadecimal) = 0011 (3 hexadecimal). The 2s complement for 3039 (hexadecimal) is calculated as follows: FFFF (hexadecimal) 3039 (hexadecimal) + 0001 (hexadecimal) CFC7 (hexadecimal). Therefore, in case of 4-digit hexadecimal value, the 2s complement can be calculated as follows: FFFF (hexadecimal) a (hexadecimal) + 0001 (hexadecimal) = b (hexadecimal). To obtain the true number from the 2s complement b (hexadecimal): a (hexadecimal) = 10000 (hexadecimal) b (hexadecimal). For example, to obtain the true number from the 2s complement CFC7 (hexadecimal): 10000 (hexadecimal) CFC7 (hexadecimal) = 3039 (hexadecimal).
Unsigned data

Example 1

Signed data

FFFF Hex ) 0001 Hex FFFE Hex Negative Flag ON Carry Flag OFF

1 +1 2 Note 1

65535 1 65534 Note 2

Note

1. Since the Negative Flag is ON, the result (FFFE hex) is a negative value (2's complement) and is thus 2. 2. Since the Carry Flag is OFF, the result (FFFE hex) is an unsigned positive value of 65534.

Example 2 FFFD Hex ) FFFF Hex FFFE Hex Negative Flag ON Carry Flag OFF

Signed data 3 1 2 Note 3

Unsigned data 65533 ) 65535 65534 Note 4

3. Since the Negative Flag is ON, the result (FFFE hex) is a negative value (2's complement) and is thus 2. 4. Since the Carry Flag is ON, the result (FFFE hex) is a negative value (2's complement) and becomes 2 when converted to a true value.

Program Example

20F55A10 B8A360E3 = 97AE06D3. In this example, the eight-digit binary value in CIO 211 and CIO 210 is subtracted from the value in CIO 201 and CIO 200, and the result is output in eight-digit binary to CIO 301 and CIO 300. If the result is negative, the instruction at (2) will be executed, and the actual result will then be output to CIO 301 and CIO 300.

355

Symbol Math Instructions

0.00 RSET 302.00 L 200 210 300 CY L #00000000 300 300 CY SET 302.00 ""display (2) (1)

Section 3-10

Subtraction at 1
Mi+1: CIO 201 2 0 F 5 Su+1: CIO 211 B 8 A 3 R+1: D301 6 8 5 1 Mi: CIO 200 5 A 1 0 Su: CIO 210 6 0 E 3 R+1: D300 F 9 2 D

CY 1

The Carry Flag (CY) is ON, so the result is subtracted from 0000 0000 to obtain the actual number.

Subtraction at 2
0 0 0 0 Su+1: CIO 301 6 8 5 1 0 0 0 0 Su: CIO 300 F 9 2 D

CY 1

R+1: CIO 301 R+1: CIO 300 9 7 A E 0 6 D 3

Final Subtraction Result

Mi+1: CIO 201 2 0 F 5 Su+1: CIO 211 B 8 5 1 Mi: CIO 200 5 A 1 0 Su: CIO210 6 0 E 3

CY 1

R+1: CIO 301 R+1: CIO 300 9 7 A E 0 6 D 3

The Carry Flag (CY) is turned ON, so the actual number is 97AE06D3. Because the content of CIO 301 and CIO 300 is negative, CY is used to turn ON CIO 302.00 to indicate this.

356

Symbol Math Instructions

Section 3-10

3-10-11 SIGNED BINARY SUBTRACT WITH CARRY: C(412)

Purpose Ladder Symbol
C(412)

Subtracts 4-digit (single-word) hexadecimal data and/or constants with the Carry Flag (CY).

Mi Su R

Mi: Minuend word Su: Subtrahend word R: Result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification C(412) @C(412) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Mi CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) --&0 to &65535 (unsigned decimal) 32768 to 0 to 32767 (signed decimal) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Su R

A448 to A959

Data Registers Index Registers Indirect addressing using Index Registers

357

Symbol Math Instructions

Description

Section 3-10
C(412) subtracts the binary values in Su and CY from Mi, and outputs the result to R. When the result is negative, it is output to R as a 2s complement.
Mi Su CY will turn ON when there is a borrow. CY R CY (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the subtraction result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases. ON when the result of subtracting a negative number and CY from a positive number is in the range 8000 to FFFF hex. OFF in all other cases. ON when the result of subtracting a positive number and CY from a negative number is in the range 0000 to 7FFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When C(412) is executed, the Error Flag will turn OFF. If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag will turn ON. If the subtraction results in a borrow, the Carry Flag will turn ON. If the result of subtracting a negative number and CY from a positive number is negative (in the range 8000 to FFFF hex), the Overflow Flag will turn ON. If the result of subtracting a positive number and CY from a negative number is positive (in the range 0000 to 7FFF hex), the Underflow Flag will turn ON. If as a result of the subtraction, the content of the leftmost bit of R is 1, the Negative Flag will turn ON. Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.00 is ON in the following example, D110 and CY will be subtracted from D100 as 4-digit signed binary values and the result will be output to D120.
0.00 D100 D110 D120

Examples

358

Symbol Math Instructions

Section 3-10

3-10-12 DOUBLE SIGNED BINARY SUBTRACT WITH CARRY: CL(413)

Purpose Ladder Symbol
CL(413) Mi Su R Mi: Minuend word Su: Subtrahend word R: Result word

Subtracts 8-digit (double-word) hexadecimal data and/or constants with the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification CL(413) @CL(413) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Mi CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) --&0 to &4294967295 (unsigned decimal) 2147483648 to 2147483647 (signed decimal) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Su R

A448 to A958

Data Registers Index Registers Indirect addressing using Index Registers

359

Symbol Math Instructions

Description

Section 3-10
CL(413) subtracts the binary values in Su and Su+1 and CY from Mi and Mi+1, and outputs the result to R, R+1. When the result is negative, it is output to R, R+1 as a 2s complement.
Mi+1 Su+1 CY will turn ON when there is a borrow. CY R+1 R Mi Su CY (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Carry Flag Overflow Flag Label ER = CY OF Operation OFF ON when the result is 0. OFF in all other cases. ON when the results in a borrow. OFF in all other cases. ON when the result of subtracting a negative number and CY from a positive number is in the range 80000000 to FFFFFFFF hex. OFF in all other cases. ON when the result of subtracting a positive number and CY from a negative number is in the range 00000000 to 7FFFFFFF hex. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Underflow Flag

UF

Negative Flag

Precautions

When CL(413) is executed, the Error Flag will turn OFF. If as a result of the subtraction, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If the subtraction results in a borrow, the Carry Flag will turn ON. If the result of subtracting a negative number and CY from a positive number is negative (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will turn ON. If the result of subtracting a positive number and CY from a negative number is positive (in the range 00000000 to 7FFFFFFF hex), the Underflow Flag will turn ON. If as a result of the subtraction, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON. Note To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.01 is ON in the following example, D1101, D1100 and CY will be subtracted from D1001 and D1000 as 8-digit signed binary values, and the result will be output to D1201 and D1200.
0.01 D1000 D1100 D1200

Examples

360

Symbol Math Instructions

Section 3-10
If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi <Su+1, Su), the result is output as a 2s complement. The Carry Flag (CY) will turn ON. To convert the 2s complement to the true number, a program which subtracts the result from 0 is necessary, as an input condition of the Carry Flag (CY). The Carry Flag turning ON thus indicates that the result of the subtraction is negative.

Note

2s Complement A 2s complement is the value obtained by subtracting each binary digit from 1 and adding one to the result. Example: The 2s complement for the binary number 1101 is as follows: 1111 (F hex) 1101 (D hex) + 1 (1 hex) = 0011 (3 hex). Example: The 2s complement for the 4-digit hexadecimal number 3039 is as follows: FFFF hex 3039 hex + 0001 hex = CFC7 hex. Accordingly, the 2s complement for the 4-digit hexadecimal value a is as follows: FFFF hex a hex + 0001 hex = b hex. And to obtain the true number a hex from the 2s complement b hex: a hex + 10000 hex b hex. Example: To obtain the true number from the 2s complement CFC& hex: 10000 hex CFC7 hex = 3039 hex.

3-10-13 BCD SUBTRACT WITHOUT CARRY: B(414)

Purpose Ladder Symbol
B(414) Mi Su R Mi: Minuend word Su: Subtrahend word R: Result word

Subtracts 4-digit (single-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification B(414) @B(414) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Mi CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 Su R

A448 to A959

361

Symbol Math Instructions

Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Mi @ D0 to @ D32767 *D0 to *D32767 Su

Section 3-10
R

0000 to 9999 (BCD) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

B(414) subtracts the BCD values in Su from Mi and outputs the result to R. If the result of the subtraction is negative, the result is output as a 10s complement.
Mi CY will turn ON when there is a borrow. CY Su R (BCD) (BCD) (BCD)

Flags
Name Error Flag Label ER Operation ON when Mi is not BCD. ON when Su is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases.

Equals Flag Carry Flag

= CY

Precautions

If Mi and/or Su are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag will turn ON. If an addition results in a borrow, the Carry Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D110 will be subtracted from D100 as 4-digit BCD values, and the result will be output to D120.
0.00 D100 D110 D120

362

Symbol Math Instructions

Section 3-10

3-10-14 DOUBLE BCD SUBTRACT WITHOUT CARRY: BL(415)

Purpose Ladder Symbol
BL(415) Mi Su R Mi: 1st minuend word Su: 1st subtrahend word R: 1st result word

Subtracts 8-digit (double-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BL(415) @BL(415) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Mi CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #99999999 (BCD) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Su R

A448 to A958

Description

BL(415) subtracts the BCD values in Su and Su+1 from Mi and Mi+1 and outputs the result to R, R+1. If the result is negative, it is output to R, R+1 as a 10s complement.
Mi +1 Mi Su R (BCD) (BCD)

CY will turn ON when there is a borrow. CY

Su+1 R+1

(BCD)

363

Symbol Math Instructions

Flags
Name Error Flag Label ER

Section 3-10

Equals Flag Carry Flag

= CY

Operation ON when Mi and/or Mi +1 are not BCD. ON when Su and/or Su +1 are not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases.

Precautions

If Mi, Mi +1 and/or Su, Su +1 are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the subtraction, the content of R, R +1 is 00000000 hex, the Equals Flag will turn ON. If an addition results in a borrow, the Carry Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D1001 and D1000 will be subtracted from D1101 and D1100 as 8-digit BCD values, and the result will be output to D1201 and D1200.
0.01 D1000 D1100 D1200

If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi <Su+1, Su), the result is output as a 10s complement. The Carry Flag (CY) will turn ON. To convert the 10s complement to the true number, a program which subtracts the result from 0 is necessary, as an input condition of the Carry Flag (CY). The Carry Flag turning ON thus indicates that the result of the subtraction is negative. Note 10s Complement A 10s complement is the value obtained by subtracting each digit from 9 and adding one to the result. For example, the 10s complement for 7556 is calculated as follows: 9999 7556 + 1 = 2444. For a four digit number, the 10s complement of A is 9999 A + 1 = B. To obtain the true number from the 10s complement B: A = 10000 B. For example, to obtain the true number from the 10s complement 2444: 10000 2444 = 7556. 9,583,960 17,072,641 = 7,488,681. In this example, the eight-digit BCD content of CIO 211 and CIO 210 is subtracted from the content of CIO 201 and CIO 200, and the result is output in eight-digit BCD to CIO 301 and CIO 300. The result is negative, so the instruction at (2) will be executed, and the true value will then be output to CIO 301 and CIO 300.

Program Example

364

Symbol Math Instructions

0.00 RSET 302.00 BL 200 210 300 CY BL #00000000 300 300 CY SET 302.00 "" display (2) (1)

Section 3-10

Subtraction at 1
Mi+1: CIO 201 0 9 5 8 Su+1: CIO 211 Mi: CIO 200 3 9 6 0 Su: CIO 210 2 6 4 1

1 7 0 7

09583960 + (100000000 17072641) CY R+1: CIO 301 R+1: CIO 300 1 9 2 5 1 1 3 1 9

The Carry Flag (CY) is ON, so the result is subtracted from 0000 0000.

Subtraction at 2
0 0 0 0 Su+1: CIO 301 0 0 0 0 Su: CIO 300 1 3 1 9

9 2 5 1

00000000 + (100000000 92511319) CY R+1: CIO 301 R+1: CIO 300 1 0 7 4 8 8 6 8 1

Final Subtraction Result

Mi+1: CIO 201 2 0 F 5 Su+1: CIO 211 Mi: CIO 200 5 A 1 0 Su: CIO 210 F 9 2 D

CY 1

6 8 5 1

R+1: CIO 301 R+1: CIO 300

0 7 4 8

8 6 8 1

The Carry Flag (CY) will be turned ON, so the actual number is 7,488,681. Because the content of CIO 301 and CIO 300 is negative, CY is used to turn ON CIO 302.00 to indicate this.

365

Symbol Math Instructions

Section 3-10

3-10-15 BCD SUBTRACT WITH CARRY: BC(416)

Purpose Ladder Symbol
BC(416) Mi Su R Mi: Minuend word Su: Subtrahend word R: Result word

Subtracts 4-digit (single-word) BCD data and/or constants with the Carry Flag (CY).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BC(416) @BC(416) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Mi CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #9999 (BCD) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Su R

A448 to A959

366

Symbol Math Instructions

Description

Section 3-10
BC(416) subtracts BCD values in Su and CY from Mi and outputs the result to R. If the result is negative, it is output to R as a 2s complement.
Mi Su CY will turn ON when there is a borrow. CY R CY (BCD) (BCD) (BCD)

Flags
Name Error Flag Label ER Operation ON when Mi is not BCD. ON when Su is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases.

Equals Flag Carry Flag

= CY

Precautions

If Mi and/or Su are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag will turn ON. If an addition results in a borrow, the Carry Flag will turn ON. Note To clear the Carry Flay (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.00 is ON in the following example, D110 and CY will be subtracted from D100 as 4-digit BCD values, and the result will be output to D120.
0.00 D100 D110 D120

Examples

3-10-16 DOUBLE BCD SUBTRACT WITH CARRY: BCL(417)

Purpose Ladder Symbol
BCL(417) Mi Su R Mi: 1st minuend word Su: 1st subtrahend word R: 1st result word

Subtracts 8-digit (double-word) BCD data and/or constants with the Carry Flag (CY).

367

Symbol Math Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-10

BCL(417) @BCL(417) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Mi CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #99999999 (BCD) ------Su R

A448 to A958

,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

BCL(417)subtracts the BCD values in Su, Su+1, and CY from Mi and Mi+1 and outputs the result to R, R+1. If the result is negative, it is output to R, R+1 as a 10s complement.
Mi +1 Su+1 CY will turn ON when there is a borrow. CY R+1 R Mi Su CY (BCD) (BCD) (BCD)

Flags
Name Error Flag Label ER Operation ON when Mi and/or Mi +1 are not BCD. ON when Su and/or Su +1 are not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases. ON when the subtraction results in a borrow. OFF in all other cases.

Equals Flag Carry Flag

= CY

368

Symbol Math Instructions

Precautions

Section 3-10
If Mi, Mi +1 and/or Su, Su +1 are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the subtraction, the content of R, R +1 is 00000000 hex, the Equals Flag will turn ON. If an subtraction results in a borrow, the Carry Flag will turn ON.

Note Examples

To clear the Carry Flag (CY), execute the Clear Carry (CLC(041)) instruction. When CIO 0.01 is ON in the following example, D1101, D1100, and CY will be subtracted from D1001 and D1000 as 8-digit BCD values, and the result will be output to D1201 and D1200.
0.01 D1000 D1100 D1200

If the result of the subtraction is a negative number (Mi<Su or Mi+1, Mi <Su+1, Su), the result is output as a 10s complement. The Carry Flag (CY) will turn ON. To convert the 10s complement to the true number, a program which subtracts the result from 0 is necessary, as an input condition of the Carry Flag (CY). The Carry Flag turning ON thus indicates that the result of the subtraction is negative. Note 10s Complement A 10s complement is the value obtained by subtracting each digit from 9 and adding one to the result. For example, the 10s complement for 7556 is calculated as follows: 9999 7556 + 1 = 2444. For a four digit number, the 10s complement of A is 9999 A + 1 = B. To obtain the true number from the 10s complement B: A = 10000 B. For example, to obtain the true number from the 10s complement 2444: 10000 2444 = 7556.

3-10-17 SIGNED BINARY MULTIPLY: *(420)

Purpose Ladder Symbol
*(420) Md Mr R Md: Multiplicand word Mr: Multiplier word R: Result word

Multiplies 4-digit signed hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition *(420) Executed Once for Upward Differentiation @*(420) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

369

Symbol Math Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Md CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 Mr

Section 3-10

R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

Data Registers Index Registers Indirect addressing using Index Registers

#0000 to #FFFF (binary) --&0 to &65535 (unsigned decimal) 32768 to 32767 (signed decimal) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

*(420) multiplies the signed binary values in Md and Mr and outputs the result to R, R+1.
Md R+1 Mr (Signed binary) (Signed binary) (Signed binary)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Precautions

When *(420) is executed, the Error Flag will turn OFF. If as a result of the multiplication, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the multiplication, the content of the leftmost bit of R+1 and R is 1, the Negative Flag will turn ON.

370

Symbol Math Instructions

Examples

Section 3-10
When CIO 0.00 is ON in the following example, D100 and D110 will be multiplied as 4-digit signed hexadecimal values and the result will be output to D121 and D120.
0.00 D100 D110 D120

3-10-18 DOUBLE SIGNED BINARY MULTIPLY: *L(421)

Purpose Ladder Symbol
*L(421) Md Mr R Md: 1st multiplicand word Mr: 1st multiplier word R: 1st result word

Multiplies 8-digit signed hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification *L(421) @*L(421) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Md CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) &0 to &4294967295 (unsigned decimal) 2147483648 to 0 to 2147483647 (signed decimal) ----Mr R CIO 0 to CIO 6140 W0 to W508 H0 to H508 A448 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764

Data Registers

371

Symbol Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-10
Md Mr --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

*L(421) multiplies the signed binary values in Md and Md+1 and Mr and Mr+1 and outputs the result to R, R+1, R+2, and R+3.
Md + 1 Mr + 1 Md Mr (Signed binary) (Signed binary)

R+3

R+2

R+1

(Signed binary)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Precautions

When *L(421) is executed, the Error Flag will turn OFF. If as a result of the multiplication, the content of R, R+1, R+2, R+3 is 0000 hex, the Equals Flag will turn ON. If as a result of the multiplication, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D201, D200 and D211, D210 will be multiplied as 8-digit signed hexadecimal values and the result will be output to D220 to D223.
0.01 D200 D210 D220

3-10-19 UNSIGNED BINARY MULTIPLY: *U(422)

Purpose Ladder Symbol
*U(422) Md Mr R Md: Multiplicand word Mr: Multiplier word R: Result word

Multiplies 4-digit unsigned hexadecimal data and/or constants.

372

Symbol Math Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-10

*U(422) @*U(422) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Md CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) --&0 to &65535 (unsigned decimal) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Mr R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

Description

*U(420) multiplies the binary values in Md and Mr and outputs the result to R, R+1.
Md R+1 Mr (Unsigned binary) (Unsigned binary)

(Unsigned binary)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Precautions

When *U(422) is executed, the Error Flag will turn OFF.

373

Symbol Math Instructions

Section 3-10
If as a result of the multiplication, the content of R, R+1 is 0000 hex, the Equals Flag will turn ON. If as a result of the multiplication, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D100 and D110 will be multiplied as 4-digit unsigned binary values and the result will be output to D121 and D120.
0.00 D100 D110 D120

3-10-20 DOUBLE UNSIGNED BINARY MULTIPLY: *UL(423)

Purpose Ladder Symbol
*UL(423) Md Mr R Md: 1st multiplicand word Mr: 1st multiplier word R: 1st result word

Multiplies 8-digit unsigned hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification *UL(423) @*UL(423) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Md CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) &0 to &4294967295 (unsigned decimal) ----Mr R CIO 0 to CIO 6140 W0 to W508 H0 to H508 A448 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764

Data Registers

374

Symbol Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-10
Md Mr --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

*UL(423) multiplies the unsigned binary values in Md and Md+1 and Mr and Mr+1 and outputs the result to R to R+3.
Md + 1 Mr + 1 Md Mr (Unsigned binary) (Unsigned binary)

R+3

R+2

R+1

(Unsigned binary)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of the result is 1. OFF in all other cases.

Precautions

When *UL(423) is executed, the Error Flag will turn OFF. If as a result of the multiplication, the content of R to R+3 is 0000 hex, the Equals Flag will turn ON. If as a result of the multiplication, the content of the leftmost bit of R to R+3 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D201, 200, D211, and D210 will be multiplied as 8-digit unsigned binary values and the result will be output to D220 to D223.
0.01 D200 D210 D220

3-10-21 BCD MULTIPLY: *B(424)

Purpose Ladder Symbol
*B(424) Md Mr R Md: Multiplicand word Mr: Multiplier word R: Result word

Multiplies 4-digit (single-word) BCD data and/or constants.

375

Symbol Math Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-10

*B(424) @*B(424) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Md CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #9999 (BCD) --DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Mr R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

Description

*B(424) multiplies the BCD content of Md and Mr and outputs the result to R, R+1.
Md R+1 Mr (BCD) (BCD)

(BCD)

Flags
Name Error Flag Label ER Operation ON when Md is not BCD. ON when Mr is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases.

Equals Flag

Precautions

If Md and/or Mr are not BCD, an error will be generated and the Error Flag will turn ON.

376

Symbol Math Instructions

Section 3-10
If as a result of the multiplication, the content of R, R+1 is 0000 hex, the Equals Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D100 and D110 will be multiplied as 4-digit BCD values and the result will be output to D121 and D120.
0.00 D100 D110 D120

3-10-22 DOUBLE BCD MULTIPLY: *BL(425)

Purpose Ladder Symbol
*BL(425) Md Mr R Md: 1st multiplicand word Mr: 1st multiplier word R: 1st result word

Multiplies 8-digit (double-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification *BL(425) @*BL(425) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Md CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #99999999 (BCD) ----Mr R CIO 0 to CIO 6140 W0 to W508 H0 to H508 A448 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764

377

Symbol Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-10
Md Mr --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

*BL(425) multiplies BCD values in Md and Md+1 and Mr and Mr+1 and outputs the result to R to R+3.
Md + 1 Mr + 1 Md Mr (BCD) (BCD)

R+3

R+2

R+1

(BCD)

Flags
Name Error Flag Label ER Operation ON when Md and/or Md+1 are not BCD. ON when Mr and/or Mr +1 are not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases.

Equals Flag

Precautions

If Md, Md+1 and/or Mr, Mr+1 are not BCD, an error will be generated and the Error Flag will turn ON. If as a result of the multiplication, the content of R, R+1, R+2, R+3 is 0000 hex, the Equals Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D201, D200, D211, and D210 will be multiplied as 8-digit unsigned BCD values and the result will be output to D220 to D223.
0.01 D200 D210 D220

3-10-23 SIGNED BINARY DIVIDE: /(430)

Purpose Ladder Symbol
/(430) Dd Dr R Dd: Dividend word Dr: Divisor word R: Result word

Divides 4-digit (single-word) signed hexadecimal data and/or constants.

378

Symbol Math Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-10

/(430) @/(430) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Dd CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) 32768 to 0 to 32767 (signed decimal) DR0 to DR15 ----#0001 to #FFFF (binary) &1 to &65535 (unsigned decimal) 32768 to 1, 1 to 32767 (signed decimal) --Dr R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

Data Registers Index Registers Indirect addressing using Index Registers

,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

/(430) divides the signed binary (16 bit) values in Dd by those in Dr and outputs the result to R, R+1. The quotient is placed in R and the remainder in R+1.
Dd R+1 Remainder Dr (Signed binary) (Signed binary)

R Quotient

(Signed binary)

379

Symbol Math Instructions

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N

Section 3-10

Operation ON when the result is 0. OFF in all other cases. ON when as a result of the division, R is 0. OFF in all other cases. ON when the leftmost bit of the R is 1. OFF in all other cases.

Precautions

When the content of Dr is 0, an error will be generated and the Error Flag will turn ON. If as a result of the division, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the division, the content of the leftmost bit of R is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D100 will be divided by D110 as 4-digit signed binary values, the quotient will be output to D120, and the remainder to D121.
0.00 D100 D110 D120

3-10-24 DOUBLE SIGNED BINARY DIVIDE: /L(431)

Purpose Ladder Symbol
/L(431) Dd Dr R Dd: 1st dividend word Dr: 1st divisor word R: 1st result word

Divides 8-digit (double-word) signed hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification /L(431) @/L(431) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Dd CIO 0 to CIO 6142 W0 to W510 H0 to H510 Dr R CIO 0 to CIO 6140 W0 to W508 H0 to H508

380

Symbol Math Instructions

Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Dd A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) &0 to &4294967295 (unsigned decimal) 2147483647 to 2147483647 (signed decimal) #00000001 to #FFFFFFFF (binary) &1 to &4294967295 (unsigned decimal) 2147483648 to 1, 1 to 2147483647 (signed decimal) Dr

Section 3-10
R A448 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764

---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

/L(431) divides the signed binary values in Dd and Dd+1 by those in Dr and Dr+1 and outputs the result to R, R+1, R+2, and R+3. The quotient is output to R and R+1 and the remainder is output to R+2 and R+3.
Dd + 1 Dr + 1 Dd Dr (Signed binary) (Signed binary)

R+3 Remainder

R+2

R+1 Quotient

(Signed binary)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation ON when the result is 0. OFF in all other cases. ON when as a result of the division, R+1, R is 0. OFF in all other cases. ON when the leftmost bit of the R+1, R is 1. OFF in all other cases.

Precautions

When the remainder of the result, R+3, R+2 is 0,the Error Flag will turn ON. If as a result of the division, the content of R+1, R is 00000000 hex, the Equals Flag will turn ON. If as a result of the division, the content of the leftmost bit of R+1, R is 1, the Negative Flag will turn ON.

381

Symbol Math Instructions

Examples

Section 3-10
When CIO 0.01 is ON in the following example, D201 and D200 will be divided by D211 and D210 as 8-digit signed hexadecimal values, the quotient will be output to D221 and D220, and the remainder will be output to D223 and D222.
0.01 D200 D210 D220

3-10-25 UNSIGNED BINARY DIVIDE: /U(432)

Purpose Ladder Symbol
/U(432) Dd Dr R Dd: Dividend word Dr: Divisor word R: Result word

Divides 4-digit (single-word) unsigned hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification /U(432) @/U(432) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Dd CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) &0 to &65535 (unsigned decimal) DR0 to 15 #0001 to #FFFF (binary) &1 to &65535 (unsigned decimal) --Dr R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

Data Registers

---

382

Symbol Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-10
Dd Dr --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

/U(432) divides the unsigned binary values in Dd by those in Dr and outputs the quotient to R and the remainder to R+1.
Dd R+1 Remainder Dr (Unsigned binary) (Unsigned binary)

R Quotient

(Unsigned binary)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation ON when the result is 0. OFF in all other cases. ON when as a result of the division, R is 0. OFF in all other cases. ON when the leftmost bit of the R is 1. OFF in all other cases.

Precautions

If as a result of the division, the content of R+1 is 0, the Error Flag will turn ON. If as a result of the division, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the division, the content of the leftmost bit of R is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON in the following example, D100 will be divided by D110 as 4-digit unsigned binary values, the quotient will be output to D120, and the remainder will be output to D121.
0.00 D100 D110 D120

383

Symbol Math Instructions

Section 3-10

3-10-26 DOUBLE UNSIGNED BINARY DIVIDE: /UL(433)

Purpose Ladder Symbol
/UL(433) Dd Dr R Dd: 1st dividend word Dr: 1st divisor word R: 1st result word

Divides 8-digit (double-word) unsigned hexadecimal data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification /UL(433) @/UL(433) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Dd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 --#00000001 to #00000000 to #FFFFFFFF #FFFFFFFF (binary) (binary) &1 to &0 to &4294967295 &4294967295 (unsigned deci(unsigned decimal) mal) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Dr R CIO 0 to CIO 6140 W0 to W508 H0 to H508 A448 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764

Data Registers Index Registers Indirect addressing using Index Registers

384

Symbol Math Instructions

Description

Section 3-10
/UL(433) divides the unsigned binary values in Dd and Dd+1 by those in Dr and Dr+1 and outputs the quotient to R, R+1 and the remainder to R+2, and R+3.
Dd + 1 Dr + 1 Dd Dr (Unsigned binary) (Unsigned binary)

R+3

R+2

R+1 Quotient

(Unsigned binary)

Remainder

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation ON when the result is 0. OFF in all other cases. ON when as a result of the division R+1, R is 0. OFF in all other cases. ON when the leftmost bit of the R+1, R is 1. OFF in all other cases.

Precautions

When the content of Dr, Dr+1 is 0, the Error Flag will turn ON. If as a result of the division, the content of R, R+1, is 0000 hex, the Equals Flag will turn ON. If as a result of the division, the content of the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D201 and D200 will be divided by D211 and D210 as 8-digit unsigned hexadecimal values, the quotient will be output to D221 and D220, and the remainder will be output to D223 and D222.
0.01 D200 D210 D220

3-10-27 BCD DIVIDE: /B(434)

Purpose Ladder Symbol
/B(434) Dd Dr R Dd: Dividend word Dr: Divisor word R: Result word

Divides 4-digit (single-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification /B(434) @/B(434) Not supported. Not supported.

385

Symbol Math Instructions

Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-10

Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Dd CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #9999 #0001 to #9999 --(BCD) (BCD) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Dr R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

Description

/B(434) divides the BCD content of Dd by those of Dr and outputs the quotient to R and the remainder to R+1.
Dd Dr (BCD) (BCD)

R+1 Remainder

R Quotient

(BCD)

Flags
Name Error Flag Label ER Operation ON when Dd is not BCD. ON when Dr is not BCD. ON when the remainder is 0. OFF in all other cases. ON when R is 0. OFF in all other cases.

Equals Flag

Precautions

If Dd or Dr are not BCD or if the remainder (R+1) is 0, an error will be generated and the Error Flag will turn ON. If as a result of the division, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the division, the leftmost bit of R is 1, the Negative Flag will turn ON.

386

Symbol Math Instructions

Examples

Section 3-10
When CIO 0.00 is ON in the following example, D100 will be divided by D110 as 4-digit BCD values and the quotient will be output to D120 and the remainder to D121.
0.00 D100 D110 D120

3-10-28 DOUBLE BCD DIVIDE: /BL(435)

Purpose Ladder Symbol
/BL(435) Dd Dr R Dd: 1st dividend word Dr: 1st divisor word R: 1st result word

Divides 8-digit (double-word) BCD data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification /BL(435) @/BL(435) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Dd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #00000001 to --#99999999 (BCD) #99999999 (BCD) --Dr R CIO 0 to CIO 6140 W0 to W508 H0 to H508 A448 to A956 T0000 to T4092 C0000 to C4092 D0 to D32764

387

Symbol Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-10
Dd Dr --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

/BL(435) divides BCD values in Dd and Dd+1 by those in Dr and Dr+1 and outputs the quotient to R, R+1 and the remainder to R+2, R+3.
Dd + 1 Dr + 1 Dd Dr (BCD) (BCD)

R+3

R+2 Remainder

R+1 Quotient

(BCD)

Flags
Name Error Flag Label ER Operation ON when Dd, Dd+1 is not BCD. ON when Dr, Dr +1 is not BCD. OFF in all other cases. ON when the result is 0. OFF in all other cases.

Equals Flag

Precautions

If Dd, Dd+1 and/or Dr, Dr+1 are not BCD or the content of Dr, Dr+1 is 0, an error will be generated and the Error Flag will turn ON. If as a result of the division, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON.

Examples

When CIO 0.01 is ON in the following example, D201 and D200 will be divided by D211 and D210 as 8-digit BCD values, the quotient will be output to D221 and D220, and the remainder will be output to D223 and D222.
0.01 D200 D210 D220

388

Conversion Instructions

Section 3-11

3-11 Conversion Instructions

This section describes instructions used for data conversion.
Instruction BCD-TO-BINARY DOUBLE BCD-TO-DOUBLE BINARY BINARY-TO-BCD DOUBLE BINARY-TO-DOUBLE BCD 2S COMPLEMENT DOUBLE 2S COMPLEMENT 16-BIT TO 32-BIT SIGNED BINARY DATA DECODER DATA ENCODER ASCII CONVERT ASCII TO HEX COLUMN TO LINE LINE TO COLUMN SIGNED BCD-TO-BINARY DOUBLE SIGNED BCD-TOBINARY SIGNED BINARY-TO-BCD DOUBLE SIGNED BINARY-TOBCD GRAY CODE CONVERSION Mnemonic BIN BINL BCD BCDL NEG NEGL SIGN MLPX DMPX ASC HEX LINE COLM BINS BISL BCDS BDSL GRY Function code 023 058 024 059 160 161 600 076 077 086 162 063 064 470 472 471 473 474 Page 389 390 392 393 395 397 398 400 404 408 411 415 417 419 422 424 427 430

3-11-1 BCD-TO-BINARY: BIN(023)

Purpose Ladder Symbol
BIN(023) S R S: Source word R: Result word

Converts BCD data to binary data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BIN(023) @BIN(023) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 R

389

Conversion Instructions
Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-11
R A448 to A959

--DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

BIN(023) converts the BCD data in S to binary data and writes the result to R.
(BCD) R (BIN)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation ON if the content of S is not BCD. OFF in all other cases. ON if the result is 0000. OFF in all other cases. OFF

Example

The following diagram shows an example BCD-to-binary conversion.

R
10 10 10 10
3 2 1 0

163 162 161 160

3-11-2 DOUBLE BCD-TO-DOUBLE BINARY: BINL(058)

Purpose Ladder Symbol
BINL(058) S R S: First source word R: First result word

Converts 8-digit BCD data to 8-digit hexadecimal (32-bit binary) data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BINL(058) @BINL(058) Not supported Not supported

390

Conversion Instructions
Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-11

Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

BINL(058) converts the 8-digit BCD data in S and S+1 to 8-digit hexadecimal (32-bit binary) data and writes the result to R and R+1.
S+1 (BCD) S (BCD) R+1 (BIN) R (BIN)

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation ON if the contents of S+1, S are not BCD. OFF in all other cases. ON if the result is 0. OFF in all other cases. OFF

391

Conversion Instructions
Examples

Section 3-11
The following diagram shows an example of 8-digit BCD-to-binary conversion.
R+1
10 710 610 510 410 310 210 110 0
4

16 716 616 516 16 3 16 216 116 0

When CIO 0.00 is ON in the following example, the 8-digit BCD value in CIO 201 and CIO 200 is converted to hexadecimal and stored in D1001 and D1000.
0.00 200 D1000

S+1: CIO 201 0 0 2 0 0 x107 x106 x105 x104

S: CIO 200 0 5 0 200050=3X164+13X162+7X161+2X160 x103 x102 x101 x100

0 x167

0 x166

0 x165

3 x164

0 x16
3

D x162

7 x161

2 x160

R+1: D1001

R: D1000

3-11-3 BINARY-TO-BCD: BCD(024)

Purpose Ladder Symbol
BCD(024) S R S: Source word R: Result word

Converts a word of binary data to a word of BCD data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BCD(024) @BCD(024) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Operand Specifications

S: Source Word S must be between 0000 and 270F hexadecimal (0000 and 9999 decimal).

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area

S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959

A448 to A959

392

Conversion Instructions
Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-11
R

--DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

BCD(024) converts the binary data in S to BCD data and writes the result to R.
(BIN) R (BCD)

Flags
Name Error Flag Equals Flag Label ER = Operation ON if the content of S exceeds 270F (9999 decimal). OFF in all other cases. ON if the result is 0000. OFF in all other cases.

Precautions Example

The content of S must not exceed 270F (9999 decimal). The following diagram shows an example BCD-to-binary conversion.
R
16 3 16 2 16 1 16 0 10 3 10 2 10 1 10 0

3-11-4 DOUBLE BINARY-TO-DOUBLE BCD: BCDL(059)

Purpose Ladder Symbol
BCDL(059) S R S: First source word R: First result word

Converts 8-digit hexadecimal (32-bit binary) data to 8-digit BCD data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BCDL(059) @BCDL(059) Not supported Not supported

393

Conversion Instructions
Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-11

Interrupt tasks OK

Operands

S: First Source Word The content of S+1 and S must be between 0000 0000 and 05F5 E0FF hexadecimal (0000 0000 and 9999 9999 decimal).

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

BCDL(059) converts the 8-digit hexadecimal (32-bit binary) data in S and S+1 to 8-digit BCD data and writes the result to R and R+1.
S+1 (BCD) S (BCD) R+1 (BIN) R (BIN)

Flags
Name Error Flag Label ER Operation ON if the contents of S and S+1 exceed 05F5 E0FF (9999 9999 decimal). OFF in all other cases. ON if the result is 0. OFF in all other cases.

Equals Flag

Precautions

The content of S+1 and S must not exceed 05F5 E0FF (9999 9999 decimal).

394

Conversion Instructions
Examples

Section 3-11
The following diagram shows an example of 8-digit BCD-to-binary conversion.
R+1
16 716 616 516 4 16 316 216 116 0

10 710 610 510 410 3 10 210 110 0

When CIO 0.00 is ON in the following example, the hexadecimal value in CIO 201 and CIO 200 is converted to a BCD value and stored in D1001 and D1000.
0.00 200 D1000

S+1: CIO 201 MBS 0 x167 0 x166 2 x165 D x164 3 x16 3

S: CIO 200 2 x162 0 x161 A x160 LSB

2X165 +13X164+3X163+2X162+10=2961930 R+1: D1001 MBS 0 x10

7

R: D1000 6 x104 1 x10 3 9 x102 3 x101 0 x100 LSB

2 x106

9 x105

3-11-5 2S COMPLEMENT: NEG(160)

Purpose Ladder Symbol
NEG(160) S R S: Source word R: Result word

Calculates the 2s complement of a word of hexadecimal data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NEG(160) @NEG(160) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 R

A448 to A959

395

Conversion Instructions
Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S @ D0 to @ D32767 *D0 to *D32767

Section 3-11
R

#0000 to #FFFF (binary) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

NEG(160) calculates the 2s complement of S and writes the result to R. The 2s complement calculation basically reverses the status of the bits in S and adds 1.
2's complement (Complement + 1) (S) (R)

Note Flags

This operation (reversing the status of the bits and adding 1) is equivalent to subtracting the content of S from 0000.

Name Error Flag Equals Flag Negative Flag

Label ER = N

Operation OFF ON if the result is 0000. OFF in all other cases. ON if bit 15 of the result is ON. OFF in all other cases.

Note Example

The result for 8000 hex will be 8000 hex. When CIO 0.00 is ON in the following example, NEG(160) calculates the 2s complement of the content of D100 and writes the result to D200.
0.00 D100 D200

Actual calculation
D100

Equivalent subtraction

Reverse bit status ) Add 1

D200

396

Conversion Instructions

Section 3-11

3-11-6 DOUBLE 2S COMPLEMENT: NEGL(161)

Purpose Ladder Symbol
NEGL(161) S R S: First source word R: First result word

Calculates the 2s complement of two words of hexadecimal data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification NEGL(161) @NEGL(161) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

NEGL(161) calculates the 2s complement of S+1 and S and writes the result to R+1 and R. The 2s complement calculation basically reverses the status of the bits in S+1 and S and adds 1.
2's complement (Complement + 1) (S+1, S) (R+1, R)

Note

This operation (reversing the status of the bits and adding 1) is equivalent to subtracting the content of S+1 and S from 0000 0000.

397

Conversion Instructions
Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if the result is 0000 0000. OFF in all other cases. ON if bit 15 of R+1 is ON. OFF in all other cases.

Section 3-11

Note Example

The result for 8000 hex will be 8000 hex. When CIO 0.01 is ON in the following example, NEGL(161) calculates the 2s complement of the content of D1001 and D1000 and writes the result to D2001 and D2000.

0.01 D1000 D2000

Actual calculation
D1001 D1000

Equivalent subtraction

Reverse bit status ) Add 1

D2001 D2000

3-11-7 16-BIT TO 32-BIT SIGNED BINARY: SIGN(600)

Purpose Ladder Symbol
SIGN(600) S R S: Source word R: First result word

Expands a 16-bit signed binary value to its 32-bit equivalent.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SIGN(600) @SIGN(600) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 R CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094

398

Conversion Instructions
Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-11
R C0000 to C4094 D0 to D32766

#0000 to #FFFF (binary) --DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Note Description

R and R+1 must be in the same data area. SIGN(600) converts the 16-bit signed binary number in S to its 32-bit signed binary equivalent and writes the result in R+1 and R. The conversion is accomplished by copying the content of S to R and writing FFFF to R+1 if bit 15 of S is 1 or writing 0000 to R+1 if bit 15 of S is 0.
Source word (S) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

If bit 15 of S is 1, FFFF is transferred to R+1. If bit 15 of S is 0, 0000 is transferred to R+1. 2nd result word (R+1) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

The content of S is transferred "as is" to R. 1st result word (R) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if the result is 0000 0000. OFF in all other cases. ON if bit 15 of R+1 is ON. OFF in all other cases.

Example

When CIO 0.00 is ON in the following example, SIGN(600) converts the 16-bit signed binary content of D100 (#8000 = 32,768 decimal) to its 32-bit equivalent (#FFFF 8000 = 32,768 decimal) and writes that result to D201 and D200.
0.00 D100 D200 S: D100 Example: 8000 Hex

R+1: D201

R: D200

399

Conversion Instructions

Section 3-11

3-11-8 DATA DECODER: MLPX(076)

Purpose Reads the numerical value in the specified digit (or byte) in the source word, turns ON the corresponding bit in the result word (or 16-word range), and turns OFF all other bits in the result word (or 16-word range).

Ladder Symbol
MLPX(076) S C R S: Source word C: Control word R: First result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification MLPX(076) @MLPX(076) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: Source Word The data in the source word indicates the location of the bit(s) that will be turned ON. C: Control Word The control word specifies whether MLPX(076) will perform a 4-to-16 bit conversion or an 8-to-256 bit conversion, the number of digits or bytes to be converted, and the starting digit or byte.
Digit number: 3 2 1 0 0 Specifies the first digit/byte to be converted 4-to-16: 0 to 3 (digit 0 to 3) 8-to-256: 0 or 1 (byte 0 or 1) Number of digits/bytes to be converted 4-to-16: 0 to 3 (1 to 4 digits) 8-to-256: 0 or 1 (1 or 2 bytes) Conversion process 0: 4-to-16 bits (digit to word) 1: 8-to-256 bits (byte to 16-word range)

R: First result word There can be anywhere from 1 to 32 result words, depending upon the type of conversion process and number of digits/bytes being converted. The result words must be in the same data area. Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 C R

A448 to A959

400

Conversion Instructions
Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 C

Section 3-11
R

------DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

MLPX(076) can perform 4-to-16 bit or 8-to-256 bit conversions. Set the leftmost digit of C to 0 to specify 4-to-16 bit conversion and set it to 1 to specify 8to-256 bit conversion. 4-to-16 bit Conversion When the leftmost digit of C is 0, MLPX(076) takes the value of the specified digit in S (0 to F) and turns ON the corresponding bit in the result word. All other bits in the result word will be turned OFF. Up to four digits can be converted.
C l =1 (Convert 2 digits.) n=2 (Start with third digit.) 4-to-16 bit decoding (Bit m of R is turned ON.) R R+1

When two or more digits are being converted, MLPX(076) will read the digits in S from right to left and will wrap around to the rightmost digit after the leftmost digit, if necessary. The following diagram shows some example values for C and the 4-to-16 bit conversions that they produce.

C: #0010

C: #0030

C: #0031

R R+1

R R+1 R+2 R+3

R R+1 R+2 R+3

401

Conversion Instructions
8-to-256 bit Conversion

Section 3-11

When the leftmost digit of C is 1, MLPX(076) takes the value of the specified byte in S (00 to FF) and turns ON the corresponding bit in the range of 16 result words. All other bits in the result words will be turned OFF. Up to two bytes can be converted.
C l=1 (Convert 2 bytes.) n=1 (Start with second byte.) 8-to-256 bit decoding (Bit m of R to R+15 is turned ON.)
15

R+1

16

R+14 R+15 R+16 R+17

R+30 R+31

When two bytes are being converted, MLPX(076) will read the bytes in S from right to left and will wrap around to the rightmost byte if the leftmost byte (byte 1) has been specified as the starting byte. The following diagram shows some example values for C and the 8-to-256 bit conversions that they produce.

C: #1010
Digit 1 Digit 0

C: #1011
Digit 1 Digit 0

Flags
Name Error Flag Label ER Operation ON if C is not within the specified ranges. OFF in all other cases.

402

Conversion Instructions
Examples 4-to-16 bit Conversion

Section 3-11

When CIO 0.00 is ON in the following example, MLPX(076) will convert 3 digits in CIO 200 beginning the second digit, as indicated by C (#0021). The corresponding bits in D100 to D102 will be turned ON.
0.00

S C R

200 D100

Bits 0 to 3: Starting digit (Digit 1) C: # Bits 4 to 7: Number of digits (3 digits)

Digits S: 200

R: D100 D101 D102

Digit 1 contains 6, so bit 6 is turned ON. Digit 2 contains A, so bit 10 is turned ON. Digit 3 contains F, so bit 15 is turned ON.

8-to-256 bit Conversion When CIO 0.01 is ON in the following example, MLPX(076) will convert the 2 bytes in S beginning with byte 1 (the leftmost byte), as indicated by C (#1011). The corresponding bits in D1000 to D1015 and D1016 to D1031 will be turned ON.
0.01

S C R

1000 D1000

Bits 0 to 3: Starting byte (Byte 1) C: # Bits 4 to 7: Number of bytes (2 bytes)

Byte 1 S: 1000

Byte 0

R: D1000 D1001 D1002 D1003

Byte 1 contains 2D, so bit 13 (D) of R+2 is turned ON.

D1015 D1016 D1017 D1018 Byte 0 contains 1A, so bit 10 (A) of R+1 is turned ON.

D1031

403

Conversion Instructions

Section 3-11

3-11-9 DATA ENCODER: DMPX(077)

Purpose Ladder Symbol
DMPX(077) S R C S: First source word R: Result word C: Control word

FInds the location of the first or last ON bit within the source word (or 16-word range), and writes that value to the specified digit (or byte) in the result word.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification DMPX(077) @DMPX(077) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: First Source Word There can be anywhere from 1 to 32 source words, depending upon the type of conversion process and number of digits/bytes being converted. The source words must be in the same data area. R: Result Word The locations of the bits that were ON in the source word(s) are written to the digits/bytes in R starting with the specified first digit/byte. C: Control Word The control word specifies whether DMPX(077) will perform a 16-to-4 bit conversion or an 256-to-8 bit conversion, whether the leftmost or rightmost ON bit will be encoded, the number of digits or bytes that will be converted, and the starting digit or byte where the results will be written.
Digit number: 3 2 1 0

Specifies the first digit/byte to receive converted data. 16-to-4: 0 to 3 (digit 0 to 3) 256-to-8: 0 or 1 (byte 0 or 1) Number of digits/bytes to be converted 16-to-4: 0 to 3 (1 to 4 digits) 256-to-8: 0 or 1 (1 or 2 bytes) Bit to encode 0: Leftmost bit (highest bit address) 1: Rightmost bit (lowest bit address) Conversion process 0: 16-to-4 bits (word to digit) 1: 256-to-8 bits (16-word range to byte)

404

Conversion Instructions
Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 -----

Section 3-11

A0 to A959

Specified values only

--DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

DMPX(077) can perform 16-to-4 bit or 256-to-8 bit conversions. Set the leftmost digit of C to 0 to specify 16-to-4 bit conversion and set it to 1 to specify 256-to-8 bit conversion. 16-to-4 bit Conversion When the fourth (leftmost) digit of C is 0, DMPX(077) finds the locations of the leftmost or rightmost ON bits in up to 4 source words and writes these locations to R beginning with the specified digit. (Set the third digit of C to 0 to find the leftmost ON bits or 1 to find the rightmost ON bits.)
C FInds leftmost bit (Highest bit address) m l=1 (Convert 2 words.)

16-to-4 bit decoding (Location of leftmost bit (m) is written to R.)

Leftmost bit

n=2 (Start with digit 2.) R

When two or more digits are being converted, DMPX(077) will write the values to the digits in R from right to left and will wrap around to the rightmost digit after the leftmost digit, if necessary. The following diagram shows some example values for C and the 16-to-4 bit conversions that they produce.

405

Conversion Instructions
C: #0011 C: #0030

Section 3-11
C: #0013

R Digit 3 Digit 2 Digit 1 Digit 0

R Digit 3 Digit 2 Digit 1 Digit 0

R Digit 3 Digit 2 Digit 1 Digit 0

C: #0032

R Digit 3 Digit 2 Digit 1 Digit 0

256-to-8 bit Conversion When the fourth (leftmost) digit of C is 1, DMPX(077) finds the locations of the leftmost (highest bit address) or rightmost (lowest bit address) ON bits in one or two 16-word ranges of source words. The locations of these bits are written to R beginning with the specified byte. (Set the third digit of C to 0 to find the leftmost ON bits or 1 to find the rightmost ON bits.)
C l =0 (Convert one 16-word range.)

Leftmost Rightmost bit bit

Finds leftmost bit (Highest bit address) 256-to-8 bit decoding (The location of the leftmost bit in the 16-word range (m) is written to R.) n=1 (Start with byte 1.) R

When two bytes are being converted, DMPX(077) will write the values to the bytes in R from right to left and will wrap around to the rightmost byte if the leftmost byte (byte 1) has been specified as the starting byte.

406

Conversion Instructions

Section 3-11
The following diagram shows some example values for C and the 256-to-8 bit conversions that they produce.

C: #1010

C: #1011

Digit 1

Digit 0

Digit 1

Digit 0

Flags
Name Error Flag Label ER Operation ON if any of the source words contains 0000 hex (i.e., no bit to encode). ON if C is not within the specified ranges. OFF in all other cases.

Precautions

If the conversion data contains 0000 hex, but other data is to be encoded, separate the conversion by using more than one DMPX(077) instructions. DMPX(077) D0 DMPX(077) DMPX(077) DMPX(077) DMPX(077) D0 D1 D2 D3 D100 D100 D100 D100 D100 #0300 #0000 #0001 #0002 #0003

Examples

When CIO 0.00 is ON in the following example, DMPX(077) will find the leftmost ON bits in CIO 200 to C202 and write those locations to 3 digits in R beginning with the second digit, as indicated by C (#0021).
0.00

S R C

200 D1000

C: # DMPX(077) finds the leftmost ON bits. S: CIO 200 CIO 201 CIO 202

Starting digit (Digit 1)

Digits R: D10000

407

Conversion Instructions

Section 3-11

3-11-10 ASCII CONVERT: ASC(086)

Purpose Ladder Symbol
ASC(086) S Di D S: Source word Di: Digit designator D: First destination word

Converts 4-bit hexadecimal digits in the source word into their 8-bit ASCII equivalents.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASC(086) @ASC(086) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: Source Word Up to four digits in the source word can be converted. The digits are numbered 0 to 3, right to left. Di: Digit Designator The digit designator specifies various parameters for the conversion, as shown in the following diagram.
Digit number: 3 2 1 0

Specifies the first digit in S to be converted (0 to 3). Number of digits to be converted (0 to 3) 0: 1 digit 1: 2 digits 2: 3 digits 3: 4 digits First byte of D to be used. 0: Rightmost byte 1: Leftmost byte Parity 0: None 1: Even 2: Odd

D: First destination word The converted ASCII data is written to the destination word(s) beginning with the specified byte in D. Three destination words (D to D+3) will be required if 4 digits are being converted and the leftmost byte is selected as the first byte in D. The destination words must be in the same data area. Any bytes in the destination word(s) that are not overwritten with ASCII data will be left unchanged.

408

Conversion Instructions
Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 Di

Section 3-11

A448 to A959

------DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ASC(086) treats the contents of S as 4 hexadecimal digits, converts the designated digit(s) of S into their 8-bit ASCII equivalents, and writes this data into the destination word(s) beginning with the specified byte in D.
Di First digit to convert

Number of digits (n+1) Left (1) Right (0)

Parity It is possible to specify the parity of the ASCII data for use in error control during data transmissions. The leftmost bit of each ASCII character will be automatically adjusted for even, odd, or no parity. When no parity (0) is designated, the leftmost bit will always be zero. When even parity (1) is designated, the leftmost bit will be adjusted so that the total number of ON bits is even. When odd parity (2) is designated, the leftmost bit of each ASCII character will be adjusted so that there is an odd number of ON bits. The status of the parity bit does not affect the meaning of the ASCII code. Examples of even parity: When adjusted for even parity, ASCII 31 (00110001) will be B1 (10110001: parity bit turned ON to create an even number of ON bits); ASCII 36 (00110110) will be 36 (00110110: parity bit remains OFF because the number of ON bits is already even).

409

Conversion Instructions

Section 3-11
Examples of odd parity: When adjusted for odd parity, ASCII 36 (00110110) will be B6 (10110110: parity bit turned ON to create an odd number of ON bits); ASCII 46 (01000110) will be 46 (01000110: parity bit remains OFF because the number of ON bits is already odd). Examples of Di When two or more digits are being converted, ASC(086) will read the bytes in S from right to left and will wrap around to the rightmost byte if necessary. The following diagram shows some example values for Di and the conversions that they produce.

Di: #0011
Digit 3 Digit 2 Digit 1 Digit 0

Di: #0112
Digit 3 Digit 2 Digit 1 Digit 0

Di: #0030
Digit 3 Digit 2 Digit 1 Digit 0

Leftmost

Rightmost

Leftmost Rightmost

Leftmost Leftmost

Rightmost Rightmost

Di: #0130
Digit 3 Digit 2 Digit 1 Digit 0

Leftmost Leftmost Rightmost Rightmost

Flags
Name Error Flag Label ER Operation ON if the content of Di is not within the specified ranges. OFF in all other cases.

Example

When CIO 0.00 is ON in the following example, ASC(086) converts three hexadecimal digits in D100 (beginning with digit 1) into their ASCII equivalents and writes this data to D200 and D201 beginning with the leftmost byte in D200. In this case, a digit designator of #0121 specifies no parity, the starting byte (when writing) is the leftmost byte, the number of digits to read is 3, and the starting digit (when reading) is digit 1.

410

Conversion Instructions
0.00

Section 3-11

S Di D

D100 D200

Di: #

Number of digits Starting digit Digits S: D100 Starting byte (leftmost byte)

D: D200 D201

3-11-11 ASCII TO HEX: HEX(162)

Purpose Ladder Symbol
HEX(162) S Di D S: First source word Di: Digit designator D: Destination word

Converts up to 4 bytes of ASCII data in the source word to their hexadecimal equivalents and writes these digits in the specified destination word.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification HEX(162) @HEX(162) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: First Source Word The contents of the source words are treated as ASCII data. Up to three source words can be used. (Three source words will be required if 4 bytes are being converted and the leftmost byte is selected as the first byte in S.) The source words must be in the same data area.

411

Conversion Instructions
Di: Digit Designator

Section 3-11

The digit designator specifies various parameters for the conversion, as shown in the following diagram.
Digit number: 3 2 1 0

Specifies the first digit in D to receive converted data (0 to 3). Number of bytes to be converted (0 to 3) 0: 1 digit 1: 2 digits 2: 3 digits 3: 4 digits First byte of S to be converted. 0: Rightmost byte 1: Leftmost byte Parity 0: None 1: Even 2: Odd

D: Destination word The converted hexadecimal digits are written into D from right to left, beginning with the specified first digit. Any digits in the destination word that are not overwritten with the converted data will be left unchanged. Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --Specified values only DR0 to DR15 --Di D

A448 to A959

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

HEX(162) treats the contents of the source word(s) as ASCII data representing hexadecimal digits (0 to 9 and A to F), converts the specified number of bytes to hexadecimal, and writes the hexadecimal data to the destination word beginning at the specified digit. An error will occur if the source words contain data which is not an ASCII equivalent of hexadecimal digits. The following table shows hexadecimal digits and their ASCII equivalents (excluding parity bits).

412

Conversion Instructions
Flags
Hexadecimal digits (4 bits) 0 to 9 A to F

Section 3-11

ASCII equivalent (2 hexadecimal digits) 30 to 39 41 to 46

The following diagram shows the basic operation of HEX(162) with Di=0021.

C: 0021
Di First byte to convert Left (1) Right (0)

Number of digits (n+1) First digit to write

Parity It is possible to specify the parity of the ASCII data for use in error control during data transmissions. The leftmost bit in each byte is the parity bit. With no parity the parity bit should always be zero, with even parity the status of the parity bit should result in an even number of ON bits, and with odd parity the status of the parity bit should result in an odd number of ON bits. The following table shows the operation of HEX(162) for each parity setting.
Parity setting (leftmost digit of Di) No parity (0) Even parity (1) Operation of HEX(162) HEX(162) will be executed only when the parity bit in each byte is 0. An error will occur if a parity bit is non-zero. HEX(162) will be executed only when there is an even number of ON bits in each byte. An error will occur if a byte has an odd number of ON bits. HEX(162) will be executed only when there is an odd number of ON bits in each byte. An error will occur if a byte has an even number of ON bits.

Odd parity (2)

Examples of Di When two or more bytes are being converted, HEX(162) will write the converted digits to the destination word from right to left and will wrap around to the rightmost digit if necessary. The following diagram shows some example values for Di and the conversions that they produce.

Di: #0112
Leftmost Rightmost Leftmost

Di: #0030
Leftmost Rightmost Rightmost Leftmost

Di: #0131
Leftmost Rightmost Rightmost

Digit 3 Digit 2 Digit 1 Digit 0

Digit 3 Digit 2 Digit 1 Digit 0

D Digit 3 Digit 2 Digit 1 Digit 0

413

Conversion Instructions
Flags
Name Error Flag Label ER

Section 3-11

Operation ON if there is a parity error in the ASCII data. ON if the ASCII data in the source words is not equivalent to hexadecimal digits ON if the content of Di is not within the specified ranges. OFF in all other cases.

Precautions

An error will occur and the Error Flag will be turned ON if there is a parity error in the ASCII data, the ASCII data in the source words is not equivalent to hexadecimal digits, or the content of Di is not within the specified ranges. When CIO 0.00 is ON in the following example, HEX(162) converts the ASCII data in D100 and D101 according to the settings of the digit designator. (Di=#0121 specifies no parity, the starting byte (when reading) is the leftmost byte, the number of bytes to read is 3, and the starting digit (when writing) is digit 1.) HEX(162) converts three bytes of ASCII data (3 characters) beginning with the leftmost byte of D100 into their hexadecimal equivalents and writes this data to D200 beginning with digit 1.
0.00

Examples

S Di D

D100 D200

Di: # Starting byte (leftmost byte)

S: D100 D101 Number of digits Starting digit (digit 1) 3 digits

D: D200

When CIO 0.00 is ON in the following example, HEX(162) converts the ASCII data in D100 beginning with the rightmost byte and writes the hexadecimal equivalents in D200 beginning with digit 1. The digit designator setting of #1011 specifies even parity, the starting byte (when reading) is the rightmost byte, the number of bytes to read is 2, and the starting digit (when writing) is digit 1.)

414

Conversion Instructions
0.00 D100 D200

Section 3-11

Starting digit in D: Digit 1 Number of bytes: 2 Starting byte in S: Rightmost Parity: Even Parity bits: Result in even parity

S: D100 Starting byte: rightmost Conversion Starting digit (digit 1) D: D200 Not changed Number of bytes (2 bytes) Not changed

3-11-12 COLUMN TO LINE: LINE(063)

Purpose Ladder Symbol
LINE(063) S N D S: First source word N: Bit number D: Destination word

Converts a column of bits from a 16-word range (the same bit number in 16 consecutive words) to the 16 bits of the destination word.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification LINE(063) @LINE(063) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

S: First Source Word Specifies the first source word. S and S+15 must be in the same data area. N: Bit Number Specifies the bit number (0000 to 000F or &0 to &15) to be copied from the source words.

415

Conversion Instructions
Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants

Section 3-11

S N D CIO 0 to CIO 0 to CIO 6143 CIO 6128 W0 to W496 W0 to W511 H0 to H496 H0 to H511 A0 to A944 A0 to A959 A448 to A959 T0000 to T4080 T0000 to T4095 C0000 to C4080 C0000 to C4095 D0 to D32752 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to 000F (binary) or &0 to &15 DR0 to DR15 ---

Data Registers Index Registers Indirect addressing using Index Registers

----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

LINE(063) copies the 16 bits with bit number N from the 16-word range S to S+15 to the destination word D. Bit N of S+m is copied to bit m of D, i.e., bit N of S is copied to bit 00 of D and bit N of S+15 is copied to bit 15 of D.
Bit 15

Bit 00

S S+1 S+2 S+3 . . . S+15

0 0 0 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1

. . .

. . .

. . .
Bit 15 Bit 00

0 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0

D 0
Flags
Name Error Flag Equals Flag Label ER =

. . . 0 1 1 1

Operation ON if N is not within the specified range of 0000 to 000F. OFF in all other cases. ON if D is 0000 after execution. OFF in all other cases.

416

Conversion Instructions
Example

Section 3-11
When CIO 0.00 is ON in the following example, LINE(063) copies bit 5 from D100 to D115 to the 16 bits in D200.
0.00 D100 &5 D200

N: #0005 S: D100 D101 D102 to D115 to

D: D200

3-11-13 LINE TO COLUMN: COLM(064)

Purpose Ladder Symbol
COLM(064) S D N S: Source word D: First destination word N: Bit number

Converts the 16 bits of the source word to a column of bits in a 16-word range of destination words (the same bit number in 16 consecutive words).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification COLM(064) @COLM(064) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

D: First Destination Word Specifies the first destination word. D and D+15 must be in the same data area. N: Bit Number Specifies the bit number (0000 to 000F or &0 to &15) to be overwritten by the source word.

Operand Specifications
Area CIO Area Work Area S CIO 0 to CIO 6143 W0 to W511 D CIO 0 to CIO 6128 W0 to W496 N CIO 0 to CIO 6143 W0 to W511

417

Conversion Instructions
Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants S D H0 to H511 H0 to H496 A0 to A959 A448 to A944 T0000 to T4095 T0000 to T4080 C0000 to C4095 C0000 to C4080 D0 to D32767 D0 to D32752 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) ---

Section 3-11
N H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

Data Registers Index Registers Indirect addressing using Index Registers

DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

#0000 to #000F (binary) or &0 to &15 DR0 to DR15

Description

COLM(064) copies the 16 bits from S to the 16 bits with bit number N in the 16-word range D to D+15. Bit m of S is copied to bit N of D+m, i.e., bit 00 of S is copied to bit N of D and bit 15 of S is copied to bit N of D+15.
Bit 15 Bit 00

0 1 1 1

Bit 15

Bi

Bit 00

D D+1 D+2 D+3 . . . D+15

Flags

0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1

. . .

. . .

. . .

0 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0

Name Error Flag Equals Flag

Label ER =

Operation ON if N is not within the specified range of 0000 to 000F. OFF in all other cases. ON if bit N is 0 in all 16 words D to D+15 after execution. OFF in all other cases.

418

Conversion Instructions
Example

Section 3-11
When CIO 0.00 is ON in the following example, COLM(064) copies the 16 bits in D200 (bits 00 through 15) to bit 5 in D100 through D115.
0.00 D200 D100

S: D200

D: D100 D101 D102 to D115 to

3-11-14 SIGNED BCD-TO-BINARY: BINS(470)

Purpose Ladder Symbol
BINS(470) C S D C: Control word S: Source word D: Destination word

Converts one word of signed BCD data to one word of signed binary data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BINS(470) @BINS(470) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Operand Specifications

C: Control Word Specifies the signed BCD format. C must be 0000 to 0003.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary

C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767

A448 to A959

419

Conversion Instructions
Area Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C *D0 to *D32767 S

Section 3-11
D

#0000 to #0003 --(binary) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

BINS(470) converts signed BCD data to signed binary data. First the signed BCD data format and range in word S are checked against the setting in the control word (C). If the source data is correct, the signed BCD data in S is converted to signed binary and output to D. If the source data is incorrect, the Error Flag will be turned ON and the instruction will not be executed.
Signed BCD format specified in C Signed BCD Signed binary

When the converted data is negative, it will be output as the 2s complement and the Negative Flag be will turned ON. NEG(160) can be used to determine the absolute value of a negative signed binary number. Refer to 3-11-5 2S COMPLEMENT: NEG(160)395 for details. A value of 0 in the source data will be treated as 0 and will not cause an error. Also, the status of bits 13 to 15 of S is not checked when C=0000. Note Some Special I/O Units output signed BCD data. Calculations using this data will normally be easier if it is first converted to signed binary data with BINS(470). The control word specifies the signed BCD format as shown below. C = 0000 (Input Data Range: 999 to 999 BCD)

3 digits BCD, 12 bits Sign bit (0: Positive; 1: Negative) Status of 3 bits: 0

C = 0001 (Input Data Range: 7999 to 7999 BCD)

3 digits BCD, 12 bits 3 bits of digit 4 (0 to 7) Sign bit (0: Positive; 1: Negative)

420

Conversion Instructions
C = 0002 (Input Data Range: 999 to 9999 BCD)

Section 3-11

3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative () A to E: Error

C = 0003 (Input Data Range: 1999 to 9999 BCD)

3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (1) F: Negative () B to E: Error

The following table shows the possible BCD values for each signed BCD format and the corresponding signed binary values.
Setting C=0000 C=0001 C=0002 C=0003 Signed BCD values 999 to 1 and 0 to 999 7999 to 1 and 0 to 7999 999 to 1 and 0 to 9999 1999 to 1 and 0 to 9999 Signed binary values FC19 to FFFF and 0000 to 03E7 E0C1 to FFFF and 0000 to 1F3F FC19 to FFFF and 0000 to 270F F831 to FFFF and 0000 to 270F

Flags
Name Error Flag Label ER Operation ON if C is not within the specified range of 0000 to 0003. ON if C=0002 and the leftmost digit of S is A to E. ON if C=0003 and the leftmost digit of S is B to E. ON if the content of S is not BCD. OFF in all other cases. ON if D is 0000 after execution. OFF in all other cases. ON if bit 15 of D is ON after execution. OFF in all other cases.

Equals Flag Negative Flag

= N

Examples

BCD Format 0 (C=#0000) When CIO 0.00 is ON in the following example, the signed BCD data format and range in D100 are checked against the format specified in the control word (0000). The source data is correct, so the signed BCD data in D100 is converted to signed binary and output to D200.
S: D100
0.00

1123
D100 D200

Signed BCD data (123)

D: D200 FF85 Signed binary data

421

Conversion Instructions
BCD Format 0 (C=#0003)

Section 3-11

When CIO 0.01 is ON in the following example, the signed BCD data format and range in D300 are checked against the format specified in the control word (0003). The source data is correct, so the signed BCD data in D300 is converted to signed binary and output to D400.
S: D300
0.01

A369

Signed BCD data (1,369)

D300 D400

D: D400 FAA7 Signed binary data

3-11-15 DOUBLE SIGNED BCD-TO-BINARY: BISL(472)

Purpose Ladder Symbol
BISL(472) C S D C: Control word S: First source word D: First destination word

Converts double signed BCD data to double signed binary data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BISL(472) @BISL(472) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands Operand Specifications

C: Control Word Specifies the signed BCD format. C must be 0000 to 0003.

Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants

C S D CIO 0 to CIO 0 to CIO 6142 CIO 6143 W0 to W511 W0 to W510 H0 to H511 H0 to H510 A0 to A959 A0 to A958 A448 to A958 T0000 to T4095 T0000 to T4094 C0000 to C4095 C0000 to C4094 D0 to D32767 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #0000 to #0003 (binary) ---

422

Conversion Instructions
Area Data Registers Index Registers Indirect addressing using Index Registers

Section 3-11
C S DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 D

Description

BISL(472) converts the double signed BCD data in S+1 and S to double signed binary data and writes the result in D+1 and D. First the signed BCD data format and range in words S+1 and S are checked against the setting in the control word (C). If the source data is correct, the signed BCD data S+1 and S is converted to signed binary and output to D+1 and D. If the source data is incorrect, the Error Flag will be turned ON and the instruction will not be executed.

Signed BCD format specified in C Signed BCD Signed BCD Signed binary Signed binary

When the converted data is negative, it will be output as the 2s complement and the Negative Flag be will turned ON. NEGL(161) can be used to determine the absolute value of a negative double signed binary number. Refer to 3-11-6 DOUBLE 2S COMPLEMENT: NEGL(161) for details. Values of 0 in the source data will be treated as 0 and will not cause an error. Also, the status of bits 13 to 15 of S+1 is not checked when C=0000. The control word specifies the signed BCD format as shown below. C = 0000 (Input Data Range: 999 9999 to 999 9999 BCD)
S+1 3 digits BCD, 12 bits Sign bit (0: Positive; 1: Negative) Status of 3 bits: 0

C = 0001 (Input Data Range: 7999 9999 to 7999 9999 BCD)

S+1 3 digits BCD, 12 bits 3 bits of digit 4 (0 to 7) Sign bit (0: Positive; 1: Negative)

C = 0002 (Input Data Range: 999 9999 to 9999 9999 BCD)

S+1 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative () A to E: Error

423

Conversion Instructions

Section 3-11
C = 0003 (Input Data Range: 1999 9999 to 9999 9999 BCD)
S+1 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (1) F: Negative () B to E: Error

The following table shows the possible BCD values for each signed BCD format and the corresponding signed binary values.
Setting C=0000 C=0001 C=0002 C=0003 Signed BCD values 999 9999 to 1 0 to 999 9999 7999 9999 to 1 0 to 7999 9999 999 9999 to 1 0 to 9999 9999 1999 9999 to 1 0 to 9999 9999 Signed binary values FF67 6981 to FFFF FFFF 0000 0000 to 0098 967F FB3B 4C01 to FFFF FFFF 0000 0000 to 04C4 B3FF FF67 6981 to FFFF FFFF 0000 0000 to 05F5 E0FF FECE D301 to FFFF FFFF 0000 0000 to 05F5 E0FF

Flags
Name Error Flag Label ER Operation ON if C is not within the specified range of 0000 to 0003. ON if C=0002 and the leftmost digit of S+1 is A to E. ON if C=0003 and the leftmost digit of S+1 is B to E. ON if the content of S+1 and S is not BCD. OFF in all other cases. ON if D and D+1 contain 0000 0000 after execution. OFF in all other cases. ON if bit 15 of D+1 is ON after execution. OFF in all other cases.

Equals Flag Negative Flag

= N

Example

When CIO 0.00 is ON in the following example, the double signed BCD data format and range in D101 and D100 are checked against the format specified in the control word (0002). The source data is correct, so the double signed BCD data in D101 and D100 is converted to double signed binary and output to D201 and D200.
0.00

S+1: D101 F345

D100 D200

S: D100 6789 Double signed BCD data (3,456,789)

D+1: D201 FFCB

D: D200 40EB Double signed binary data

3-11-16 SIGNED BINARY-TO-BCD: BCDS(471)

Purpose Converts one word of signed binary data to one word of signed BCD data.

424

Conversion Instructions
Ladder Symbol
BCDS(471) C S D C: Control word S: Source word D: Destination word

Section 3-11

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BCDS(471) @BCDS(471) Not supported Not supported

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand

C: Control Word Specifies the signed BCD format. C must be 0000 to 0003. S: Source Word Contains the signed binary data to be converted. The content of S must be within the valid range of the BCD format specified in C.
Setting C=0000 C=0001 C=0002 C=0003 Allowed values for S FC19 to FFFF or 0000 to 03E7 E0C1 to FFFF or 0000 to 1F3F FC19 to FFFF or 0000 to 270F F831 to FFFF or 0000 to 270F

D: Destination word Contains the converted signed BCD data. See the description section below for an explanation of the BCD formats. Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #0003 (binary) DR0 to DR15 --S D

A448 to A959

425

Conversion Instructions
Area Index Registers Indirect addressing using Index Registers

Section 3-11
C S --,IR0 to ,IR15 2048 to +2047 ,IR0 to 12048 to +2047 ,IR5 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 D

Description

BCDS(471) converts signed binary data to signed BCD data. First the signed binary data in word S is checked to verify that it is within the valid range for the signed BCD format specified in the control word (C). If the source data is correct, the signed binary data in S is converted to signed BCD and output to D. If the source data is incorrect, the Error Flag will be turned ON and the instruction will not be executed.

Signed BCD format specified in C Signed binary Signed BCD

Note

(1) Values of 0 in the source data will be treated as 0 and will not cause an error. (2) Some Special I/O Units require signed BCD data inputs. BCDS(471) can be used to convert signed binary data for output to these Units. The control word specifies the signed BCD format that will be used for the result, as shown below. C = 0000 (Output Data Range: 999 to 999 BCD)

3 digits BCD, 12 bits Sign bit (0: Positive; 1: Negative) Status of 3 bits: 0

C = 0001 (Output Data Range: 7999 to 7999 BCD)

3 digits BCD, 12 bits 3 bits of digit 4 (0 to 7) Sign bit (0: Positive; 1: Negative)

C = 0002 (Output Data Range: 999 to 9999 BCD)

3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative ()

426

Conversion Instructions
C = 0003 (Output Data Range: 1999 to 9999 BCD)

Section 3-11

3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (1) F: Negative ()

The following table shows the possible signed binary values for each signed BCD format. An error will occur if the source data is not within the allowed range for the specified signed BCD format.
Setting C=0000 C=0001 C=0002 C=0003 Signed binary values FC19 to FFFF and 0000 to 03E7 E0C1 to FFFF and 0000 to 1F3F FC19 to FFFF and 0000 to 270F F831 to FFFF and 0000 to 270F Signed BCD values 999 to 1 and 0 to 999 7999 to 1 and 0 to 7999 999 to 1 and 0 to 9999 1999 to 1 and 0 to 9999

Flags
Name Error Flag Label ER Operation ON if C is not within the specified range of 0000 to 0003. ON if C=0000 and the source data is not within the allowed ranges (FC19 to FFFF or 0000 to 03E7). ON if C=0001 and the source data is not within the allowed ranges (E0C1 to FFFF or 0000 to 1F3F). ON if C=0002 and the source data is not within the allowed ranges (FC19 to FFFF or 0000 to 270F). ON if C=0003 and the source data is not within the allowed ranges (F831 to FFFF or 0000 to 270F). OFF in all other cases. ON if D is 0000 after execution. OFF in all other cases. ON if C=0000 or 0001 and the results sign bit is ON after execution. ON if C=0002 and the leftmost digit of the result is F. ON if C=0003 and the leftmost digit of the result is A or F. OFF in all other cases.

Equals Flag Negative Flag

= N

3-11-17 DOUBLE SIGNED BINARY-TO-BCD: BDSL(473)

Purpose Ladder Symbol
BDSL(473) C S D C: Control word S: First source word D: First destination word

Converts double signed binary data to double signed BCD data.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BDSL(473) @BDSL(473) Not supported Not supported

427

Conversion Instructions
Operands C: Control Word Specifies the signed BCD format. C must be 0000 to 0003. S: First Source Word

Section 3-11

Source words S+1 and S contain the double signed binary data to be converted. Their content must be within the valid range of the BCD format specified in C.
Setting C=0000 C=0001 C=0002 C=0003 Allowed values for S+1 and S FF67 6981 to FFFF FFFF or 0000 0000 to 0098 967F FB3B 4C01 to FFFF FFFF or 0000 0000 to 04C4 B3FF FF67 6981 to FFFF FFFF or 0000 0000 to 05F5 E0FF FECE D301 to FFFF FFFF or 0000 0000 to 05F5 E0FF

D: First destination word Destination words D+1 and D contain the converted double signed BCD data. See the description section below for an explanation of the BCD formats. Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C S D CIO 0 to CIO 0 to CIO 6142 CIO 6143 W0 to W511 W0 to W510 H0 to H511 H0 to H510 A0 to A959 A0 to A958 A448 to A958 T0000 to T4095 T0000 to T4094 C0000 to C4095 C0000 to C4094 D0 to D32767 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #0000 to #0003 --(binary) DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

BDSL(473) converts double signed binary data to double signed BCD data. First the double signed binary data in S+1 and S is checked to verify that it is within the valid range for the signed BCD format specified in the control word (C). If the source data is correct, the double signed binary data in S+1 and S is converted to double signed BCD and output to D+1 and D. If the source data is incorrect, the Error Flag will be turned ON and the instruction will not be executed.
Signed BCD format specified in C Signed binary Signed binary Signed BCD Signed BCD

428

Conversion Instructions
Note

Section 3-11
Values of 0 in the source data will be treated as 0 and will not cause an error. The control word specifies the signed BCD format that will be used for the result, as shown below. C = 0000 (Output Data Range: 999 9999 to 999 9999 BCD)
S+1 S 7 digits BCD, 28 bits Sign bit (0: Positive; 1: Negative) Status of 3 bits: 0

C = 0001 (Output Data Range: 7999 9999 to 7999 9999 BCD)

S+1 S 7 digits BCD, 28 bits 3 bits of digit 8 (0 to 7) Sign bit (0: Positive; 1: Negative)

C = 0002 (Output Data Range: 999 9999 to 9999 9999 BCD)

S+1 S 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD F: Negative ()

C = 0003 (Output Data Range: 1999 9999 to 9999 9999 BCD)

S+1 S 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD A: Negative (1) F: Negative ()

The following table shows the possible double signed binary values for each signed BCD format. An error will occur if the source data is not within the allowed range for the specified signed BCD format.
Setting C=0000 C=0001 C=0002 C=0003 Signed binary values FF67 6981 to FFFF FFFF 0000 0000 to 0098 967F FB3B 4C01 to FFFF FFFF 0000 0000 to 04C4 B3FF FF67 6981 to FFFF FFFF 0000 0000 to 05F5 E0FF FECE D301 to FFFF FFFF 0000 0000 to 05F5 E0FF Signed BCD values 999 9999 to 1 0 to 999 9999 7999 9999 to 1 0 to 7999 9999 999 9999 to 1 0 to 9999 9999 1999 9999 to 1 0 to 9999 9999

429

Conversion Instructions
Flags
Name Error Flag Label ER

Section 3-11

Equals Flag Negative Flag

= N

Operation ON if C is not within the specified range of 0000 to 0003. ON if C=0000 and the source data is not within the range: FF67 6981 to FFFF FFFF or 0000 0000 to 0098 967F. ON if C=0001 and the source data is not within the range: FB3B 4C01 to FFFF FFFF or 0000 0000 to 04C4 B3FF. ON if C=0002 and the source data is not within the range: FF67 6981 to FFFF FFFF or 0000 0000 to 05F5 E0FF. ON if C=0003 and the source data is not within the range: FECE D301 to FFFF FFFF or 0000 0000 to 05F5 E0FF. OFF in all other cases. ON if D and D+1 contain 0000 0000 after execution. OFF in all other cases. ON if C=0000 or 0001 and the results sign bit is ON after execution. ON if C=0002 and the leftmost digit of the result is F. ON if C=0003 and the leftmost digit of the result is A or F. OFF in all other cases.

Example

When CIO 0.00 is ON in the following example, the double signed binary data in D101 and D100 are checked against the format specified in the control word (0003). The source data is correct, so the double signed binary data in D101 and D100 is converted to double signed BCD and output to D201 and D200.
0.00

S+1: D101 FF8B

D100 D200

S: D100 344F Double signed binary data

D+1: D201 F765

D: D200 4321 Double signed BCD data (7,654,321)

3-11-18 GRAY CODE CONVERT: GRY(474)

Purpose Ladder Symbol
GRY(474) C S D C: First control word S: Source word D: First destination word

Converts the gray binary code in a specified word to standard binary data, BCD data, or an angle at the specified resolution.

Variations
Variations Executed Each Cycle for ON Condition GRY(474) Executed Once for Upward Differentiation @GRY(474) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported

430

Conversion Instructions
Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-11

Interrupt tasks OK

Operands
15 C

C: Control Word Specifies the parameters for the conversion as shown below.
12 11 87 Do not use (0). 43 0

Resolution 0 or 1 to F hex (1 to 15 decimal) bits 0 hex = User specified in bits 12 to 15 of C+2. Conversion Mode 0 hex = Binary Mode, 1 hex = BCD Mode, 2 hex = 360 Mode Operating Mode 0 hex = Gray binary code conversion C+1

Zero Point Compensation (0000 to 7FFF Hex (Binary Data)) Note: Zero point compensation that exceeds the resolution set in the word C of the control data cannot be specified. 15 C+2 Encoder Remainder Compensation (Binary Data) Note: The range that can be set depends on the user-specified resolution. User-specified Resolution 0 hex = 256, 1 hex = 360, 2 hex = 720, 3 hex = 1,024, 4 to F hex = Do not use. Note: The above setting is valid when the resolution is set to 0 hex in bits 00 to 03 of C. 12 11 0

S: Source Word Contains the gray binary code to be converted. The range must be within the number of bits determined by the resolution specified in bits 00 to 03 of C. All bits outside of the number of bits for the specified resolution will be ignored. For example, if the specified resolution is 08 hex and S contains FFFF hex, the gray binary code will be taken as 00FF hex.
S

D: First destination word Destination words D+1 and D contain the results of converting the gray binary code at the resolution specified in bits 00 to 03 of the control data word C and the conversion mode specified in bits 04 to 07 of the control data word C. The leftmost word is output to D+1 and the rightmost word is output to D. The ranges of data that are output are as follows: Binary Mode: 0000 0000 to 0000 7FFF hex BCD Mode:0000 0000 to 0003 2767 360 Mode:0000 0000 to 0000 3599 (0.0 to 359.9 in 0.1 increments, BCD)

431

Conversion Instructions
D D+1 Rightmost word Leftmost word

Section 3-11

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C S CIO 0 to CIO 0 to CIO 6141 CIO 6143 W0 to W509 W0 to W511 H0 to H509 H0 to H511 A0 to A957 A0 to A959 T0000 to T4093 T0000 to T4095 C0000 to C4093 C0000 to C4095 D0 to D32765 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --#0000 to #FFFF (binary) DR0 to DR15 --D CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

GRY(474) converts the gray binary code in the word specified in S at the resolution specified in C using one of the following conversion modes (binary, BCD, or 360), also specified in C, and places the results in D and D+1.
Conversion mode Function Binary Mode Gray binary code is converted to binary data between 0000 0000 and 0000 7FFF hex. Zero point offset and remainder compensation is applied and then the result is output to D and D+1. BCD Mode Gray binary code is converted to BCD data. Zero point offset and remainder compensation is applied, the data is converted to BCD between 0000 0000 and 0003 2767, and then the result is output to D and D+1. 360 Mode Gray binary code is converted to BCD data. Zero point offset and remainder compensation is applied, the data is converted to an angle between 0000 0000 and 0000 3599 (0.0 to 359.9 in 0.1 increments), and then the result is output to D and D+1.

Note

(1) GRY(474) is normally used when inputting, through a DC Input Unit, a parallel signal (2n) from an absolute encoder that outputs a gray binary code. (2) If the word specified for S is allocated to an Input Unit, the input data converted by GRY(474) will be for the gray binary code from the previous CPU Unit cycle, i.e., it will be one cycle time old.

432

Conversion Instructions
Flags
Name Error Flag Label ER

Section 3-11

Equals Flag Negative Flag

= N

Operation ON if bits 12 to 15 of C are not 0 hex (operating mode = gray binary code conversion). ON if the zero point offset in C+1 is not within the specified resolution (including user-specified resolutions). ON if bits 04 to 07 of C are not 0 hex (= Binary Mode), 1 hex (= BCD Mode), or 2 hex (= 360 Mode). ON if the specified encoder remainder compensation exceeds the set user-specified resolution when bits 00 to 03 of C are 0 hex (= user-specified resolution). ON if the converted binary value is less than the encoder remainder compensation when bits 00 to 03 of C are 0 hex (= user-specified resolution). ON if the converted binary value is less than the resolution when bits 00 to 03 of C are 0 hex (= user-specified resolution). OFF in all other cases. OFF in all cases. OFF in all cases.

Examples

When CIO 0.00 is ON in the following example, the gray binary code in CIO 1000 is converted according to the settings in the control data in D0 to D2 and the result is output to D200.
0.00 GRY C S D D0 1000 D200

Example 1: Converting to Binary Data with an 8-bit Resolution and Zero Point Offset of 001A Hex
87 0 0 43 8 Resolution: 8-bit Conversion mode: Binary Mode 0

15 C: D0 0

12 11

Operating mode: Gray binary code conversion C+1: D1 001A Zero point offset: 001A hex C+2: D2 0 000

User-specified resolution: Not used.

S: 1000 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 Gray binary code Converted and offset. D: D200 D+1: D201 0017 0000 Result of binary conversion and offsetting stored.

433

Conversion Instructions

Section 3-11
Example 2: Converting to Angle Data with a 10-bit Resolution and Zero Point Offset of 0151 Hex
15 C: D0 0 12 11 0 87 2 43 A Resolution: 10-bit Conversion mode: 360 Mode Operating mode: Gray binary code conversion C+1: D1 0151 Zero point offset: 0151 hex C+2: D2 0 000 0

User-specified resolution: Not used. S: 1000 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 Gray binary code Converted and offset. D: D200 D+1: D201

3488 0000

Angle data stored.

Example 3: Converting to BCD Data with for an OMRON E6C2-AG5C Absolute Encoder (Resolution: 360/rotation, Encoder Remainder Compensation: 76) and Zero Point Offset of 0000 Hex
87 0 1 43 0 Resolution: User-specified Conversion mode: BCD Mode 0

15 C: D0 0

12 11

Operating mode: Gray binary code conversion C+1: D1 0000 Zero point offset: 0000 hex C+2: D2 1 04C

User-specified resolution: 360, Encoder remainder compensation: 04C hex (76 decimal) S: 1000 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 Gray binary code Converted and offset. D: D200 D+1: D201 0100 0000 Result of BCD conversion and offsetting stored.

434

Conversion Instructions

Section 3-11
Example 4: Converting to BCD Data with for an OMRON E6C2-AG5C Absolute Encoder (Resolution: 360/rotation, Encoder Remainder Compensation: 76) and Zero Point Offset of 000A Hex
87 0 1 43 0 0

15 C: D0 0

12 11

Resolution: User-specified Conversion mode: BCD Mode Operating mode: Gray binary code conversion C+1: D1 000A Zero point offset: 000A hex C+2: D2 1 04C

User-specified resolution: 360, Encoder remainder compensation: 04C hex (76 decimal) S: 1000 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 Converted and offset. D: D200 D+1: D201 0100 0000 Result of BCD conversion and offsetting stored. Gray binary code

435

Logic Instructions

Section 3-12

3-12 Logic Instructions

This section describes instructions which perform logic operations on word data.
Instruction LOGICAL AND DOUBLE LOGICAL AND LOGICAL OR DOUBLE LOGICAL OR EXCLUSIVE OR DOUBLE EXCLUSIVE OR EXCLUSIVE NOR DOUBLE EXCLUSIVE NOR COMPLEMENT DOUBLE COMPLEMENT Mnemonic ANDW ANDL ORW ORWL XORW XORL XNRW XNRL COM COML Function code 034 610 035 611 036 612 037 613 029 614 Page 436 437 439 440 442 444 445 447 449 450

3-12-1 LOGICAL AND: ANDW(034)

Purpose Ladder Symbol
ANDW(034) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical AND of corresponding bits in single words of word data and/ or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ANDW(034) @ANDW(034) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants I1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) --I2 R

A448 to A959

436

Logic Instructions
Area Data Registers Index Registers Indirect addressing using Index Registers I1 I2

Section 3-12
R

DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ANDW(034) takes the logical AND of data specified in I1 and I2 and outputs the result to R. The logical AND is taken of corresponding bits in I1 and I2 in succession. When the content of corresponding bits in both I1 and I2 are 1 or when either is 0, a 0 will be output to the corresponding bit in R. I1, I2 R
I1 1 1 0 0 I2 1 0 1 0 R 1 0 0 0

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Precautions

When ANDW(034) is executed, the Error Flag will turn OFF. If as a result of the AND, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the AND, the leftmost bit of R is 1, the Negative Flag will turn ON.

3-12-2 DOUBLE LOGICAL AND: ANDL(610)

Purpose Ladder Symbol
ANDL(610) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical AND of corresponding bits in double words of word data and/ or constants.

437

Logic Instructions
Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-12

ANDL(610) @ANDL(610) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers I1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 I2 R

A448 to A958

Description

ANDL(610) takes the logical AND of data specified in I1, I1+1 and I2, I2+1 and outputs the result to R, R+1. (I1, I1+1), (I2, I2+1) (R, R+1)
I1, I1+1 1 1 0 0 I2, I2+1 1 0 1 0 R, R+1 1 0 0 0

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Precautions

When ANDL(610) is executed, the Error Flag will turn OFF. If as a result of the AND, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON.

438

Logic Instructions

Section 3-12
If as a result of the AND, the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When the execution condition CIO 0.00 is ON, the logical AND will be taken of corresponding bits in CIO 1001, CIO 1000 and CIO 2001, CIO 2000 and the results will be output to corresponding bits in D201 and D200.
0.00 1000 2000 D200

S1: CIO 1000 S1+1: CIO 1001

1000.00 1000.01 1000.02 1000.03 1000.04 1001.13 1001.14 1001.15

S 2: CIO 2000 S2+1: CIO 2001

2000.00 2000.01 2000.02 2000.03 2000.04 2001.13 2001.14 2001.15

D: D200 D+1: D201

Note: The vertical arrow indicates logical AND.

3-12-3 LOGICAL OR: ORW(035)

Purpose Ladder Symbol
ORW(035) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical OR of corresponding bits in single words of word data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ORW(035) @ORW(035) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary I1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 I2 R

A448 to A959

439

Logic Instructions
Area Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers I1 *D0 to *D32767 I2

Section 3-12
R

#0000 to #FFFF (binary) --DR0 to DR15 --,IR0 to ,IR15 2048 to+2047 ,IR0 to 2048 to+2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ORW(035) takes the logical OR of data specified in I1 and I2 and outputs the result to R. The logical OR is taken of corresponding bits in I1 and I2 in succession. When either one of the corresponding bits in I1 and I2 are 1 or when both of them are 0, a 0 will be output to the corresponding bit in R. I1 + I2 R
I1 1 1 0 0 I2 1 0 1 0 R 1 1 1 0

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Precautions

When ORW(035) is executed, the Error Flag will turn OFF. If as a result of the OR, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the OR, the leftmost bit of R is 1, the Negative Flag will turn ON.

3-12-4 DOUBLE LOGICAL OR: ORWL(611)

Purpose Ladder Symbol
ORWL(611) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical OR of corresponding bits in double words of word data and/ or constants.

440

Logic Instructions
Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-12

ORWL(611) @ORWL(611) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers I1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 I2 R

A448 to A958

Description

ORWL(611) takes the logical OR of data specified in I1 and I2 as double-word data and outputs the result to R, R+1. When any of the corresponding bits in I1, I1+1, I2, and I2 +1are 1, a 1 will be output to the corresponding bit it R+1. When any of them are 0, a 0 will be output to the corresponding bit in R+1. (I1, I1+1) + (I2, I2+1) (R, R+1)
I1, I1+1 1 1 0 0 I2, I2+1 1 0 1 0 R, R+1 1 1 1 0

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

441

Logic Instructions
Precautions When ORWL(611) is executed, the Error Flag will turn OFF.

Section 3-12

If as a result of the OR, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If as a result of the OR, the leftmost bit of R+1 is 1, the Negative Flag will turn ON. Examples When the execution condition CIO 0.00 is ON, the logical OR will be taken of corresponding bits in CIO 1001, CIO 1000 and CIO 2001, CIO 2000 and the results will be output to corresponding bits in D501 and D500.
0.00 1000 2000 D500

S1: CIO 1000 S1+1: CIO 1001 1000.00

1000.01 1000.02 1000.03 1000.15 1001.00 1001.15

S2: CIO 2000 S2+1: CIO 2001 2000.00

2000.01 2000.02 2000.03 2000.15 2001.00 2001.15

D: D500 D+1: D501

D500

D501

Note: The vertical arrow indicates logical OR.

3-12-5 EXCLUSIVE OR: XORW(036)

Purpose Ladder Symbol
XORW(036) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical exclusive OR of corresponding bits in single words of word data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition XORW(036) Executed Once for Upward Differentiation @XORW(036) Executed Once for Downward Differentiation Not supported. Not supported. Immediate Refreshing Specification

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area I1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 I2 R

A448 to A959

442

Logic Instructions
Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers I1 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) I2

Section 3-12
R

---

DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

XORW(036) takes the logical exclusive OR of data specified in I1 and I2 and outputs the result to R. The logical exclusive OR is taken of corresponding bits in I1 and I2 in succession. When the content of corresponding bits of I1 and I2 are different, a 1 will be output to the corresponding bit of R and when there are different, 0 will be output to the corresponding bit in R. I1, I2 + I1, I2 R
I1 1 1 0 0 I2 1 0 1 0 R 0 1 1 0

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Precautions

When XORW(036) is executed, the Error Flag will turn OFF. If as a result of the OR, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the OR, the leftmost bit of R is 1, the Negative Flag will turn ON.

443

Logic Instructions

Section 3-12

3-12-6 DOUBLE EXCLUSIVE OR: XORL(612)

Purpose Ladder Symbol
XORL(612) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical exclusive OR of corresponding bits in double words of word data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification XORL(612) @XORL(612) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers I1 CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 I2 R

A448 to A958

Description

XORL(612) takes the logical exclusive OR of data specified in I1 and I2 as double-word data and outputs the result to R, R+1. When the content of any of the corresponding bits in I1, I1+1, I2, and I2 +1are different, a 1 will be output to the corresponding bit it R, R+1. When any of them are the same, a 0 will be output to the corresponding bit in R, R+1.

444

Logic Instructions
(I1, I1+1), (I2, I2+1) + (I1, I1+1), (I2, I2+1) (R, R+1)
I1, I1+1 1 1 0 0 I2, I2+1 1 0 1 0 R, R+1 0 1 1 0

Section 3-12

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Precautions

When XORL(612) is executed, the Error Flag will turn OFF. If as a result of the exclusive OR, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If as a result of the exclusive OR, the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When the execution condition CIO 0.00 is ON, the logical exclusive OR will be taken of corresponding bits in CIO 1001, CIO 1000 and D1001, D1000 and the results will be output to corresponding bits in D1201 and D1200.
S: CIO 1000 S1+1: CIO 1001
1000 D1000 D1200 1000.00 1000.01 1000.02 1000.03 1000.15 1001.00 1001.15 D1001 D1201 D1000

0.00

S: D1000 S2+1: D1001

D1200

D: D1200 D+1: D1201

Note: The symbol indicates exclusive logical OR.

3-12-7 EXCLUSIVE NOR: XNRW(037)

Purpose Ladder Symbol
XNRW(037) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical exclusive NOR of corresponding single words of word data and/or constants.

445

Logic Instructions
Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-12

XNRW(037) @XNRW(037) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers I1 CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0000 to #FFFF (binary) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 I2 R

A448 to A959

Description

XNRW(037) takes the logical exclusive NOR of data specified in I1 and I2 and outputs the result to R. The logical exclusive NOR is taken of corresponding bits in I1 and I2 in succession. When the content of corresponding bits of I1 and I2 are different, a 0 will be output to the corresponding bit of R and when they are different, 1 will be output to the corresponding bit in R. I1, I2 + I1, I2 R
I1 1 1 0 0 I2 1 0 1 0 R 1 0 0 1

446

Logic Instructions
Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Section 3-12

Precautions

When XNRW(037) is executed, the Error Flag will turn OFF. If as a result of the NOR, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of the NOR, the leftmost bit of R is 1, the Negative Flag will turn ON.

3-12-8 DOUBLE EXCLUSIVE NOR: XNRL(613)

Purpose Ladder Symbol
XNRL(613) I1 I2 R I1: Input 1 I2: Input 2 R: Result word

Takes the logical exclusive NOR of corresponding bits in double words of word data and/or constants.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification XNRL(613) @XNRL(613) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers I1 CIO 0 to CIO 6142 W0 toW 510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ----I2 R

A448 to A958

447

Logic Instructions
Area Index Registers Indirect addressing using Index Registers I1 I2

Section 3-12
R

--,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

XNRL(613) takes the logical exclusive NOR of data specified in I1 and I2 and outputs the result to R, R+1. When the content of any of the corresponding bits in I1, I1+1, I2, and I2 +1are different, a 0 will be output to the corresponding bit in R, R+1. When any of them are the same, a 1 will be output to the corresponding bit in R, R+1. (I1, I1+1), (I2, I2+1) + (I1, I1+1), (I2, I2+1) (R, R+1)
I1, I1+1 1 1 0 0 I2, I2+1 1 0 1 0 R, R+1 1 0 0 1

Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Precautions

When XNRL(613) is executed, the Error Flag will turn OFF. If as a result of the exclusive NOR, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If as a result of the exclusive NOR, the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples

When CIO 0.00 is ON, the logical exclusive NOR will be taken of corresponding bits in CIO 1001, CIO 1000, and CIO 2001, CIO 2000 and the results will be output to corresponding bits in D501 and D500.
0.00 1000 2000 D500

S 1: CIO 1000 S1+1: CIO 1001

1000.00 1000.01 1000.02 1000.03 1000.15 1001.00 1001.15

S 2: CIO 2000 S2+1: CIO 2001

2000.00 2000.01 2000.02 2000.03 2000.15 2001.00 2001.15 D501 D500

D: D500 D+1: D501

Note: The symbol indicates exclusive logical NOR.

448

Logic Instructions

Section 3-12

3-12-9 COMPLEMENT: COM(029)

Purpose Ladder Symbol
COM(029) Wd Wd: Word

Turns OFF all ON bits and turns ON all OFF bits in Wd.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification COM(029) @COM(029) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

Description Note Flags

COM(029) reverses the status of every specified bit in Wd. WdWd: 1 0 and 0 1 When using the COM instruction, be aware that the status of each bit will change each cycle in which the execution condition is ON.

Name Error Flag Equals Flag Negative Flag

Label ER = N

Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

449

Logic Instructions
Precautions When COM(029) is executed, the Error Flag will turn OFF.

Section 3-12

If as a result of COM, the content of R is 0000 hex, the Equals Flag will turn ON. If as a result of COM, the leftmost bit of R is 1, the Negative Flag will turn ON. Examples When CIO 0.00 is ON in the following example, the status of each bit will be D100 is reversed.
0.00 D100 D100 D100

3-12-10 DOUBLE COMPLEMENT: COML(614)

Purpose Ladder Symbol
COML(614) Wd Wd: Word

Turns OFF all ON bits and turns ON all OFF bits in Wd and Wd+1.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification COML(614) @COML(614) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers CIO 0 to CIO 6142 W0 to W510 H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Wd

450

Special Math Instructions

Description Note Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON when the result is 0. OFF in all other cases. ON when the leftmost bit of R is 1. OFF in all other cases.

Section 3-13
COML(614) reverses the status of every specified bit in Wd and Wd+1. (Wd+1, Wd)(Wd+1, Wd) When using the COM instruction, be aware that the status of each bit will change each cycle in which the execution condition is ON.

Precautions

When COML(614) is executed, the Error Flag will turn OFF. If as a result of COML, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If as a result of COML, the leftmost bit of R+1 is 1, the Negative Flag will turn ON.

Examples
0.01

When CIO 0.01 is ON in the following example, the status of each bit in D201 and D200 will be reversed.
D201 D200 D201 D200 D200

3-13 Special Math Instructions

This section describes instructions used for special math calculations.
Instruction BINARY ROOT BCD SQUARE ROOT ARITHMETIC PROCESS FLOATING POINT DIVIDE BIT COUNTER Mnemonic ROTB ROOT APR FDIV BCNT Function code 620 072 069 079 067 Page 451 453 456 467 470

3-13-1 BINARY ROOT: ROTB(620)

Purpose Computes the square root of the 32-bit signed binary contents (positive value) of the specified words and outputs the integer portion of the result to the specified result word.

Ladder Symbol
ROTB(620) S R S: First source word R: Result word

451

Special Math Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-13

ROTB(620) @ROTB(620) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

Description

ROTB(620) computes the square root of the 32-bit binary number in S+1 and S and outputs the integer portion of the result to R. The non-integer remainder is eliminated.
S+1 S R Binary data (16 bits)

Binary data (32 bits)

The range of data that can be specified for words S+1 and S is 0000 0000 to 3FFF FFFF. If a number from 4000 0000 to 7FFF FFFF is specified, it will be treated as 3FFF FFFF for the square root computation. An error will occur if the content of the source words is greater than 7FFF FFFF, i.e., if bit 15 of S+1 is 1. Flags
Name Error Flag Equals Flag Label ER = Operation ON if bit 15 of S+1 is 1 (ON). OFF in all other cases. ON if the result is 0000. OFF in all other cases.

452

Special Math Instructions

Name Overflow Flag Label OF

Section 3-13
Operation ON if the content of S+1 and S is 4000 0000 to 7FFF FFFF. OFF in all other cases. OFF OFF

Underflow Flag Negative Flag

UF N

Precautions

The content of S+1 and S must be less than 8000 0000. The operands of this instruction (S+1, S, and R) are all treated as binary values. If the input data is BCD, use the ROOT(072) instruction. When CIO 0.00 is ON in the following example, ROTB(620) calculates the square root of the data in CIO 1001 and CIO 1000, and writes the integer portion of the result in D100.
0.00 1000 D100

Example

CIO 1001 014B

CIO 1000 5A91 Square root computation (remainder eliminated)

D100 1234

3-13-2 BCD SQUARE ROOT: ROOT(072)

Purpose Ladder Symbol
ROOT(072) S R S: First source word R: Result word

Computes the square root of an 8-digit BCD number and outputs the integer portion of the result to the specified result word.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ROOT(072) @ROOT(072) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

453

Special Math Instructions

Area Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S *D0 to *D32767

Section 3-13
R

#00000000 to #99999999 --(BCD) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

ROOT(072) computes the square root of the 8-digit BCD number in S+1 and S and outputs the integer portion of the result to R. The non-integer remainder is eliminated.
S+1 S R BCD data (4 digits)

BCD data (8 digits)

Flags
Name Error Flag Equals Flag Label ER = Operation ON if the data in S+1 and S is not BCD. OFF in all other cases. ON if the result is 0000. OFF in all other cases.

Precautions Examples

The operands of this instruction (S+1, S, and R) are all treated as BCD values. If the input data is binary, use the ROTB(620) instruction. Square Root of 8-digit Number When CIO 0.00 is ON in the following example, ROOT(072) calculates the square root of the data in D101 and D100, and writes the integer portion of the result in D200. Note Figures after the decimal point are truncated for 8-digit numbers.
0.00 D100 D200

S+1: D101

S: D100

R: D200

Truncated

Square Root of a 4-digit Number The following example shows how to take the square root of a 4-digit number and round off the result. This program example calculates the square root of the 4-digit number in CIO 1000, rounds off the result, and writes it to CIO 2000. (Basically, the 4-digit number is multiplied by 10,000 (1002) and the result is divided by 100, increasing the precision of the calculation by a factor of 100.)

454

Special Math Instructions

Note

Section 3-13
Figures after the decimal point are rounded for 4-digit numbers.

The values after the decimal point should be rounded.

0.00
@BSET

D100 D101
@MOV

1000 D101
@ROOT

D100 D102
@MOV

2000
@MOV

D103
@MOVD

D102

5
2000
@MOVD

D102 D103
@INC

D103

2000

1,2,3...

1. The source words (D101 and D100) to be are cleared to 0000 0000. 2. The 4-digit number is moved from CIO 1000 to D101.
6 CIO 1000 0 1 7 D101 0 1 7 D100 0 0

3. ROOT(072) calculates the square root of D101 and D100 and writes the result to D102.

455

Special Math Instructions

D101 6017 D100 0000

Section 3-13

60, 170, 000 = 7, 756.932

D102 7756

Square root computation (Remainder eliminated)

4. D103 and the result word, CIO 2000, are cleared to 0000 0000. 5. The result of the square root calculation is divided by 100, with the integer portion written to CIO 2000 and the remainder going to D103.
7 D102 7 5 6

CIO 2000 0 7 7

D103 6 0 0

6. If the content of D103 is greater than 4900, CIO 2000 is incremented by 1. In this case, the result is 78.

5600 > 4900

CIO 2000 0 0 7 8

3-13-3 ARITHMETIC PROCESS: APR(069)

Purpose Calculates the sine, cosine, or a linear extrapolation of the source data. The linear extrapolation function allows any relationship between X and Y to be approximated with line segments.

Ladder Symbol
APR(069) C S R C: Control word S: Source data R: Result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification APR(069) @APR(069) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operands

Sine Function (C = 0000 Hex)

Operand Value C 0000 hex S 0000 to 0900 (BCD) D 0000 to 9999 (BCD) 9999 (BCD) Data range --0 to 90 0.0000 to 0.9999 1.0000

456

Special Math Instructions

Cosine Function (C = 0001 Hex)
Operand Value C 0001 hex S 0000 to 0900 (BCD) D 0000 to 9999 (BCD) 9999 (BCD)

Section 3-13

Data range --0 to 90 0.0000 to 0.9999 1.0000

Linear Extrapolation Function (C = Data area address)

Operand Value C Data area address S 16-bit unsigned BCD data 16-bit unsigned binary data 16-bit signed binary data1 32-bit signed binary data1 Floating-point data1 Data range --0000 to 9999 0 to 65,535 32,768 to 32,767 2,147,483,648 to 2,147,483,647 , 3.402823 1038 to 1.175494 1038, 1.175494 1038 to 3.402823 1038, + 0000 to 9999 0 to 65,535 32,768 to 32,767 2,147,483,648 to 2,147,483,647 , 3.402823 1038 to 1.175494 1038, 1.175494 1038 to 3.402823 1038, +

16-bit unsigned BCD data 16-bit unsigned binary data 16-bit signed binary data1 32-bit signed binary data1 Floating-point data1

Note

If C is a word address, APR(069) extrapolates the Y value for the X value in S based on coordinates (forming line segments) entered in advance in a table beginning at C. Refer to the Description section below for details.

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers C CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 Specified values only ----DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 S R

A448 to A959

457

Special Math Instructions

Description

Section 3-13
The operation of APR(069) depends on the control word C. If C is 0000 or 0001, APR(069) computes the sine or cosine of S with S in units of tenths of degrees. If C is a word address, APR(069) extrapolates the Y value for the X value in S based on coordinates (forming line segments) entered in advance in a table beginning at C. Sine Function (C=0000) When C is 0000, APR(069) calculates the SIN(S) and writes the result to R. The range for S is 0000 to 0900 BCD (0.0 to 90.0) and the range for R is 0000 to 9999 BCD (0.0000 to 0.9999). The remainder of the result beyond the fourth decimal place is eliminated. Cosine Function (C=0001) When C is 0001, APR(069) calculates the COS(S) and writes the result to R. The range for S is 0000 to 0900 BCD (0.0 to 90.0) and the range for R is 0000 to 9999 BCD (0.0000 to 0.9999). The remainder of the result beyond the fourth decimal place is eliminated. Linear Extrapolation APR(069) linear extrapolation is specified when C is a word address. The content of word C specifies the number of coordinates in a data table starting at C+2, the form of the source data, and whether data is BCD or binary. Unsigned Integer Data (Binary or BCD)
15 14 13 12 11 10 9 C 0 0 0 0 8 0 7 6 5 4 3 2 1 0

Number of coordinates minus one (m-1), 00 to FF hex (1 m 256) Floating-point specification for S and D 0: Integer data Signed data specification for S and D 0: Unsigned binary data Source data form 0: f(x) = f(S) 1: f(x) = f(Xm S) Output (D) data format 0: Binary 1: BCD Input (S) data format 0: Binary 1: BCD

458

Special Math Instructions

Signed Integer Data (Binary)
15 14 13 12 11 10 9 C 0 0 0 0 1 0 8 0 7 6 5 4 3 2 1 0

Section 3-13

Number of coordinates minus one (m-1), 00 to FF hex (1 m 256) Floating-point specification for S and D 0: Integer data Data length specification for S and D (note 1) 0: 16-bit signed binary data 1: 32-bit signed binary data Signed data specification for S and D 1: Signed binary data

Single-precision Floating-point Data

15 14 13 12 11 10 9 C 0 0 0 0 0 0 1 8 0 7 6 5 4 3 2 1 0

Number of coordinates minus one (m-1), 00 to FF hex (1 m 256) Floating-point specification for S and D 1: Single-precision floating-point data

If 16-bit binary or BCD data is being used, the line-segment data is contained in words C+1 through C+2m+2. If 32-bit binary or floating point data is being used, the line-segment data is contained in words C+1 through C+4m+4. Bits 00 to 07 contain the number (binary) of line coordinates less 1, m1. Bits 08 to 12 are not used. Bit 13 specifies either f(x)=f(S) or f(x)=f(XmS): OFF specifies f(x)=f(S) and ON specifies f(x)=f(XmS). Bit 14 determines whether the output is BCD or binary: OFF specifies binary and ON specifies BCD. Bit 15 determines whether the input is BCD or binary: OFF specifies binary and ON specifies BCD.
16-bit BCD16-bit binary (signed or unsigned) or 16-bit BCD data
C+1 C+2 C+3 C+4 C+5 C+6 X0 (*1) Y0 X1 Y1 X2 Y2

32-bit signed binary data

C+1 X0 (rightmost 16 bits) C+2 X0 (leftmost 16 bits) C+3 Y0 (rightmost 16 bits) C+4 Y0 (leftmost 16 bits) C+5 X1 (rightmost 16 bits) C+6 X1 (leftmost 16 bits) C+7 Y1 (rightmost 16 bits) C+8 Y1 (leftmost 16 bits)

Floating-point data
C+1 X0 (rightmost 16 bits) C+2 X0 (leftmost 16 bits) C+3 Y0 (rightmost 16 bits) C+4 Y0 (leftmost 16 bits) C+5 X1 (rightmost 16 bits) C+6 X1 (leftmost 16 bits) C+7 Y1 (rightmost 16 bits) C+8 Y1 (leftmost 16 bits)

Xn Yn

to

to

to

to

C+ (4n+1) Xn (rightmost 16 bits) C+ (4n+2) Xn (leftmost 16 bits) C+ (4n+3) Yn (rightmost 16 bits) C+ (4n+4) Yn (leftmost 16 bits)

C+ (4n+1) Xn (rightmost 16 bits) C+ (4n+2) Xn (leftmost 16 bits) C+ (4n+3) Yn (rightmost 16 bits) C+ (4n+4) Yn (leftmost 16 bits)

C+ (2m+1) C+ (2m+2)

Xm Ym

Note: Write Xm (max. X to to value in the table) in word C+1 when the I/O data in C+ (4m+1) Xm (rightmost 16 bits) S and D contain signed data (bit 11 of C = 0). C+ (4m+2) Xm (leftmost 16 bits)
C+ (4m+3) Ym (rightmost 16 bits) C+ (4m+4) Ym (leftmost 16 bits)

to

to

C+ (4m+1) Xm (rightmost 16 bits) C+ (4m+2) Xm (leftmost 16 bits) C+ (4m+3) Ym (rightmost 16 bits) C+ (4m+4) Ym (leftmost 16 bits)

459

Special Math Instructions

Note

Section 3-13
The X coordinates must be in ascending order: X1 < X2 < ... < Xm. Input all values of (Xn, Yn) as binary data, regardless of the data format specified in control word C. Operation of the Linear Extrapolation Function APR(069) processes the input data specified in S with the following equation and the line-segment data (Xn, Yn) specified in the table beginning at C+1. The result is output to the destination word(s) specified with D.

Y (Binary data)
Ymax

Y0

X0 A B

Xmax C

X (Binary data)

1. For S < X0 Converted value = Y0 2. For X0 S Xmax, if Xn < S < Xn+1 Converted value = Yn +[{Yn + 1 Yn}/{Xn + 1 Xn}] [Input data S Xn}
Y (binary data) Equation: Yn+1Yn f(Y)= Yn+ Xn+1Xn (SXn) Yn+1

Calculation result

Yn+1Yn

Yn Xn+1Xn SXn Xn S Xn+1 X (binary data)

Input data

3. Xmax < S Converted value = Ymax Up to 256 endpoints can be stored in the line-segment data table beginning at C+1. The following 5 kinds of I/O data can be used: 16-bit unsigned BCD data 16-bit unsigned binary data 16-bit signed binary data 32-bit signed binary data Single-precision floating-point data

460

Special Math Instructions

Setting the Data Format in Control Word C

Section 3-13

16-bit Unsigned BCD Data The input data and/or the output data can be 16-bit unsigned BCD data. Also, the linear extrapolation function can be set to operate on the value specified in S directly or on XmS. (Xm is the maximum value of X in the line-segment data.)
Setting name Input data (S) format Output data (D) format Source data form Signed data specification for S and D Data length specification for S and D Floating-point specification Bit in C 15 14 13 11 10 09 Setting 0: Binary 1: BCD 0: Binary 1: BCD 0: Operate on S 1: Operate on XmS 0: Unsigned data Invalid (fixed at 16 bits) 0: Integer data

16-bit Unsigned Binary Data The input data and/or the output data can be 16-bit unsigned binary data. Also, the linear extrapolation function can be set to operate on the value specified in S directly or on XmS. (Xm is the maximum value of X in the line-segment data.)
Setting name Input data (S) format Output data (D) format Source data form Signed data specification for S and D Data length specification for S and D Floating-point specification Bit in C 15 14 13 11 10 09 Setting 0: Binary 1: BCD 0: Binary 1: BCD 0: Operate on S 1: Operate on XmS 0: Unsigned data Invalid (fixed at 16 bits) 0: Integer data

16-bit Signed Binary Data

Setting name Input data (S) format Output data (D) format Source data form Signed data specification for S and D Data length specification for S and D Floating-point specification Bit in C 15 14 13 11 10 09 Setting 0: Binary 0: Binary 0 1: Signed data 0: 16-bit signed binary data 0: Integer data

32-bit Signed Binary Data

Setting name Input data (S) format Output data (D) format Source data form Signed data specification for S and D Data length specification for S and D Floating-point specification Bit in C 15 14 13 11 10 09 Setting 0: Binary 0: Binary 0 1: Signed data 1: 32-bit signed binary data 0: Integer data

461

Special Math Instructions

Note

Section 3-13
If the Data length specification for S and D in bit 10 of C is set to 1 and a 16-bit constant is input for S, the input data will be converted to 32-bit signed binary before the linear extrapolation calculation.
Bit in C 15 14 13 11 10 09 Setting 0: Binary 0: Binary 0 0 0 1: Floating-point data

Floating-point Data
Setting name Input data (S) format Output data (D) format Source data form Signed data specification for S and D Data length specification for S and D Floating-point specification

Note Flags
Name Error Flag

If the Floating-point specification in bit 09 of C is set to 1, a constant cannot be input for S.

Label ER

Operation ON if C is a constant greater than 0001. ON if C is a word address but the X coordinates are not in ascending order (X1 X2 ... Xm). ON if C is a word address and bits 9, 11, and 15 of C indicate BCD input, but S is not BCD. ON if C is a word address and bit 9 of C indicates floatingpoint data, but S is a one-word constant. ON if C is 0000 or 0001 but S is not BCD between 0000 and 0900. OFF in all other cases. ON if the result is 0000. OFF in all other cases. ON if bit 15 of R is ON. OFF in all other cases.

Equals Flag Negative Flag

= N

Precautions

The actual result for SIN(90) and COS(0) is 1, but 9999 (0.9999) will be output to R. An error will occur if C is a constant greater than 0001. An error will occur if linear extrapolation is specified but the X coordinates are not in ascending order (X1 < X2 < ... < Xm). An error will occur if linear extrapolation is specified and BCD input is specified (bit 15 of C ON) but S is not BCD. An error will occur if a trigonometric function is specified (C=0000 or 0001) but S is not BCD between 0000 and 0900.

Examples

Sine Function (C: #0000) The following example shows APR(069) used to calculate the sine of 30.
0.00

Source data
S: D0 0
D0 D100

Result
R: D100 101 0
1

101 3

100 0

101 5

102 0

103 0

104 0

Set the source data in 10 degrees. (0000 to 0900, BCD)

Result data has four significant digits, fifth and higher digits are ignored. (0000 to 9999, BCD)

462

Special Math Instructions

Cosine Function (C: #0001)

Section 3-13

The following example shows APR(069) used to calculate the cosine of 30. (SIN(30) = 0.8660)
0.00

Source data
S: D10 0
D10 D200

Result
R: D200 101 0 101 8 102 6 103 6 104 0

101 3

100 0

Set the source data in 101 degrees. (0000 to 0900, BCD)

Result data has four significant digits, fifth and higher digits are ignored. (0000 to 9999, BCD)

Linear Extrapolation (C: Word Address) Using 16-bit Unsigned BCD or Binary Data APR(069) processes the input data specified in S based on the control data in C and the line-segment data specified in the table beginning at C+1. The result is output to D.
Y

Word C+1 C+2 C+3 C+4

Coordinate Xm (max. X value) Y0 X1 Y1 X2 Y2 Xm (max. X value) Ym

Ym

Y4

Y3 Y1

C+5 C+6 C+(2m+1) C+(2m+2)

X X0 X1 X2 X3 X4 Xm

Y2 Y0

Yn = f(Xn), Y0 = f(X0) Be sure that Xn1 < Xn in all cases. Input all values of (Xn, Yn) as binary data.
0.00 D1000 1000 1001

This example shows how to construct a linear extrapolation with 12 coordinates. The block of data is continuous, as it must be, from D1000 to D1026 (C to C + (2 12 + 2)). The input data is taken from CIO 1000, and the result is output to CIO 1001.
Content Coordinate

Bit 15

Bit 00

D1000 D1001 D1002 D1003 D1004 D1005 D1006 D1025 D1026

000B Hex 05F0 Hex 0000 Hex 0005 Hex 0F00 Hex 001A Hex 0402 Hex

0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 X12 Y0 X1 Y1 X2 Y2 x=S Output and input both binary (m1 = 11: 12 coordinates)

05F0 Hex X12 1F20 Hex Y12

463

Special Math Instructions

Section 3-13
In this case, the source word, CIO 1000, contains 0014, and f(0014) = 0726 is output to R, CIO 1001.
Y $1F20

$0F00

(x,y) $0726 $0402 X (0,0) $0005 $0014 $001A $05F0

The linear-extrapolation calculation is shown below. 0402 0F00 - ( 0014 0015 ) Y = 0F00 + -------------------------------001A 0005 = 0F00 ( 0086 000F ) = 0726

Values are all hexadecimal (hex).

464

Special Math Instructions

Linear Extrapolation (C: Word Address) Using 32-bit Signed Binary Data

Section 3-13

In this example, APR(069) is used to convert the fluid height in a tank to fluid volume based on the shape of the holding tank.
Fluid height to volume conversion table (32-bit signed binary data)
C+1 X0 (rightmost 16 bits) C+2 X0 (leftmost 16 bits) C+3 Y0 (rightmost 16 bits) C+4 Y0 (leftmost 16 bits)

Variation from standard = X Fluid volume= Y

C+5 X1 (rightmost 16 bits) C+6 X1 (leftmost 16 bits) C+7 Y1 (rightmost 16 bits) C+8 Y1 (leftmost 16 bits)

to

to

C+ (4n+1) Xn (rightmost 16 bits) C+ (4n+2) Xn (leftmost 16 bits) C+ (4n+3) Yn (rightmost 16 bits) C+ (4n+4) Yn (leftmost 16 bits)

to

to

C+ (4m+1) Xm (rightmost 16 bits) C+ (4m+2) Xm (leftmost 16 bits) C+ (4m+3) Ym (rightmost 16 bits) C+ (4m+4) Ym (leftmost 16 bits) 0.00

APR C S R
Linear extrapolation of table

Y: Fluid volume

Ym

R R+1
Y data range: 2,147,483,648 to 2,147,483,647

X: Variation from standard The linear extrapolation can use signed source data if 32-bit signed binary data is used.

Y0

X0

Xm S S+1
High-resolution 32-bit signed binary data X data range: 2,147,483,648 to 2,147,483,647

465

Special Math Instructions

Linear Extrapolation (C: Word Address) Using Floating-point Data

Section 3-13

In this example, APR(069) is used to convert the fluid height in a tank to fluid volume based on the shape of the holding tank.
C+1 X0 (rightmost 16 bits)

Fluid height to volume conversion table (Floating-point data)

C+2 X0 (leftmost 16 bits) C+3 Y0 (rightmost 16 bits) C+4 Y0 (leftmost 16 bits) C+5 X1 (rightmost 16 bits) C+6 X1 (leftmost 16 bits) C+7 Y1 (rightmost 16 bits) C+8 Y1 (leftmost 16 bits)

Fluid volume =Y

Fluid height = X

to

to

C+ (4n+1) Xn (rightmost 16 bits) C+ (4n+2) Xn (leftmost 16 bits) C+ (4n+3) Yn (rightmost 16 bits) C+ (4n+4) Yn (leftmost 16 bits)

to

to

C+ (4m+1) Xm (rightmost 16 bits) C+ (4m+2) Xm (leftmost 16 bits) C+ (4m+3) Ym (rightmost 16 bits) C+ (4m+4) Ym (leftmost 16 bits) 0.00

APR C S R
Linear extrapolation of table

Y: Fluid volume

Ym
Y data range: , 3.402823 1038 to 1.175494 1038, 1.175494 1038 to 3.402823 1038, or +

R R+1

The linear extrapolation can provide a smooth, high-resolution curve floating-point data is used.

Y0

X0 S S+1

Xm

X: Fluid height

High-resolution floating point data

X data range: , 3.402823 1038 to 1.175494 1038, 1.175494 1038 to 3.402823 1038, or +

466

Special Math Instructions

Section 3-13

3-13-4 FLOATING POINT DIVIDE: FDIV(079)

Purpose Divides one 7-digit floating-point number by another. The floating-point numbers are expressed in scientific notation (7-digit mantissa and 1-digit exponent).

Ladder Symbol
FDIV(079) Dd Dr R Dd: First dividend word Dr: First divisor word R: First result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification FDIV(079) @FDIV(079) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Dd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Dr R

A448 to A958

Description

FDIV(079) divides the floating-point value in Dd and Dd+1 by that in Dr and Dr+1 and places the result in R and R+1.
Quotient R+1 R

Dr+1

Dr

Dd+1

Dd

467

Special Math Instructions

Section 3-13
To represent the floating-point values, the rightmost seven digits are used for the mantissa and the leftmost digit is used for the exponent, as shown in the diagram below. The leftmost digit can range from 0 to F; positive exponents range from 0 to 7 and negative exponents range from 8 to F (0 to 7). The rightmost 7 digits must be BCD.

First word 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 1 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1

Second word 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1

Exponent (0 to 7) Sign of exponent 0: + 1:

Mantissa (leftmost 3 digits)

Mantissa (rightmost 4 digits)

= 0.1111113 x 10 2

Two more examples of floating-point values are: 6123 4567: 0.1234567 106 (6 = 0110 binary) B123 4567: 0.1234567 103 (B = 1011 binary) The following table shows the maximum and minimum values allowed.
Limit Maximum value Minimum value (Divisor and dividend) Minimum value (Result) 8-digit hexadecimal 7999 9999 F000 0001 F100 0000 Floating-point 0.9999999 107 0.0000001 107 0.1000000 107

Flags
Name Error Flag Label ER Operation ON if the mantissa (leftmost 7 digits) in Dd+1 and Dd is not BCD. ON if the mantissa (leftmost 7 digits) in Dr+1 and Dr is not BCD. ON if the divisor (Dr+1 and Dr) is 0. ON if the result is not between 0.1000000 107 and 0.9999999 107. OFF in all other cases. ON if the result is 0. OFF in all other cases.

Equals Flag

Precautions

The result is expressed as a floating-point value, so it has 7 significant digits. The eighth and higher digits are eliminated. The result must be between 0.1000000 107 and 0.9999999 107.

Examples

Basic Floating-point Division When CIO 0.00 is ON in the following example, FDIV(079) divides the floating-point number in D101 and D100 by the floating-point number in CIO 201 and CIO 200 and writes the result to D301 and D300.
0.00

A
D100 200 D300

D101 5 6

D100 0 0

0.5670000 102 0.1234567 103

CIO 201 1 2 3 D301 4 5 9

CIO 200 5 6 7 D300 7 0

0.4592703 102

468

Special Math Instructions

Floating-point Division of Two BCD Numbers

Section 3-13

In this example, the 4-digit BCD number in D0 is divided by the 4-digit BCD number in D1 and the floating-point result is written to D2 and D3. To perform the floating point division, the BCD value in D0 is converted to floating-point format in D2001 and D2000 and the BCD value in D1 is converted to floating-point format in D2003 and D2002.
0.00
@MOV

#0 D2000
@MOV

#0 D2002
@MOV

D2001
@MOV

D2003
@MOVD

D0 #21 D2001
@MOVD

D0 #300 D2000
@MOVD

D1 #21 D2003
@MOVD

D1 #300 D2002
@FDIV

D2000 D2002 D2

469

Special Math Instructions

1,2,3...

Section 3-13
1. D2000 and D2002 are set to 0000 and D2001 and D2003 are set to 4000.
Dividend
D0

Divisor
D1

D2001

D2000

D2003

D2002

#4000 transferred. (3452 = 0.3452 x 104 0079 = 0.0079 x 104)

#0000 transferred. (D2000 and D2002 cleared.)

2. MOVD(083) is used to move the digits of the original source words to the proper digits in the 2-word floating-point formats.
3 D1000 4 5 2 D2000 0 0 0 D1001 0 7 9 D2002 0 0 0

D2001 3 4 5

D2003 0 0 7

3. FDIV(079) divides the floating-point number in D2001 and D2000 by the floating-point number in D2003 and D2002.
4 D2001 3 4 5 2 D2000 0 0 0 0.3452000 104

D2003 0 0 7 D3

D2002 0 0 D2

0.0079000 104

0.4369620 102

3-13-5 BIT COUNTER: BCNT(067)

Purpose Ladder Symbol
BCNT(067) N S R N: Number of words S: First source word R: Result word

Counts the total number of ON bits in the specified word(s).

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification BCNT(067) @BCNT(067) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

470

Special Math Instructions

Operands N: Number of words

Section 3-13

The number of words must be 0001 to FFFF (1 to 65,535 words). S: First source word S and S+(N1) must be in the same data area. Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants N CIO 0 to CIO 6143 W0 to W511 H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767 #0001 to #FFFF --(binary) or &1 to &65,535 DR0 to DR15 --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 S R

A448 to A959

Data Registers Index Registers Indirect addressing using Index Registers

Description

BCNT(067) counts the total number of bits that are ON in all words between S and S+(N1) and places the result in R.
N words Counts the number of ON bits. Binary result R

to S+(N1)

Flags
Name Error Flag Label ER Operation ON if N is 0000. ON if result exceeds FFFF. OFF in all other cases. ON if the result is 0000. OFF in all other cases.

Equals Flag

Precautions

An error will occur if N=0000 or the result exceeds FFFF.

471

Floating-point Math Instructions

Example

Section 3-14

When CIO 0.00 is ON in the following example, BCNT(067) counts the total number of ON bits in the 10 words from CIO 200 and CIO 209 and writes the result to D1000.
0.00 BCNT

N S R

&10 200 D1000

10 words

200 201 to 209 to

Counts the number of ON bits (35).

R:D1000

23 hexadecimal (35 decimal)

3-14 Floating-point Math Instructions

The Floating-point Math Instructions convert data and perform floating-point arithmetic operations.
Instruction FLOATING TO 16-BIT FLOATING TO 32-BIT 16-BIT TO FLOATING 32-BIT TO FLOATING FLOATING-POINT ADD FLOATING-POINT SUBTRACT FLOATING-POINT MULTIPLY FLOATING-POINT DIVIDE DEGREES TO RADIANS RADIANS-TO-DEGREES SINE COSINE TANGENT ARC SINE ARC COSINE ARC TANGENT SQUARE ROOT EXPONENT LOGARITHM EXPONENTIAL POWER Mnemonic FIX FIXL FLT FLTL +F F *F /F RAD DEG SIN COS TAN ASIN ACOS ATAN SQRT EXP LOG PWR Function code 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 840 Page 478 480 481 483 484 486 488 490 492 493 495 496 498 500 502 503 505 507 509 511

Refer to 3-15-21 Double-precision Floating-point Input Instructions for details on double-precision floating-point instructions.
Instruction Single-precision Floatingpoint Symbol Comparison Instructions FLOATING-POINT TO ASCII ASCII TO FLOATINGPOINT Mnemonic Function code LD, AND, OR 329 to 334 + =F, <>F, <F, <=F, >F, or >=F FSTR 448 FVAL 449 Page 512

516 521

472

Floating-point Math Instructions

Data Format

Section 3-14

Floating-point data expresses real numbers using a sign, exponent, and mantissa. When data is expressed in floating-point format, the following formula applies. Real number = (1)s 2e127 (1.f) s: Sign e: Exponent f: Mantissa The floating-point data format conforms to the IEEE754 standards. Data is expressed in 32 bits, as follows:
Sign s 31 30 Exponent e 23 22 Mantissa f 0

Data s: sign e: exponent

No. of bits 1 8

f: mantissa

23

Contents 0: positive; 1: negative The exponent (e) value ranges from 0 to 255. The actual exponent is the value remaining after 127 is subtracted from e, resulting in a range of 127 to 128. e=0 and e=255 express special numbers. The mantissa portion of binary floating-point data fits the formal 2.0 > 1.f 1.0.

Number of Digits Floating-point Data

The number of effective digits for floating-point data is 24 bits for binary (approximately seven digits decimal). The following data can be expressed by floating-point data: 3.402823 x 1038 value 1.402398 x 1045 0 1.402398 x 1045 value 3.402823 x 1038 + Not a number (NaN)
1.402398 x 10 3.402823 x 1038
45 45

1.402398 x 10

3.402823 x 1038 +

Special Numbers

The formats for NaN, , and 0 are as follows: NaN*: +: : 0: e = 255, f 0 e = 255, f = 0, s= 0 e = 255, f = 0, s= 1 e=0

*NaN (not a number) is not a valid floating-point number. Executing floatingpoint calculation instructions will not result in NaN.

473

Floating-point Math Instructions

Writing Floating-point Data

Section 3-14

When floating-point is specified for the data format in the I/O memory edit display in the CX-Programmer, standard decimal numbers input in the display are automatically converted to the floating-point format shown above (IEEE754-format) and written to I/O Memory. Data written in the IEEE754-format is automatically converted to standard decimal format when monitored on the display.
15 n n+1 s e f 7 6 0

It is not necessary for the user to be aware of the IEEE754 data format when reading and writing floating-point data. It is only necessary to remember that floating point values occupy two words each.

Numbers Expressed as Floating-point Values

The following types of floating-point numbers can be used.

Mantissa (f) 0 0 Not 0 0 Non-normalized number Exponent (e) Not 0 and All 1s (255) not all 1s Normalized number Infinity NaN

Note

A non-normalized number is one whose absolute value is too small to be expressed as a normalized number. Non-normalized numbers have fewer significant digits. If the result of calculations is a non-normalized number (including intermediate results), the number of significant digits will be reduced. Normalized numbers express real numbers. The sign bit will be 0 for a positive number and 1 for a negative number. The exponent (e) will be expressed from 1 to 254, and the real exponent will be 127 less, i.e., 126 to 127. The mantissa (f) will be expressed from 0 to 233 1, and it is assume that, in the real mantissa, bit 233 is 1 and the binary point follows immediately after it. Normalized numbers are expressed as follows: (1)(sign s) x 2(exponent e)127 x (1 + mantissa x 223) Example
31 30 23 22 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Normalized Numbers

Sign: Exponent: Mantissa: Value: Non-normalized Numbers

128 127 = 1 1 + (222 + 221) x 223 = 1 + (21 + 22) = 1 + 0.75 = 1.75 1.75 x 21 = 3.5

Non-normalized numbers express real numbers with very small absolute values. The sign bit will be 0 for a positive number and 1 for a negative number. The exponent (e) will be 0, and the real exponent will be 126. The mantissa (f) will be expressed from 1 to 233 1, and it is assume that, in the real mantissa, bit 233 is 0 and the binary point follows immediately after it. Non-normalized numbers are expressed as follows: (1)(sign s) x 2126 x (mantissa x 223)

474

Floating-point Math Instructions

Example
31 30 23 22 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Section 3-14

Sign: Exponent: Mantissa: Value: Zero

126 0 + (222 + 221) x 223 = 0 + (21 + 22) = 0 + 0.75 = 0.75 0.75 x 2126

Values of +0.0 and 0.0 can be expressed by setting the sign to 0 for positive or 1 for negative. The exponent and mantissa will both be 0. Both +0.0 and 0.0 are equivalent to 0.0. Refer to Floating-point Arithmetic Results, below, for differences produced by the sign of 0.0. Values of + and can be expressed by setting the sign to 0 for positive or 1 for negative. The exponent will be 255 (28 1) and the mantissa will be 0. NaN (not a number) is produced when the result of calculations, such as 0.0/ 0.0, /, or , does not correspond to a number or infinity. The exponent will be 255 (28 1) and the mantissa will be not 0. Note There are no specifications for the sign of NaN or the value of the mantissa field (other than to be not 0).

Infinity NaN

Floating-point Arithmetic Results

Rounding Results The following methods will be used to round results when the number of digits in the accurate result of floating-point arithmetic exceeds the significant digits of internal processing expressions. If the result is close to one of two internal floating-point expressions, the closer expression will be used. If the result is midway between two internal floating-point expressions, the result will be rounded so that the last digit of the mantissa is 0. Overflows, Underflows, and Illegal Calculations Overflows will be output as either positive or negative infinity, depending on the sign of the result. Underflows will be output as either positive or negative zero, depending on the sign of the result. Illegal calculations will result in NaN. Illegal calculations include adding infinity to a number with the opposite sign, subtracting infinity from a number with the opposite sign, multiplying zero and infinity, dividing zero by zero, or dividing infinity by infinity. The value of the result may not be correct if an overflow occurs when converting a floating-point number to an integer. Precautions in Handling Special Values The following precautions apply to handling zero, infinity, and NaN. The sum of positive zero and negative zero is positive zero. The difference between zeros of the same sign is positive zero. If any operand is a NaN, the results will be a NaN. Positive zero and negative zero are treated as equivalent in comparisons. Comparison or equivalency tests on one or more NaN will always be true for != and always be false for all other instructions.

Floating-point Calculation Results

When the absolute value of the result is greater than the maximum value that can be expressed for floating-point data, the Overflow Flag will turn ON and the result will be output as . If the result is positive, it will be output as +; if negative, then .

475

Floating-point Math Instructions

Section 3-14

The Equals Flag will only turn ON when both the exponent (e) and the mantissa (f) are zero after a calculation. A calculation result will also be output as zero when the absolute value of the result is less than the minimum value that can be expressed for floating-point data. In that case the Underflow Flag will turn ON. Example In this program example, the X-axis and Y-axis coordinates (x, y) are provided by 4-digit BCD content of D0 and D1. The distance (r) from the origin and the angle (, in degrees) are found and output to D100 and D101. In the result, everything to the right of the decimal point is truncated.
y P (100, 100)

476

Floating-point Math Instructions

0.00 D0 D200

Section 3-14
(1)

D1 D201

D200 D202

D201 D204

(2)
D202 D202 D206

D204 D204 D208

D206 D208 D210

D210 D212

(3)
D204 D202 D214

D214 D216

D216 D218

(4)
D212 D220

D218 D221

D220 D100

D221 D101

477

Floating-point Math Instructions

Calculations Distance r = Angle
+y
2 2

Section 3-14
Example Distance r = Angle
100 + 100 = 141.4214
2 2

= tan-1 (

y x

)
x y

= tan-1 (

100 100

) ( 180 ) = 45.0
r

DM Contents D0 D1 #0100 (BCD) #0100 (BCD) D100 0 1 4 1 (BCD) D101 0 0 4 5 (BCD)

1. This section of the program converts the data from BCD to floating-point. a. The data area from D200 onwards is used as a work area. b. First BIN(023) is used to temporarily convert the BCD data to binary data, and then FLT(452) is used to convert the binary data to floatingpoint data. The value of x that has been converted to floating-point data is output to D203 and D202.

c.

d. The value of y that has been converted to floating-point data is output to D205 and D204. 2. In order to find the distance r, Floating-point Math Instructions are used to calculate the square root of x2+y2. The result is then output to D213 and D212 as floating-point data. 3. In order to find the angle , Floating-point Math Instructions are used to calculate tan1 (y/x). ATAN(465) outputs the result in radians, so DEG(459) is used to convert to degrees. The result is then output to D219 and D218 as floating-point data. 4. The data is converted back from floating-point to BCD. a. First FIX(450) is used to temporarily convert the floating-point data to binary data, and then BCD(024) is used to convert the binary data to BCD data. b. c. The distance r is output to D100. The angle is output to D101.

3-14-1 FLOATING TO 16-BIT: FIX(450)

Purpose Ladder Symbol
FIX(450) S R S: First source word R: Result word

Converts a 32-bit floating-point value to 16-bit signed binary data and places the result in the specified result word.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification FIX(450) @FIX(450) Not supported. Not supported.

478

Floating-point Math Instructions

Applicable Program Areas
Block program areas Step program areas OK OK Subroutines OK

Section 3-14

Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) --DR0 to DR15 --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R CIO 0 to CIO 6143 W0 to W511 H0 to H511 A448 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767

Description

FIX(450) converts the integer portion of the 32-bit floating-point number in S+1 and S (IEEE754-format) to 16-bit signed binary data and places the result in R.
S+1 S

Floating-point data (32 bits)

Signed binary data (16 bits)

Only the integer portion of the floating-point data is converted, and the fraction portion is truncated. The integer portion of the floating-point data must be within the range of 32,768 to 32,767. Example conversions: A floating-point value of 3.5 is converted to 3. A floating-point value of 3.5 is converted to 3. Flags
Name Error Flag Label ER Operation ON if the data in S+1 and S is not a number (NaN). ON if the integer portion of S+1 and S is not within the range of 32,768 to 32,767. OFF in all other cases. ON if the result is 0000. OFF in all other cases. ON if bit 15 of the result is ON. OFF in all other cases.

Equals Flag Negative Flag

= N

479

Floating-point Math Instructions

Precautions

Section 3-14

The content of S+1 and S must be floating-point data and the integer portion must be in the range of 32,768 to 32,767.

3-14-2 FLOATING TO 32-BIT: FIXL(451)

Purpose Ladder Symbol
FIXL(451) S R S: First source word R: First result word

Converts a 32-bit floating-point value to 32-bit signed binary data and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification FIXL(451) @FIXL(451) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ()IR15 R

A448 to A958

480

Floating-point Math Instructions

Description

Section 3-14

FIXL(451) converts the integer portion of the 32-bit floating-point number in S+1 and S (IEEE754-format) to 32-bit signed binary data and places the result in R+1 and R.
S+1 S

Floating-point data (32 bits) Signed binary data (32 bits)

R+1

Only the integer portion of the floating-point data is converted, and the fraction portion is truncated. (The integer portion of the floating-point data must be within the range of 2,147,483,648 to 2,147,483,647.) Example conversions: A floating-point value of 2,147,483,640.5 is converted to 2,147,483,640. A floating-point value of 214,748,340.5 is converted to 214,748,340. Flags
Name Error Flag Label ER Operation ON if the data in S+1 and S is not a number (NaN). ON if the integer portion of S+1 and S is not within the range of 2,147,483,648 to 2,147,483,647. OFF in all other cases. ON if the result is 0000 0000. OFF in all other cases. ON if bit 15 of R+1 is ON after execution. OFF in all other cases.

Equals Flag Negative Flag

= N

Precautions

The content of S+1 and S must be floating-point data and the integer portion must be in the range of 2,147,483,648 to 2,147,483,647.

3-14-3 16-BIT TO FLOATING: FLT(452)

Purpose Ladder Symbol
FLT(452) S R S: Source word R: First result word

Converts a 16-bit signed binary value to 32-bit floating-point data and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification FLT(452) @FLT(452) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area S CIO 0 to CIO 6143 W0 to W511 R CIO 0 to CIO 6142 W0 to W510

481

Floating-point Math Instructions

Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S H0 to H511 A0 to A959 T0000 to T4095 C0000 to C4095 D0 to D32767 @ D0 to @ D32767 *D0 to *D32767

Section 3-14
R H0 to H510 A448 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766

#0000 to #FFFF (binary) --DR0 to DR15 ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

FLT(452) converts the 16-bit signed binary value in S to 32-bit floating-point data (IEEE754-format) and places the result in R+1 and R. A single 0 is added after the decimal point in the floating-point result.
S

Signed binary data (16 bits)

R+1

Floating-point data (32 bits)

Only values within the range of 32,768 to 32,767 can be specified for S. To convert signed binary data outside of that range, use FLTL(453). Example conversions: A signed binary value of 3 is converted to 3.0. A signed binary value of 3 is converted to 3.0. Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the result is negative. OFF in all other cases.

Precautions

The content of S must contain signed binary data with a (decimal) value in the range of 32,768 to 32,767.

482

Floating-point Math Instructions

Section 3-14

3-14-4 32-BIT TO FLOATING: FLTL(453)

Purpose Ladder Symbol
FLTL(453) S R S: First source word R: First result word

Converts a 32-bit signed binary value to 32-bit floating-point data and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification FLTL(453) @FLTL(453) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

FLTL(453) converts the 32-bit signed binary value in S+1 and S to 32-bit floating-point data (IEEE754-format) and places the result in R+1 and R. A single 0 is added after the decimal point in the floating-point result.
S+1 S

Signed binary data (32 bits)

R+1

Floating-point data (32 bits)

483

Floating-point Math Instructions

Section 3-14

Signed binary data within the range of 2,147,483,648 to 2,147,483,647 can be specified for S+1 and S. The floating point value has 24 significant binary digits (bits). The result will not be exact if a number greater than 16,777,215 (the maximum value that can be expressed in 24-bits) is converted by FLTL(453). Example Conversions: A signed binary value of 16,777,215 is converted to 16,777,215.0. A signed binary value of 16,777,215 is converted to 15,777,215.0. Flags
Name Error Flag Equals Flag Negative Flag Label ER = N Operation OFF ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the result is negative. OFF in all other cases.

Precautions

The result will not be exact if a number with an absolute value greater than 16,777,215 (the maximum value that can be expressed in 24-bits) is converted.

3-14-5 FLOATING-POINT ADD: +F(454)

Purpose Ladder Symbol
+F(454) Au Ad R Au: First augend word AD: First addend word R: First result word

Adds two 32-bit floating-point numbers and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification +F(454) @+F(454) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Au CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 Ad R

A448 to A958

484

Floating-point Math Instructions

Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Au @ D0 to @ D32767 *D0 to *D32767 Ad

Section 3-14
R

#00000000 to #FFFFFFFF (binary) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

+F(454) adds the 32-bit floating-point number in Ad+1 and Ad to the 32-bit floating-point number in Au+1 and Au and places the result in R+1 and R. (The floating point data must be in IEEE754 format.)
Au+1 Au Ad

Augend (floating-point data, 32 bits) Addend (floating-point data, 32 bits)

Ad+1

R+1

Result (floating-point data, 32 bits)

If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. The various combinations of augend and addend data will produce the results shown in the following table.
Addend 0 Numeral + NaN 0 0 Numeral + Numeral Numeral See note 1. + Augend + + + + See note 2. See note 2. See note 2. NaN

Note

(1) The results could be zero (including underflows), a numeral, +, or . (2) The Error Flag will be turned ON and the instruction will not be executed.

Flags
Name Error Flag Label ER Operation ON if the augend or addend data is not recognized as floating-point data. ON if the augend or addend data is not a number (NaN). ON if + and are added. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases.

Equals Flag

485

Floating-point Math Instructions

Name Overflow Flag Underflow Flag Negative Flag Label OF UF N

Section 3-14
Operation ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. ON if the result is negative. OFF in all other cases.

Precautions

The augend (Au+1 and Au) and Addend (Ad+1 and Ad) data must be in IEEE754 floating-point data format.

3-14-6 FLOATING-POINT SUBTRACT: F(455)

Purpose Ladder Symbol
F(455) Mi Su R Mi: First Minuend word Su: First Subtrahend word R: First result word

Subtracts one 32-bit floating-point number from another and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification F(455) @F(455) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Mi CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ----Su R

A448 to A958

486

Floating-point Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-14
Mi Su --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

Description

F(455) subtracts the 32-bit floating-point number in Su+1 and Su from the 32-bit floating-point number in Mi+1 and Mi and places the result in R+1 and R. (The floating point data must be in IEEE754 format.)
Mi+1 Mi Su

Minuend (floating-point data, 32 bits) Subtrahend (floating-point data, 32 bits)

Su+1

R+1

Result (floating-point data, 32 bits)

If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. The various combinations of minuend and subtrahend data will produce the results shown in the following table.
Subtrahend 0 Numeral + NaN 0 0 Numeral + Numeral Numeral See note 1. + Minuend + + + See note 2. + See note 2. NaN

See note 2.

Note

(1) The results could be zero (including underflows), a numeral, +, or . (2) The Error Flag will be turned ON and the instruction will not be executed.

Flags
Name Error Flag Label ER Operation ON if the minuend or subtrahend data is not recognized as floating-point data. ON if the minuend or subtrahend is not a number (NaN). ON if + is subtracted from +. ON if is subtracted from . OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

487

Floating-point Math Instructions

Precautions

Section 3-14

The Minuend (Mi+1 and Mi) and Subtrahend (Su+1 and Su) data must be in IEEE754 floating-point data format.

3-14-7 FLOATING-POINT MULTIPLY: *F(456)

Purpose Ladder Symbol
*F(456) Md Mr R Md: First Multiplicand word Mr: First Multiplier word R: First result word

Multiplies two 32-bit floating-point numbers and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification *F(456) @*F(456) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Md CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Mr R

A448 to A958

488

Floating-point Math Instructions

Description

Section 3-14

*F(456) multiplies the 32-bit floating-point number in Md+1 and Md by the 32bit floating-point number in Mr+1 and Mr and places the result in R+1 and R. (The floating point data must be in IEEE754 format.)
Md+1 Md Mr

Multiplicand (floating-point data, 32 bits) Multiplier (floating-point data, 32 bits)

Mr+1

R+1

Result (floating-point data, 32 bits)

If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. The various combinations of multiplicand and multiplier data will produce the results shown in the following table.
Multiplier 0 Numeral + NaN 0 0 0 See note 2. See note 2 Numeral 0 See note 1. +/ +/ Multiplicand + See note 2. See note 2. +/ +/ + + NaN

See note 2.

Note

(1) The results could be zero (including underflows), a numeral, +, or . (2) The Error Flag will be turned ON and the instruction will not be executed.

Flags
Name Error Flag Label ER Operation ON if the multiplicand or multiplier data is not recognized as floating-point data. ON if the multiplicand or multiplier is not a number (NaN). ON if + and 0 are multiplied. ON if and 0 are multiplied. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The Multiplicand (Md+1 and Md) and Multiplier (Mr+1 and Mr) data must be in IEEE754 floating-point data format.

489

Floating-point Math Instructions

Section 3-14

3-14-8 FLOATING-POINT DIVIDE: /F(457)

Purpose Ladder Symbol
/F(457) Dd Dr R Dd: First Dividend word Dr: First Divisor word R: First result word

Divides one 32-bit floating-point number by another and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification /F(457) @/F(457) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers Dd CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ------,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 Dr R

A448 to A958

490

Floating-point Math Instructions

Description

Section 3-14

/F(457) divides the 32-bit floating-point number in Dd+1 and Dd by the 32-bit floating-point number in Dr+1 and Dr and places the result in R+1 and R. (The floating point data must be in IEEE754 format.)
Dd+1 Dd Dr

Dividend (floating-point data, 32 bits) Divisor (floating-point data, 32 bits)

Dr+1

R+1

Result (floating-point data, 32 bits)

If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. The various combinations of dividend and divisor data will produce the results shown in the following table.
Divisor 0 Numeral + NaN 0 See note 3. 0 0 0 Numeral +/ See note 1. See note 2. See note 2. Dividend + + +/ See note 3. See note 3. +/ See note 3. See note 3. NaN

See note 3.

Note

(1) The results could be zero (including underflows), a numeral, +, or . (2) The results will be zero for underflows. (3) The Error Flag will be turned ON and the instruction will not be executed.

Flags
Name Error Flag Label ER Operation ON if the dividend or divisor data is not recognized as floating-point data. ON if the dividend or divisor is not a number (NaN). ON if the dividend and divisor are both 0. ON if the dividend and divisor are both + or . OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The Dividend (Dd+1 and Dd) and Divisor (Dr+1 and Dr) data must be in IEEE754 floating-point data format.

491

Floating-point Math Instructions

Section 3-14

3-14-9 DEGREES TO RADIANS: RAD(458)

Purpose Ladder Symbol
RAD(458) S R S: First source word R: First result word

Converts a 32-bit floating-point number from degrees to radians and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification RAD(458) @RAD(458) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

RAD(458) converts the 32-bit floating-point number in S+1 and S from degrees to radians and places the result in R and R+1. (The floating point source data must be in IEEE754 format.)
S+1 S

Source (degrees, 32-bit floating-point data)

R+1

Result (radians, 32-bit floating-point data)

Degrees are converted to radians by means of the following formula:

492

Floating-point Math Instructions

Degrees /180 = radians

Section 3-14

If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-10 RADIANS TO DEGREES: DEG(459)

Purpose Ladder Symbol
DEG(459) S R S: First source word R: First result word

Converts a 32-bit floating-point number from radians to degrees and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification DEG(459) @DEG(459) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 R

A448 to A958

493

Floating-point Math Instructions

Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S D0 to D32766 @ D0 to @ D32767 *D0 to *D32767

Section 3-14
R

#0000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to+2047 ,IR0 to 2048 to+2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

DEG(459) converts the 32-bit floating-point number in S+1 and S from radians to degrees and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
S+1 S

Source (radians, 32-bit floating-point data)

R+1

Result (degrees, 32-bit floating-point data)

Radians are converted to degrees by means of the following formula: Radians 180/ = degrees If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

494

Floating-point Math Instructions

Section 3-14

3-14-11 SINE: SIN(460)

Purpose Ladder Symbol
SIN(460) S R S: First source word R: First result word

Calculates the sine of a 32-bit floating-point number (in radians) and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SIN(460) @SIN(460) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

SIN(460) calculates the sine of the angle (in radians) expressed as a 32-bit floating-point value in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
SIN S+1 S

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

495

Floating-point Math Instructions

Section 3-14

Specify the desired angle (65,535 to 65,535) in radians in S+1 and S. If the angle is outside of the range 65,535 to 65,535, an error will occur and the instruction will not be executed. For information on converting from degrees to radians, see 3-14-19 LOGARITHM: LOG(468) DEGREES-TO-RADIANS: RAD(458). The following diagram shows the relationship between the angle and result.
R S: Angle (radian) data R: Result (sine)

Flags
Name Error Flag Label ER Operation ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 65,535. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. OFF OFF ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-12 COSINE: COS(461)

Purpose Ladder Symbol
COS(461) S R S: First source word R: First result word

Calculates the cosine of a 32-bit floating-point number (in radians) and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification COS(461) @COS(461) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

496

Floating-point Math Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767

Section 3-14

A448 to A958

#00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

COS(461) calculates the cosine of the angle (in radians) expressed as a 32bit floating-point value in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
COS S+1 S

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

Specify the desired angle (65,535 to 65,535) in radians in S+1 and S. If the angle is outside of the range 65,535 to 65,535, an error will occur and the instruction will not be executed. For information on converting from degrees to radians, see 3-14-9 DEGREES TO RADIANS: RAD(458). The following diagram shows the relationship between the angle and result.
R S: Angle (radian) data R: Result (cosine)

497

Floating-point Math Instructions

Flags
Name Error Flag Label ER

Section 3-14

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Operation ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 65,535. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. OFF OFF ON if the result is negative. OFF in all other cases.

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-13 TANGENT: TAN(462)

Purpose Ladder Symbol
TAN(462) S R S: First source word R: First result word

Calculates the tangent of a 32-bit floating-point number (in radians) and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification TAN(462) @TAN(462) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ----R

A448 to A958

498

Floating-point Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-14
S R --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

TAN(462) calculates the tangent of the angle (in radians) expressed as a 32bit floating-point value in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
TAN S+1 S

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

Specify the desired angle (65,535 to 65,535) in radians in S+1 and S. If the angle is outside of the range 65,535 to 65,535, an error will occur and the instruction will not be executed. For information on converting from degrees to radians, see 3-14-9 DEGREES TO RADIANS: RAD(458). If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . The following diagram shows the relationship between the angle and result.
R S: Angle (radian) data R: Result (tangent)

Flags
Name Error Flag Label ER Operation ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 65,535. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. OFF

Equals Flag Overflow Flag

= OF

499

Floating-point Math Instructions

Name Underflow Flag Negative Flag Label UF N Operation OFF ON if the result is negative. OFF in all other cases.

Section 3-14

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-14 ARC SINE: ASIN(463)

Purpose Calculates the arc sine of a 32-bit floating-point number and places the result in the specified result words. (The arc sine function is the inverse of the sine function; it returns the angle that produces a given sine value between 1 and 1.)

Ladder Symbol
ASIN(463) S R S: First source word R: First result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ASIN(463) @ASIN(463) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

500

Floating-point Math Instructions

Description

Section 3-14

ASIN(463) computes the angle (in radians) for a sine value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
SIN
1

S+1

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

The source data must be between 1.0 and 1.0. If the absolute value of the source data exceeds 1.0, an error will occur and the instruction will not be executed. The result is output to words R+1 and R as an angle (in radians) within the range of /2 to /2. The following diagram shows the relationship between the input data and result.
R S: Input data (sine value) R: Result (radians)

Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 1.0. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. OFF OFF ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

501

Floating-point Math Instructions

Section 3-14

3-14-15 ARC COSINE: ACOS(464)

Purpose Calculates the arc cosine of a 32-bit floating-point number and places the result in the specified result words. (The arc cosine function is the inverse of the cosine function; it returns the angle that produces a given cosine value between 1 and 1.)

Ladder Symbol
ACOS(464) S R S: First source word R: First result word

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification ACOS(464) @ACOS(464) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

ACOS(464) computes the angle (in radians) for a cosine value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
COS 1 S+1 S

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

502

Floating-point Math Instructions

Section 3-14

The source data must be between 1.0 and 1.0. If the absolute value of the source data exceeds 1.0, an error will occur and the instruction will not be executed. The result is output to words R+1 and R as an angle (in radians) within the range of 0 to . The following diagram shows the relationship between the input data and result.
R S: Input data (cosine value) R: Result (radians)

Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 1.0. OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. OFF OFF ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-16 ARC TANGENT: ATAN(465)

Purpose Calculates the arc tangent of a 32-bit floating-point number and places the result in the specified result words. (The arc tangent function is the inverse of the tangent function; it returns the angle that produces a given tangent value.)

Ladder Symbol
ATAN(465) S R S: First source word R: First result word

503

Floating-point Math Instructions

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification

Section 3-14

ATAN(465) @ATAN(465) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

Description

ATAN(465) computes the angle (in radians) for a tangent value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
TAN1 S+1 S

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

The result is output to words R+1 and R as an angle (in radians) within the range of /2 to /2. The following diagram shows the relationship between the input data and result.

504

Floating-point Math Instructions

R
S: Input data (tangent) R: Result (radians)

Section 3-14

Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. OFF OFF ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-17 SQUARE ROOT: SQRT(466)

Purpose Ladder Symbol
SQRT(466) S R S: First source word R: First result word

Calculates the square root of a 32-bit floating-point number and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification SQRT(466) @SQRT(466) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

505

Floating-point Math Instructions

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767

Section 3-14

A448 to A958

#00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

SQRT(466) calculates the square root of the 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.)
S+1 S

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

The source data must be positive; if it is negative, an error will occur and the instruction will not be executed. If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . The following diagram shows the relationship between the input data and result.
R

S: Input data R: Result

506

Floating-point Math Instructions

Flags
Name Error Flag Label ER

Section 3-14

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Operation ON if the source data is not recognized as floating-point data. ON if the source data is negative. ON if the source data is not a number (NaN). OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. OFF OFF

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-18 EXPONENT: EXP(467)

Purpose Ladder Symbol
EXP(467) S R S: First source word R: First result word

Calculates the natural (base e) exponential of a 32-bit floating-point number and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification EXP(467) @EXP(467) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to 4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF (binary) ----R

A448 to A958

507

Floating-point Math Instructions

Area Index Registers Indirect addressing using Index Registers

Section 3-14
S R --,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15

Description

EXP(467) calculates the natural (base e) exponential of the 32-bit floatingpoint number in S+1 and S and places the result in R+1 and R. In other words, EXP(467) calculates ex (x = source) and places the result in R+1 and R.
S+1 S

e
R+1 R

Source (32-bit floating-point data)

Result (32-bit floating-point data)

If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . If the absolute value of the result is less than the minimum value that can be expressed as floating-point data, the Underflow Flag will turn ON and the result will be output as 0. Note The constant e is 2.718282. The following diagram shows the relationship between the input data and result.
R

S: Input data R: Result

Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value.

Equals Flag Overflow Flag

= OF

508

Floating-point Math Instructions

Name Underflow Flag Negative Flag Label UF N

Section 3-14
Operation ON if the absolute value of the result is too small to be expressed as a 32-bit floating-point value. OFF

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

3-14-19 LOGARITHM: LOG(468)

Purpose Ladder Symbol
LOG(468) S R S: First source word R: First result word

Calculates the natural (base e) logarithm of a 32-bit floating-point number and places the result in the specified result words.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification LOG(468) @LOG(468) Not supported. Not supported.

Applicable Program Areas

Block program areas Step program areas OK OK Subroutines OK Interrupt tasks OK

Operand Specifications
Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area Indirect DM addresses in binary Indirect DM addresses in BCD Constants Data Registers Index Registers Indirect addressing using Index Registers S CIO 0 to CIO 6142 W0 to W510 H0 to H510 A0 to A958 T0000 to T4094 C0000 to C4094 D0 to D32766 @ D0 to @ D32767 *D0 to *D32767 #00000000 to #FFFFFFFF --(binary) ----,IR0 to ,IR15 2048 to +2047 ,IR0 to 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,( )IR0 to, ( )IR15 R

A448 to A958

509

Floating-point Math Instructions

Description

Section 3-14

LOG(468) calculates the natural (base e) logarithm of the 32-bit floating-point number in S+1 and S and places the result in R+1 and R.

loge

S+1

Source (32-bit floating-point data)

R+1

Result (32-bit floating-point data)

The source data must be positive; if it is negative, an error will occur and the instruction will not be executed. If the absolute value of the result is greater than the maximum value that can be expressed as floating-point data, the Overflow Flag will turn ON and the result will be output as . Note The constant e is 2.718282. The following diagram shows the relationship between the input data and result.
R
S: Input data R: Result

Flags
Name Error Flag Label ER Operation ON if the source data is not recognized as floating-point data. ON if the source data is negative. ON if the source data is not a number (NaN). OFF in all other cases. ON if both the exponent and mantissa of the result are 0. OFF in all other cases. ON if the absolute value of the result is too large to be expressed as a 32-bit floating-point value. OFF ON if the result is negative. OFF in all other cases.

Equals Flag Overflow Flag Underflow Flag Negative Flag

= OF UF N

Precautions

The source data in S+1 and S must be in IEEE754 floating-point data format.

510

Floating-point Math Instructions

Section 3-14

3-14-20 EXPONENTIAL POWER: PWR(840)

Purpose Ladder Symbol
PWR(840) B E R B: First base word E: First exponent word R: First result word

Raises a 32-bit floating-point number to the power of another 32-bit floatingpoint number.

Variations
Variations Executed Each Cycle for ON Condition Executed Once for Upward Differentiation Executed Once for Downward Differentiation Immediate Refreshing Specification PWR(840) @PWR(840) Not supported. N