EE471
Lab 1
Autumn 2010
MIPS 32 by 32 Register File
Due by 5:00, 30/9/10 Introduction: For this lab you are to onstru t a 32 by 32 re!ister "ile usin! #erilo!$ %he re!ister "ile is intro&u e& in ha'ter 4 o" the lass te(t1$ )ithin the 32 by 32 re!ister "ile is an array o" 32 &i""erent 32bit re!isters$ %hese re!isters must be onstru te& "rom D flip-flops *'ositi#e e&!e+tri!!ere&,$ -ote that "or ./01 re!ister 2ero is har&3ire& to al3ays out'ut the #alue 2ero, re!ar&less o" 3hat may or may not be 3ritten to it$ %he "i!ure belo3 sho3s a blo 4 &ia!ram o" a re!ister "ile *this is a mo&i"ie& re'ro&u tion o" "i!ure 4$7 on 'a!e 310 o" the te(tboo4,$ 5 5 5 R ead R e g is t e r 1 R ead R e g is t e r 2 W r it e R e g is t e r W r it e D a ta R ead D a ta 2 32
R ead D a ta 1
32
32
R e g W r ite
5ea& 5e!ister 1 an& 5ea& 5e!ister 2 sele t the re!isters 3hose #alues are out'ut on the 5ea& Data 1 bus an& 5ea& Data 2 bus res'e ti#ely$ %he )rite 5e!ister in'ut bus &esi!nates the re!ister into 3hi h the in"ormation on the )rite Data bus is to be 3ritten 3hen the 5e!)rite ontrol si!nal is hi!h$ Implementation: A sim'le im'lementation o" the 32 by 32 ./01 re!ister "ile an be ma&e usin! 5e!isters om'ose& o" D "li'+"lo's, a 5:32 enable& &e o&er, an& t3o lar!e 32(32 to 32 multi'le(ors$ %his is sho3n in the "ollo3in! blo 4 &ia!ram *note that the lo 4 is omitte& "or larity,$
67om'uter 8r!ani2ation an& Desi!n9 by 0atterson an& :ennessy
0a!e 1
EE471
Lab 1
Autumn 2010
0
R e g is t e r 1
32
32
R e g is t e r 2
32
Multiplexor
R e g W r ite
Decoder
32
Read D a ta 1
R e g is te r 3 1
32
R e a d R e g is te r 1
W r ite R e g is t e r
5 32 32
W r ite D a ta
32
32
Multiplexor
32
R ead D a ta 2
32
R e a d R e g is te r 2
Ea h re!ister is sim'ly an array o" 32 D "li'+"lo's, the blo 4 re'resentation o" 3hi h is as "ollo3s$
32
D a ta In
R e g is te r R e g is te r
32
D a ta O u t
0a!e 2
W r ite E n a b le
EE471
Lab 1
Autumn 2010
)here the D in'ut o" ea h D "li'+"lo' orres'on&s to a sin!le bit in the 32 bit &ata in'ut bus an& the ; out'ut o" ea h D "li'+"lo' orres'on&s to the a''ro'riate bit in the 32 bit &ata out'ut bus$ %he enable o" e#ery D "li'+"lo' is onne te& to the same 3rite enable in'ut si!nal$ %his element 3ill also re ei#e a lo 4 in'ut, 3hi h syn hroni2es the re!isters$ -ote that the lo 4 an& the 3rite enable are se'arate si!nals$ %he lo 4 is a 'ure, 'erio&i si!nal 3ith no !lit hes or other 3eir& beha#iors$ %he 3rite enable may ha#e !lit hes an& ha2ar&s, an& thus must be mo&erate& by the lo 4 < ma4e sure that ran&om transitions o" the 3rite enable, as lon! as they are not simultaneous 3ith the a ti#atin! lo 4 e&!e *'ositi#e e&!e,, &o not ause the re!ister to s'uriously !rab a ne3 #alue$ %he &e o&er sele ts 3hi h re!ister re ei#es the 5e!)rite ontrol si!nal as its enable in'ut$ )hen a re!ister is not sele te& its enable in'ut shoul& be "alse$ Also note that the least si!ni"i ant out'ut line o" the &e o&er is "loatin! in the blo 4 &ia!ram "or the re!ister "ile$ %his is be ause the 2ero re!ister is har&3ire& to 2ero so it &oes not nee& 3rite enable in'ut$ /n "a t, instea& o" usin! a re!ister, you an =ust har&+ o&e the in'uts to the out'ut mu(es "or re!ister 2ero to all 2eroes$ %he most &i""i ult 'art o" this lab is onstru tin! the lar!e 32(32 to 32 multi'le(ors$ 8ne 3ay to &o this is to "irst onstru t a 32 to 1 multi'le(or an& use 32 o" these 32 to 1 multi'le(ors to onstru t the lar!er 32(32 to 32 mu($ W R!I!": 8n this lab there is an easy 3ay *throu!h hierar hy, an& a har& 3ay to &o thin!s$ /" you "in& yoursel" 3ritin! a L8% o" lines that are all i&enti al, e( e't 3ith some bus in&e(es han!e&, you are &oin! it the :A5D 3ay < rea& the se tion in the tutorial on hierar y> #ab Re$uirements %applies to all labs& 1$, ?se the "ile 6re!stim$#9 as your testben h$ @ou shoul& alter the testin! as ne essary to ma4e sure your unit 3or4s$ %he %As 3ill ha#e their o3n testben h "or use &urin! the &emos, so you must ma4e sure your re!ister "ile ta4es the same in'uts A out'uts, in the same or&er, as is 'resente& in the 'ro#i&e& testben h$ 2$, All lo!i must be !ate le#el, stru tural$ %hat is, built "rom e('li it A-D, 85, -A-D, -85, B85, /-CE5%E5, et $ !ates$ -o assi!n statements *e( e't an assi!n to set a 3ire to a onstant #alue or onne t 3ires to!ether,, 7A1E statements, et $ 3$, All !ates must ha#e at most 4 in'uts$ @ou an ha#e 'ro e&ures 3ith more in'uts *an& an buil& lar!er !ates u' this 3ay,, but the basi !ates you 3ill buil& your ir uit out o" annot ha#e more than 4 in'uts$ 4$, All !ates ha#e a &elay o" 50's$ 0ro essor 'er"orman e 3onDt be a !ra&in! riteria "or the lass *unless you &o really ri&i ulous thin!s,, but you nee& &elay to sho3 ho3 thin!s beha#e$ 5$, @ou may onstru t a DFF beha#iorally "or use else3here: module D_FF (q, d, clk); output q; input d, clk; 0a!e 3
EE471
Lab 1
Autumn 2010
reg q; // Indicate that q is stateholding always @(posedge clk) // old !alue e"cept at edge q # d; endmodule ?se this stru ture to buil& u' all the other statehol&in! elements an& re!isters in your 'ro=e t$ E$, )hen 3e !et to labs 3 an& 4, you an &o the ontrol lo!i beha#iorally, or as &ata"lo3 *assi!n statements,$ %he &ata'ath annot be beha#ioral at all, e( e't "or the DFF, but the ontrol an be built any 3ay you hoose$ 'urn In: For this lab you 3ill &emo the "un tionality o" your re!ister "ile to the %As, an& must also turn in, &urin! lass, the "ollo3in!: 1$ A 'rintout o" your o&e 2$ Full 1 hemati at the !ate le#el$ /t 3ill li4ely be multi+le#el *i$e$ bo(es on an u''er le#el ha#e a lo3er+le#el sheet 3ith the &etails,$ 1in e this &ia!ram 3ill rea''ear in all subseFuent labs, 'hoto o'y it or &o it ele troni ally$ GG DE.8-1%5A%/8-1 )/%: %:E %As A5E 5E;?/5ED, ):E%:E5 @8?5 LAH )85I1 85 -8% GG /" you &o not &emo your assi!nment, you automati ally !et a 0$ .issin! your &emo slot 3ithout 'rior a''ro#al 3ill im'ose a late 'enalty on the entire lab$
0a!e 4
