1989

General Information

DSP
PRODUCTS
DSP Processors
DATABOOK
Microcoded Support Components

Floating-Point Components

Analog Devices, Inc., 1989
Fixed-Point Components
All Rillhts Reserved
Package Information

Application Notes

IlANALOG
DEVICES
Appendix

",ANALOG
.... OEVICES
DSPPRODUCTSDATABOOK
April 1989
Analog Devices. Inc . 1989
All Rights Reserved
Information furnished by Analog Devices is believed to be accurate and reliable. However. no responsibility
is assumed by Analog Devices for its use; nor for any infringements of patents or other rights ofthird parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Products in this book may be covered byone or more of the following patents. Additional patents are pending.
U.S.:
RE29.619. RE29.992. RE30.586. RE31.850. DES. 233.909.3.007.114.3.278.736.3.355.670. 3,441.913. 3.467.908.
3.500.218.3.530.390.3.533.002. 3.685.045. 3.729.660. 3.793.563. 3.803.590. 3.842,412. 3.868.583. 3.890.611.
3.906.486.3.909.908.3.932.863.3.940.760. 3.942.173. 3.946.324. 3.950.603. 3.961.326. 3.978,473. 3.979.688.
4.016.559.4.020,486.4.029.974.4.034.366. 4.054.829. 4.092.698. 4.123.698. 4.136.349. 4.141.004. 4.213.806.
4.250.445.4.268.759.4.270.118.4/286.225. 4/309.693. 4.313/083. 4/323/795/ 4/338/591/ 4/349/811. 4.363.024.
4/374/314/4/383/222/4/395/647/4/399/345/ 4,400/689/ 4,400/690/ 4,427/973/ 4,439.724/ 4,460/891/ 4,475/103/
4,475/169/4/476/538.4,481.708.4,484.149. 4,485.372. 4,491/825/ 4/511,413/ 4/521/764/ 4/543/560/ 4.543.561/
4/547/766/4/547/961/4/556/870/4/558/242/ 4/562,400/ 4.565/000/ 4/586/019/ 4/586/155/ 4/590,456/ 4/596/976/
4/601/760/4/604/532/4/608/541/4/622/512/ 4/626/769/ 4/639/683/ 4/644/253/ 4/646/056/ 4/646/238/ 4/678/936/
4/684/922/4/685/200/4/694/276/4/697/151/ 4/703/283/ 4/707/682/ 4/709/167/ 4/717/883/ 4/722/910/ 4/742/331.
4.751,455/4.752.9004/761.636/4/769/564/ 4/771/011/ 4/774/685/ 4/791/551
France:
111.833/70.10561/75.27557.7608238.77 20799/ 7810462/ 79 24041/ 80 00960/ 8011312.81 02661/8114845/
8209758/8303140
Japan:
1/092/928/1/242/936/ 1/242.965/ 1/306/235.1/337/318.1,401/661/ 1,412/991
West Germany:
2/014034/ 2540451.7/ 2611858.1
U.K.:
1.310/591/1/310/592/1/537/542/1/590.136. 1.590.137. 1.599/538/ 2/008/876/ 2/032/659/ 2/040/087/ 2/050/740/
2.054.992.2.075.295.2.081.040.2.100.081. 2.103.884. 2.104.288. 2.107.951. 2/115.932. 2.118.386. 2.119.139.
2/119/547/2/126/445/2/126/814/2/135.545/2/137/787
Canada:
984/015/1/006/236/1/025/558/1/035,464/ 1/054/248/ 1/141/034. 1/141.820/ 1/142,445/ 1/143/306/ 1/150,414/
1.153.607.1.157.571/1/159.956.1.177.127. 1.177/966. 1/184/662/ 1.184/663/ 1/191/715. 1.192/310/ 1/192/311/
1.192.312.1/203/628/ 1/205/920/ 1/212/730.1/214.282.1.219.679.1.219.966.1.223/086
Sweden:
7603320-8
General Information
Contents
Page
General Introduction .................................................... 1 - 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 - 3
GENERAL INFORMA TION 1-1
- ~ - ------- - - ~
Introduction
DSP AT ANALOG DEVICES
Analog Devices is the industry's leading supplier of high
performance signal processing integrated circuits. As the leader,
Analog Devices was quick to recognize the important opportuni-
ties made possible by the growth of digital signal processing. In
1983, the DSP Division introduced the industry's first CMOS
fixed-point multipliers and multiplier-accumulators. These
matched the speed of bipolar alternatives while cutting power
requirements by a factor of twenty. This breakthrough shifted
the focus of the industry from bipolar to CMOS for high speed
VLSI circuits.
PRODUCT GROWTH & INNOVATION
From a base in industry-standard components, we brought out
a complete line of building block VLSI processors for high end
DSP and numeric processing systems. These include several 64-
bit IEEE floating-point chipsets and a single-precision (32-bit)
version of one of the same chipsets. Other products in the fam-
ily are an address generator, two program sequencers and a reg-
ister me.
In 1986 we introduced the first full off-chip Harvard architec-
ture DSP microprocessor, the ADSP-2l00, complemented by a
superior set of interactive development tools.
TECHNOLOGY GROWTH
From our original CMOS wafer fabrication in 5 micron geo-
metries we moved, in 1985, to 1.5 micron double-layer metal
CMOS. We are currently in production with both the 1.5
micron and our newer 1.0 micron CMOS processes. Our
12.5MHz ADSP-2l00A is the 1.0 micron version of our original
1.5 micron ADSP-2100, for example. Analog Devices continues
to develop advanced processes such as specialized bipolar and
gallium arsenide both internally and through our strategic
investments.
Our manufacturing facilities include factories in Wilmington,
Massachusetts and assembly in the Philippines. Our digital
VLSI test capability is located in Norwood, Massachusetts, the
Division's headquarters.
APPLICATIONS & SUPPORT GROWTH
Analog Devices supports its products with a technically strong
direct sales force and readily available applications assistance.
Our Applications Engineering staff in Norwood, Massachusetts;
Santa Ana, California; Tokyo, Japan; Newbury, UK and other
locations worldwide understands the specialized requirements of
designing and supporting DSP systems. Our quarterly DSP
applications newsletter, DSPatch, brings you up-to-date applica-
tions information and is available free by request.
nsp PRODUCTS DATABOOK
This book provides complete technical data on DSP products
from Analog Devices. Included are:
Comprehensive Data Sheets on some 20 significant product
families
Selection Guides for rapid product fmding
DSP Application Notes
1-2 GENERAL INFORMA TION
List of available Technical Publications on real-world analog
and digital signal processing
Worldwide Service Directory
Index.
Besides this Databook, the present series includes a Linear
Products Databook and a Data Conversion Products Databook;
like this book, the latest versions of both are available free upon
request.
TECHNICAL SUPPORT
Our extensive technical literature discusses the technology and
applications of products for precision measurement and control.
Besides tutorial material and comprehensive data sheets, includ-
ing a large amount in our Databooks, we offer Application
Notes, Application Guides, Technical Handbooks (at reasonable
prices), and several serial publications; for example, Analog Pro-
duetlog provides brief information on new products being intro-
duced, and Analog Dialogue, our technical magazine, provides
in-depth discussions of new developments in analog and digital
circuit technology as applied to data acquisition, signal process-
ing, control, and test. We maintain a mailing list of engineers,
scientists, and technicians with a serious interest in our prod-
ucts. In addition to Databook catalogs, we also publish several
short-form catalogs on specific product families. You will fmd
typical pUblications described on pages 8-2 and 8-3 at the back
of the book.
SALES OFFICES
Backing up our design and manufacturing capabilities and our
extensive array of publications is a network of sales offices and
representatives throughout the United States and most of the
world. They are staffed by experienced sales and applications
engineers, and many of them maintain a local stock of Analog
Devices products. Our Worldwide Service Directory, as of the
publication date, appears on pages 8-6 and 8-7 at the back of the
book.
RELIABILITY
The manufacture of reliable products is a key objective at Ana-
log Devices. We maintain facilities that have been qualified
under such standards as MIL-M-385l0 for ICs in the U.S. and
Ireland and MIL-STD-1772 for hybrids. A growing number of
our products have qualified for JAN part numbers; others are in
the process. Most of our ICs are available in versions that com-
ply with MIL-STD-883C Class B.
We publish a Military Produets Databook for designers who spec-
ify ICs and hybrids for military contracts (the 1987 issue con-
tains data on nearly 150 available product families). A newslet-
ter, Analog Briefings, provides current information about the
status of reliability at AD!.
PRICES
Accurate, up-to-date prices are an important consideration in
making a choice among the many available product families.
Since prices are subject to change, current prices lists and/or
quotations are available upon request from our sales offices.
nsp Processors - Section 2
Introduction . . . . . . . . . . . . . . . .
ADDS-21XX DSP Software Development Tools.
ADDS-21XX DSP Hardware Development Tools
ADSP-2101 In-Circuit Emulator ........... .
ADSP-2100/ADSP-2100A 12.5 MIPS DSP Microprocessor.
ADSP-210IlADSP-2102 12.5 MIPS DSP Microcomputer .
Microcoded Support Components - Section 3
Introduction . . . . . . . . . . . . . . . . . .
Selection Guide . . . . . . . . . . . . . . . .
ADSP-1401- Word-Slice Program Sequencer
ADSP-1402 - Word-Slice Program Sequencer
ADSP-1410 - Word-Slice Address Generator.
ADSP-3128A - Multiport Register File ....
Floating-Point Components - Section 4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Selection Guide . . . . . . . . . . . . . . . . . . . . . . . .
ADSP-320IlADSP-3202 - 32-Bit IEEE Floating-Point Chipset ..
ADSP-321O/ADSP-321l1ADSP-3220/ADSP-3221 - 64-Bit IEEE Floating-Point Chipsets
ADSP-3212/ADSP-3222 - 64-Bit IEEE Floating-Point Chipset
Fixed-Point Components - Section 5
Introduction . . . . . . . . . . . . . . . .
Selection Guide . . . . . . . . . . . . . . . . . . . . . .
Industry Standard Fixed-Point Components
ADSP-I080A - 8 x 8-Bit Twos Complement CMOS Multiplier.
ADSP-1081A - 8 x 8-Bit Unsigned-Magnitude CMOS Multiplier
ADSP-1012A - 12 x 12-Bit CMOS Multiplier ..... .
ADSP-I016A - 16 x 16-Bit CMOS Multiplier ...... .
ADSP-lOO8A - 8 x 8-Bit CMOS Muitiplier/Accumuiator ..
ADSP-lOO9A - 12 x 12-Bit CMOS Muitiplier/Accumuiator .
ADSP-IOIOA - 16 x 16-Bit CMOS Multiplier/Accumulator .
ADSP-IOIOB - 16 x 16-Bit CMOS Multiplier/Accumulator .
Enhanced Fixed-Point Components
ADSP-I024A - 24 x 24-Bit CMOS Multiplier ...... .
ADSP-lIIOA - 16 x 16-Bit CMOS Single Port Muitiplier/Accumuiator
ADSP-IIOI - Integer Arithmetic Unit .....
Package Information - Section 6
Table of Contents
Page
.2-1
.2 - 2
.2- 5
.2- II
.2-17
.2-19
2 - 53
3 - I
.3-3
........ 3-4
.. 3 - 5
3 - 25
.3- 29
.3 - 45
.4-1
.4-3
.. 4-4
.4- 5
.4-39
.4- 85
.. 5 - I
.5-3
.5-4
. 5 - 5
. 5-II
. 5 - IS
. 5 - 21
. 5 - 27
. 5 - 33
5 - 39
. 5 - 45
. 5 - 51
5 - 59
5 - 73
6 - I
GENERAL INFORM A TlON 1-3
Application Notes - Section 7
Introduction . . . . . . . . . . . . . . . . . .
Sharing the Output Bus of the ADSP-1401 Microprogram Sequencer
Implement a Writeable Control Store in Your Word-Slice System
Replacing the Am2910 with the ADSP-1402 Program Sequencer
Loading an ADSP-2101 Program via the Serial Port
Disk Drive Head Positioning with the ADSP-2101 ..... .
Digital Filtering with the ADSP-2100A ........... .
Power and Ground Connection Guidelines for Pin Grid Arrays
Appendix - Section 8
Technical Publications ...
Ordering Guide . . . . . . .
Worldwide Service Directory
Product Index . . . . . . . .
1-4 GENERAL INFORMA TION
Page
.7-1
.7-2
.7-3
.7-5
.7-9
7 - 13
7 - 17
.7- 19
7 - 23
.8- I
.8-2
.8-4
.8-6
Inside Back Cover
Introduction . . . . . . . . . . . . . . . . . . . . . .
ADDS-21XX DSP Software Development Tools .
ADDS-21XX DSP Hardware Development Tools ... .
ADSP-2101 In-Circuit Emulator ............ .
ADSP-2100/ADSP-2100A 12.5 MIPS DSP Microprocessor.
ADSP-2101lADSP-2102 12.5 MIPS DSP Microcomputer .
nsp Processors
Contents
Page
.2-2
.2-5
.. 2-11
.. 2 - 17
. 2 - 19
. 2 - 53
DSP PROCESSORS 2-1
Introduction
The ADSP-2100 family of digital signal processors provides a
core architecture optimized for digital signal processing and
other high speed numeric processing applications. The family
consists of the ADSP-2l00 and ADSP-2l00A microprocessors
and the ADSP-2l0l and ADSP-2l02 microcomputers. All
devices share the core set of features:
1. Easy-to-Attain High Performance
The ADSP-2l00 core integrates an arithmetic/1ogic unit
(ALU), multiplier-accumulator (MAC), barrel shifter, data
address generators and a program sequencer in a single
device. It incorporates modified Harvard architecture (that is,
data can also be stored in program memory) for efficient
access to program and data memories. The result combines
the functions and performance of a bit-slice or building block
system with the ease-of-design and development of a general-
purpose microprocessor.
2. Easy-to-Understand Instruction Set
The ADSP-2l00 family instruction set uses an algebraic syn-
tax, similar to high level languages, making it easier to write
and understand source code. This results in easier and faster
code development and maintenance.
3. Easy-to-Use Development Tools & Support
The complete set of development tools available for the fam-
ily (including a C Compiler, Simulator and In-circuit Emula-
tor each described later in this section) minimizes both
design time and effort. Your application is up and running
faster with this powerful development. In addition, our
Applications Engineering Group supports only DSP with
application notes, applications handbooks, a customer
newsletter, a bulletin board service and excellent telephone
support.
4. Easy-to-Design System Interface
The advanced design of the ADSP-2l00 family allows simple
interconnections of memories and YO devices, minimizes the
external logic required to handle interrupts and supports
straightforward host interface and multiprocessing designs.
ADSP-2100/ADSP-2100A Microprocessor
The microprocessor members of the family include the ADSP-
2100 and the 1.0 micron ADSP-2l00A which are pin and code-
compatible. In addition to the core, these devices offer the
following:
Modified off-chip Harvard architecture. The processor can
access up to 16K words of l6-bit data memory and up to 32K
24-bit words of program memory containing both instructions
and data.
2-2 DSP PROCESSORS
A l6-instruction on-chip cache memory with allows the pro-
cessor to fetch two operands in parallel when executing out of
the cache. Since the instruction set supports a high degree of
parallelism, the loops of many algorithms can be efficiently
coded in 16 instructions or less.
A sample set of benchmarks for the l2.5MHz ADSP-2l00A is
shown in the table below.
ADSp2101/ADSp2102 Microcomputer
The microcomputer members of the family include the RAM
based ADSP2l0l and the mask programmable ROM-based
ADSP-2102. Both are upwardly code compatible with the
ADSP2100 and ADSP2l00A. In addition to the core, these
devices offer the following:
Modified on-board Harvard architecture. The processor has
2K words of (24bit) program memory RAM and lK of l6-bit
data memory RAM on-chip. Off-chip memories share one
address and one data bus which can be used to fetch instruc-
tions, data and to boot the processor from external memory.
A l6-bit programmable timer with an 8-bit presca!ing factor
that generates its own interrupt.
Two serial ports offering a wide set of possible framing and
timing options for interfacing easily to any serial device. Com-
panding is supported in hardware.
The diagram on the following page graphically shows the micro-
processor and microcomputer devices.
ADSp2100 Family Benchmarks
Algorithm Performance @ 12.SMHz
FIR Filter 80ns per Tap (I cycle per Tap)
Complex FIR Filter 320ns per Tap (4 cycles per Tap)
Biquad Filter Section S60ns per Section (7 cycles per Section)
Lattice Filter Section 400ns per Section (5 cycles per Section)
1024-point Complex
FFT (Radix-2) 2.9ms
4096-point Complex
FFT (Radix-2) 19.8ms
ADSP-21001 ADSP-2100A
Core
ALU, MAC and Barrel Shifter
Two Data Address Generators, one with bit-reversing
capability
Separate Program Memory and Data Memory address and
data buses
Powerful Sequencer for Zero Overhead looping and single-
cycle branches
Bus Grant and Bus Request Signals for host interfacing
Highly Readable Source Code for ease of development and
maintenance
PMA
OMA
PMO
OMO
ADSP-2100/ADSP-2100A Specific Features
All Program and Data Memory buses extended off-chip
Single-cycle access to external memory
Up to 16K of 16-bit word data memory
Up to 32K of 24-bit word program memory (may also hold
data)
Data Memory Acknowledge Signal (DMACK) for interfacing
to slow, memory-mapped peripherals
On-chip instruction cache for three bus performance
Four interrupt request lines
IOO-pin PGA and IOO-lead PQFP packages
DSP PROCESSORS 2-3

ADSP2101/ADSp2102

r=Dt'NSTRUCTION
REGISTER
V I"
PROORAM CATA BOOT
SPIAM SRAM ADDFIESS
DATA
I DATA I
2K )( 24 lK X 16 GENERATOR
ADDAEBa ADDRESS
'ROO RAM I
OENERATOR

I
S;QUENCER
y
"
to ;:.. L
.:;

"'l"-
II

EXTERNAL
14 PMA BUS
ADDRESS
F= F=
'--
!=
BU'

" 7' " >-
MU'

14 OMA BUS
F=
'-c-
24 PMO BUB , 7
V
EXTERNAL
'--
DATA
t=-I"- r=
BU'
aUB
MU'

EXCHANOE
:7" , 7

t,
t. ;:..

t. ;:..
It ' L;:" DMD BU. LJ L-,
....
7' 7'
" 7
IN'UT R,oa .:.<! I COM'ANDINO INPUT REOS INPUT FlEOS
CIRCUITRY
?D
ALU
?D
MAC
crt
SHIFTER CONTROL
LOOIC "",mil R', T.onomll R"
TIMER
A
OUTFtUT REGS , ...... OUTPUT REGS \. r- OUTPUT FlEGS
-<j RBUSO 0
Core
ALU, MAC and Barrel Shifter
Two Data Address Generators, one with bit-reversing
capability
Separate Program Memory and Data Memory address and
data buses
Powerful Sequencer for Zero Overhead looping and single-
cycle branches
Bus Grant and Bus Request Signals for host interfacing
Highly Readable Source Code for ease of development and
maintenance
2-4 DSP PROCESSORS
'::
"
Fltctlve Fl.; Fltetlye Fltg
'---
SERIAL SERIAL
'"'""-
POAT 0 FORT 1

ADSp2101/ADSp2102 Specific Features
2K of 24-bit on-chip program memory RAM
lK of 16-bit on-chip data memory RAM
Up to 16K of 16-bit word data memory using external
memory
Up to 16K of 24-bit word program memory using external
memory
Up to three memory accesses (one may be off-chip) in a single
cycle
Timer interrupt with programmable period and prescaler
Two complete serial ports with companding in hardware
68-pin PGA and 68-lead PLCe packages
11IIIIIIII ANALOG
WDEVICES
FEATURES
Release 1.5 Supports the ADSP-2100 and ADSP-2100A
DSP Microprocessors
C COMPILER
Programming in C Eases Development of Applications
Software
Supports In-Line Assembly Code
Provides FRACT Data Type (1.15 Format) for DSP
Algorithms
Complete Calling Interface to Assembly Language
Routines
Produces ROM able Code
Floating Point Emulation Support
Conforms to ANSI Draft Standard (X3J11)
SYSTEM BUILDER
Architecture Description File Specifies Target
Hardware
ASSEMBLER
Supports High Level Constructs
Supports Flexible Macro Processing
Encourages Modular Code Development
Provides a Full Range of Diagnostics
LINKER
Library Support
Maps Assembler Output to Target Hardware
PROM SPLITTER
Formats ROM Memory Image for Uploading to PROM
Programmers
SIMULATOR
Interactive User-Friendly Interface
Full Symbolic Disassembly
Simulates Hardware Configuration
Simulates Port 1/0 Handling
Flags Illegal Operations
GENERAL DESCRIPTION
The ADSP-2100 Cross-Software Development tools allow the
programmer to develop applications software for implementation
on ADSP-2100 and ADSP-2100A DSP microprocessors. The
software tools include the C compiler, System Builder, Assem-
bler, Linker, PROM Splitter and Simulator.
DSP Software Development Tools
ADDS-21XX I
CCOMPILER
The C Compiler supports the development of application pro-
grams in the C programming language. Consisting of a Prepro-
cessor and Compiler which conform to the ANSI draft standard
(X3Jll), the C Compiler produces ADSP-2100 assembly lan-
guage source code. Applications written in C are then compiled,
assembled and linked to produce code that can be simulated
using the Simulator or executed on the Emulator or Evaluation
Board.
The Preprocessor supports the complete ANSI draft standard
set of options, and reads directives such as #include. The
#pragma directive supports in-line assembly code in a C pro-
gram. This allows the user to execute efficient assembly lan-
guage routines within the C environment.
From the code produced by the Preprocessor, the compiler
creates a stack-oriented run-time environment using the Data
Address Generators to implement the stack. The stack may be
located in program or data memory RAM. It is used for param-
eter passing and local and temporary storage. Because the
ADSP-2100 cannot write an immediate value to program mem-
ory, locating the stack in data memory is usually more efficient.
OSP PROCESSORS 2-5
The example in Figure 1 illustrates how a simple function
implemented in ADSP-2100 source code is interfaced to a C
function call.
int iJ,k;
mainO
{
k=add(iJ);
add(x,y)
{
#pragma ADSP2100
{ Function add (x,y)
{ int x,y;
{
{ Returns: z=x+y;
dm(i4,m7) = ayO;
dm(i4,m7) = ar;
i6=1;
madiJY( i6, m4);
axO=dm(i6,mS);
ayO=dm(i6,mS);
ar=axO+ayO;
axO=ar;
i6= -I;
madiJY( i6, m4);
ayO = dm(i6,m7);
ar = dm( i6,m7);
#pragma ADSP2100
}
{ save registers }
{ get first parameter }
{ mS = 1, i6 points to 2nd parameter }
{ get second parameter }
{ perform addition }
{ return 16-bit values in axO }
{ restore registers }
Figure 1. Assembly Language to C Language Interface
The stack is managed by a frame pointer and stack pointer. The
following diagram illustrates the implementation of the stack
during a call. The previous frame pointer and local variables are
popped unto the stack.
High Me .. o"
High III"""
' ..... polnle'
A B
Figure 2. Stack Implementation in ADSP-2100 Memory
Space
Though the ADSP-2100 is a 16-bit processor, the C Compiler
supports certain 32-bit operations. The following arithmetic data
types are supported directly:
int
long int
unsigned int
unsigned long int
fract
float
16-bit twos-complement value
32-bit twos-complement value
16-bit unsigned value
32-bit unsigned values
16-bit fractional value (1.15 format)
32-bit real.
Type tract is not a standard C data type but is an extension cre-
ated to support the 1.15 data format used in digital signal pro-
cessing applications. The compiler also supports all standard
storage classes, types and modifiers.
2-6 DSP PROCESSORS
Classes
Types
Modifiers
auto, extern, register, static, typedef
All including void
const, volatile plus pm, dm, ram, rom
Register values, though accepted by the compiler, are not imple-
mented as actual processor registers. The modifiers pm, tim, rom
and ram are extensions that are supported. In addition, the fasts-
witch statement, an extension to the language, has been added to
support the DO UNTIL capability of the processors. It is syn-
tactically identical to the standard switch statement but produces
faster ADSP-2100 assembly code.
SYSTEM BUILDER
The System Builder translates a user-defmed description of the
target hardware system into a form which can be utilized by
other Cross-Software Modules. The Cross-Software Modules
require knowledge of the target hardware system for the Linker
to place relocatable segments, the Simulator to simulate external
memory configurations, and for the PROM Splitter to generate
separate program and data flies. The user specifies the target
program memory, data memory and I/O port configurations by
writing a System Specification Source File. The System Builder
translates this into an Architecture Description File which is
read by the other Cross-Software Modules. For example, the
Linker resolves the references in the source code and the actual
addresses by reading the Architecture File.
The Architecture File is comprised of the following directives
that define the ADSP-2100 system:
. SYSTEM first statement in .ACH flie, specifies the name
of the system
.ENDSYS
.CONST
.PORT
.SEG
last statement in .ACH flie, specifies the end of
the flie
defmes constants
declares memory-mapped 1/0 ports
specifies the type of memory in the system
(program or data, RAM or ROM).
The following example of an architecture (.ACH) flie shows the
use of the directives:
SYSTEM fir .sysum, lsystem name for fir .system}
program.mem{4096] ldeelare code space}
coeff.storage{1S] ldeclare coeff table}
delay./me{IS] ldeclare data memory}
PORTIABS 16382 ad.sample ldeclare vo parts}
ENDSYS llnd.cates end of file}
The .SYSTEM directive defmes the name of the ADSP-2100
system. This name is used by the other software modules. The
.SEG directive declares memory segments specifying the physi-
cal address, segment length, memory area (PM, DM), memory
type (RAM, ROM) and memory attributes (CODE, DATA or
both). In the above example, program.mem is a 4K-word buffer
located in program memory ROM beginning at address 0 con-
sisting of program code. The buffer, coefLstorage, is fifteen
words of data located in program memory RAM beginning at
address 4096. Finally, delay.line is a IS-word buffer located in
data memory RAM starting at address O. The .PORT directive
declares memory-mapped 1/0 ports by specifying a name for the
port and the absolute physical address. In the example, an
analog-to-digital converter named ad.sample occupies location
16382 in data memory space.
ASSEMBLER
The Assembler translates source code modules into relocatable
object code modules. The user creates an assembler source code
module using the ADSP-2JOO Assembly Language and defining
variable data buffers and symbolic constants using the Assem-
bler Directives. An assembly module becomes a unit of the com-
plete system source code. Separately assembled object code
modules are linked together to form the final running system
using the Linker.
Assembler directives support a variety of data and program
structures. Invocation switches modify the assembly process.
.MODULE defines the beginning of an assembly module
. ENDMOD
.VAR
.CONST
.PORT
.INIT
.INCLUDE
.MACRO
.ENDMACRO
.LOCAL
.EXTERNAL
.GLOBAL
.ENTRY
the last statement in a source code file
declare variables and data buffers, the
/CIRC qualifier defines circular buffers
declare constants
declares a memory-mapped I/O port in
data memory
use to initialize declared variables and
data buffers
use to read another source file
defines the beginning of a macro
terminates a macro
use only within a macro, directs the
Assembler to create a unique label with
local scope
assigns external attribute to identifiers
declared in other modules
assigns the global attribute to ports,
variables and buffers
assigns entry attribute to label names
Macros can be created using the .MACRO directive. For exam-
pie, the macro shown below is a general purpose memory trans-
fer routine which can transfer data buffers from one memory
area (program or data memory) to the other.
lMACRO declaratIOn}
.MACRO memory_cransf(%O, %1, %2, %3, %4); {pass five arguments}
. LOCAL transf;
/4=%0;



DO trans! UNTIL CE;
51 %3(14,M4);
transf
ENDMACRO
{set 14 to source Slart address}
{set IS to destmatton start address}
{set pomter update to szngle mcrement}
lset length of buffer}
1 transfer data}
llransfer from type %3 memory}
ltransfer from type %4 memory}
To call the macro within an assembly language program, execute:
memory_transf CcoefLtable, -buffer, buff length, PM, DM);
LINKER
The Linker generates the Program Memory/Data Memory Im-
age File, a complete executable program, by linking together
object-code modules which were assembled separately. The
hardware environment defined by the Architecture File is used
ADDS-21XX
by the Linker to place program and data in the defined memory
area and location. This output file is used by the Simulator,
PROM Splitter, Emulator, and Evaluation Board. Another
Linker output, the Debug Symbol Table File, contains a list of
all symbols encountered by the Linker and enables the Simula-
tor to utilize user-defined source code level symbols in its inter-
face with user.
To aid the user in interpreting the Linker result, a Map Listing
file can be generated.
This file includes:
1. A cross-reference listing of all symbols encountered, arranged
by module. Information on each symbol such at memory
type, absolute address, length and symbol type is given .
2. A map of the memory sections and the attributes of each
section.
3. A map of the allocated segments in program memory, listed
sequentially from low order address to high order address.
4. A map of the allocated segments in data memory, listed se-
quentially from low order address to high order address.
5. Linker error messages.
6. A list of libraries searched and used.
PROM SPLITTER
The PROM Splitter extracts the address information and the
contents of the ROM portion of the PMlDM Image File and
formats the extracted images for uploading to PROM burners.
Commercially available PROM burners expect input data to
be eight bits wide. The PROM Splitter separates the memory
image into a byte-wide format. It creates three one-byte wide
PROM image files for the 24-bit program memory, and two
one-byte wide PROM image files for the 16-bit data memory.
Both program and data memory can be optionally output as a
single stream of one-byte wide file. The PROM image file is
generated in either Motorola S Record, Intel Hex Record or
Daisy VLA format. For one-byte wide files, the Motorola S2
format is supported.
SIMULATOR
The Simulator simulates the operation of the ADSP-2JOO and
allows the user to observe the contents of the registers, buses,
stacks and program and data memories as a program is being
executed. The Simulator is user friendly, interactive and screen-
oriented. Figure 4 shows the basic Register Display .
ADSP-2100 Slmulator vl 5 Devlces Inc
>LV
AXO uuuu ",,0
AXl uuuu AR uuuu AN 0
NXO 2000
NXl uuuu
NYO FE8C
MYl uuuu
51 2000
> r8glatet
,
AI' uuuu Ii.V 0
AI a Ii.SO
Nult1plie:a::-A.ecUlllUlato:a::
HR2 00 Nl\1 004A MIlO 0644
... 0000
ICY 0
Sbift.1:
S. uu Sill uuuu SilO uuuu
FIR_SYSTEM
AddreSII GeneratOIl: 1t1
:IO 0009 NO 0001 LO OOaF
11 """" Xl UUIIII Ll 0000
I2 Uuuu M2 uuuu L2 0000
x3 uuuu M3 IIUUU L3 0000
Add<
Addrellil Genexcatoxc '2
14 1000 N4 0001 L4 OOOF
IS uuuu M5 uuuu Ls 0000
Ii uuuu Hi uuuu L6 0000
M7 uuuu
Figure 3. Register Display
DSP PROCESSORS 2-7
By reading the Architecture Description File output of the Sys-
tem Builder, the Simulator configures itself to match the target
system hardware. This enables the Simulator to flag operations
such as attempting to write to ROM or nonexistent memory lo-
cations.
The Simulator supports full symbolic disassembly via the Debug
Symbol Table File output of the Linker.
The Simulator supports three execution modes: Emulator, Ex-
tend and Single-Step. In Emulator mode, the Simulator runs at
its fastest speed. The display is updated every 256 cycles. In
Extend mode, the display is updated every cycle. In Single-Step
mode the Simulator executes a single instruction per run com-
mand and updates the screen.
The basic format of the Simulator display includes a status line
containing information about the status words, program counter
and accumulated cycle time. It also provides a command win-
dow for interactive typing of commands and display of error
messages and warnings. The Simulator's major informational
displays i n c l u d ~ the following:
Register
Program Memory
Data Memory
Data Memory Plot
Status
Stack
Trace Buffer
Cache Memory
Cross Reference
Modules
Help
The register display shows the basic
processor data registers (primary or
secondary bank), arithmetic status and
the state of the buses and data address
generators.
This window displays instructions in
fully symbolic form. The user can
change opcodes and instructions as
needed.
This window displays the numeric con-
tents of data memory.
This window plots the contents of
a selected range of data memory on
hardware configurations that support
graphics.
This informational display shows break-
points, watchpoints, port status and
interrupt status.
The four columns of the Stack window
each represent one of the four stacks
of the processor. The user can modify
the values through push and pop
operations.
This displays the history of up to 4K
states of the four external buses of the
processor.
This displays (symbolically) the con-
tents of cache memory and whether or
not an instruction in the cache is
deemed valid.
Displays the location of all symbol
names.
Lists all available modules by name.
Displays a list of Simulator commands
and provides further information on
them as requested.
In addition, the Simulator allows the user to modify the con-
tents of most registers, memories and status words. Breakpoints
can be set in Program Memory and watchpoints in Data Mem-
ory. Command files can be created to execute the same set of
2-8 DSP PROCESSORS
commands. This is useful for repetitive commands to bring the
simulation to a specific starting condition.
User-defined addresses or values can be displayed symbolically.
The state of the Simulator can be saved and restored for future
simulation sessions. Contents of program and data memory can
be dumped to files for use with the hardware development tools.
The Simulator supports decimal and hexadecimal numeric for-
mats. 110 to and from ports reads and writes data files which
can later be analyzed.
Simulator Commands
Simulator commands allow the user to change the state of the
processor. A quick summary of Simulator commands is shown
below. Only the letters shown in caps must be entered to invoke
the command.
Display Control Commands
ALternate displays secondary data registers
BACkup forces PM/DM/Trace displays to scroll back
BEep enables beeps on user's terminal
CAche invokes cache display mode
DECimal forces all numbers to be displayed in deci-
mal format
DM
FOrward
HELp
HEXadecimal
Modules
NOBeep
NOSymbolic
PLotdm
PM
PRimary
REGister
STACk
STATus
SYmbolic
TOggle
TRace
Wipe
Xreference
invokes data memory display mode
forces PM/DMlTrace displays to scroll
forward
displays command list for access to help
information
forces all numbers to be displayed in hexa-
decimal (the default)
displays all source modules
suppresses beeps at the user's terminal
forces the simulator to be non-symbolic
plots the contents of a selected section of
DM
invokes program memory display mode
displays primary data registers
invokes register display mode
invokes stack display mode
displays Interrupt, Break and Port status
forces the simulator to be symbolic
(default)
toggles display of primary and secondary
register banks
invokes trace display mode
rewrites current display
displays cross-reference list
Operation Control Commands
EMulator invokes emulator mode
EXTend invokes extend mode
SInglestep invokes single-step mode
Break Control Commands
CLEARBreak clears a PM break address
CLEARStoptime clears any stop times currently defined
CLEARWatch clears a DM access watch address
COunt
SETBreak
SETStoptime
SETWatch
sets iteration count and delay on break
points
sets a PM break address
sets a time in ns for the processor to halt
sets a DM access watch address
Context Control Commands
SETModuie sets the module the Simulator uses for sym-
bolic context
File Control Commands
COMmfile executes simulator commands found in a
DUMPDm
DUMPPm
Load
READImage
READSymbol
batch file
forces a DM image dump to a file
forces a PM image dump to a file
reads .EXE and .SYM files and sets default
module context
reads a memory image file
reads a symbol table file
Modify/Inspect Control Commands
CLEARTime clears the time display
CYCLetime sets the cycle period in ns
FINDDm finds the occurrence of a value in DM
FINDPm finds the occurrence of a value in PM
RESEtstack clears stacks and reset pointers
SETDm sets a segment of DM
SETPC sets the PC
SETPM sets a segment of PM
SETRegister sets a register value
Assembly Commands
ADdsymbol adds a user-defined symbol name
DELete deletes one line of assembly code from PM
EXEcute executes an assembly instruction
PAtch patches one line of assembly code into PM
REMovesymbol deletes a user-defined symbol name
Configuration Control Commands
BATch turns off screen update in Emulator mode
CHipreset simulates the hardware chip RESET
CLOse closes a DM memory mapped 110 port
HArdware simulates hardware powerup and sets ROM
to undefined
Interrupts
Open
POwerup
activates the interrupt source
opens a DM memory mapped 110 port
simulates the hardware powerup condition
Execution Control Commands
RUn starts processor running in Extend and Em-
ulator modes
<cr> starts processor running in Single-step mode
ADDS-21XX
Exit Command
EXIt exits from the Simulator and returns to the
host
ADDITIONAL INFORMATION
The ADSP-2100 Software Development System is available for
the PC-DOS*, MS-DOS, VAXlVMS* and UNIX* BSD 4.2 on
the Sun-3. The ADSP-2IOO Cross-Software Manual provides
complete information on these tools.
Analog Devices offers a hands-on mul tiday workshop on pro-
gramming the ADSP-2100 family of processors. The workshop
is taught by our DSP Applications Engineering group and is
presented several times a year at the factory in Norwood, Massa-
chusetts. The fee includes all manuals and workbooks and lab
time. The workshop can also be conducted at your site; consult
us for site pricing.
ORDERING INFORMATION
Part Number Description
ADDS-21l0 Cross-Software for VAXlVMS
ADDS-212It System Builder, Assembler, Linker, PROM
Splitter for IBM-PC*
ADDS-2122t Simulator for IBM-PC
ADDS-2123-C Cross-Software for Sun-3 (UNIX BSD 4.2)
ADDS-2130 C Compiler and Cross-Software for
VAXIVMS*
ADDS-2131 C Compiler and Cross-Software for IBM-PC
ADDS-2133-C C Compiler and Cross-Software for Sun-3
(UNIX BSD 4.2)
ADDS-2190 ADSP-2100 Family Workshop
*PC-DOS and IBM PC are trademarks of International Business
Machines Corp. VAXlVMS is a trademark of Digital Equip-
ment Corp. UNIX is a trademark of AT&T.
tNote that ADDS-2121 and ADDS-2122 must both be ordered
to make up a complete IBM-PC Cross-Software system without
the C Compiler.
OSP PROCESSORS 2-9
2-10 DSP PROCESSORS
IIIIIIIIIII ANALOG
WOEVICES
FEATURES
ADSP-2100A EVALUATION BOARD
Can Be Used to Benchmark Real-Time Performance
Interfaces to an IBM-PC or VAX Host via RS-232
Connectors
Operates at 8MHz
Same Interactive, Symbolic User Interface as the
Emulator and Simulator
Three Execution Modes: Single-Step, Extend, Emulator
Displays Contents of ADSP-2100A Registers, Program
Memory, Data Memory and Stack
Multiple Program Memory Breakpoints Supported
4K Program and 2K Data Memory Installed with
Sockets for Expanding to Full 32K Program and
16K Data Memory
Fully Documented Prototyping Expansion Connector to
Customize Evaluation Board to Your Application
Bidirectional Codec Channel to Process Real-World
Signals
12-Bit Linear DAC Provides an Oscilloscope Interface
Input Preamp with Microphone Jack and Output
Amplifier with Speaker Jack Directly Supports
Audio and Speech Applications
ADSP-2100A IN-CIRCUIT EMULATOR
Performs In-Circuit Emulation
Interfaces to an IBM-PC or VAX Host via Two RS-232
Connectors
Operates at 8MHz
Same Interactive, Symbolic User Interface as the
ADSP-2100 Simulator and Evaluation Board
Three Execution Modes: Single-Step, Extend, Emulator
Displays Contents of ADSP-2100A Registers, Program
Memory, Data Memory and Stack
Supports Multiple Program Memory Breakpoints
User-Selectable Program Memory Source: Emulator or
Target System
User-Selectable System Clock Source: Emulator,
Target System or External
OPTIONAL TRACE BOARD FOR IN-CIRCUIT EMULATOR
Buffers Up To 8K of Bus Activity for Display and
Analysis
Break Triggering on an Extensive Set of Possible Bus
Conditions
Buffer Can Be Uploaded to Host for Further Analysis
Installs Inside Emulator Case
DSP Hardware Development Tools
ADDS-21XX I
GENERAL DESCRIPTION
The ADSP-2100A Hardware Development Tools support the
prototyping, development and debugging of applications in
hardware.
The Evaluation Board allows the user to benchmark real-time
performance by executing Analog Devices-supplied or
user-developed DSP routines.
The In-Circuit Emulator allows the user to debug code in the
actual target system.
The Trace Board enhances the In-Circuit Emulator by capturing
activity on the four external buses of the processor.
The Hardware Development Tools have the same interactive,
symbolic user interface as the Simulator. Single-step, extend and
emulator execution modes run the processor as required for your
debugging activity. Four major display modes enable users to
examine contents of ADSP-2100A registers, program memory,
data memory and stack. Multiple program memory breakpoints
are supported.
DSP PROCESSORS 2-11
ADSP-2100A EVALUATION BOARD
The Evaluation Board is an easy-to-use development tool for
evaluating the ADSP-2100A DSP Microprocessor in real-time
applications. It has three roles in the design process. As a dem-
onstration system, you can observe the ADSP-2100A's real-time
performance in executing standard DSP benchmarks. As an
evaluation system, it can be used prior to designing hardware
for the real-time execution of your application routines. As a
simulation accelerator, application code can be executed in real
time for increased productivity of software developers.
The Evaluation Board is a stand alone system consisting of an
ADSP-2100A DSP Microprocessor, 4K words of (24-bit) pro-
gram memory, and 2K words of (l6-bit) data memory. Addi-
tional program and data memory sockets are provided and can
be populated as desired up to the full 32K program and 16K
data memory address space.
Program
Memory Code
16K x 24 Bits
Program
Memory Data
16K x 16 Bits
2-12 DSP PROCESSORS
Prototype
Expansion
Scope Trigger
ADSP-2100
Single-Chip DSP
Microprocessor
External
Clock
External
Interrupt
External
Host
Figure 1. Evaluation Board Block Diagram
12-Bit DAC
Data
Memory
16K x 16 Bits
The Evaluation Board's ADSP-Z100A runs under the control of
an on-board host processor enabling the user to access a variety
of powerful debugging tools. When interfaced to an external
host computer system running the Cross-Software, the Evalua-
tion Board serves as a real-time development tool.
The emulator mode runs the processor at full speed. Extend
mode updates the screen every cycle during program execution.
Single-step mode executes a single instruction per carriage
return. In addition, multiple program memory breakpoints are
supported.
PROGRAM
MEMORY
INSTRUCTION
SPACE
DATA MEMORY
DATA SPACE
___ c:=Jc:J
___ c::::J EJ
___ c:::::J cz:::J
___ c::::::J 1(/ I
___ cz:::J I .:'\.1
___ F,.II;>">.I
___ I:",,,;:.;.. .. >d[::,;'::.::,,:,,::,:]
___ pn;!"kn,;,,::,1
ADSP-2100A
-- D
--
--
PROGRAM __
--i----i __
SPACE __
--
ADDS-21XX
The Evaluation Board has four major display modes: register,
program memory, data memory and stack. Register mode dis-
plays the contents of the ADSP-ZlOOA's primary and alternate
registers. Program memory mode displays the contents of pro-
gram memory. Data memory mode displays the contents of data
memory. Stack display shows the contents of the ADSP-2100A's
program counter stack and count stack.
The Evaluation Board connects to a terminal and host computer
via two RS-Z3ZC serial connectors.
Y1 CLOCK S 1
OSCILLATOR RESET
O
S2
INTERRUPT
IRQ2
OJ
OJ

FAULT [j
U39 PAL C:=J TP 1 0
U46 PAL c::=J
TP 20
U61 CODEC r--1
L--.-J
TP 30 -s. @
TP 4 0 Ii....-_....J@
TP S
o
U66
12 BIT DAC
@
J3 EXTERNAL CLOCK
J4 SCOPE VERTICAL
OUTPUT
J5 SCOPE TRIGGER
POWER SUPPLY
INDICATOR LEOS
P1 ANALOG GND
P2 .12V ANALOG
P3 -12V ANALOG
P4 .SV DIGITAL
P5 DIGITAL GND
J7 SPEAKER JACK
J1
CHANNEL A
RS232 PORT
--
MEMORY MAP
CONFIGURATION
8.192MHz r---l POSTS
J8 MICROPHONE JACK
'-----+ R32 OUTPUT AMPLIFIER GAIN
J9 EXTERNAL INTERRUPT
IRQ1
J2
CHANNEL B
RS232 PORT
U109
8088 HOST
PROCESSOR
CODEC CLOCK L---J
E 11111 [ffi
POSTS
1111111111/1111111/1111/11111/11
ADSP-2100A EVALUATION BOARD
U108, U11S, U123
FIRMWARE
J6
PROTOTYPING
EXPANSION CONNECTOR
Figure 2. Evaluation Board
R34 INPUT AMPLIFIER GAIN
R37 INPUT OFFSET ADJUST
OSP PROCESSORS 2-13

Built-in analog interfaces provide access to real signals for easy
implementation of audio, speech and telecommunications appli-
cations. A bidirectional codec channel and an undedicated 12-bit
linear DI A converter process real-world signals. The proto typing
expansion bus allows you to construct custom hardware to
reflect or test the eventual hardware environment. In addition,
three BNC connectors interface to external instrumentation. An
integral microphone jack and input pre-amplifier, along with a
speaker jack and output amplifier, support speech and telecom-
munication applications.
With a microphone, speaker and oscilloscope you can easily
implement audio and speech applications. The microphone and
speaker are connected to the bidirectional codec channel via
jacks on the input preamp and output amplifier. The codec is
a National Semiconductor TP30SI. It is a memory-mapped
peripheral of the ADSP-2100A that can be written to or read
from using the Data Memory Read and Data Memory Write
commands. The codec represents the input/output sample in an
8-bit binary form. By using the standard wlaw nonlinear trans-
formation, the codec's effective dynamic range can be extended
to 13 bits. The codec samples data at a frequency of 8. 192kHz
using a dedicated clock generator. Communication between the
codec and the ADSP-2100A is synchronized with the DMACK
signal. The codec rejects signals that do not fall in the range of
200Hz to 3400Hz and should be used only in speech or audio
applications in which telephone-quality signals are adequate. An
input pre-amplifier (Analog Devices AD741 operational ampli-
fier) and output audio amplifier (National Semiconductor
LM338 Audio Power Amplifier) are connected to the input and
output of the codec.
To display processed data, the oscilloscope is connected to the
12-bit linear DAC via a BNC connector. The DAC is an Analog
Devices AD667 12-bit D/A converter. It is a memory-mapped
peripheral of the ADSP-2100A that can be written using the
Data Memory Write commands. The DAC is intended for use
as an analog output for the display of processed data on an oscil-
loscope. It is not intended as a means of reconstructing sampled
data processed by the ADSP-2100A; it lacks the deglitching cir-
cuitry and anti-imaging filtering required of such a system. The
user can construct a linear analog interface consisting of an AID
converter, D/A converter, antialiasing filter and anti-imaging
filter using the prototyping expansion connector.
The prototyping expansion connector provides the data, address
and interface signals for customizing the Evaluation Board. For
example, analog circuitry composed of linear AID and D/A con-
verters and antialiasing filters may be connected to the Evalua-
tion Board for implementing filtering applications. The
96-contact prototyping expansion connector brings out the fol-
lowing signals:
2-14 OSP PROCESSORS
Input Signals
EIRQ3
EIRQ2
IRQ 1
EIRQO
EBR
EDMACK
THALT
RESETOUT
Output Signals
External Interrupt Request 3 (Highest Priority)
External Interrupt Request 2
External Interrupt Request 1
External Interrupt Request 0
External Bus Request. Allows your target board
to request control of the data memory interface.
Data Memory Acknowledge. Used for asynchro-
nous transfers across the data memory interface.
Processor Halt by Target System. Assertion of
THALT halts the ADSP-2100A.
System Reset Output. The ADSP-2100A's RE-
SET line is available at this contact as an output
only.
+ 12V + 12V Analog
AGND Analog Ground
-12V -12V Analog
GND
DMA13-O
DMRD
TRAP
ECE8-1
Digital Ground
Bus Grant. Acknowledges an external bus re-
quest (BR).
Data Memory Address bits
Data Memory Read. Indicates a read operation
on the data memory interface.
Data Memory Write. Indicates a write operation
on the data memory interface.
Data Memory Select. Signals a data memory
access on the data memory interface.
Indicates the execution of a TRAP instruction.
The ADSP-2100A halts execution and the
TRAP signal remains asserted until THAL T is
asserted.
External Chip Enables 8 through 1. These out-
puts are memory-mapped locations.
Bidirectional Signals
DMD1S-0 Data Memory Data Bus
The Evaluation Board must be interfaced to an IBM-PC (with
VT100 emulation) or VAXNMS system via the RS-232 connec-
tors. This host computer must also run the ADSP-2100 Cross-
Software. The board requires == 12V and + SV power
supplies.
ADSP-2100A IN-CIRCUIT EMULATOR
The In-Circuit Emulator allows you to debug code (developed
with the Software Development tools) in the actual target sys-
tem. The Emulator uses an ADSP-2100A to emulate the proces-
sor. It plugs into the target system's ADSP-2100A socket and
operates at the ADSP-2100A's cycle rate. The Emulator pro-
vides a software interface similar to the Cross-Software Simula-
tor and to the Evaluation Board.
Once your program has been debugged in the software environ-
ment you can further prove and debug in the hardware area
using the Emulator. It provides a variety of ways to download
your program into the actual hardware, executing out of emula-
tor program memory or target system program memory, for
example, or using any of three sources for the system clock.
The Emulator supports three execution modes. In emulator
mode the Emulator runs at the full processor speed and halts
only when a break condition is encountered. Break conditions
include breakpoints, traps, halt on keyboard interrupt and target
system voltage below 4.SV. While the Emulator is running in
emulator mode, only the program counter and elapsed time
infortnation is updated. When the Emulator halts, the full
screen is updated.
Extend mode runs the processor in a continuous single-step
manner, updating the display after each processor cycle. Instruc-
tions are disassembled on the screen as they are executed. In
emulator and extend modes, emulation can be halted by setting
a breakpoint at a specified location in program memory.
In single-step mode, the Emulator executes one instruction and
halts. All display contents are updated and instructions are dis-
assembled as they are executed. The next instruction is executed
if you type a carriage return or enter the RUN command.
The Emulator has four major display modes (five with the Trace
Board installed). Register display shows the contents of the
ADSP-2100A's primary and secondary registers. The program
memory and data memory displays show the contents of pro-
gram and data memories. Stack display shows the contents of
the ADSP-2100A's program counter stack and count stack.
Using the same interactive, symbolic user interface as the Simu-
lator, the Emulator allows the user to modify the contents of
registers, program memory, data memory and the program
counter. Breakpoints can be set in the emulator-based program
memory. User-defined addresses and values can be displayed
symbolically. Numbers can be specified and displayed in either
decimal or hexadecimal format.
The Emulator has other features. The baud rate and parity set-
tings for communications between the Emulator and the host
computer can be specified by the user's terminal. The Emulator
Pod can be activated and deactivated under software control.
The program memory source can be either the Emulator's inter-
nal program memory RAM or the target system's program
memory. Also, files can be downloaded from the host system.
The system clock can be selected from either the Emulator's
internal clock, the target system's clock or an external clock
generator.
ADDS-21XX
Propagation Delays
Although the Emulator matches the ADSP-2100A closely in per-
formance for a few signals, its timing is degraded somewhat
from that of the processor. Propagation delays and, in some
cases, software overhead account for the delays. The signals
with degraded timing are:
CLKIN
IRQ
BR
RESET
HALT
TRAP
PMWR and PMRD
All other signals operate at essentially the same timing as the
processor in a non-emulator system. Complete information and
timing diagrams are given in Appendix B of the ADSP-2IOO
Emulator Manual.
TRACE BOARD FOR ADSP-2100A IN-CIRCUIT
EMULATOR
The Emulator supports an optional, factory-installed Trace
Board. The Trace Board keeps a running history of past exter-
nal bus states PMA, DMA and DMD in an 8K buffer. The
Trace Buffer Display shows the past external bus states of the
ADSP-2100A.
The Trace Board allows you to trigger on bus conditions. Emu-
lation can be halted after detecting a specified combination of
bus states. The IGNORE option turns off the trace during cer-
tain PMA ranges in order to skip over sections of code. The
Trace Board can trigger on the following eleven different bus
combinations:
PMAANDDMA
PMAANDDMD
DMA AND DMD
PMA AND DMA AND DMD
PMA OR (DMA AND DMD)
DMA OR (PMA AND DMD)
DMD OR (PMA AND DMA)
PMA OR DMA OR DMD
(PMA AND DMA) OR (PMA AND DMD)
(PMA AND DMA) OR (DMA AND DMD)
(PMA AND DMA) OR (DMA AND DMD)
In addition, the trace buffer can be uploaded from trace board
to host computer.
ADDITIONAL INFORMATION
Request the ADSP-2IOO Emulator Manual or the ADSP-2IOO
EvaluatIOn Board Manual from your Analog Devices Sales Engi-
neer for further information.
DSP PROCESSORS 2-15

2-16 OSP PROCESSORS
ORDERING INFORMATION
Part Number Description
ADDS-2150A* 8MHz ADSP-2100A In-Circuit Emulator
(l10V)
ADDS-2l50AE* 8MHz ADSP-2l00A In-Circuit Emulator
(220V)
ADDS-2l51A* 8MHz ADSP-2100A In-Circuit Emulator
with Trace Board (lIOV)
ADDS-2l51AE* 8MHz ADSP-2100A In-Circuit Emulator
with Trace Board (220V)
ADDS-2l60* 8MHz ADSP-2100A Evaluation Board
Upgrade Kits
ADDS-2l6l Trace Board Upgrade for ADDS-2l50
ADDS-2l62 Trace Board Upgrade for ADDS-2l50A
* A l2.5MHz version of this product is planned. Please contact factory for
further information.
r.ANALOG
WDEVICES
FEATURES
Supports the ADSP2101 DSP Microcomputer
Performs InClrcult Emulation
Operate. at the Full Clock Rate of the ADSP2101
(12.5MHzl
Same Interactive. Symbolic User Interface as the
ADSP2101 Simulator
SlngleStep. Full Speed and Periodic Updete Execution
Support. Breakpoints and Triggers
User Selectable Memory Source: Emulator or Target
System
User Selectable Clock Source: Emulator or Target
System
RS232C Interface to Host System Supporting Up to
19.2 kb/s
8K Trace Buffer
OnLine A .. embly/Dlsa .. embly
Performance Analysis
In-Circuit Emulator
ADSP-2101 I
Histogram Profiling of Executing Code
TlmeTags on Trace Buffer Contents
Modular Hardware Based on VME Bus
windows. The contents of the ADSP2101's registers are dis
played including serial port control registers, interval timer con
trol registers and registers. The memory win
dows can of all memories on and off chip
rileDiqry. 'the trace display shows the contents of
," .,;,.; buffer. The execution profile shows the use of
GENERAL DESCRIPTION " i'!*a1rJ moduli;, to'1neasure the efficiency and performance of
The ADSP-2101 In-Circuit Emulator :;:.;< <' ,,', '" ' ,; ,""
code developed with the J46iiti1es i,\ the user to modify the contents of registers
an actual target system. The Emulatot! w'lIicli'U8eS an .l\PliP!{" ,;; 'i:dIW.JIUIInory. Breakpoints can be set and user-defined addresses
2101 to emulate the processor, plug&'into the be symbolically. ease of use, the
ADSP.2101 socket and operates at the deCImal or hexadecimal format.
The Emulator supports three different types aSllembiy allows users to modify the code starting at a
gram memory, data memory and boot memory. All memoriit ';: f;'$Ptcified location and load instructions on a line-byline basis.
can be downloaded by the user. The boot memory interface It;,"' The disassembled contents of each address can be displayed
supported. The Emulator can operate from either emulator or before a new assembled instruction is stored.
target system based memory. The Emulator supports an 8192-frame deep trace buffer that
The Emulator can run at the full processor speed updating the data and address bus
7
s as well as. control Trigger-
di la nl h ti hal Th E ula al . mg on bus events, control lines and senal ports IS supported.
sP, Y 0 .y w en on . ts. e m tor can so run m These events can be logically ANDed, ORed or negated to
seuu-real tlDle updatmg the display at a predetermined rate up defme a trigger event.
to every cycle. The user can also single-step through code from
the keyboard.
The Emulator displays information about the state of the emula-
tion in a variety of windows, similar to the ADSP-210l Simula-
tor. These include register, memory, execution profile and trace
Consult the factory for current status.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing,
DSP PROCESSORS 2-17
2-18 DSP PROCESSORS
r.ANALOG
WDEVICES
FEATURES
Pln- and Code-Compatible DSP Microprocessors
ADSP-2100, 6.144MHz and 8.192MHz
ADSP-2100A, 10.24MHz and 12.5MHz
Separate Program and Data Buses, Extended Off-Chip
Single-Cycle Direct Access to 16K x 16 of Data Memory
Single-Cycle Direct Access to 32K x 24 of Program
Memory
Dual Purpose Program Memory for Both Instruction
and Data Storage
Three Independent Computational Units: ALU,
Multiplier/Accumulator and Barrel Shifter
Two Independent Data Address Generators
Powerful Program Sequencer
Internal Instruction Cache
Provisions for Multiprecision Computation and
Saturation Logic
Single-Cycle Instruction Execution
Multifunction Instructions
Four External Interrupts
BOns Cycle Time (ADSP-2100A)
790mW Maximum Power Dissipation (ADSP-2100A,
J and K Grades)
100-Pin Grid Array, 100-Lead PQFP (JEDEC Style)
APPLICATIONS
Optimized for DSP Algorithms Including
Digital Filtering
Fast Fourier Transforms
Applications Include
Image Processing
Radar, Sonar
Speech Processing
Telecommunications
GENERAL DESCRIPTION
The ADSP-2100 and ADSP-2100A are pin- and code-compatible
single-chip microprocessors optimized for digital signal processing
(DSP) and other high-speed numeric processing applications.
The ADSP-2100 and ADSP-2100A are both fabricated in a low-
power double-layer metal CMOS process. Together, they offer a
span of performance from 6MHz to 12.SMHz. All descriptions
of the ADSP-2100 in the text of this data sheet refer to both the
ADSP-2100A and the ADSP-2100 versions since they have
identical architectures and instruction sets. Timing and electrical
specifications differ as shown in those sections of the data sheet.
Both processors integrate computational units, data address
generators and a program sequencer in a single device. The
ADSP-2100 architecture makes efficient use of external memories
for program and data storage, freeing silicon area for increased
12.5 MIPS DSP Microprocessor
ADSP-21 DD/ADSP-21 DDA I
processor performance. The resulting processor combines the
functions and performance of a bit-slice/building block system
with the ease of design and development support of a general
purpose microprocessor.
The ADSP-2100A (K grade) operates at 12.5MHz. Every in-
struction executes in a single 80ns cycle. The ADSP-2100A (J
and K grades) dissipates less than 790mW while the ADSP-2100
dissipates less than 47SmW.
The ADSP-2100's flexible architecture and comprehensive in-
struction set support a high degree of operational parallelism.
Because all instructions execute in a single cycle, MHz = MIPS.
In one cycle the ADSP-2100 can:
generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation.
DEVELOPMENT SYSTEM
The ADSP-2100 and ADSP-2100A are supported by a complete
set of tools for software and hardware system development. The
Cross-Software System provides a System Builder for defining
the architecture of simulated systems under development, an
Assembler, a Linker and a interactive Simulator. An ANSI
(draft) Standard C Compiler supports program development in
this widely used programming language, producing ADSP2100
Assembly code which may be assembled, linked and simulated
with the other development system tools. A PROM Splitter
generates PROM burner compatible files. An In-Circuit Emulator
is available for hardware debugging.
An Evaluation Board is available for quick assessment of actual
processor performance in a prepackaged hardware environment.
DSP PROCESSORS 2-19
ADDITIONAL INFORMATION
For additional information on the architecture and instruction
set of the processor, refer to the ADSP-2100 User's Manual.
For more information about programming and the Development
System, refer to the ADSP-2100 Cross-Software Manual and the
ADSP-2100 Emulator Manual. For examples of applications
routines, refer to the ADSP-2100 Applications Handbook, Volume
I or Volume 2. Manuals are available only from your local Analog
Devices sales office. There is also a quarterly newsletter,
DSPatch TM, supporting Analog Devices' digital signal processing
customers.
ARCHITECTURE OVERVIEW
Figure I is an overall block diagram of the ADSP-2100. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the Shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primitives
are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations. The Shifter
performs logical and arithmetic shifts, normalization, denormali-
zation and derive exponent operations. The Shifter can be used
to efficiently implement any degree of numeric format control,
up to and including full floating point representations. The
computational units are arranged side-by-side instead of serially
for flexible operation sequencing. The internal result (R) bus
directly connects the computational units so that the output of
any unit may be the input of any unit on the next cycle.
A powerful program sequencer' and two dedicated data address
generators ensure efficient use of these computational units. The
program sequencer generates the next instruction address. To
minimize overhead cycles, the sequencer supports conditional
jumps, subroutine calls and returns in a single cycle. With
internal loop counters and loop stacks, the ADSP-2100 executes
looped code with zero overhead; no explicit jump instructions
are required to maintain the loop.
The data address generators (DAGs) handle address pointer
updates. Each DAG keeps track of up to four address pointers.
Whenever the pointer is used to access external data (indirect
addressing), it is modified by a prespecified value. A length
value may be associated with each pointer to implement automatic
modulo addressing for circular buffers. With two independent
DAGs, the processor can generate two addresses simultaneously
.for dual operand fetches.
Efficient data transfer is achieved with the use of five internal
buses.
Program Memory Address (PMA) bus
Program Memory Data (PMD) bus
Data Memory Address (DMA) bus
Data Memory Data CDMD) bus
Result CR) bus
PMA
DMA
PMD
DMD
Figure 1. ADSP-2100 Block Diagram
DSPatch is a trademark of Analog Devices, Inc.
2-20 OSP PROCESSORS
ADSP-21 DD/ADSP-21 DDA
The program memory (PMD, PMA) buses and data memory
(DMA, DMD) buses extend offchip to provide direct connections
to external memories. The DMD bus is the primary bus for
routing data internally and to/from external data memory. The
14-bit DMA bus provides direct addressing of 16K x 16 of external
memory. Although the primary function of the program memory
is for storing instructions, it can also store data. In this case, the
PMD bus provides a path for routing data to/from program
memory, permitting dual operand fetches. The 14-bit PMA bus
provides direct addressing of 16K x 24 of external memory,
expandable to 32K x 24 by using the program memory data
access (PMDA) signal as the 15th address line.
The data memory interface supports slower memories and memory
mapped peripherals with wait states. The data memory ac
knowledge (DMACK) signal provides the necessary handshake.
External devices can gain control of program or data buses
independently with bus request! grant signals (BR, and BG).
The ADSP-2100 can respond to four external interrupts, which
are internally prioritized, maskable and independently pro
grammable as either edge or levelsensitive. Additional external
controls are provided by the RESET, HALT and TRAP signals.
With both BR and RESET recognized, the ADSP-2100 idles,
consuming the least possible current.
The ADSP-2100 instruction set provides flexible data moves
When a data fetch from program memory is required, an extra
memory cycle is automatically appended to enable the next
instruction fetch. To avoid this extra cycle, the ADSP-2100 has
an internal instruction cache (16 instructions deep) which serves
as an alternate source for the next instruction. The cache monitor
circuit transparently determines when the cache contents are
valid. When the next instruction Is in the cache, no extra cycle
is necessary.
and multifunction (data moves with a computation) instructions.
Every instruction can be executed in a single processor cycle.
The ADSP-2100 assembly language uses an algebraic syntax for
ease of coding and readability. A comprehensive set of development
tools supports program development.
A pin description and detailed discussion of each section of the
ADSp-2100 follows.
Pin Description
This section summarizes the pin description of the processor by interface. In this data sheet, when groups of pins are identified
with subscripts, as in P M D 2 ~ ' the highest numbered pin (PMD23) is the MSB.
Pin Name
Clocks:
CLKIN
CLKOUT
Type
Input
Output
Interrupt Request Lines:
IRQ>-o Input
Control Interface:
Input
Input
TRAP Output
Input
Output
Program Memory Interface:
PMA
13
_
0
Output
PMD23_0
PMS
Bidirectional
Output
Function
Master input clock operating at four times the processor instruction rate. Nominally 50% duty
cycle. The phases of eLKIN define the eight internal processor states making up one instruction
cycle.
Output clock operating at the processor instruction rate with a 50% duty cycle. Synchronized to
the internal processor states.
Interrupt Request lines that may be either edge triggered or level sensitive. Interrupts are prioritized
and individually maskable.
Master Reset must be asserted long enough to assure proper reset. When RESET is released,
execution begins at program memory location 0004.
Used to halt the processor. All control signals become inactive and the address and data buses are
driven for observation.
Used to indicate the execution of a TRAP instruction. Remains asserted until HALT is asserted
by an external device.
Bus Request used by an external device to request control of the program and data memory interface.
Upon receiving BR the processor halts execution at the completion of the current cycle and relinquishes
the program and data memory interface by tristating PMA, PMD, PMS, PMWR, PMRD, PMDA,
DMA, DMD, DMS, DMRD and DMWR. The processor regains control when BR is released.
Bus Grant. Acknowledges a bus request (BR), indicating that the external device may take control.
BG is held asserted until BR is released.
Program Memory Address Bus; tristated when BG is asserted.
Program Memory Data Bus; tristated when BG is asserted.
Program Memory Select signals a program memory access on the PM interface. Usable as a chip
select signal for external memories. Remains asserted on successive program memory accesses. HI
only when the processor is halted or after execution of a TRAP instruction. Tristated when BG is
asserted.
DSP PROCESSORS 2-21

Program Memory Interface:
PMRD Output Program Memory Read indicates a read operation on the PM interface. Also usable as a read
strobe or output enable signal. Tristated when BG is asserted.
Output
PMDA Output
Program Memory Write establishes the direction of data transfer on the PM interface. Also usable
as a write strobe. Tristated when BG is asserted.
Program Memory Data Access used to distinguish instruction and data fetches from PM. Asserted
high when data, as opposed to instruction, are accessed. Also usable as a fifteenth PM address bit.
Tristated when BG is asserted.
Data Memory Interface:
DMAn_o Output Data Memory Address Bus; tristated when BG is asserted.
DMACK
Bidirectional Data Memory Data Bus; tristated when BG is asserted.
Output Data Memory Select signals a Data Memory Access on the Data Memory interface. Usable as a
chip select signal for external memories. Remains asserted on successive data memory accesses.
HI only when the processor is halted or after execution of a TRAP instruction. Tristated when
BG is asserted.
Output Data Memory Read indicates a read operation on the Data Memory interface. Also usable as a
read strobe or output enable signal. Tristated when BG is asserted.
Output Data Memory Write indicates a write operation on the Data Memory interface. Also usable as a
write strobe. Tristated when BG is asserted.
Input Data Memory Acknowledge signal used for asynchronous transfers across the DM interface. Indicates
that data memory or memory-mapped peripherals are ready for data transfer. If DMACK is not
asserted when checked by the processor, wait states are automatically generated until DMACK is
asserted.
Supply Rails:
VDD
GND
Supply
Ground
Power supply rail nominally + SVDC. There are four VDD pins.
Power supply return. There are nine GND pins.
PMD BUS
DMD BUS
AZ
AN
AC
AV
AS
AQ
16
Figure 2. ALU Block Diagram
ArithmeticlLogic Unit
Figure 2 shows a block diagram of the Arithmetic/Logic Unit
(ALU).
The ALU provides a standard set of general purpose arithmetic
2-22 DSP PROCESSORS
and logic functions: add, subtract, negate, increment, decrement,
absolute value, AND, OR, Exclusive OR and NOT. Two divide
primitives are also provided to facilitate division. The ALU
takes two 16-bit inputs, X and Y, and generates one 16-bit
output, R. It accepts the carry (AC) bit in the arithmetic status
register (AST AT) as the carry-in (CI) bit. The carry-in feature
enables multiprecision computations. Six arithmetic status bits
are generated: AZ (zero), AN (negative), AV (overflow), AC
(carry), AS (sign) and AQ (quotient). These status bits are
latched in ASTAT.
The X input port can be fed by either the AX register file or
any result registers on the R-bus (AR, MRO, MRI, MR2, SRO,
or SRI). The AX register file contains two registers, AXO and
AXl. The AX registers can be loaded from the DMD bus. The
Y input port can be fed by either the A Y register file or the
ALU feedback (AF) register. The AY register file contains two
registers, AYO and AYl. The AY registers can be loaded from
either the DMD bus or the PMD bus.
The register file outputs are dual ported so that one register can
drive the ALU input while either one simultaneously drives the
DMD bus. The ALU output can be latched in either the AR
register or the AF register.
The AR register has a saturation capability; it can automatically
output plus or minus the maximum value if an overflow or
underflow occurs. The saturation mode is enabled by a bit in
the mode status register (MSTAT). The AR register can drive
both the R-bus and the DMD bus and can be loaded from the
DMDbus.
The ALU contains a duplicate bank of registers shown in Figure
2 as a "shadow" behind the primary registers. The secondary
set contains all the registers described above (AXO, AXI, AYO,
AYI, AF, AR). Only one set is accessible at a time. The two
sets of registers allow fast context switching for interrupt servicing.
The active set is determined by a bit in MST AT.
Multiplier/Accumulator
The multiplier/accumulator (MAC) implements high-speed
multiply, multiply/add and multiply/subtract operations.
Figure 3 shows a block diagram of the MAC section.
Figure 3. MAC Block Diagram
The multiplier takes two 16-bit inputs, X and Y, and generates
one 32-bit output, P. The 32-bit output is routed to a 40-bit
accumulator which can add or subtract the P output from the
value in MR. MR is a 4O-bit register which is divided into three
sections: MRO (bits 0-15), MRI (bits 16-31), and MR2 (bits
32-39). The result of the accumulator is either loaded into the
MR register or into the 16-bit MAC feedback (MF) register.
The multiplier accepts the X and Y inputs in either signed or
unsigned formats. The result is shifted one bit to the left auto-
matically to remove the redundant sign bit for fractional justifi-
cation. The accumulator generates one status bit, MV, which is
set when the accumulator result overflows the 32-bit boundary.
A saturate command is available to change the content of the
MR register to the maximum or minimum 32-bit value when
MV is set. The accumulator also has the capability for rounding
the 40-bit result at the boundary between bit IS and bit 16.
The MAC and ALU registers are similar. The X input port can
be fed by either the MX register file (MXO, MXI) or any result
registers on the R-bus (AR, MRO, MRI, MR2, SRO or SRI).
ADSP-21 DD/ADSP-21 DDA
The MX register file is readable and loadable from the DMD
bus and has dual-ported outputs.
The Y input port can be fed by either the MY register file
(MYO, MYI) or the MF register. The MY register file is readable
from the DMD bus and readable and loadable from both the
DMD and the PMD bus. Its outputs are dual ported.
The accumulator output can be latched in either the MR register
or the MF register. The MR register is connected to both the
R-bus and the DMD-bus. Like the ALU section, the MAC
section contains two complete banks of registers (MXO, MXI,
MYO, MYI, MF, MRO, MRI, MR2) to allow fast context
switching.
Shifter
The Shifter gives the ADSP-2100 its unique capability to handle
data formatting and numeric scaling. Figure 4 shows a block
diagram of the Shifter.
The Shifter can be divided into the following components: the
shifter array, the ORIPASS logic, the exponent detector and the
exponent compare logic. These components give the Shifter its
six basic functions: arithmetic shift, logical shift, normalization,
denormalization, derive exponent and derive block exponent.
The shifter array is a 16 x 32-barre1 shifter. It accepts a 16-bit
input and can place it anywhere in the 32-bit output field, from
off-scale right to off-scale left. The Shifter can perform arithmetic
shifts (shifter output is sign-extended to the left) or logical shifts
(shifter output is zero-filled to the left). The placement of the
16-bit input is determined by the control code (C) and the HIILO
reference signal. The control code can come from one of three
sources: directly from the instruction (immediate arithmetic or
logical shift), from the SE register (denormalization) or the
negated value of the SE register (normalization). The shifter
input can come from either the 16-bit SI register or any result
register on the R-bus. The 32-bit output of the shifter array is
fed to the OR/PASS circuit. The result can be either logically
OR-ed with the current contents of the SR register or passed
directly to the SR register. The SR register is divided into two
16-bit sections: SRO (bits 0-15) and SRI (bits 16-31).
The shifter input is also routed to the exponent detector circuitry.
The exponent detector generates a value to indicate how many
places the input must be up-shifted to eliminate all but one of
the sign bits. This value is effectively the base 2 exponent of the
number. The result of the exponent detector can be latched into
the SE register (for a normalize operation) or can be sent to the
exponent compare logic. The exponent compare logic compares
the derived exponent with the value in the SB register and
updates the SB register only when the derived exponent value is
larger than the current value in the SB register. Therefore, the
exponent compare logic can be used to find the largest exponent
value in an array of shifter inputs.
The Shifter includes the following registers: the SI register, the
SE register, the SB register and the SR register. All these registers
are readable and loadable from the DMD-bus. The SR register
can also drive the R-bus. Like the ALU and MAC, the Shifter
contains two complete banks of registers for context switching.
Each set contains all the registers described above, but only one
set is accessible at a time. The active set is determined by a bit
in MSTAT.
DSP PROCESSORS 2-23
From
INSTRUCTION
R BUS
Figure 4. Shifter Block Diagram
Data Address Generators
Figure 5 shows a block diagram of a data address generator.
The data addreas generators (DAGs) provide indirect addresaing
for data stored in external memories. The processor contains
two independent DAGs so that two data operands (one in program
memory and one in data memory) can be addressed simultaneously.
The two data address generators are identical except that DAGl
has a bit reveraal option on the output and can only generate
FROM
INSTR.
ADDRESS
Figure 5. Data Address Generator
2-24 DSP PROCESSORS
data memory addresses, while DAG2 can generate both program
and data memory addreases but has no bit reveraal capability.
There are three register files in each DAG: the modify (M)
register file, the indirect (I) register file, and the length (L)
register file. Each of these register files contain four 14-bit registers
which are readable and loadable from the DMD-bus. The I
registers hold the actual addresses used to access external memory.
When uaing the indirect addresaing mode, the selected I register
content is driven onto either the PMA or DMA bus. This value
is post-modified by adding the content of the selected M register.
The modified address is passed through the modulus logic.
Associsted with each I register is an L register which may contain
the length of the buffer addressed by the I register. The L
register and the modulus logic together enable circular buffer
addressing with automatic wrap around at the buffer boundary.
The modulus logic is disabled by setting the length of the associsted
buffer to zero.
Program Sequencer
The program sequencer incorporates powerful and flexible
mechanistns for program flow control such as zero-overhead
looping, single-cycle branching (both conditional and uncondi-
tional), and automatic interrupt processing. Figure 6 shows a
block diagram of the program sequencer.
The sequencing logic controls the flow of the program execution.
It outputs a program memory address onto the PMA bus from
one of four sources: the PC incrementer, PC stack, instruction
register or interrupt controller. The next address source selector
controls which of these four sources are selected based on the
current instruction word and the processor status. A fifth possible
source for the next program memory address is provided by
DAG2 when a register indirect jump is executed.
The program counter (PC) is a l4-bit register which contains
the address of the currently executing instruction. The PC output
goes to the incrementer. The incremented output is selected as
the next program memory address if program flow is sequential.
The PC value is pushed onto the 16 x 14 PC stack when a CALL
instruction is executed or when an interrupt is processed. The
PC stack is popped when a return from subroutine or interrupt
is executed. The PC stack is also used in zero-overhead looping.
The program sequencer section contains five status registers.
These are the Arithmetic Status register (ASTAT), the Stack
Status register (SSTAT), the Mode Status register (MSTAT),
the Interrupt Control register (ICNTL) and the Interrupt Mask
register (IMASK). These registers are described in detail in the
next section.
COUNTER
LOGIC
STATUS
LOGIC
IAOO-3
DMD BUS ,.
14
,.
ADSP-2100/ADSP-2100A
The interrupt controller allows the processor to respond to one
of four external interrupts with a minimum of overhead. The
interrupts are internally prioritized and are individually maskable.
Each interrupt can be set to be either edge- or level-sensitive.
Depending on a bit in the interrupt control register (ICNTL),
interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially, with
only one interrupt service active at a time. When responding to
an interrupt, the status registers ASTAT, MSTAT, IMASK are
pushed onto the status stack and the PC counter is loaded with
the appropriate vectored address. The status stack is four levels
deep to allow four levels of interrupt nesting. The stack is auto-
matically popped when return from interrupt is executed.
The vector addresses for each interrupt are fixed at the lowest
four addresses in the program memory space. Single-word,
single-cycle branch instructions may be placed at these locations
to transfer control to the appropriate interrupt service routine.
The down counter and the count stack implement a powerful
looping mechanism. The down counter is a 14-bit register with
CONDITION coDe (4 bltl)
ADDRESS of JUMP (14 bltl)
FUNCTION FIELD
ADDRESS of
LAST INSTRUCTION
In LOOP (14 bltl)

TERMINATION
CONDITION (4 bill)
I
14
Figure 6. Program Sequencer
DSP PROCESSORS 2-25
auto-decrement capability. It is loaded from the DMD bus with
the loop count. The count is decremented every time the counter
value is checked; when the count expires, the counter expired
(CE) flag is set. The count stack allows the nesting of loops by
storing temporarily dormant loop counts. When a new value is
loaded into the counter from the DMD bus, the current counter
value is automatically pushed onto the count stack as program
flow enters a loop. The count stack is automatically popped
whenever the CE flag is tested and is true, thereby resuming
execution of the code outside the loop.
The DO UNTIL instruction executes a zero-overhead loop
using the loop stack and the loop comparator. For a DO UNTIL
instruction, a 14-bit termination address and a 4-bit termination
condition are pushed onto the 18-bit loop stack. The address of
the next instruction (which identifies the top of the loop) is
puahed onto the PC stack. The loop comparator continuoualy
compares the current PC value against the termination address
on the top of the loop stack. When the termination address is
detected, the processor checks if the termination condition is
met. If the termination condition is not met, then the top of the
PC stack is used as the next PC address, returning program
flow to the beginning of the loop. If the termination condition is
met, then the PC stack is popped, the current PC is incremented
by one, and program flow falls out of the loop. The loop stack
is four levels deep, permitting four levels of zero-overhead loop
nesting.
Instruction Cache Memory
The instruction cache memory is 16 levels deep and one instruction
(24 bits) wide. The cache memory maintains a short history of
previously executed instructions so they can be fetched internally
if they are needed again.
Every time an instruction is fetched from external memory, it is
also written into the cache memory. When the program enters a
loop which fits within the cache, all the instructions in the loop
are stored in cache during the first pass. On subsequent passes,
the instructions can be fetched from the instruction cache when
a program memory data access is required. This allows the
program memory to be used for data access without penalty.
The ADSP-2100 then becomes, in effect, a three-bus system
with two data buses and one program bus. For the multiply/ac-
cumulate operations typical of digital signal processing algorithms,
this gives significant speed advantages.
Instructions are fetched from cache memory only when a program
memory data fetch is required. The cache monitor circuit auto-
matically keeps track of when the next instruction is contained
in the cache. No maintenance or overhead is needed to store
externally fetched instructions in the cache or to read previously
fetched instructions from cache.
PMD-DMD Bus Exchange
The PMD-DMD bus exchange circuit couples the PMD and
DMD buses. The PMD bus is 24 bits wide and the DMD bus
is 16 bits wide. The upper 16 bits of PMD are connected to the
DMD bus. An 8-bit register (PX) allows transfer of the full
width of the PMD bus. When data is read from the PMD bus,
the lower 8 bits of the PMD bus are loaded into PX. When
writing to the PMD bus, the contents of PX are appended to
the upper 16 bits, forming a 24-bit value. The PX register is
readable and loadable from the DMD bus.
2-26 OSP PROCESSORS
STATUS REGISTERS
The ADSP-2100 maintains five status registers, each of which
can be read over the DMD bus and four of which can be written.
These registers are:
AST AT Arithmetic Status register
SST AT Stack Status register (read-only)
MSTAT Mode Status register
ICNTL Interrupt Control register
IMASK Interrupt Mask register
ASTAT
ASTAT is 8 bits wide and holds the status information generated
by the computational sections of the processor. The bita in
ASTAT are defined as follows:
o AZ (ALUresultzero)
I AN (ALUresultnegative)
2 AV (ALUoverflow)
3 AC (ALUcatry)
4 AS (ALUX inputsign)
5 AQ (ALU quotient flag)
6 MV (MAC overflow)
7 SS (Shifter input sign)
The bits which express a particular condition (AZ, AN, AV,
AC, MV) are all positive sense (1 = true, 0 = false). Each of the
bits are automatically updated whenever a new status is generated
by an arithmetic operation. As such, each bit is affected only by
a certain subset of arithmetic operations, as defined by the
following table:
Status Bit
AZ,AN,AV,AC
AS
AQ
MV
SS
SSTAT
Updated on:
Any ALU operation except division
ALU absolute value operation
ALU divide operations
Any MAC operation except saturate MR
Shifter exponent detect operation
SST A T is 8 bits wide and holds the status of the four internal
stacks. The bits in SSTAT are:
o PC Stack Empty
I PC Stack Overflow
2 Count Stack Empty
3 Count Stack Overflow
4 Status Stack Empty
5 Status Stack Overflow
6 Loop Stack Empty
7 Loop Stack Overflow
All of the bits are positive sense (1 = true, 0 = false). The empty
status bits indicate that the number of pop operations for the
stack is greater than or equal to the number of push operations
(if no stack overflow has occurred) since the last reset. The
owrfiow status bits indicate that the number of push operations
for the stack has exceeded the number of pop operations by an
amount that is greater than the depth of the stack. When this
occurs, the item(s) most recently pushed will be missing from
the stack (old data is considered more important than new). The
stack overflow status bits "stick" once they are set, so that
subsequent pop operations have no effect on them. A processor
reset must be executed to clear the stack overflow status.
MSTAT
MSTAT is a 4-bit register that defmes various operating modes
of the processor. The Mode Control instruction enables or disables
the four operating modes. The bits in MSTAT are:
o Data Register Bank Select
Bit Reverse Mode (DAG I only)
2 ALU Overflow Latch Mode
3 AR Saturation Mode
The data register bank select bit determines which set of data
registers is currently active (0 = primary, I = secondary). The
data registers include all of the result and input registers to the
ALU, MAC, and Shifter (AXO, AXI, AYO, AYI, AF, AR,
MXO, MXI, MYO, MYI, MF, MRO, MRI, MR2, SB, SE, SI,
SRO and SRI). At initialization, the data register bank select bit
is cleared.
The bit reverse mode, when enabled, bit-wise reverses all addresses
generated by DAG 1. This is most useful for reordering the
input or output data in a radix-2 FFT algorithm.
The ALU overflow latch mode causes the AV (ALU overflow)
status bit to "stick" once it is set. In this mode, when an ALU
overflow occurs, AV will be set and remain set, even if subsequent
ALU operations do not generate overflows. AV can then only
be cleared by writing a zero into it from the DMD bus.
The AR saturation mode, when set, causes AL U results to be
saturated to the maximum positive (H#7FFF) or negative
(H#8000) values when an ALU overflow occurs.
IMASK
IMASK is four bits wide and allows the four interrupt inputs to
be individually enabled or disabled. The bits in IMASK are:
o IRQO Enable
I IRQI Enable
2 IRQ2 Enable
3 IRQ3 Enable
Code
EQ
NE
LT
Status Condition
ALUEqualZero
ALU Not Equal Zero
ALU Less Than Zero
ADSP-21 OO/ADSP-21 OOA
The bits are all positive sense (0 = disabled, I = enabled). IMASK
is set to zero upon a processor reset so that all interrupts are
disabled initially.
ICNTL
ICNTL is a 5-bit register configuring the interrupt modes of the
processor. The bits in ICNTL are:
o IRQO Sensitivity
I IRQ I Sensitivity
2 IRQ2 Sensitivity
3 IRQ3 Sensitivity
4 Interrupt Nesting Mode
The IRQ sensitivity bits determine whether a given interrupt
input is edge- or level-sensitive (0 = level-sensitive, I = edge-
sensitive). These bits are all undefined after a processor reset.
The interrupt nesting mode determines whether nesting of in-
terrupt service routines is allowed. When set to zero, all interrupt
levels will be masked automatically when an interrupt service
routine is entered. When set to one, IMASK will be set so that
only equal and lower priority interrupts will be masked, permitting
higher priority interrupts to interrupt the current interrupt
service routine. This bit is undefined after a processor reset.
CONDITION CODES
The condition codes are used to determine whether a conditional
instruction, such as a jump, trap, call, return, MAC saturation
or arithmetic operation, is performed. The sixteen composite
status conditions and their derivations are given in Table I.
Since arithmetic status is latched into AST A T at the end of a
processor cycle, the condition logic outputs represent conditions
generated on a previous cycle.
True If:
AZ=I
AZ=O
GE
LE
GT
AC
NOTAC
AV
NOTAV
MV
NOTMV
NEG
POS
NOTCE
TRUE
ALU Greater Than or Equal Zero
ALU Less Than or Equal Zero
ALU Greater Than Zero
ALUCarry
AN .xOR. AV = I
AN .XOR.AV=O
(AN .XOR. AV) .OR. AZ = I
(AN .XOR. AV) .OR. AZ = 0
AC=I
Not ALU Carry
ALU Overflow
NotALUOverflow
MAC Overflow
Not MAC Overflow
ALU X Input Sign Negative
ALU X Input Sign Positive
Not Counter Expired
True
AC=O
AV=I
AV=O
MV=I
MV=O
AS=I
AS=O
CE"O
Always True
Table I. Condition Codes
DSP PROCESSORS 2-27
SYSTEM INTERFACE
Figure 7 shows a basic system configuration with the
ADSP-2100.
Clock Signals
The ADSP-2100 takes a TTL-compatible clock signal, CLKIN,
running at four times the basic processor cycle time as an input.
Using this clock input, the processor divides the internal processor
cycle into eight states, defined by the edges of the input clock.
The active processor cycle consists of states 1 through 7. State 8
is a dead zone to provide a neutral stopping point for halting
the processor.
A clock output (CLKOUT) signal is generated by the processor
to synchronize external devices to the processor's internal cycles.
CLKOUT is high during states 8, 1,2 and 3, and low during
states 4, S, 6 and 7. Its frequency is one-fourth of that of CLKIN.
Except during RESET, the CLKOUT signal runs continuously.
Bus Interface
The ADSP-2100 can relinquish control of the memory buses to
an external device. When the external device requires access to
memory, it asserts the Bus Request (BR) signal. After completing
the current instruction, the processor halts program execution,
tristates the PMA, PMD, PMS, PMRD, PMWR and PMDA
output drivers and the DMA, DMD, DMS, DMRD and DMWR
output drivers, and asserts the Bus Grant (BG) signal. When the
BR signal is released, the processor re-enables the output drivers,
releases the BG signal, and continues program execution from
the point where it stopped.
Program Memory Interface
The Program Memory Interface supports two buses: the program
memory address bus (PMA) and the program memory data bus
(P MD). The 14-bit P MA bus directly addresses up to 16K
words. The PMD bus is bidirectional and 24 bits wide.
CLKOUT
CE
PMS
5E
P'M'RD
PROGRAM
WE PMWR
MEMORY
ADSP-2100
16/32k x 24
PMDA
14
ADDR PMA
24
DATA
PMD
RESET TRAP IRQ
Since program memo;:y can be used for both instruction code
and data storage, the Program Memory Data Access (PMDA)
signal is asserted whenever data, as opposed to an instruction
code, is fetched. There is no placement restriction for instruction
code and data in program memory area if less than 16K words
are used. Since the timing of PMDA is compatible with that of
the PMA lines, it may be used as a 15th address line if desired.
This effectively doubles the program memory area to 32K,
which must be split into 16K dedicated to instruction codes and
16K to data.
The program memory data lines are bidirectional. The Program
Memory Select (PMS) signal indicates access to the Program
Memory and can be used as a chip select signal. The Program
Memory Write (PMWR) signal indicates a write operation and
can be used as a write strobe. The Program Memory Read
(PMRD) signal indicates a read operation and can be used as a
read strobe or output enable signal.
Although the processor internal data bus is only 16 bits, the
ADSP-2100 can write to the full 24-bit program memory using
the PX register.
Data Memory Interface
The Data Memory Interface supports two buses: the Data Memory
Address bus (DMA) and the Data Memory Data bus (DMD).
The 14-bit DMA bus directly addresses up to 16K words of
data. The DMD bus is bidirectional and 16 bits wide. The Data
Memory Select (DMS) signal indicates access to the Data Memory
and can be used as a chip select signal. The Data Memory Write
(DMWR) signal indicates a write operation and can be used as a
write strobe. The Data Memory Read (DMRD) signal indicates
a read operation and can be used as a read strobe or output
enable signal.
The ADSP-2100 supports memory-mapped I/O, with the peripher-
als memory mapped into the data memory address space and
accessed by the processor in the same manner as data memory.
CE
OMs
OE
DATA
ii"iiRo WE
MEMORY
DMWR
ADDR
16k X 16
DMACK
DATA
DMA
DMD
CE
OE
BR SG
WE
PERIPHERALS
ACK
DATA
Figure 7. Basic System Configuration
2-28 DSP PROCESSORS
To allow interfacing to slower peripherals, the data memory
acknowledge (DMACK) signal is provided. The ADSP-2100
checks the status of the DMACK signal at the end of each
processor cycle. If the D MACK signal is not asserted, the processor
extends the current cycle by another full cycle. This extension
occurs as many times as necessary until the DMACK signal is
assened and the access is completed.
Interrupt Handling
The ADSP-2100 provides four direct interrupt input pins, IRQo
to IRQ3' Each interrupt pin corresponds to a panicular interrupt
priority level from 3 (highest) to 0 (lowest). The four interrupt
levels are internally prioritized and individually maskable.
These input pins can be programmed to be either level- or edge-
sensitive.
The ADSP-2100 supports a vectored interrupt scheme: when an
external interrupt is acknowledged, the processor switches program
control to the interrupt vector address corresponding to the
interrupt level (program memory locations 0000 to 0003). Inter-
rupts can optionally be nested so that a higher priority interrupt
can preempt the currently executing interrupt service routine.
Processor Control Interface
The processor control interface provides external control over
the activity of the processor. The control signals are RESET,
HALT and TRAP.
The RESET signal initiates a master reset of the ADSP-2100.
The RESET signal must be asserted after the chip is powered
up to assure proper initialization. The master reset perfonns the
following:
I Initialize internal clock circuitry
2 Reset all internal stack pointers
3 Clear the cache memory monitor
4 If there is no pending bus request, PMA is driven with 0004
5 Mask all interrupts
6 Clear MST A T register.
The HALT signal is used to suspend program execution tem-
porarily. When HALT is asserted, the processor stops at the
end of the current instruction. To ensure that the processor
always halts after completion of an instruction fetch, an external
fetch of the next instruction is forced even if the instruction is
available from internal cache memory. Since the processor always
stops after an external instruction fetch cycle, the controlling
device is able to observe the instruction address where the program
was stopped. The halt condition can be sustained for any length
of time, during which all signals generated by the processor will
remain static (maintaining the output at state 8). The processor
will continue nonnal execution when the HALT line is
released.
The TRAP signal is generated by the processor whenever a
TRAP instruction is executed. Assertion of the TRAP signal
indicates that the processor has stopped instruction execution
just after the end of the cycle which executed the TRAP instruction.
The TRAP state is identical to the HALT state, with the processor
output frozen in state 8. In this case, the processor PMA bus
contains the address of the instruction following the TRAP
instruction. The TRAP signal remains asserted until the HALT
signal is assened externally. When the HALT signal assertion is
sensed, the processor releases the TRAP signal. However, the
processor remains in the halt condition until the HALT line is
released.
ADSP-21 OO/ADSP-21 OOA
Multiprocessor Synchronization
Even when multiple ADSP-2100s are driven from the same
CLKIN signal, there is a phase ambiguity between the various
processors. This ambiguity can be prevented by using a single
master RESET signal synchronized to CLKIN. When the master
RESET is released, all the processors begin state 5 on the same
edge of CLKIN. Once initialized in this manner, the cycle
states of the processors remain synchronized with each other.
INSTRUCTION SET DESCRIPTION
The ADSP-2100 assembly language uses an algebraic syntax for
ease of coding and readability. The sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.
Nevenheless, every instruction assembles into a single 24-bit
word and executes in a single cycle. The instructions encompass
a wide variety of instruction types along with a high degree of
operational parallelism. There are five basic categories of in-
structions: data move instructions, computational instructions,
multifunction instructions, program flow control instructions
and miscellaneous instructions. Each of these instruction types
is described briefly. The complete instruction set is summarized
in Table IV at the end of this section.
Data Move Instructions
Table II gives a list of all registers that are accessible using the
data move instructions. (Only the program counter (PC), the
instruction register, the arithmetic feedback register (AF) and
the multiplier feedback register (MF) are not on this list.) This
set of registers is denoted as reg in the instruction set summary
given in Table IV. A subset of the reg group associated with the
computational units, which generally hold data as opposed to
address or status information, is denoted as dreg.
The data move instructions include transfers between internal
registers, between data memories and internal registers, between
program memories and internal registers, and immediate value
loading of registers and data memories. The content of every reg
AXO,AXI
AYO,AYI
AR
MXO,MXI
MYO,MYI
MRO,MRI,MR2
SI
SE
SRO,SRI
SB
PX
Data
Registers
(dreg)
10, II, 12, 13, 14, 15, 16, 17
MO,MI,M2,M3,M4,M5,M6,M7
LO, LI, L2, L3, L4, L5, L6, L7
CNTR
ASTAT
MSTAT
SSTAT
IMASK
ICNTL
Accessible
Registers
(reg)
Table II. Register Classification
OSP PROCESSORS 2-29
can also be loaded to any other reg. Every reg can be loaded
with an immediate value which is the full width of the particular
register being loaded.
Two addressing modes are supported for data memory transfers:
direct addressing and indirect addressing. In direct addressing,
the memory address is supplied from the instruction word. In
indirect addressing, one of the data address generators provides
the address. Using direct addressing, the content of a data memory
location can be written and read by any reg. Using indirect
addressing, the content of a data memory location can only be
written and read by a dreg. Immediate data load to data memory
is permitted with indirect addressing. Only the indirect addressing
mode is supported for program memory data transfers, and
contents of a program memory location can be read and written
to any dreg.
Computational Instructions
There are three types of operations associated with the computa-
tional units: AL U operations, MAC operations and shifter oper-
ations. With few exceptions, all these computational instructions
can be made conditional. (The permissible conditions are specified
in Table I.) Each computational unit has a set of input registers
and output registers. A list of permissible input operands and
result registers for each of the units is given in Table III.
Multifunction Instructions
Multifunction instructions execute one computational operation
with one or two data moves. All of the multifunction instructions
utilize various combinations of the computational and data move
operations described above. Since the instruction word is only
24 bits wide, only certain combinations are valid. In general,
the following rules are followed.
2
3
4
Only one unconditional computational operation can be
specified
Any memory transfer must use the indirect addressing
mode
Data move operations can only involve data registers
(dregs)
Only an ALU or a MAC operation can be specified with
two operand fetches, one from program memory and one
from data memory.
2-30 DSP PROCESSORS
Program Flow Control Instructions
Program flow control instructions include JUMP, CALL, return
from subroutine, return from interrupt, DO UNTIL and TRAP.
All of these instructions can be made conditional. The JUMP
and CALL instructions support both direct addressing, with the
destination address specified by the instruction word, and indirect
addressing, with the destination address specified by one of the
I registers in DAG2.
Miscellaneous Instructions
Miscellaneous instructions include indirect register modify,
stack control, mode control and NOP operations.
ALU
Source for
X input port (xop)
AXO,AXI
AR
MRO,MRI,MR2
SRO,SRI
MAC
Source for
X input port (xop)
MXO,MXl
AR
MRO,MRI,MRZ
SRO SRI
Shifter
Source for
Shifter input (xop)
SI
AR
MRO,MRI,MR2
SRO,SRI
Source for
Y input port (yop)
AYO,AYI
AF
Source for
Y input port (yop)
MYO,MYI
MF
Destination for
output port R
AR
AF
Destination for
output port R
MR(MR2,MRI,MRO)
MF
Destination for
Shifter output
SR (SRI, SRO)
Table III. Computational Input/Output Registers
These conventions are used in Table IV:
1. All keywords are shown in capital letters .
2. Brackets enclose optional parts of the syntax.
3. Vertical lines indicate that one parameter must be chosen from those
enclosed.
4. Table I defmes the conditions for condition.
S. Table II defmes the set of registers for dreg and reg.
6. Table III defmes the set of registers for xop andyop.
7. <data> represents an immediate value.
S. <address> may bean immediate value or label.
9. <comp>, in a multifunction instruction, represents all legal AL U ,
MAC Shifter operations with these restrictions:
- All operations are performed unconditionally
- Shift Immediate operations are not allowed
- ALU division (DIVS, DIVQ) is not allowed
DATA MOVE INSTRUCTIONS
Register Move
reg = reg;
Load Register Immediate
reg = <data>;
Data Memory Read (direct address)
reg = DM address;
Data Memory Read (indirect address)
dreg = DM( ); 10 , MO
11 MI
12 M2
13 M3
14 M4
IS MS
16 M6
17 M7
Program Memory Read (indirect address)
dreg = PM (14 M4);
IS MS
16
17
M6
M7
Data Memory Write (direct address)
DM address = reg;
Data Memory Write (indirect address)
DM( ) = I dreg I;
<data>
10 , MO
II MI
12 M2
13 M3
14 M4
IS MS
16 M6
17 M7
Program Memory Write (indirect address)
PM ( 14 , M4 ) = dreg;
IS MS
16 M6
17 M7
COMPUTATIONAL INSTRUCTIONS: ALU
Add/ Add with Carry
[ IF condition] I I
= xop
I
+yop I

ADSP-2100/ADSP-2100A
Subtract X-Y/Subtract X-Y with Borrow
[ IF condition]
I
= xop
I-YOP I
-yop+C-1
Subtract Y -X/Subtract Y -X with Borrow
[ IF condition]
I
= yop
I-xo
p
-xop+C-1
AND, OR, Exclusive OR
[ IF condition]

xop
I
yop
XOR
Pass/Clear
[ IF condition]
I
PASS xop
yop
Negate
I
[ IF condition] xop
yop
NOT
[ IF condition]
I
NOT xop
yop
Absolute Value
[ IF condition]

ABS
I
xop
yop
Increment
[ IF condition J
I
yop +1
Decrement
[ IF condition]
I
yop -I
Divide
DIVS yop, xop ;
DIVQ xop ;
COMPUTATIONAL INSTRUCTIONS: SHIFTER
Arithmetic Shift
[ IF condition]
Logical Shift
[ IF condition]
Normalize
[ IF condition]
Derive Exponent
SR
SR
SR
[ IF condition] SE
Block Exponent Adjust
[SR OR] ASHIFT xop I (HI) I
(La)
[SR OR] LSHIFT xop I (HI) I
(La)
[SR OR] NORM xop
EXPxop I (HI) I;
(LO)
(HIX)
I
(HI) I
(La)
[IFcondition] SB = EXPADJ xop
asp PROCESSORS 2-31

Arithmetic Shift Immediate
SR = [SRORl ASHIFT xop BY <data>
Logical Shift Immediate
SR =[SROR] LSHIFT xop BY <data>
COMPUTATIONAL INSTRUCTIONS: MAC
MUltiply
[IF condition] MR xop*yop
MF
Multiply Accumulate
[ IF condition]
I MR
MR+xop*yop
MF
Multiply Subtract
[ IF condition]
I MR
MR-xop*yop
MF
Clear
[ IF condition]
I ~ I
0
TransferMR
[ IF condition]
I ~ I
MR [(RND)]
MULTIFUNCTION INSTRUCTIONS
Computation with Memory Read
<comp> , dreg = DM( IO
2-32 DSP PROCESSORS
II
12
I3
14
IS
16
17
PM ( 14
IS
16
17
, MO
Ml
M2
M3
M4
MS
M6
M7
, M4
MS
M6
M7
(
(
I (HI) I
(LO)
I (HI) I
(LO)
SS ) ;
SU
US
UU
RND
SS
SU
US
UU
RND
SS
SU
US
UU
RND
) ;
Conditional MR Saturation
IFMVSATMR;
PROGRAM FLOW CONTROL INSTRUCTIONS
Jump
[IF condition] JUMP ( 14
Call
15
16
17
<address>
[IF condition] CALL ( 14
Return from Subroutine
[IFcondition] RTS ;
Return from Interrupt
[ IF condition] R TI
Do Until
IS
16
17
<address>
DO <address> [UNTIL condition]
Trap
[ IF condition] TRAP ;
) ;
Computation with Data Register Move
<comp> , dreg = dreg ;
Computation with Memory Write
DM( ) = dreg, <comp> 10 , MO
II
12
I3
14
IS
16
17
PM ( 14
IS
16
17
Ml
M2
M3
M4
MS
M6
M7
M4
MS
M6
M7
ADSP-21 OO/ADSP-21 OOA
Data & Program Memory Read
AXO = DM ( 10 , MO ),
AXI 11 Ml
AYO
AYI
MYO
MYI
= PM ( 14
15
16
17
, M4 );
MS
MXO 12 M2 M6
MXl 13 M3 M7
ALU/MAC Operation with Data & Program Memory Read
I
<ALU> , AXO = DM ( 10 , MO ), AYO = PM ( 14
<MAC> AXI 11 Ml A Yl 15
MXO 12 M2 MYO 16
MXl 13 M3 MYI 17
* AL U Division operations not allowed.
MISCELLANEOUS INSTRUCTIONS
Stack Control
[IPUSHI STS] [,POPCNTR] [,POPPC]
[ POP
Modify Address Register
MODIFY ( ) ; 10 , MO
No Operation
NOP;
11
12
13
14
IS
16
17
Ml
M2
M3
M4
MS
M6
M7
[,POPLOOP] ;
Table IV. Instruction Set Summary
, M4 );
MS
M6
M7
DSP PROCESSORS 2-33

SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ADSP2100/ADSp2100A
J,K,AJ,AK S,AS,AT
Grades Grades
Parameter
Min Max Min Max
Voo
Supply Voltage 4.75 5.25 4.50 5.50
TAMB
Ambient Operating Temperature 0 +70 -55 + 125
ELECTRICAL CHARACTERISTICS
ADSP2100
J&K S
Grades Grade
Parameter Test Conditions Min Max Min Max Unit
VIH Hi-Level Input Voltage' @Vnn=max 2.0 2.2
VIL Lo-Level Input Voltage' @Vnn=min O.S O.S V
VOH Hi-Level Output Voltage
2
@Vnn=min,loH=-lmA 2.4 2.4 V
VOL Lo-Level Output Voltage
2
@Vnn=min,loL=4mA 0.4 0.6 V
IIH Hi-Level Input Current
3
@Vnn=max,VIN=max 10 10 .,.A
IlL Lo-Level Input Current
3
@Vnn=max,VIN=OV 10 10 .,.A
IOZH Tristate Leakage Current' @;VOD=max, VIN =max
7
10 10 .,.A
lozL
Tristate Leakage Current' @Vnn=max,VIN=OV7 10 10 .,.A
IOZL
Tristate Pullup Current" @Vnn=max,VIN=OV7 150 150 .,.A
Inn Supply Current (Power-Down)" @Vnn =max,V
IN
=OV"7 10 15 rnA
Inn
Supply Current (Dynamic) @Vnn=max,maxclockrate" 90 100 rnA
ADSP-2100A
AJ&AK AS AT
Grades Grade Grade
Parameter Test Conditions Min Max Min Max Min Max Unit
VIH Hi-Level Input Voltage' @Vnn=max 2.0 2.2 2.2 V
VIH Hi-Level Input Voltage at CLKIN @Vnn=max 2.2 2.4 2.4 V
VII. Lo-Level Input Voltage' @Vnn=min O.S O.S O.S V
VII. Lo-Level Input Voltage at CLKIN @Vnn=min O.S O.S O.S V
VOH Hi-Level Output Voltage
2
@Vnn=min,loH= -lmA 2.4 2.4 2.4 V
VOL Lo-Level Output Voltage
2
@Vnn =min,loL =4mA 0.4 0.6 0.6 V
IIH Hi-Level Input Current
3
@IVDD=max,VIN=max 10 10 10 .,.A
III. Lo-Level Input Current
3
@Vnn=max,VIN=OV 10 10 10 .,.A
IOZH Tristate Leakage Current' @Vnn=max,VIN=max7 10 10 10 .,.A
IozL Tristate Leakage Current> @Vnn-max, VIN-OV
7
10 10 10 .,.A
IozL Tristate Pullup Current" @Vnn=max, VIN =OV
7
ISO ISO ISO .,.A
Inn Supply Current (Power-Down)" @Vnn =max,VIN=OV"7 10 15 15 rnA
Inn Supply Current (Dynamic) @Vnn = max, max clock rate" 150 130 ISO rnA
NOTES
I Applies to pins: DMDo_15 , SR, IROo_ 3, DMACK, RESET, HALT, (48 tnput pms for ADSP-2100A). Includes eLKIN for ADSP-2100 (49 input pms).
2Applies to pins: PMAo_w PMS, PMDo_wPMRD. PMWR, PMDA, BG, DMA
o
_
lJ
, OMS, DMD
o
_
1s
DMRD. DMWR, TRAP,CLKOUT(78 output pins).
l Applies to pins: BR. IRQ,_l' DMACK, RESET , HALT, CLKIN (9 mputonly pms).
4Applies to pins: PMAo. 13' PMS, PMDo_23 PMRD. PMWR, PMDA, DMAo. 13' DMS, DMDo_15 , DMRD. DMWR(75 lrlstateable pms).
5 Applies to pins: PMAo_IJ' PMDA, (29 tristateable pins wlo pullup).
6Applies to pins: PMD
O
_2j, PMS, PMRD. PMWR, DMD
o
_
15
DMS, DMRD. DMWR(46 tristateable pms w/pullup).
7 Additional Test Condaions: VIN = OV on iiR and RESET, CLKIN active, forces tristate condition.
8Addaional TestCondittons: Outputs loaded TTL loads w/lOOpFcapacitance. V1H = 2AV, V1L = O.4V,ciock rate = max.
9<'Power-down" refers to an idle state. While the processor does not have any special standby or low-power mode, these conditions represent the
lowest power consumption state.
2-34 DSP PROCESSORS
Unit
V
C
ADSP-2100/ADSP-2100A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . -0.3V to +7V
Input Voltage . . . . . -0.3V to VDD +0.3V
Output Voltage Swing. -0.3V to VDD +0.3V
Operating Temperature Range (Ambient) - 55'C to + 125'C
Storage Temperature Range . . . - 65'C to + 150'C
Lead Temperature (IOsec) PGA . . . .. ... .. + 300'C
Lead Temperature (5sec) PQFP . . . .. + 280'C
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specificatlon is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ORDERING INFORMATION
Temperature
Part Number Speed (MHz) Range Package
ADSP-2100JG 6.144 Oto + 70'C l00-Pin Grid Array
ADSP-2100KG 8.192 Oto + 70'C IOO-Pin Grid Array
ADSP-2100AJG 10.24 Oto +70'C 100-Pin Grid Array
ADSP-2100AKG 12.50 Oto + 70'C 100-Pin Grid Array
ADSP-2100JP 6.144 Oto +70'C IOO-PQFP
ADSP-2100KP 8.192 Oto +70'C 100-PQFP
ADSP-2100AJP 10.24 Oto + 70'C lOO-PQFP
ADSP-2100AKP 12.50 Oto +70'C 100-PQFP
ADSP-2100SG 6.144 - 55'C to + 125'C 100-Pin Grid Array
ADSP-2100ASG 8.192 - 55'Cto + 125'C l00-Pin Grid Array
ADSP-2100ATG 10.24 - 55'C to + 125'C 100-Pin Grid Array
ADSP-2100SGI883B 6.144 - 55'C to + 125'C IOO-Pin Grid Array
ADSP-2100ASGI883B 8.192 - 55'C to + 125'C IOO-Pin Grid Array
ADSP-2100ATGI883B 10.24 - 55'C to + 125'C IOO-Pin Grid Array
ADSP-2100/ ADSP2100A Development Tools
Description
Cross-Software and Simulator (VAXIVMS)
Cross-Software (IBM PCIDOS)
Simulator (IBM PCIDOS)
Cross-Software and Simulator (Sun 213, Unix BSD 4.2)
C Compiler, Cross-Software and Simulator (V AXIVMS)
Package
Outline
G-lOOA
G-IOOA
G-IOOA
G-IOOA
P-IOO
P-IOO
P-lOO
P-lOO
G-IOOA
G-IOOA
G-IOOA
G-lOOA
G-lOOA
G-IOOA
Part Number
ADDS-2110
ADDS-2I21
ADDS-2122
ADDS-2123-C
ADDS-2I30
ADDS-2l31
ADDS-2I33-C
C Compiler, Cross-Software and Simulator (IBM PCIDOS)
CCompiler, Cross-Software and Simulator (Sun 213, Unix BSD 4.2)
ESD SENSITIVITY
ADDS-2150A
ADDS-2150AE
ADDS-215IA
ADDS-215IAE
ADDS-2161
ADDS-2160
ADDS-2169
ADDS-2190
ADSP-2100A 8MHz In-Circuit Emulator (lIOV)
ADSP-2IOOA 8MHz In-Circuit Emulator (220V)
ADSP-2100A 8MHz In-Circuit Emulator (lIOV) with Trace Board
ADSP-2100A 8MHz In-Circuit Emulator (220V) with Trace Board
Trace Board Option for ADDS-2150 or ADDS-2150E
ADSP-2100A 8MHz Evaluation Board
University Package (ADDS-2I31 and ADDS2160)
Three Day ADSP-2100 Workshop
The ADSP-2100 and ADSP-2100A feature proprietary input protection circuitry. Per Method 3015
of MIL-STD-883, the ADSP-2100 has been classified as a Class I device and the ADSP-2100A as a
Class 2 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance degra-
dation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and
discharge without detection. Unused devices must be stored in conductive foam or shunts, and the
foam should be discharged to the destination socket before devices are removed. For further informa-
tion on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
WARNING! 0
~ ~ D E V I C E
DSP PROCESSORS 2-35
SWITCHING CHARACTERISTICS
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While
this addition or subtraction would yield meaningful results for an individual part, the values given in this data sheet reflect statistical
variations and worst cases. Consequently, you cannot meaningfully add up parameters to derive or "verify" longer times.
TIMING NOTES
Switching characteristics specify how the processor is switching its signals. The user has no control over this operation. It is
dependent on the internal design. Timing requirements specify the timing of signals that the user has control over such as the
placement of data on the DMD bus as input for a read operation.
Timing requirements are used by a designer to guarantee that the processor operates correctly with another device while switching
characteristics inform the designer what the device is doing under any given circumstance. Switching characteristics are also
referenced to ensure that any timing requirement of a device connected to the processors (such as a memory) is satisfied.
SPECIFICATIONS
In this edition of the data sheet a number of specifications have been removed. The old parameter numbering has been retained
for continuity. The specifications in this data sheet are the only ones required to design with the ADSP2100.
MEMORV REQUIREMENTS
This chart links common memory device specification names and ADSP2100/ADSP2100A timing parameters for your
convenience.
Parameter Parameter CommoDMemory Device
Number Name SpecificatioD Name
41 PMA Valid toPMWR Low Address Set Up Time
79 DMA Valid to DMWR Low Address Set Up Time
42 mwiHigh to PMA Invalid Address Hold Time
80 DMWR High to DMA Invalid Address Hold Time
55 PMD Out Valid to PMWR High Data Set Up Time
91 DMD Out Valid to DMWR High Data Set Up Time
54 PMWR High to PMD Out Invalid Data Hold Time
90 DMWR High to DMD Out Invalid Data Hold Time
58 PMRDLowtoPMDInputValid OE to Data Valid
94 DMRD Low to DMD Input Valid OE to Data Valid
59 PMA ValidtoPMDInputValid Address Access Time
95 DMA Valid to DMD Input Valid Address Access Time
Notes I and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP2100 Test JGrade KGrade SGrade Derating
Clock Signals Code Min Max Min Max Min Max Uaits Factor
Timing Requirements
I CLKIN Period I A 40.5 30.5 40.5 ns
2 CLKIN Width Low A 11 8 11 ns
3 CLKIN Width High A 18 12 18 ns
Switching C haracteTistics
4 CLKIN Low (3-4) to CLKOUT Low B 13 34 13 29 11 34 ns
5 CLKIN Low (7-8) to CLKOUT High B 6 24 6 20 5 24 ns
6 CLKOUTWidth Low A 60 45 60 ns 4
2-36 DSP PROCESSORS
ADSP-21 DD/ADSP-21 DOA
Notes I and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP-2100A Test AJGrade AKGrade AS Grade AT Grade
Clock Signals Code Min Max Min Max Min Max Min Max Units
Timing Requirements
I CLKIN Period
1
A 24.4 20 30.5 24.4 ns
2 CLKIN Width Low A 7 4 8 7 ns
3 CLKIN Width High A 9 8 12 9 ns
Switching Characteristics
4 CLKIN Low (3-4) to CLKOUT Low B 24 22 29 24 ns
5 CLKIN Low (7-8) to CLKOUT High B 20 18 20 20 ns
6 CLKOUT Width Low A 36 28 45 36 ns
ClKIN
r.'I _.

: : -1
1 I
i r

, '.:::..J '
ClKOUT
NOTE
The Processor Cycle is Divided into 8 Internal States Determined by the Rising and Falling Edges
of ClKIN. CLKOUT is Synchronizad to the Processor States as Shown Above,
Figura 8, Clock Signals
Notes I and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP-2100 Test JGrade KGrade SGrade Derating
Control Signals Code Min Max Min Max Min Max Units Factor
Timing Requirements
7 RESET Low to CLKIN High B 2 2 2 ns
8 CLKIN High to RESET High B 6 36 4 26 6 36 ns 2 (max only)
9 RESET Width Low A 162 122 170 ns 8
ADSP-2100A Test AJGrade AKGrade AS Grade AT Grade
Control Signals Code Min Max Min Max Min Max Min Max Units
Timing Requirements
7 RESET Low to CLKIN High B 2 2 2 2 ns
8 CLKIN High to RESET High B 4 20 4 16 6 26 4 20 ns
9 RESET Width Low A 98 80 128 98 ns
ClKIN
NOTE
The Reset signal determines the phase of the processor cycle.
The processor starts from state 4 after the release of the Reset signal.
Figura 9. ifESE'f Signal
Derating
Factor
4
Derating
Factor
2 (max only)
8
DSP PROCESSORS 2-37

Notes 1 and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP2100 Test JGrade KGrade SGrade Derating
Control Signals Code Min Max Min Max Min Max Units Factor
Timing Requirements
10 HALT Valid to CLKIN Low (34) B 0 0 0 ns
11 CLKIN Low (3-4) to HALT Invalid B 12 10 12 ns
Switching Characteristics
12 CLKIN Low (78) to TRAP Valid B 25 20 25 ns
Interrupts
Timing Requirements
13 CLKIN Low (78) to IRQ Valid B 2 2 1 ns
14 CLKIN Low (78) to IRQ Invalid B 21 17 21 ns
ADSP.2100A Test AJGrade AKGrade AS Grade AT Grade
Control Signals Code Min Max Min Max Min Max MiD Max Units
Timing Requirements
10 HALT Valid to CLKIN Low (34) B 2 2 2 2 ns
11 CLKIN Low (34) to HALT Invalid B 10 8 10 10 DS
Switching Characteristics
12 CLKIN Low (7-8) to TRAP Valid B 18 16 20 18 ns
Interrupts
Timing Requirements
13 CLKIN Low (7-8) to IRQ Valid B 1 1 1 1 DS
14 CLKIN Low (7-8) to IRQ Invalid B 14 14 17 14 DS
elKIN
: 4
i i-@
:

TRAP
-: :+@ .,
t X'---_
IRQO3
NOTE
---i:

_i:+@

The Control Signals are Shown in Relationship to the Processor States in Which They are
or Asserted as Defined by ClKIN. There is No Implied Relationship between
HALT, TRAP, and IRQ._3'
Figure 10. Control Signals
2-38 DSP PROCESSORS
Derating
Factor
ADSP-2100/ADSP-2100A
Notes 1 and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP2100
Bus Request Asserted
Timing Requirements
15 BR Valid to CLKIN Low (34)
16 CLKIN Low (34) to BR Invalid
Switching Characteristics
17 CLKIN Low (34) to BG Low
19 BG Low to xMxx Disable
2
ADSP2100A
Bus Request Asserted
Timing Requirements
15 BR Valid to CLKIN Low (34)
16 CLKIN Low (34) to BR Invalid
Switching Characteristics
17 CLKIN Low (34) to BG Low
19 BG Low to xMxx Disable
2
elKIN
Test
Code
B
B
B
D
Test
Code
B
B
B
D
.
.
JGrade
Min Max
I
10
38
22
AJGrade
Min Max
4
4
26
16
KGrade SGrade Derating
Min Max Min Max Units Factor
1 1 ns
7 10 ns
30 38 ns
17 22 ns
AKGrade AS Grade AT Grade Derating
Min Max Min Max Min Max Units Factor
4 1 4 ns
4 7 4 ns
24 30 26 ns
16 17 16 ns

ir-T"T"T""C01I......-rT""lIOIIr-r-r-r-r/IR-r-r-r-T01-
-.:

-.: j4-@
xMxx
____ ----:...-----J}-
NOTE: RESET NOT PERMITTED DURING BR.
Figure 11. Bus Request Asserted
DSP PROCESSORS 2-39
Notes 1 and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP-2100 Test JGrade KGrade SGrade Derating
Bus Request Negated Code Min Max Min Max Min Max Units Factor
Timing Requirements
IS BR ValidtoCLKINLow(3-4) B I I I ns
16 CLKIN Low (3-4) to BR Invalid B 10 7 10 ns
Switching Characteristics
18 CLKIN Low (7-8) to BG High B 31 25 31 ns
20 xMxx Enable to BG High
2
F 12 10 12 ns
ADSP-2100A Test AJGrade AKGrade AS Grade AT Grade Derating
Bus Request Negated Code Min Max Min Max Min Max Min Max Units Factor
Timing Requirements
IS BR Valid to CLKIN Low (34) B 4 4 I 4 ns
16 eLKIN Low (3-4) to BR Invalid B 4 4 7 4 ns
SwilChingCharacteristics
18 CLKIN Low (7-8) to BG High B 24 20 25 24 ns
20 xMxx Enable to BG High
2
F 10 8 10 10 ns
elKIN

-+:i+-@
ommtl m\\\\\\\\\\\\\\\\\
:: : :
" , -+i j4-@
i ,tr--"----

--
xMxx
Figure 12. Bus Request Negated
2-40 DSP PROCESSORS
ADSP-2100/ADSP-2100A
Notes 1 and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP2100 Test JGracie KGrade SGrade Deratilll
Bus Request/Grant with mET Low Code Min Max Min Max Min Max Units Factor
Switching Characteristics
21 BR Low to BG Low durinll: reset A 28 23 28 ns
22 BR High to BG High during reset A 21 18 21 ns
ADSP2100A Test AJGrade AKGrade AS Grade AT Grade
Bus Request/Grant with Low Code Min Max Min Max Min Max Min Max Units
Switching Characteristics
21 BR Low to BG Low during reset A 18 16 23 18 ns
22 BR High to BG High during reset A 16 14 18 16 ns
NOTE
During Reset, the Processor Bus Ignores the elKIN Signal and Therefore the Bus Request/Grant
Signals Operate Asynchronously.
Figure 13. Bus Request/Grant with RESET Low
Derating
Factor
DSP PROCESSORS 2-41
Notes I and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP2100 Test JGrade KGrade SGrade Derating
Program Memory Read Code Min Max Min Max Min Max Units Factor
Switching Characteristics
31 PMRDWidthLow A 60 45 60 ns 4
32 PMA Valid to PMRD Low A 18 II 18 ns 3
33 PMRD High to PMA Invalid A 20 16 20 ns I
34 PMDAValid toPMRD Low A 41 31 41 ns 3
35 PMRD High to PMDA Invalid A 23 18 22 ns I
36 PMS Valid to PMRD Low A 55 40 55 ns 3
37 PMRD High to PMS Invalid A 16 12 16 ns I
TIming Requirements
58 PMRD Low to PMD Input Valid A 45 37 45 ns 4
59 PMA Valid toPMD Input Valid A 57 50 57 ns 7
60 PMS Valid to PMD Input Valid A 90 65 90 ns 7
97 PMRD High to PMD Input Invalid A 0 0 0 ns
ADSP.2100A Test AJGrade AKGrade AS Grade AT Grade Derating
Program Memory Read Code Min Max Min Max Min Max Min Max Units Factor
Switching Characteristics
31 PMRD Width Low A 36 28 45 36 ns 4
32 PMA Valid toPMRD Low A 6 4 14 6 ns 3
33 PMRD High to PMA Invalid A 8 6 10 8 ns I
34 PMDA Valid toPMRD Low A 20 18 24 20 ns 3
35 PMRD High to PMDA Invalid A 10 10 12 10 ns I
36 PMS Valid toPMRD Low A 32 26 40 32 ns 3
37 PMRD High to PMS Invalid A 8 6 8 8 ns I
Timing Requirements
58 PMRD Low to PMD Input Valid A 28 20 33 28 ns 4
59 PMA Valid toPMD Input Valid A 46 32 so 46 ns 7
60 PMS Valid to PMD Input Valid A 50 45 65 50 ns 7
97 PMRD High to PMD Input Invalid A 0 0 0 0 ns
2-42 OSP PROCESSORS
ADSP-2100/ADSP-2100A
, ,
i+@+j
________ I -C
L4J

PMDA -----Jx [ I I X,----
@::!
: 6:: \ I t \,... ____ _
'\ 1 ! I
PMRD
PMD
Figure 14. ProgramMemoryRead
DSP PROCESSORS 2-43
--- - -- --
Notes I and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADsp:noo Test JGrade KGrade SGrade Deratiq
Program Memory Write Code Min Max Min Max Min Max Units Factor
Switching C haracleristics
40 PMWR Width Low A 60 4S 60 ns 4
41 PMAValidtoPArWl{Low A 16 10 16 ns 3
42 PMWR High to PMA Invalid A 19 IS 19 ns I
43 PMDA Valid toPMWR Low A 39 29 39 ns 3
44 PMWR High to PMDA Invalid A 20 16 21 ns I
45 I'MS Valid to PMWR Low A S4 40 S4 nil 3
46 PMWR High to PMS Invalid A 15 11 14 ns I
51 PMWR Low to PMD Out Enable F 15 10 15 ns I
52 PMWR High to PMD Out Disable D 43 37 43 ns I
53 PMWRLowtoPMDOutValid A 40 32 40 ns I
54 PMWR High to PMD Out Invalid A 23 18 21 ns I
55 PMD Out Valid to PMWR High A 33 25 33 ns 3
ADSP2100A Test AJGrade AKGrade AS Grade AT Grade Deratiq
Program Memory Write Code Min Max Min Max Min Max Min Max Units Factor
SwilChingCharaclerislics
40 PMWRWidth Low A 36 28 45 36 ns 4
41 PMAValidtoPMWRLow A 8 4 12 8 ns 3
42 PMWR High to PMA Invalid A 8 6 10 8 ns I
43 PMDA Valid to PMWR Low A 20 16 28 20 ns 3
44 PMWRHigh toPMDA Invalid A 10 8 12 10 ns I
45 PMS Valid to PMWR Low A 32 26 40 32 ns 3
46 PMWRHigh toPMS Invalid A 6 4 8 6 ns 1
51 PMWR Low to PMD Out Enable F 8 6 8 8 ns I
52 PMWR High toPMD Out Disable D 32 29 38 32 ns I
53 PMWR Low to PMD Out Valid A 29 26 32 29 ns 1
54 PMWRHigh to PMD Out Invalid A 10 8 12 10 ns I
55 PMD Out Valid to PMWR High A 16 13 25 16 ns 3
2-44 DSP PROCESSORS
PMA
PMDA
PMD
,
,
ADSP-21 DD/ADSP-21 DDA
:,------V-::,

7 ! N
____________ J i : ,
!:
:---:-"-.;1- ---------- I , :
:: \: rt ..... -------
I \ \ \
I \ \ \
I \ \ \
I \ \ \
" , , ,
--.l
:
,
,
, :
! !
, , ,

I: 1
, "
, "
=-; \'----
'I
-J "V I

-+i I : ::

1 1 : !: :
Figure 15. Program Memory Write
DSP PROCESSORS 2-45

Notes 1 and 2 and information about the Derating Factors and Test Codes appear on page 2-50.
ADSP-2100 Test JGrade
Data Memory Read Code Min Max
Switching Characteristics
67 DMRD Width Low A 60
68 DMAValid toDMRD Low A 21
69 DMRD High to DMA Invalid A 19
70 DMS Valid to DMRD Low A 35
71 DMRD High to DMS Invalid A 22
101 DMACK Low to CLKOUT High A 45
Timing Requirements
74 DMRD Low to DMACK Valid A 31
75 DMA Valid to DMACK Valid A 57
94 DMRD Low to DMD Input Valid A 57
95 DMA Valid to DMD Input Valid A 82
96 DMS Valid to DMD Input Valid A 96
98 DMRD High to DMD Input Invalid A 0
100 DMACKWidth A 81
102 CLKOUT Low to DMACK High A 28
ADSP2100A Test AJGrade
Data Memory Read Code Min Max
Switching Characteristics
67 DMRD Width Low A 36
68 DMA Valid to DMRD Low A 6
69 DMRD High to DMA Invalid A 8
70 DMS Valid to DMRD Low A 18
71 DMRD High to DMS Invalid A 8
101 DMACK Low to CLKOUT High A 36
Timing Requirements
74 DMRD Low to DMACK Valid A 16
75 DMA Valid to DMACK Valid A 30
94 DMRD Low to DMD Input Valid A 30
95 DMA Valid to DMD Input Valid A 48
96 DMS Valid to DMD Input Valid A 52
98 DMRD High to DMD Input Invalid A 0
100 DMACKWidth A 50
102 CLKOUT Low to DMACK High A 17
NOTE ON GENERATING WAlT STATES
FigUles 16a and 17a show the timing of DMACK relative to the
data memory bus and control signals. If DMACK is not asserted
in this time frame, a wait state will result. Figures 16b and 17b
provide additional timing for DMACK with respect to CLKOUT
so that any number of additional wait states can be introduced.
Since CLKOUT is the only output active during a wait state, it
can be used as a cycle counter to determine when the appropriate
number of wait states has elapsed. DMACK can be latched for
the appropriate number of cycles or a counter can be used to
count CLKOUT cycles.
2-46 DSP PROCESSORS
KGrade SGrade Derating
Min Max Min Max Units Factor
45 60 ns 4
16 21 ns 3
15 19 ns 1
27 35 ns 3
18 21 ns 1
37 45 ns 1
21 31 ns 3
42 57 ns 6
41 55 ns 4
61 79 ns 7
70 96 ns 7
0 0 ns
61 81 ns 4
19 28 ns 3
AKGrade AS Grade AT Grade Derating
Min Max Min Max Min Max Units Factor
28 45 36 ns 4
4 14 6 ns 3
6 10 8 ns 1
14 27 18 ns 3
6 10 8 ns 1
32 37 36 ns 1
10 21 16 ns 3
20 42 30 ns 6
20 37 28 ns 4
32 59 46 ns 7
45 67 50 ns 7
0 0 0 ns
40 61 50 ns 4
12 19 17 ns 3
Specification # 101 shows the time from the assertion of DMACK
until the rising edge of CLKOUT. DMACK should be held low
at least this amount of time if the rising edge of CLKOUT is
used to latch the DMACK signal into your wait state logic.
Specification # 102 indicates the maximum amount of time from
the falling edge of CLKOUT to when DMACK must be brought
high to terminate the wait state condition. The falling edge of
CLKOUT can be used to clear your wait state logic.
DMA
DMACK
DMD
CLKOUT
DMACK
ADSP-2100/ADSP-2100A
i4 i I @ .: :

1 --.11--8

: :: :
Figure 16a. Data Memory Read

.

\\ f
rrTTT1ll00
-rrrr-/o
Figure 16b. Data Memory Wait States Extended with DMACK
DSP PROCESSORS 2-47
Notes I and 2 and information about the Derating Factors and Test Codes appear orl page 2-50.
ADSP2100 Test JGrade
Data Memory Write Code Min Max
SWItching Characteristics
78 DMWR Width Low A 60
79 DMA Valid to DMWR Low A 24
80 DMWR High to DMA Invalid A 20
81 DMS Valid to DMWR Low A 37
82 DMWRHillh toDMS Invalid A 22
87 DMWR Low to DMD Out Enable F 14
88 DMWR High to DMD Out Disable D 40
89 DMWR Low to DMD Out Valid A 38
90 DMWR High to DMD Out Invalid A 21
91 DMDOut Valid to DKWR High A 33
101 DMACK Low toCLKOUT High A 4S
Timing Requirements
7S DMA Valid to DMACK Valid A S7
99 DMWR Low to DMACK Valid A 31
100 DMACKWidth A 81
102 CLKOUT Low to DMACK High A 28
ADSP2100A Test AJGrade
Data Memory Write Code Min Max
Switching Characteristics
78 DMWR Width Low A 36
79 DMA Valid to DMWR Low A 8
80 DMWR High to DMA Invalid A 8
81 DMS Valid to DMWR Low A 20
82 DMWR High to DMS Invalid A 6
87 DMWR Low to DMDOut Enable F 8
88 DMWR Hjah to DMD Out Disable D 32
89 DMWR Low to DMD Out Valid A 29
90 DMWR High to DMD Out Invalid A 10
91 DMD Out Valid to DM"""WR: High A 18
101 DMACK Low toCLKOUT High A 36
Timing Requirements
7S DMA Valid to DMACK Valid A 30
99 DMWR Low to DMACK Valid A 16
100 DMACKWidth A 50
102 CLKOUT Low to DMACK High A 17
NOTE ON GENERATING WAIT STATES
Figures 16a and 17a show the timing of DMACK relative to the
data memory bus and control signals. If DMACK is not asserted
in this time frame, a wait state will result. Figures l6b and 17b
provide additional timing for DMACK with respect to CLKOUT
so that any number of additional wait states can be introduced.
Since CLKOUT is the only output active during a wait state, it
can be used as a cycle counter to determine when the appropriate
number of wait states has elapsed. DMACK can be latched for
the appropriate number of cycles or a counter can be used to
count CLKOUT cycles.
2-48 DSP PROCESSORS
KGrade SGrade Derating
Min Max Min Max Units Factor
45 60 ns 4
17 24 ns 3
15 19 ns 1
28 37 ns 3
19 22 ns 1
9 14 ns 1
3S 40 ns 1
32 38 ns 1
16 19 ns 1
21 33 ns 3
37 4S ns 1
42 57 ns 6
21 31 ns 3
61 81 ns 4
19 28 ns 3
AKGrade AS Grade AT Grade Derating
Min Max Min Max Min Max Units Fal:tor
28 4S 36 ns 4
4 17 8 ns 3
6 10 8 ns 1
16 28 20 ns 3
.
4 8 6 ns 1
6 8 8 ns 1
29 38 32 ns 1
26 32 29 ns 1
8 12 10 ns 1
13 2S 16 ns 3
32 37 36 ns 1
20 42 30 ns 6
10 20 16 ns 3
40 61 50 ns 4
12 19 17 ns 3
Specification #101 shows the time from the assertion of DMACK
until the rising edge of CLKOUT. DMACK should be held low
at least this amount of time if the rising edge of CLKOUT is
used to latch the DMACK signal into your wait state logic.
Specification # 102 indicates the maximum amount of time from
the falling edge of CLKOUT to when DMACK must be brought
high to terminate the wait state condition. The falling edge of
CLKOUT can be used to clear your wait state logic.
ADSP-21 OO/ADSP-21 OOA
DMA
--,1---fC
i! (

DMACK
DMD
Figure 17a. Data Memory Write
CLKOUT
DMACK
. .
~
\\ i fmmo
!
ill. i
Figure 17b. Data Memory Wait States Extended with DMACK
DSP PROCESSORS 2-49
NOTES
IRise and fall times ,,;4ns for ADSP-2100A, Sns for ADSP-2100.
2"xMxx" refers to PMA
o
_
13
, PMS, PMRD, PMWR, PMDA, DMA
O
_
i3
' DMS, DMRD and DMWR.
TEST CODES
Code Test Type Level Reference
A Inputs, Outputs Low=O.8V, High = 2.0V
B CLKIN I.SV
to/from
Inputs, Outputs Low = O.8V, High = 2.0V
D Output Low=O.8V, High =2.0V
to
Output Disable Low = VOL +O.SV, High = VOH-O.SV
F Output Low=O.8V,High=2.0V
to/from
Output Enable Low = VT -O.IV, High = VT +O.IV
VT = 1.SV, the voltage to which tristated outputs are forced.
DERATING FACTOR
The value N in the Derating Column shows, for each timing
parameter affected, how many of the eight internal clock states
are used by this timing parameter; N, therefore, ranges between
I and 8. The formula for changing any individual parameter T
uses timing parameter number one, CLKIN Period, shown as
P#I:
T new = Told + N P# Incw - P# laId) /2)
You determine the new value of P# I based on the derating you
wish to accomplish. If no N value is given for derating, that
timing parameter does not change with clock changes.
CAPACITANCE IN PGA PACKAGE
Input capacitance
Output capacitance
IOpF typical
IOpF typical
Note that output-only pads (PMA
i3
_
0
, PMDA and DMA
i3
_
o
)
and bidirectional pads (PMD
z3
_
0
and DMD
I5
_
0
) have SOk!}
(typical) pull-up resistors between the output and V nn present
when the output driver is off.
TO
OUTPUT
PIN
I100PF
+1.5V
Figure 18. Normal Load for ae Measurements
2-50 OSP PROCESSORS
ADSP-21 DD/ADSP-21 DDA
13 12 11 10
N PMD18 PMD20 PMD21 PMD23 BG VDD GND GND PMS TRAP HALT RESET DMAO
M PMD16 PMD17 PMD19 PMD22 PMRD iiR DMRD DMWR DMS PMDA DMACK GND DMA2
PMD14 PMD15 ClKOUT ClKIN PMWR DMAI DMA3
K PMD12 PMD13 DMA4 DMA5
PMD10 PMDII DMA6 GND
GND PMD8 PMD9 DMA7 DMA8 VDD

H
G VDD PMD7 PMD6 DMA10 DMA11 DMA9
F PMD5 PMD4 PMD3 DMD15 DMA13 DMA12
E
GND PMD2 DMD13 DMD14
D PMDI PMDO DMDII DMD12
IRQ2 iRoo
INDEX
PMAO PMA2 PMAII
PIN
DMD9 DMD10 c
B
PMAI PMA4 PMA6 PMA7 PMA9 PMA12 IRQ3 IRQl DMDI DMD3 DMD6 DMD7 DMD8
A PMA3 PMA5 GND PMAS PMA10 PMA13 VDD GND DMDO DMD2 DMD4 DMD5 GND
Figure 19. ADSP-2100 Pins, Top View, Pins Down
function Location Function Location function Location Function LocetIon
VOD A7 PMA1 B13 PMD12 K13 DMAS G1
VOD G13 PMA2 C12 PMD13 K12 DMA10 G3
VOD H1 PMA3 A13 PMD14 L13 DMA11 G2
VOD NI PMA4 B12 PMD1S L12 DMA12 F1
GND A1 PMA5 A12 PMD1S M13 DMA13 F2
GND AS PMAS B11 PMD17 M12 DMDO A5
GND A11 PMA7 B10 PMD11 N13 DMD1 B5
GND E13 PMA6 A10 PMD19 M11 DMD2 A4
GND H13
PMA9 B9 PMD20 N12 DMD3 B4
GND J1 PMA10 AS PMD21 N11 DMD4 A3
GND M2 PMA11 C8 PMD22 M10 DMD5 A2
GND N6 PMA12 B8 PMD23 N10 DMD6 B3
GND N7 PMA13 AS PMS N5 DMD7 B2
CLKlN L7 PMDO D12 PMWR L6 DMDB B1
CLKOUT L6 PMD1 D13 PMRD M9 DMD9 C2
iii M8 PMD2 E12 PMDA M4 DMD10 C1
BG Nt PMD3 F11 DMAO N1 DMD11 D2
iRiii C8 PMD4 F12 DMA1 L2 DMD12 D1
iiiQi B8 PMOS F13 DMA2 M1 DMD13 E2
IRQ2 C7 PMDB G11 DMA3 L1 DMD14 E1
iiii3 B7 PMD7 G12 DMA4 K2 DMD15 F3
Rm'i' N2 PMDB H12 DMA5 K1 DMS M5
TRAP N4 PMD9 H11 DMAS J2 6MWR MS
HALf N3 PMD10 J13 DMA7 H3 6Mii6 M7
INDEX PIN NC PMD11 J12 DMAS H2 DMACK M3
PMAO C13
Table V. ADSP-2100 Pins by Function - G-100A
DSP PROCESSORS 2-51
PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION PIN FUNCTION
1 PMD6 21 PMA10 41 DMD9 61 DMA2 81 BG
2 VDD 22 PMA11 42 DMD10 62 DMA1 82 PMRD
3 PMD5 23 PMA12 43 DMD11 63 DMAO 83 PMD23
4 PMD4 24 PMA13 44 DMD12 64 GND 84 PMD22
5 PMD3 25 IRQ3 45 DMD13 65 RESET 85 PMD21
6 GND 26 IRQ2 46 DMD14 66 DMACK 86 PMD20
7 PMD2 27 VDD 47 DMD15 67 HALT 87 PMD19
8 PMD1 28 GND 48 DMA13 68 PMDA 88 PMD18
9 PMDO 29 IRQ1 49 DMA12 69 TRAP 89 PMD17
10 PMAO 30 IRQO 50 DMA11 70 DMS 90 PMD16
11 PMA1 31 DMDO 51 DMA10 71 PMS 91 PMD15
12 PMA2 32 DMD1 52 DMA9 72 PMWR 92 PMD14
13 PMA3 33 DMD2 53 VDD 73 DMWR 93 PMD13
14 PMA4 34 DMD3 54 DMA8 74 GND 94 PMD12
15 PMA5 35 DMD4 55 DMA7 75 DMRD 95 PMD11
16 PMA6 36 DMD5 56 GND 76 ClKIN 96 PMD10
17 GND 37 DMD6 57 DMA6 77 GND 97 PMD9
18 PMA7 38 GND 58 DMA5 78 VDD 98 PMD8
19 PMA8 39 DMD7 59 DMA4 79 BR 99 GND
20 PMA9 40 DMD8 60 DMA3 80 ClKOUT 100 PMD7
Table VI. ADSP-2100PinsbyFunction-P-100
2-52 DSP PROCESSORS
~ A N A L O G
WDEVICES
FEATURES
Complete DSP Microcomputer
ADSP-2100 Code & Function Compatible
2K Words of Program Memory RAM
ADSP-2102 Version Has Up to 2K Words of Mask
Programmable Program Memory
1 K Words of Data Memory RAM
Separate Program and Data Buses On-Chip
Dual Purpose Program Memory for Both Instruction
and Data Storage
Three Independent Computational Units: ALU,
Multiplier/Accumulator and Barrel Shifter
Two Independent Data Address Generators
Powerful Program Sequencer
Zero Overhead Looping
Conditional Arithmetic Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable Interval Timer
Programmable Wait State Generation
Automatic Booting from Byte-Wide External Memory,
e.g., EPROM
Provisions for Multiprecision Computation and
Saturation Logic
Single-Cycle Instruction Execution
Multifunction Instructions ,
Three Edge- or Level-Sensitive Externallnterrupt8
80ns Cycle Time
80mW Maximum Power Dissipation ill Standby Mode
68-Pin PGA and 68-Lead PLCC
GENERAL DESCRIPTION
The ADSP-2101lADSP-2102 is a single-chip microcomputer op-
timized for digital signal processing (DSP) and other high speed
numeric processing applications. Its instruction set is a fully
compatible superset of the ADSP-2100 instruction set. It com-
bines the complete ADSP-2100 architecture (three computa-
tional units, data address generators and a program sequencer)
with two serial ports, a programmable timer, extensive interrupt
capabilities and on-chip program and data memory SRAM (or
RAM and ROM in ADSP-2102). The ADSP-2101lADSP-2102
surpasses other single-chip DSP microcomputers in both perfor-
mance and ease of design and development.
Fabricated in a high speed 1.0 micron double-layer metal CMOS
process, the ADSP-2101lADSP-2102 operates at 12.5MHz. Ev-
ery instruction executes in a single cycle, resulting in a 12.5
MIPS processor. Fabrication in CMOS results in low power re-
12.5MIPS DSP Microcomputer
ADSP-21 01/ADSP-21 02 I
quirements. The ADSP-2101lADSP-2102 dissipates less than
1 W under all conditions and no more than 80m Wunder
standby conditions.
The ADSP.2101 ill a RAM based microcomputer with IK words
of (Hi-bit) dara memory and 2K words of (24-bit) program
~ . The ADSP-2102 is a mask programmable version al-
lowing' any RAM loCation to be changed to ROM. In this data
sheet, all referencts to the ADSP-2101 are applicable to the
ADSP-ZI02 except where noted.
The ADSP-2101's flexible architecture and comprehensive in-
struction set support a high degree of operational parallelism. In
one eycle the' ADSP-2101 can:
gellerate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation
receive and transmit data via the two serial ports.
DEVELOPMENT SYSTEM
The ADSP-2101 is supported by a complete set of tools for
software and hardware system development. The cross-software
system is a set of modules. The System Builder provides a high
level method for defming the architecture of systems under de-
velopment. The Assembler produces object code and the Linker
combines object modules and library calls into an executable
file. The Simulator provides an interactive instruction level sim-
ulation with a reconfigurable user interface. A PROM splitter
generates PROM burner compatible files. The C Compiler gen-
erates ADSP-2101 assembly source code. An Emulator will be
available for hardware debugging of ADSP-2101 systems.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice,
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-53
ADDITIONAL INFORMATION
For additional information on the architecture and instruction
set of the processor, refer to the ADSP-21OIIADSP-2102 User's
Manual. For more information about the development aystem
and ADSP-2101 programmer's reference information, refer to
the ADSP-2IOX Cross-Software Manual and the (forthcoming)
ADSP-21OIIADSP-2102 Emulator Manual.
ARCHITECTURE OVERVIEW
Figure I is an overall block diagram of the ADSP-2101. For
compatibility with the ADSP-2100 processor, the additional fea-
tures of the ADSP-2101 appear in the form of new mode con-
trols, new processor registers and a group of memory mapped
control registers residing between data memory addresses
H#3FEO and H#3FFF.
The processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; divi-
sion primitives are also supported. The MAC performs single
cycle multiply, multiply/add and multiply/subtract operations.
The shifter performs logical and arithmetic shifts, normalization,
denormalization, and derive exponent operations. The shifter
can be used to efficiently implement numeric format control
including multiword floating point representations.
The internal result (R) bus directly tfMt CQmputlltiWUli
units so that the output of any unit may be '!he ilwut of any unit
on the next cycle.
A powerful program sequencer and two dedicawd data address
generators ensure efficient use of these computational, units.
The sequencer supports conditional jumps, subroutine calls and
returns in a single cycle. With internal loop counters and loop
stacks, the ADSP-2101 executes looped code with zero over-
head; no explicit jump instructions are required to maintain
the loop.
It
r=Ct'NSTRUCTION 0
REGISTER "'"
V DATA
I OATA I
ADDRESS ADDRESS
GENERATOR
GENE,AZATOR
SEQUENCER
..
The data address generators (DAGs) handle address pointer up-
dates. Each DAG keeps track of four address pointers. When-
ever the pointer is used to access data (indirect addressing), it is
post-modified by the value of a specified modify register. A
length value may be associated with each pointer to implement
automatic modulo addressing for circular buffers. With two in-
dependent DAGs, the processor can generate two addresses si-
multaneously for dual operand fetches. The circular buffering
feature is also used by the serial ports for automatic data trans-
fers; these are described in the section on serial ports.
Efficient data transfer is achieved with the use of five internal
buses.
Program Memory Address (PMA) bus
Program Memory Data (PMD) bus
Data Memory Address (DMA) bus
Data Memory Data (DMD) bus
Result (R) bus
The two address buses (pMA and DMA) share a single external
address bus, and the two data buses (PMD and DMD) share a
single external data bus. The BMS, DMS and PMS signals indi-
cate which memory which the external buses are being
used. .
As in the program memory can store both instruc-
tjallS and data, permittillg the ADSP-2101 to fetch two operands
In a single cycle, _ frain program memory and one from data
memory. Because on-clrip program memory is so fast, the
fetch 'an operand from program memory and
thl: nest inStruction in the same cycle. (This eliminates the need
for the cache memory found on the ADSP-2100, as well as any
overhea4 cycles $at were associated with initial loading of the
caGtl.e.) ,
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of buses with bus request!
grant signals (BR and BG). One execution mode allows the
PROGRAM DATA BOOT
SRAM SAAN ADDRESS
"
2K X 24 1K X 16 GENERATOR
V
L. '" ......... EXTERNAL
I PROGRAM, 1
II

jl
it
L.
PMA BUS
AODFIESS
BUS
= ==
" 7 " 7-
-
MUX
"
DMA BUS
- r- -= -
V
"
PMD BUS
" '7 =:----
=


BUS
BUS
MUX


" " "
7
1==
.....

L.
g"7
';::"

,
L.
DMOBU:

7
INPUT REGS INPUT REGS INPUT REGS
,.MoMPANDING
?D
r
?D
CIRCUITRY
ALU MAC SHIFTER
CONTROL TIMER
LOGIC T".om" ... T" ........
.11 .11
Receive Rtg Receive ....
OUTPUT REGS OUTPUT REGS OUTPUT REGS . r=-
.& "
R.US
"
'--
SERIAL SERIAL
'---
"
PORT PORT 1

Figure 1. ADSP-2101IADSP-2102 Block Diagram
This information applies to a product under development. Its characteristics and specifications are subject to change without notice,
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-54 DSP PROCESSORS
PIN DESCRIPTION
The ADSP-2JOI is available in a 68-pin PGA and a 68-lead PLCC.
Pin Group
Name
Address
Data
RESET
IRQ2
BR
BG
PMS
DMS
BMS
RD
# of
Pins
14
24
Function
Address output for program, data and
boot memory spaces
Data I/O pins for program and data
memories. Input only for boot memory
space, with two MSBs used as boot
space addresses.
Processor reset input
External interrupt request #2 input
External bus request input
External bus grant output
External program memory select
External data memory select
Boot memory select
External memC!ry read enable output
ADSP-21 01/ADSP-21 02
WR External memory write enable output
MMAP Memory map select
CLKIN,
XTAL 2 External clock or quartz crystal input
CLKOUT Processor clock output
SPORTO Serial Port 0 I/O pins
SPORT! Serial Port 1 I/O pins
or
IRQl External interrupt request # 1 input
IRQO External interrupt request #0 input
SCLK Programmable clock output
FO Flag output pin
FI Flag input pin
GND 4 Ground pins
Voo
3 Power Supply
Table I. ADSP-2101 Pin List
ADSP-2JOI to continue running while the buses are granted to
another master as long as an external memory operation is not
required. The other execution mode requires the processor to
halt while buses are granted.
The ADSP-2101 can respond to six interrupts. There can be up
to three external interrupts, configured as edge- or level-
sensitive. Internal interrupts can be generated by the Timer and
the Serial Ports ("SPORTS"). There is also a master RESET
signal.
The two serial ports provide a complete serial interface with
companding in hardware and a wide variety of framed and
frameless data transmit and receive modes of operation. Each
port can generate an internal programmable serial clock or ac-
cept an external serial clock.
Boot circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After RESET
three wait states are automatically generated. This allows, for
example, an 80ns ADSP-2JOI to use an external 250ns EPROM
as boot memory. Multiple programs can be selected and loaded
from the EPROM with no additional hardware.
The ADSP-2JOI instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) in-
structions. Every instruction can be executed in a single proces-
sor cycle. The ADSP-2101 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
ArithmeticlLogic Unit
Figure 2 shows the Arithmetic/Logic Unit (ALU).
The ALU provides a standard set of arithmetic and logic func-
tions: add, subtract, negate, increment, decrement, absolute
value, AND, OR, Exclusive OR and NOT. Two divide primi-
tives are also provided. The AL U takes two 16-bit inputs, X
and Y, and generates one 16-bit output, R. It accepts the carry
(AC) bit in the arithmetic status register (AST A T) as the carry-
in (Cl) bit. The carry-in feature enables multiword computa-
tions. Six arithmetic status bits are generated: AZ (zero), AN
(negative), AV (overflow), AC (carry), AS (sign) and AQ (quo-
tient). These status bits are latched in ASTAT.
Figure 2. ALU Block Diagram
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-55
The X input port can be fed by either the AX register set or
any result register via the R bus CAR, MRO, MRI, MR2, SRO,
or SRI). The AX register set contams two registers, AXO and
AXI. The AX registers can be loaded from the DMD bus. The
Y input port can be fed by either the A Y register set or the
ALU feedback (AF) register. The A Y register set contains two
registers, A YO and A YI. The A Y registers can be loaded from
either the DMD bus or the PMD bus.
The register outputs are dual-ported so that one register can
provide input to the ALU while either one simultaneously drives
the DMD bus. The ALU output can be loaded into either the
AR register or the AF register.
The AR register has a saturation capability; it can be automati-
cally set to plus or minus the maximum value if an overflow or
underflow occurs. The saturation mode is enabled by a bit in
the mode status register (MSTAT). The AR register can drive
both the R bus and the DMD bus and can be loaded from the
DMD bus.
The ALU contains a duplicate bank of registers shown in Figure
2 as a "shadow" behind the primary registers. The secondary
set contains all the registers described above (AXO, AXI, AYO,
AYI, AF, AR). Only one set is accessible at a time. The two
sets of registers allow fast context switching, such as for inter-
rupt servicing. The active set is determined by a bit in MSTAT.
Multiplier/Accumulator
The multiplier/accumulator (MAC) implements high speed mul-
tiply, multiply/add and multiply/subttact oJ)tratron$, Figure 3
shows a block diagram of the MAC section.
Figure 3. MAC Block Diagram
The multiplier takes two 16-bit inputs, X and Y, and generates
one 32-bit output, P. The 32-bit output is routed to a 40-bit
accumulator which can add or subtract the P output from the
value in MR. MR is a 40-bit register which is divided into three
sections: MRO (Bits O-IS), MRI (Bits 16-31), and MR2 (Bits
32-39). The result of the accumulator is either loaded into the
MR register or into the 16-bit MAC feedback (MF) register.
The multiplier accepts the X and Y inputs in either signed or
unsigned formats.
In the default operation (ADSP-2100 mode) the result is shifted
one bit to the left to remove the redundant sign bit for fractional
justification; an optional mode on the ADSP-2101 inhibits this
shift for integer operations. The accumulator generates one sta-
tus bit, MV, which is set when the accumulator result overflows
the 32-bit boundary. A saturate instruction is available to change
the contents of the MR register to the maximum or minimum
32-bit value if MV is set. The accumulator also has the capabil-
ity for rounding the 40-bit result at the boundary between Bit
IS and Bit 16.
The MAC and ALU registers are similar. The X input port can
be fed by either the MX register set (MXO, MXI) or any result
register via the R bus (AR, MRO, MRI, MR2, SRO or SRI).
The MX register set is readable and loadable from the DMD
bus and has dual ported outputs.
The Y input port can be fed by either the MY register set
(MYO, MYI) or the MF register. The MY register set is read-
able from the DMD bus and readable and loadable from both
the DMD and the PMD bU$. Its outputs are also dual ported.
The accumulator output can be loaded into either the MR regis-
tet ot the MP' register. The MR register is connected to both
the R bus and the DMD bus. Like the ALU section, the MAC
section contains twO complete banks of registers (MXO, MXI,
MYO. MYl, MF, MRO, MRI, MR2) to allow fast context
switching.
Shifter
The shifter g l ~ the ADSP-2101 its unique capability to handle
data formattipg and numeric scaling. Figure 4 shows a block
diagram of the shifter.
Figure 4. Shifter Block Diagram
The shifter can be divided into the following components: the
shifter array, the OR/PASS logic, the exponent detector and the
exponent compare logic. These components give the shifter its
six basic functions: arithmetic shift, logical shift, normalization,
denormalization, derive exponent and derive block exponent.
The shifter array is a 16x32 barrel shifter. It accepts a 16-bit
input and can place it anywhere in the 32-bit output field, from
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-56 DSP PROCESSORS
off scale right to off scale left. The shifter can perform arith-
metic shifts (shifter output is sign extended to the left) or logical
shifts (shifter output is zero filled to the left). The placement of
the 16-bit input is determined by the control code (C) and the
HIILO reference signal. The control code can come from one of
three sources: directly from the instruction (immediate arith-
metic or logical shift), from the SE register (denormalization), or
the negated value of the SE register (normalization). The shifter
input can come from either the 16-bit SI register or any result
register via the R bus. The 32-bit output of the shifter array is
fed to the ORIPASS circuit. The result can be either logically
ORed with the current contents of the SR register or passed di-
rectly to the SR register. The SR register is divided into two
16-bit sections: SRO (Bits 0-15) and SRI (Bits 16-31).
The shifter input is also routed to the exponent detector cir-
cuitry. The exponent detector generates a value to indicate how
many places the input must be up shifted to eliminate all but
one of the sign bits. This value is effectively the base 2 exponent
of the number. The result of the exponent detector can be
latched into the SE register (for a normalize operation) or can be
sent to the exponent compare logic. The exponent compare logic
compares the derived exponent with the value in the SB register
and updates the SB register only when the derived exponent
value is larger than the current value in the SB register. There-
fore, the exponent compare logic tan be used t\) find the largest
exponent value in an array of shifter inputs.
The shifter includes the following registers! the $1 register, the
SE register, the SB register and the SR register. All these regis-
ters are readable and loadable from the DMD bus. The SR. reg
ister can also drive the R bus. Like the ALU and MAC, the
shifter contains two complete banks of registers for context
switching. Each set contains all the registers described above,
but only one set is accessible at a time. The active set is deter-
mined by a bit in MSTAT.
Data Address Generators
Figure 5 shows a block diagram of a data address generator.
DMD lUI
Figure 5. Data Address Generator Block Diagram
The data address generators (DAGs) provide indirect addressing
for data stored in the program and data memory spaces. The
processor contains two independent DAGs so that two data op-
erands (one in program memory and one in data memory) can
be addressed simultaneously. The two data address generators
are identical except that DAG I has a bit-reversal option on the
output and can only generate data memory addresses, while
DAG2 can generate both program and data memory addresses
ADSP-21 01 IADSP-21 02
but has no bit-reversal capability. Both DAGs can also be u,cd
for serial port autobuffering.
There are three register files in each DAG: the modify (M) reg-
ister file, the index (I) register file and the length (L) register
file. Each of these register files contains four l4-bit regi,ters
which are readable and loadable from the DMD bus. The I reg-
isters hold the actual addresses used to access external memory.
When using the indirect addressing mode, the selected I register
content is driven onto either the PMA or DMA bus. This value
is post-modified by adding the (signed) contents of the selected
M register. The modified address is passed through the modulus
logic.
Associated with each I register is an L register which contains
the length of the buffer addressed by the I register. The L regis-
ter and the modulus logic together enable circular buffer ad-
dressing with automatic wraparound at the buffer boundary.
Automatic wraparound is also used by the serial ports to gener-
ate the serial port interrupt when operating in auto buffering
mode. The modulus logic is disabled by setting the L register to
zero.
PMD.I>MD Bus Exchange
The PMD-DMD bus exchange circuit couples the PMD and
DMD buses. The PMD bus is 24 bits wide and the DMD bus
is 16 bits wide. The upper 16 bits of PMD are connected to the
DMD bus. An 8-bit register (PX) allows transfer of the full
width of the PMD bus. When data (as distinct from an instr\w-
tion) is read from the PMD bus, the lower 8 bits of the PML>
bus are 1000ded into PX. When writing to the PMD bus, the
C<lntents of PX are appended to the upper 16 bits, forming a
24-bit value. The PX register is also readable and loadable from
the DMD bus.
Program Sequencer
The program sequencer incorporates powerful and flexible
mechanisms for program flow control such as zero overhead
looping, single cycle branching (both conditional and uncondi-
tional) and automatic interrupt processing. Figure 6 shows a
block diagram of the program sequencer.
Figure 6. ADSP-2101 Program Sequencer
This information applies to a product under development. Its characteristics and sUbi.e.ct to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherWise agreed to In writing.
DSP PROCESSORS 2-57
The sequencing logic controls the flow of the program execu-
tion. It outputs a program memory address onto the PMA bus
from one of four sources: the PC incrementer, PC stack,
instruction register or interrupt controller. The next address
source selector controls which of these four sources are selected
based on the current instruction word and the processor status.
A fifth possible source for the next program memory address is
provided by DAG2 when a register indirect jump is executed.
The program counter (PC) is a 14-bit register which contains the
address of the currently executing instruction. The PC output
goes to the incrementer. The incremented output is selected as
the next program memory address if program flow is sequential.
The PC value is pushed onto the 16 x 14 PC stack when a CALL
instruction is executed or when an interrupt is processed. The
PC stack is popped when the return from a subroutine or inter-
rupt is executed. The PC stack is also used in zero overhead
looping.
The program sequencer section contains six status registers.
These are the Arithmetic Status register (ASTAT), the Stack
Status register (SSTAT), the Mode Status register (MSTAT),
the Interrupt Control register (ICNTL), the Interrupt Mask reg-
ister (IMASK) and the Interrupt Force and Clear register (IFC).
Interrupts
The interrupt controller allows the processor to respond to the
six possible interrupts with a minimum of overhead. Individqal
interrupt requests are logically ANDed with the bitS ip IMASK; ,
the highest priority unmasked interrupt i., then '
The interrupt control register, ICNTL;'alloW!l each interrupt to "
be set as either edge or level sensitive. DependinJ OIi, a bidn
ICNTL, interrupt routines can either be nested with higher pri-
ority interrupts taking precedence or processed sequentially with '
only one interrupt service active at a time.
The 12-bit interrupt force and clear register, IFC, contains a
force bit and a clear bit for each of the six possible interrupts.
When responding to an interrupt, the status registers ASTAT,
MST AT, IMASK are pushed onto the status stack and the PC
counter is loaded with the appropriate vector address. The sta-
tus stack is seven levels deep to allow interrupt nesting. The
stack is automatically popped when a return from the interrupt
is executed.
The vector addresses for each interrupt are fixed. In the ADSP-
2101 each vector location identifies a block of four instructions.
Short service routines can be executed without an additional
JUMP, minimizing overhead.
IMASK
IMASK is six bits wide and allows the interrupt inputs to be
individually enabled or disabled. The bits in IMASK are:
o Timer interrupt enable
I IRQO or SPORT I receive interrupt enable
2 IRQI or SPORTI transmit interrupt enable
3 SPORTO receive interrupt enable
4 SPORTO transmit interrupt enable
5 IRQ2 interrupt enable.
The bits are all positive sense (0 = disabled, I = enabled).
IMASK is set to zero upon a processor reset so that all inter-
rupts are disabled initially.
ICNTL
ICNTL is a 5-bit register configuring the interrupt modes of the
processor. The bits in ICNTL are:
o IRQO or SPORT I receive sensitivity
I IRQI or SPORT! transmit sensitivity
2 IRQ2 sensitivity
3 Zero
4 Interrupt Nesting Mode.
The sensitivity bits determine whether a given interrupt input is
edge- or level-sensitive (0= level-sensitive, I = edge-sensitive).
The interrupt nesting mode determines whether nesting of inter-
rupt service routines is allowed. When set to zero, all IMASK
bits are automatically set to zero when an interrupt service rou-
tine is entered. Previous IMASK values are pushed on the
stack. When set to one, IMASK is set so that equal and lower
priority interrupts are masked, permitting higher priority inter-
rupts to interrupt the current interrupt service routine.
Edge-triggered interrupts are automatically cleared when the
interrupt service routine is called. They can also be cleared by
writing a one to the apprqprjate IFC bit.
The timer and serial'port act as edge-sensitive inter-
rupts which can be masked, 'cleared or forced with software. If
force.a level-sensitive interrupt in software, it is automati-
cally cleared. For proper operation, the SPORT! sensitivity bits
must be set tocedge-sensitive.
Il'C
The IPc register is twelve bits wide and contains a bit for clear-
ing and a bit for forcing each of the six possible interrupts in
the ADSP-21OL"The bits in IFC are defined as follows.
B;it<t
Bit I
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Timer interrupt clear
SPORTI receive or IRQO interrupt clear
SPORTI transmit or IRQI interrupt clear
SPORTO receive interrupt clear
SPORTO transmit interrupt clear
IRQ2 interrupt clear
Timer interrupt force
SPORT! receive or IRQO interrupt force
SPORT I transmit or IRQI interrupt force
SPORTO receive interrupt force
SPORTO transmit interrupt force
IRQ2 interrupt force.
Pending edge-sensitive interrupts can be cleared by writing a
one to the appropriate clear Bit (0-5) in IFC. Edge-triggered
interrupts are normally cleared automatically when the corre-
sponding interrupt service routine is called.
Interrupts can be forced under program control by writing a one
to the force Bit (6-11) corresponding to the desired interrupt.
This causes the interrupt to be serviced once, unless masked.
The timer and SPORT interrupts behave like edge-sensitive in-
terrupts and can be masked, cleared and forced.
Loop Mechanisms
The DO UNTIL instruction executes a zero overhead loop us-
ing the loop stack and the loop comparator. For a DO UNTIL
instruction, a 14-bit termination address and a 4-bit termination
condition are pushed onto the 18-bit loop stack. The address of
the next instruction (which identifies the top of the loop) is
pushed onto the PC stack. The loop comparator continuously
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-58 OSP PROCESSORS
compares the current PC value against the termination address
on the top of the loop stack. When the termination address is
detected, the processor checks if the termination condition is
met. If the termination condition is not met, then the top of the
PC stack is used as the next PC address, returning program flow
to the beginning of the loop. If the termination condition is met,
then the PC stack is popped, the current PC is incremented by
one and program flow falls out of the loop. The loop stack is
four levels deep, permitting four levels of zero overhead loop
nesting.
The down counter and the count stack also support this power-
fullooping mechanism. The down counter is a l4-bit register
with auto decrement capability. It is loaded from the DMD bus
with the loop count. The count is decremented every time the
counter value is checked; when the count expires, the counter
expired (CE) flag is set. The count stack allows the nesting of
loops by storing temporarily dormant loop counts. When a new
value is loaded into the counter from the DMD bus, the current
counter value is automatically pushed onto the count stack, as
program flow enters a loop. The count stack is automatically
popped whenever the CE flag is tested and is true, thereby
resuming execution of the outside the loop. "
Status Registers ' ", J',
The ADSP-2101 maintains six be'
accessed over the DMD bus (one md one i,s
only, however). These registers arel, ' '
ASTAT
SSTAT
MSTAT
Arithmetic Status Register
Stack Status Register
Mode Status Register
(Read-Only) ", ,
ICNTL
IMASK
IFC
Interrupt Control Register
Interrupt Mask Register
Interrupt Force and Clear. (Write-On(y)
The interrupt registers are described in a previous section; the
other three are discussed below.
ASTAT
,:,
ASTAT is 8 bits wide and holds the status information gener-
ated by the computational sections of the processor. The bits in
ASTAT are defmed as follows:
o AZ (ALU Result Zero)
I AN (ALU Result Negative)
2 AV (ALU Overflow)
3 AC (ALU Carry)
4 AS (ALU X Input Sign)
5 AQ (ALU Quotient Flag)
6 MV (MAC Overflow)
7 SS (Shifter Input Sign).
The bits are positive sense (I;" true, 0 = false). They are
automatically updated when a new status is generated by the
arithmetic operations affecting them, as defmed by the following
table:
Status Bit
AZ,AN,AV,AC
AS
AQ
MV
SS
Updated On
Any ALU operation except division
ALU absolute value operation
ALU divide operations
Any MAC operation except saturate MR
Shifter exponent detect operation.
ADSP-21 01 IADSP-21 02
SSTAT
SST A T is 8 bits wide and holds the status of the four internal
stacks. The bits in SSTAT are:
o PC Stack Empty
I PC Stack Overflow
2 Count Stack Empty
3 Count Stack Overflow
4 Status Stack Empty
5 Status Stack Overflow
6 Loop Stack Empty
7 Loop Stack Overflow.
All of the bits are positive sense (1 = true, 0 = false). The empty
status bits indicate that the stack is empty. The overflow status
bits indicate that the stack has overflowed. Since the stack over-
flow status bits "stick" once they are set, subsequent pop opera-
tions have no effect on them. This means that the stack can be
both overflowed and empty under certain circumstances. A pro-
cessor reset or a softWl\I'O- reboot must be executed to clear the
stack ovedlow 'jItBtUs. '
, " i' '
MSTAT" ,,,"
" MST'AT is a ?-bit register that defines various operating modes
''of the procesS9l'. TlIe mode control instruction enables or dis-
ables The bits in MSTAT are:
.r- .:- ,
, , 0: ':,Pm -Register Bank Select
, I"" Bit-Reverse Mode (DAGl Only)
2 AtU,Overflow Latch Mode
3 AR.Saturation Mode
4 MAc Result P Placement Mode
5 Timer Enable
6 Go Mode.
The data register bank select bit determines which set of data
registers is currently active (0 = primary, I = secondary). The
data registers include all of the result and input registers to the
ALU, MAC and shifter (AXO, AXI, AYO, AYI, AF, AR,
MXO, MXI, MYO, MYI, MF, MRO, MRI, MR2, SB, SE, SI,
SRO and SRI). At RESET, the data register bank select bit is
cleared.
The bit-reverse mode, when enabled, bit-wise reverses all ad-
dresses generated by DAG 1. This is most useful for reordering
the input or output data in a radix-2 FFT algorithm.
The ALU overflow latch mode causes the AV (ALU overflow)
status bit to "stick" once it is set. In this mode, when an ALU
overflow occurs, AV will be set and remain set, even if subse-
quent ALU operations do not generate overflows. AV can then
only be cleared by writing a zero into it from the DMD bus.
The AR saturation mode, when set, causes ALU results to be
saturated to the maximum positive (H#7FFF) or negative
(H#8000) values when an ALU overflow or underflow occurs.
The MAC Result P Placement bit, when set to 0, results in the
ADSP-2100 result placement of the multiplier product in the
MR register (one bit shift). When this bit is I, no shift occurs.
The Timer Enable bit, when set to I, enables the timer decre-
ment mechanism.
The Go Mode bit, when set to I, allows the processor to con-
tinue operations internally (when possible) while the external
address and data buses are tristated during a bus grant.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-59
-------
CONDITION CODES
The condition codes are used to determine whether a conditional
instruction, such as a jump, trap, call, return, MAC saturation
or arithmetic operation, is performed. The 16 basic composite
status conditions and their derivations are shown in Table II.
Since arithmetic status is latched into AST AT at the end of a
processor cycle, the condition logic represents conditions gener-
ated on the previous cycle.
Code Status Condition True If
EQ
NE
LT
GE
ALU Equal Zero
ALU Not Equal Zero
ALU Less Than Zero
ALU Greater Than or Equal
Zero
AZ = 1
AZ=O
AN .XOR. AV=1
AN .XOR. AV =0
Each serial port has a 5-pin interface consisting of the following
signals.
Signal Name Function
SCLK
RFS
TFS
DR
DT
Serial Clock 110
Receive Frame Synch 1/0
Transmit Frame Synch 1/0
Serial Data Receive
Serial Data Transmit,
Here is a brief list of the capabilities of the ADSP-2101
SPORTs. Figure 7 shows a simplified block diagram of a single
SPORT.
Bidirectional: each SPORT has a separate transmit and re-
LE ALU Less Than or Equal
Zero
(AN .XOR.
.OR. AZ = 1
(AN .XOR.
.OR. AZ =0
AC=1
AV)
ceive section.
Double buffered: each SPORT section (both receive and
transmit) has a data register accessible to the user and an
internal transfer register. The double buffering provides
additional time to service the SPORT.
GT ALU Greater Than Zero AV)
AC
NOTAC
AV
NOTAV
MV
NOTMV
NEG
POS
NOTCE
FOREVER
ALU Carry
Not ALU Carry
ALU Overflow
Not ALU Overflow
MAC Overflow
Not MAC Overflow
ALU X Input Sign Negative
ALU X Input Sign Positive
Not Counter Expired ,',
Always
Table II. Condition Codes
AC=O
AV=1
AV=O
MV=I
MV=O
AS=1

., CE'':'O
Alw6)'ilTrue
In addition to the basic 16 conditions, the JUMp"and CALL
instructions also support the use of the FI pin as a conditional :-. ,
flag. This pin is one of the five used for serial port 1. It is avail- .
able if serial port 1 is not configured.
FLAG_IN
NOT FLAG_IN
FI Pin Last Sampled 1
FI Pin Last Sampled 0
Table III. Additional Condition Codes For JUMP and CALL
Timer
A programmable interval timer can generate periodic interrupts.
When the decrementing mechanism is enabled, a 16-bit count
register (TCOUNT) is decremented every n cycles, where n-l is
a scaling value stored in an S-bit register (TSCALE). When the
value of the count register reaches zero, an interrupt is gener-
ated and the count register is reloaded fl'9m a 16-bit period reg-
ister (TPERlOD). Timer interrupts can be masked, cleared and
forced in software if desired.
The ADSP-2101 S-bit prescaler allows periodic interrupts over a
wide range of possible times. In a processor with an sOns cycle
time, for example, the timer interrupt could occur as infre-
quendy as every 1. 34 seconds if a maximum scaling value is
used. With a minimum scaling value a maxim\llll period of
5.24ms can be timed.
SERIAL PORTS
The ADSP-2101 incorporates two complete serial ports
(SPORTO and SPORTl) for serial communications and multi-
processor coordination.
Flexible clocking: each SPORT can use an external serial
clock (up to the .. sor cycle rate) or generate its own
(from 94Ha up to olle hidf the processor cycle rate).
F1taibICl :eadt SroRT section (receive and transmit)
CIiIn fUll in an unframed mode; with internally generated or
ftl;emally generllted synch signals; with active high or
inverted frame either of two pulse widths!
". for the receive and transmit sections is
. independent but shares the same serial clock.
'. Flexibj,e VI'\)l'Q length: each SPORT supports serial data word
, Jed!!. to sixteen bits.
Companding in hardware: each SPORT provides optional
A-law and ....-law companding according to CCITT recommen-
dation G. 711. Different companding can be used for each
SPORT, for example, A-law for SPORTO and .... -law for
SPORT 1.
Flexible interrupt scheme: each SPORT section (receive and
transmit) can generate a unique interrupt upon completing a
data word transfer or after transferring an entire buffer (see
next item).
Autobuffering with single cycle overhead: using the ADSP-
2101 DAGs, each SPORT can receive andlor transmit an en-
tire circular buffer of data with an overhead of only one cycle
per data word. Transfers to and from the SPORT and the
circular buffer are automatic in this mode and do not require
additional programming. An interrupt is generated only when
pointer wraparound occurs in the circular buffer.
Multichannel capability: SPORTO provides a multichannel
interface for selective receipt and transmission of arbitrary
data channels from a 24- or 32- word, time division multi-
plexed, serial bitstream. This is especially useful for Tl or
CEPT interfaces or as a network communication acherne for
multiple processors.
Alternate configuration: SPORTI can be configured as two
extemal interrupt inputs (IRQO and IRQl) and the Flag In
and Flag Out signals. The internally generated serial clock
may still be used in this configuration.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-60 DSP PROCESSORS
Figure 7. Serial Port Block Diagram
SPORT OPERATION
Each SPORT has a receive and a transmit register; SPORTO's
registers are RXO and TXO; SPORTl's are RXI and TXI.
Companding (a contraction of COMpressing and exPANDing) is
the process of logarithmically encoding data to minimize the
number of bits that must be sent. Both SPORTs share the _.r-
panding hardware: one expansion and one comptes$lon opera-"'1'/
tion can occur in each processor cycle, ,l!hhe l:if {lOdten-
tion, SPORTO has priority. The
I Clock or r "
"
ADSP-21 01/ADSP-21 02
the widely used algorithms for companding: A-law and ....-law.
The type of companding can be independently selected for each
SPORT.
The TXn and RXn registers are identified by name in the
ADSP-2101 assembly language, not memory-mapped. TXn and
RXn can be read and written (like other non-data registers) with
the following instructions: read/write to data memory (direct
address), load non-data immediate, and internal (register-to-
register) moves. They cannot be accessed by instructions that
require indirect addressing, i.e., addresses generated by the
DAGs.
There are two ways to generate the SPORT interrupts after the
transmission or receipt of (1) each data word or (2) each com-
plete buffer of data words.
Normal (Word by Word) Operation
Writing to the TXn register readies the SPORT for transmis-
sion; the TFS silw;lllW.tes it. The value in TXn is shifted
into iQJernat, J;I13nsnltt, register, and after framing synchroni-
; required), the bits are sent, MSB first.
bit.s been transferred, the SPORT generates
ithe"tranJli9it . TXn is now available for the next
Qf; data, the transmission of the first is not
r,
',- '/';:'2'ir 'j,'

T:
f

-,
'" ,1,
, .
elKIN XTAL ClKOUT /' GND

"FS
SERIAL TFS
Senal Device
--<0 RESET
PORT 0
DT
--<0 IRQ2
(Optional)
ADSP-2101
DR
--<0 BR
--
8G
SCLK
RFS or IAOO
MMAP
SERIAL
TFS or i"IRf'f
Senal Device
--<0
PORT 1
OT or FO
PMS AOWR ADDRESS DATA fm DR or FI
, . 2.
,
2*
,. ,
'ye
A D CS A D CS A D n
(Option, I)
PROGRAM
MEMORV
Oe Oe OE
WE WE
BOOT
EPROM
(Opt/on.')
2764
DATA
27128
MEMORV
27256
8
27512
PERIPHERALS
250"1
NOTE: The two MSSI ot thl Boot EPROM Add ..... are 11.0 the two MSI. (
of the Data lUI. Thll II only requl ... d for the 27258 and 27512.
The eight data bit. of thl Boot Memory Spice cor .... pond to D 15-8
The Ilxt.en date bit. 01 the Da'i Mlmory SPICI cor .... pond to D
23
_,
Figure 8. ADSP-2101 Basic System Configuration
(OpflOnlJl)
D
23
, 22 )
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-61
In the receiving section, bits accumulate as they are received in
an internal receive register. When a complete word has been
received, it is shifted into the RXn register and the receive in-
terrupt for that SPORT is generated. RXn may then be read.
Autobuffered Operation
In autobuffered operation, the interrupt is not generated until a
complete buffer of data words has been received or transmitted.
To do this, the user sets up a circular buffer in data memory
and identifies the I and M registers in the DAG used to point to
this buffer. The SPORT automatically transfers each data word
to or from the buffer, stealing a single cycle for each word. (For
example, to buffer 16 words of data would require just 16 addi-
tional cycles.) When the modulus logic detects buffer wrap-
around, the SPORT interrupt is generated. Transmitting in au-
tobuffered mode must be started by explicitly writing the first
word of the transmit buffer to TXn. The transmission of this
word starts the automatic cycling through the transmit buffer.
These serial port features, in conjunction with other features of
the ADSP-2101, make it possible to interface to most codecs,
NDs, DACs and to additional ADSP-210Is with no additional
hardware and limited software overhead.
SYSTEM INTERFACE
Figure 8 shows a basic system configuration with the ADSP-
2101, two serial codecs, a boot EPROM and optional external
program and data memories. Up to 16K words of data memOry :
and 16K words of program memory can be l!UPJlorted. Program-
mable wait state generation allows the ptO<;e$SOl. to interfat!e
easily to slow memories. . "
The ADSP-2101 also provides one external interrupt two
serial ports or three external interrupts and one Serial port.
Clock Signals
The ADSP-2101 takes a TTL-compatible clock signal, CLKIN;
running at the instruction rate. Because the ADSP-2101 contains
an internal oscillator, an external crystal may be used in place of
an external clock oscillator. A clock output (CLKOUT) signal is
generated by the processor synchronized to the processor's inter-
nal cycles. The rising edge of CLKOUT is aligned with the ris-
ing edge of CLKIN. eLKIN may not be halted, changed dur-
ing operation or operated below the specified frequency.
Bus Interface
The ADSP-2101 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. After
completing the current instruction, the processor halts program
execution, tristates the data and address bus, the PMS, DMS,
BMS, RD, WR output drivers and asserts the bus grant (BG)
signal. When the BR signal is released, the processor releases
the BG signal, re-enables the output drivers and continues pro-
gram execution from the point where it stopped.
If the Go mode is set, the processor continues execution (from
internal memory) while the bus is granted. In this mode, while
BG is asserted, the processor only halts if an external memory
access is required.
Wait States
The ADSP-2101 can be easily interfaced to slow memories
using its programmable wait state generation capability. Three
registers control wait state generation for the boot, program and
data memory interface. Wait states for boot memory default to 3
cycles at RESET, while program and data memory each default
to 7 cycles. You can specify 0 to 7 wait states for each memory
interface.
PROGRAM MEMORY INTERFACE
The program memory address bus (PMA) and the program
memory data bus (PMD) are multiplexed with DMA and
DMD, sharing the external data and address bus. The 14-bit
address bus directly addresses up to 16K words of which 2K is
on chip. The data bus is bidirectional and 24 bits wide to exter-
nal program memory.
There is no placement restriction for instruction code and data
in the program memory space, except for the locations used for
interrupt and restart vectors.
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to the program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
Although the processor internal data bus is only 16 bits, the
ADSP-2101 can write to the full 24-bit program memory using
the PX regist((t.
PfOgtam. MeOlOry Maps
, PrOgram memory can be mapped in two ways, depending on the
stan! of the MMAP pin. Figure 9 shows the two configurations.
When MMAP=O, internal RAM occupies 2K words beginning
0000; external program memory uses the remaining
.. 14K Wbrds 'beginning at address H#0800. In this configuration,
. the boot 19adil:lg sequence (described below) is automatically
initiated when RESET is released.
whim MMAP= I, 14K words of external program memory be-
gin at address 0000 and internal RAM is located in the upper
2K words, beginning at address H#3800. In this configuration,
program memory is not loaded although it can be written to and
read from under program control.
ADSP-2102 ROM Memory
In the ADSP-2102 ROM-based system, both program memory
maps are available, selected by the MMAP pin as above. Auto-
matic boot loading is optional.
0000
RAM or ROM
RAM
LOADED from
EXTERNAL
I-_S_TO_R_A_G_E--j
EXTERNAL
1..-___ --' 3FFF
,------,0000
EXTERNAL
1------1 37FF
INTERNAL
RAM or ROM
NOT
LOADED
3800
'--____ ...I 3FFF
MMAP=O MMAP=l
Figure 9. ADSP-2707IADSP-2702 Program Memory Maps
Boot Memory Interface
The boot memory space consists of an external 64 K by 8 space,
This information applies to a product under development Its characteristics and specifications are subject to change without notice,
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing,
2-62 DSP PROCESSORS
ADSP-21 01/ADSP-21 02
divided into eight separate 8K by 8 pages. Three bits in the sys
tem control register select which page is loaded by the boot
memory interface. Another bit in the system control register
allows the user to force a boot loading sequence under software
control. The boot loading after RESET is initiated if
MMAP=O.
At RESET, the ADSp-2101 generates three wait states while
booting. This allows a 12.5MHz processor to use a slow (250ns),
lowcost EPROM for program storage. Program memory is
loaded a byte at a time and converted to 24-bit words.
The boot memory interface defaults to three wait states after
RESET and can be set to any value in the range 0 to 7.
BR is recognized during the booting sequence. The bus is
granted after the completion of loading the current byte. BR
during booting may be used to implement booting under the
control of a host processor.
The BMS and RD signals are used to select and strobe the boot
memory interface. Only gbit data is read over the data bus. To
accommodate up to eight pages of boot memory, the two MSBs
of the data bus are used in the boot memory interface as the two
MSBs of the boot space address.
The ADSp-210X Assembler and Linker suppon the creation of
programs and data structures requiring multiple boot pages
during execution. Table IV shows the state of various processor
registers after RESET and after a software forced boot.
Control Field
Data Registers
PX
All others
SralUS Registers
lMASK
ASTAT
MSTAT
SSTAT
Description
Control Registers (Memory-M_)" ,; . ,,'
I '
BW AIT wi,t i) 3
BPAGE Boot page :; ',,:,r" 0
SPORT 1 configure Configuration:' ,," 1
SPEO SPORTO enable 0
SPEI SPORT! enable 0
DW AIT0-4 Data memory wait states 7
PW AIT Program memory wait 7
TCOUNT Timer count register undefmed
TPERIOD Timer period register undefined
TSCALE Timer scale register undefined
Serial Port Control Registers (Memory-Mapped, One Ser Per SPORT)
ISCLK Internal serial clock
RFSR, TFSR
RFSW,TFSW
IRFS,ITFS
INVRFS, INVTFS
SLEN
MCE
MCL
SCLKDIV
RFSDIV
Multichannel word enable bits
FO
RBUF,TBUF
Frame sync required
Frame sync width
Internal frame sync
Inven frame sense
Serial word length
Multichannel enable
Multichannel length
Serial clock divide
RFS divide
Flag Out value
Autobuffering enable
o
o
o
o
o
o
o
o
undefmed
undefined
undefined
undefined
o
Table IV. RESET and Software Boot Machine State
Reboot
undefmed
unchanged
o
no change
no change
H#SS
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
no change
o
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-63
Data Memory Interface
The ,data' memory. address bus (DMA) and the data memory
data bus (DMD) are multiplexed with PMA and PMD, sharing
the external data lI!ld address bus. The 14-bit address bus
directly addresses up to 16K words of data, The data bus is
bidirectional and 16 bits wide.
The data memory select (DMS) signal indicates access to the
data memory and can be used as a chip select signal. The write
, (WR) signal indicates a write operation and can be used as a
write strobe, The'read (RD) signal indicates a read operation
and can be used as a read strobe or output enable signal.
The ADSP-2101 supports memory-mapped 1/0, with the
peripherals memory mapped into the data memory address space
and accessed by the processor in the same manner as data
memory.
Data Memory Map
The on-chip data memory RAM resides in the IK words of data
memory beginning at address H#3800, as shown in Figure 10.
In addition, data memory locations from H#3COO to the end of
data memory at H#3FFF are reserved. Control registers for the
system, timer, wait state configuration and serial port operations
are located in this region of memory.
The remaining 14K of data memory is external. External data
memory is divided into five zones associated with five different
wait states. This allows slower peripherals to be mapped)nto
zones of data memory with more wait states. Figute 10 shows
these zones.
.. L
1K External
DWAITO
1K Extarnal
DWAIT1
0000
0400
0800
flAM
10K Extarnal
j
DWAIT2
1K Extarnal
DWAIT3
1K EX1emll
DWAIT4
3000
3400
3800
1K Internal
3COO
Memory Mlpped
Aeglstar.
And FI rved
3FFF
Figure 10. ADSP-2101 Data Memory Map
Interrupt HandUng
The ADSP-2101 provides up to three external interrupt input
pins, IRQO to IRQ2. IRQ2 is always available as a dedicated
pin; IRQI and IRQO may be alternately configured as part of
Serial Port I. Each interrupt pin corresponds to a particular in-
terrupt priority level from 2 (highest) to 0 (lowest),
The ADSP-2101 also supports internal interrupts from the timer
and the two serial ports. The interrupt levels are internally pri-
oritized and individually maskable. These input pins can be pro-
grammed to be either level- or edge-sensitive. The priorities of
all six interrupts are shown in Table V.
The ADSP-2101 supports a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
level. Interrupts can optionally be nested so that a higher prior-
ity interrupt can pre-empt the currently executing interrupt ser-
vice routine. Each interrupt vector location is four instructions
in length, so that simple service routines can be coded entirely
in this space. Longer routines require an additional JUMP or
CALL.
Source of Interrupt
IRQ2 (external pin)
SPORTO Transmit (internal)
SPORTO Receive (internal)
SPORT I Transmit (internal) or
IRQl (external)
SPORT1 Receive (internal) or
IRQO (external)
Timer (itternal}
Interrupt Vector
0004 (highest pnonty)
0008
OOOC
0010
0014
0018 (lowest priority)
Table V. Interrupts & Interrupt Vector Addresses

The R'llrET signal initiates a master reset of the ADSP-210 1.
The RESET signal must be asserted after the chip is powered
up to assure proper initialization. If RESET follows initial
power-up, it must be held long enough to allow the internal
clock to stabilize. If RESET is activated subsequently, the clock
continues and does not require this stabi1ization time. The mas-
ter reset performs the following:
I. Initialize internal clock circuitry, if necessary
2. Reset all internal stack pointers to empty stack condition
3. Mask all interrupts
4. Clear MSTAT register
5. When RESET is released, if there is no pending bus request,
execute the boot-loading sequence (if configured)
6. Drive PMA with the restart vector, H#OOOO.
Interproceslor Communication
The serial ports provide a way to bidirectionally link two
ADSP-2101s in a system with no additional hardware required.
Figure II shows a typical system configuration with two
ADSP-2101 processors.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing,
2-64 DSP PROCESSORS
ADSP-21 01 IADSP-21 02
FS,
ADSP-2101
2764
250ns
FS.

PCMoul
CLKR
CLKX
ANALOG IN
ANALOG out
ANALOG IN
ANALOG OUT
ADSP-2101
TFS
RF.
DR
DT T
SCLK 1
250nl
2764
,/{f
/-'1\} ";h"
fJ3 {;onfir;,uration Figure 11.
INSTRUCTION SET DESCRIPTION . tL
The ADSP-2101 assembly Ian
rs'tnd data memories. The content of every reg
other reg.
an algebraic syntax for ease of c 1.' The . .
sources and destinations of comp " ng modes are supported for data memory transfers:
are written explicitly in each assembly " ' essing and indirect addressing. In direct addressing,
cryptic assembler mnemonics. Every instru into a '1' dress is supplied from the instruction word. In
single 24-bit word and executes in a single he '" "> . ng, one of the data address generators provides
tions encompass a wide variety of instruction types along W;th 't,'rihe ilddress. Using direct addressing, the contents of a data
high degree of operational parallelism. There are five basic\lirafe'.' memory location can be written and read by any reg. Using indio
gories of instructions: data move instructions, computational rect addressing, the contents of a data memory location can only
instructions, multifunction instructions, program flow control be written and read by a dreg. Immediate data load to data
instructions and miscellaneous instructions. Each of these in memory is permitted with indirect addressing. Only the indirect
struction types is described briefly. The complete instruction set addressing mode is supported for program memory data trans
is summari2ed at the end of this section. The ADSP-2IOI User's fers and contents of a program memory location can be read and
Manual gives an overview and the ADSP-2IOX Cross-Software written to any dreg.
Manual contains a complete reference to the instruction set. AXO, AXI --------....... ----
ADSP.2100 Compatibility AYO, AYI
ADSp-2101 source code is a superset of the ADSP-2100 instruc. AR
tion set. The ADSP.2101 is source and object code compatible MXO, MXI
with the ADSp-2100. An ADSp-2100 program may need to be MYO, MYI Data
relocated to utilize internal memory and conform to the new MRO, MRI, MR2
interrupt vector placement. SI
SE
The TRAP instruction, however, is not supported since the
ADSp-2101 does not have the TRAPIHALT signals.
SRO, SRI
SB
J
> Registers
(dreg)
______ -.J
Data Move Instructions
Table VI gives a list of all registers that are accessible using the
data move instructions. This set of registers is denoted as reg in
the instruction set summary given in Table IX at the end of this
publication. A subset of the reg group associated with the com
putational units, which generally hold data as opposed to ad
dress or status information, are denoted as dreg. Memory
mapped control registers are treated as data memory locations,
not as registers.
The data move instructions include transfers between internal
registers, between data memories and internal registers, between
program memories and internal registers, and immediate value
PX
10, l\, 12, 13, 14, 15, 16, 17
MO, MI, M2, M3, M4, MS, M6, M7
LO, LI, L2, L3, L4, LS, L6, L7
CNTR
ASTAT
MSTAT
SSTAT
IMASK
ICNTL
RXO, TXO
RXI,TXI ___________________ --'
Table VI. Register Classification
Accessible
>- Registers
(reg)
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-65
Memory-Mapped Registers
In addition to the registers listed in the table above, the ADSP-
21O! provides a set of memory-mapped registers for controllmg
system features, serial ports and the timer. The table below
summarizes these registers.
Memory
Location
3FFF
3FFE
3FFD
3FFC
3FFB
3FFA & 3FF9
3FF8 & 3FF7
3FF6
3FFS
3FF4
3FF3
3FF2
3FF!
3FFO
3FEF
Register Use
System control
Data memory wait state control register
Timer period
Timer count
Timer scaling factor
SPORTO multichannel receive word enables
SPORTO multichannel transmit word enables
SPORTO control
SPORTO serial clock divide modulus
SPORTO receive frame sync divide modulus
SPORTO autobuffer control
SPORT! control
SPORT I serial clock divide modulus
SPORT! receive frame sync divide modulus
SPORT! autobuffer control
Table VII. Memory-Mapped Registers
Computational Instructions
There are three types of operations associated with the .
tional units: AL U operations, MAC oPerations iind shifter oper-
ations. With few exceptions, all these computational inStructions
can be made conditional. (The permissible condition$ are speci-
fied in Table II.) Each computational unit has a tet of input reg-
isters and output registers. A list of permissible input operands
and result registers for each of the units is given in Table VIII.
ALU
Source for
X Input (xop)
AXO, AXI
AR
MRO, MRI, MR2
SRO, SRI
MAC
Source for
X Input (xop)
MXO, MXl
AR
MRO, MRl, MR2
SRO, SRI
Shifter
Source for
Shifter Input (xop)
SI
AR
MRO, MRl, MR2
SRO, SRI
Source for
Y Input (yap)
AYO, AYI
AF
Source for
Y Input (yap)
MYO,MYI
MF
Destination for
Output Port R
AR
AF
Destination for
Output Port R
MR (MR2, MRI, MRO)
MF
Destination for
Shifter Output
SR (SRI, SRO)
Table VIII. ComputationallnputiOutput Registers
Multifunction Instructions
Multifunction instructions execute one computational operation
with one or two data moves. All of the multifunction instruc-
tions utilize various combinations of the computational and data
move operations described above. Since the instruction word is
only 24 bits wide, only certain combinations are valid. In gen-
eral, the following rules are followed.
1. Computation must be unconditional.
2. Any memory transfer must use the indirect addressing mode.
3. Data move operations can only use data registers (dregs).
Program Flow Control Instructions
Program flow control instructions include JUMP, CALL, return
from subroutine, return from interrupt, DO UNTIL, SET,
CLEAR and TOGGLE the FLAG_OUT, and IDLE. All except
the IDLE and FLAG OUT instructions can be made condi-
tional. The JUMP and CALL instructions support both direct
addressing, with the destination address specified by the instruc-
tion word, and indirect addressing, with the destination address
specified by one of the I registers in DAG2. JUMP and CALL
also accept the addinooal cobdition based on the state of the FI
(Flag In) pin with direct addressing
lOLl! puts the processor into a low-power, wait-for-interrupt
mOde of operation.
MisceIlIll1_us IlIiItrIrQtiom
instructions include indirect register modify, stack
cootrOl, mode control and NOP operations. Mode control allows
the user to el'!llble or disable bit-reversal (DAG I), ALU overflow
iat}:hing, AR rl:liister saturation, use of secondary register set,
Go 1l10de; MAC format adjust mode and the timer.
Table IX Instruction Set Summary
The following conventions are used in this table:
1. All keywords are shown in capital letters.
2. Brackets enclose optional parts of the syntax.
3. Vertical lines indicate that one parameter must be chosen
from those enclosed.
4. Table VI defines the set of registers for dreg and reg.
5. Table VIII defines the set of registers for xop and yap.
6. Tables II and III define the conditions for <condition>.
7. <data> represents an immediate value or a pointer to (1\) or
length of (%) operator used with an identifier.
8. <address> may be an immediate value or label.
9. <comp>, in a multifunction instruction, represents all legal
ALU, MAC or shifter operations (the restrictions are detailed
in the ADSP-2IOX Cross-Software Manual).
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-66 DSP PROCESSORS
MULTIFUNCTION INSTRUCTIONS
<ALU'> I '
AXO
<MAC> AXl
MXO
MXl
AXO = DM( IO
AXl II
MXO 12
MXl I3
I
<ALU> I' dreg=
<MAC>
<SHIFTt>
DM( IO , MO
II , Ml
12 , M2
I3 , M3
14 , M4
IS , MS
16 , M6
17 , M7
PM (14 M4
IS MS
16 M6
17 M7
<ALU> I' dreg
<MAC>
<SHIFT>
= DM( 10 MO ) ,
II Ml
12 M2
I3 M3
MO ) , AYO = PM (
Ml AYl
M2 MYO
M3 MYl
DM( IO , MO
II , Ml
12 , M2
I3 , M3
14 , M4
IS , M$
16
:.'
, M6,
t7

M.7
:( I I '0
", i6' "MIS",'
, ". 11 " M7 ,
, ,
"
<AUJ> 'I;
,<MAC>
<SHIFT>
= dreg"
dreg;
ADSP-2101/ADSP-2102
AYO = PM( 14 M4 ) ;
AYl IS MS
MYO 16 M6
MYl 17 M7
14 M4 ) ;
IS MS
16 M6
17 M7
tAll computation is unconditional; ALU division and shift immediate operations prohibited.
This information applies to a product under development, Its characteristics and specifications are subject to change without notice,
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing,
DSP PROCESSORS 2-67
ALU INSTRUCTIONS
[IF condition]
I ~ I
xop
+ yop I
+C
+ yep + C
[IF condition]
I ~ I
xop
- yop I
-yop+C-l
[IF condition]
I ~ I
yop
- xop I
-xop+C-l
[IF condition]
I ~ I
xop
AND yoP I
OR
XOR
[IF condition]
I ~ I
PASS xop
yop
0
1
[IF condition]
[IF condition]
DIVS yop, xop ;
DIVQ xop;
MAC INSTRUCTIONS
[IF condition]
I ~ I
xop * yop ( SS ) ;
SU
US
UU
RND
[IF condition]
I ~ I
MR + xop * yop ( S5 ) ;
SU
US
UU
RND
[IF condition]
I ~ I
MR-xop*yop ( S5 ) ;
SU
US
UU
RND
[IF condition]
I ~ I
o ,
[IF condition]
I:: I
MR[( RND)];
IF MV SAT MR;
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-68 OSP PROCESSORS
SHIFTER INSTRUCTIONS
[IF condition] SR [SR OR] ASHIFT xop
[IF condition] SR [SR OR) LSHIFT xop
[IF condition) SR [SR OR) NORM xop
[IF condition) SE EXP xop
[IF condition) SB = EXPAOJ xop;
SR [SR OR) ASHIFT xop BY <data>
SR [SR OR) LSHIFT xop BY <data>
MOVE INSTRUCTIONS
reg
reg
dreg
OM( 10
Il
12
13
14
15
16
17
OM address
reg
dreg
PM( 14
15
16
17
,
,
,
,
,
,
,
,
MO
Ml
M2
M3
M4
MS
M6
M7
M4
MS
M6
M7
reli .. ,":
OM::
" "
OM C 10
reg;
<data>;
I
dreg I
<data>
PM ( 14
15
16
17
dreg
Il , ,
12 '.'
""13 ':"
:14
15
16
17
M4 );
MS
M6
M7
ADSP-2101/ADSP-2102
I HI
) ;
LO
I HI
) ;
LO
I HI
) ;
LO
It?xl
) ;
I HI
) ;
LO
I HI
) ;
LO

This information applies to a product under development Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
DSP PROCESSORS 2-69
PROGRAM FLOW CONTROL INSTRUCTIONS
[IF condition]
(IF condition]
IF
IF
[IF condition]
[IF condition]
JUMP
CALL
I
FLAG IN I
NOTFLAG)N
\
FLAG IN] \
NOT FLAG_IN
RTS
RTI
DO <address> [UNTIL termination]
IDLE' :

,,:;;
TO.EE:' j' ' -
""'< , ,;" "
.....:;' ...... : ,:A ',. ,,",f.
MISCELLANBoU$lNmUCTIQNS
(14)
(15)
(16)
(17)
<address>
(14)
(15)
(16)
(17)
<address>
CALL <address>
JUMP <address>
, '
<, '
," ;"< \\.
NOP; IpUSH IsTS [, POP POP PC] [, POP LOOP]
POP I
l
ENA \
DIS
BIT REV [, ... ]
AV_LATCH
AR SAT
SEC REG
TIMER
GO_MODE
MODIFY ( 10 , MO ) ;
II , Ml
12 , M2
13 M3
14 , M4
15 , Ms
16 , M6
17 , M7
Table ,X. Instruction Set Summary
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
2-70 DSP PROCESSORS
Microcoded Support Components
Contents
Introduction . . . . . . . . . . . . . . . . . .
Selection Guide . . . . . . . . . . . . . . . .
ADSP-1401 - Word-Slice Program Sequencer
ADSP-1402 - Word-Slice Program Sequencer
ADSP-1410 - Word-Slice Address Generator
ADSP-3128A - Multiport Register File ....
- ~ ~ - - ~ - - - -
Page
.3-3
.3-4
.3-5
.3 - 25
.3 - 29
. 3 - 45
MICROCODED SUPPORT COMPONENTS 3-1
-----_.-------- - ~ ~ - - - ~ ~ -
3-2 MICROCODED SUPPORT COMPONENTS
GENERAL INFORMATION
Support for microcoded systems is provided by the Word-Slice
family of microcoded building blocks. The current members of
the Word-Slice family of microcode components include the
ADSP-I40l and ADSP-1402 Program Sequencers, the ADSP-
1410 Address Generator and the ADSP-3l28A Flexible Register
File. The pro,lram sequencers and address generator feature the
Look-Ahead pipeline which eliminates the need for external
microcode pipeline registers by internally latching instructions
and addresses. The ADSP-3l28A Register File has five ports
and fast access times to maximize computational throughput of
microcoded systems using high speed floating-point components.
The ADSP-3l28A also provides flexible shared memory for mul-
tiprocessing systems using the ADSP-2100 family of micropro-
cessors. The ADSP-I401 and ADSP-14l0 are fabricated in a fast
l.S .... m CMOS process. The ADSP-1402 and ADSP-3l28A are
fabricated in a l ~ CMOS. These components improve perfor-
mance, reduce board space and ease development compared to
bit-slice and byte-slice solutions.
ADSP-1401 and ADSP-1402 PROGRAM SEQUENCERS
The ADSP-1401 and ADSP-I402 are l6-bit microprogram
sequencers with many high performance features such as single-
cycle branching. This makes them ideal for the demanding
sequencing tasks found in digital signal processors and high
speed, general purpose computers. In addition to high speed,
these sequencers feature on-chip storage and control of ten pri-
oritized and maskable interruptgj four decrementing event
counters; absolute, relative and indirect addressing capability;
and a dynamically configurable 64-word RAM. The ADSP-1402
is fully code-compatible with the ADSP-1401 but offers higher
speed and more 110 pins for interrupts, traps and reset than the
Introduction
ADSP-l401. The ADSP-1402 can support 20MIPS (million
instructions per second) operation. The ADSP-l40l can be used
in 11.lMIPS systems.
ADSP-1410 ADDRESS GENERATOR
The ADSP-1410 is a fast, flexible address generator that rapidly
generates the data memory addresses required by operations
such as digital filters, FFTs, matrix operations and DMAs. The
ADSP-1410 features a l6-bit ALU, a comparator and thirty 16-
bit registers. In a single cycle the ADSP-1410 can output a 16-
bit memory address, modify this address and detect when the
value has crossed a preset boundary and conditionally loop back
to the top of a circular buffer.
A 2SS-page Word-8lic, User's Manual covers all aspects of pro-
gramming with the ADSP-l40l, ADSP-1402 and ADSP-1410.
Third-party support is available in the form of meta-assemblers,
development systems and behavioral models. Contact Analog
Devices for further information on third-party support.
ADSP-3128A MULTIPORT REGISTER FILE
This l28x 16 or 64x32 register file provides high speed local
storage for our floating-point components and microprocessors
while also providing flexibility in operand data transfers with its
five-port structure. The register file is fast enough to provide
full computational throughput rates for our latest 1.0 .... m
floating-point parts. The ADSP-3l28A contains on-chip latches
for a multitude of system interfacing configurations without the
need for external glue logic. On-chip multiplexers automatically
sequence double-precision data transfers.
WordSlice is a registered trademark of Analog Devices, Inc.
Look-Ahead is a trademark of AnaJog Devices, Inc.
MICROCODED SUPPORT COMPONENTS 3-3

-- - - ~ - - ------ -- - - - - - - - - - - ~ -----
Selection Guide
ADSP-1410 ADDRESS GENERATOR
C1ock-to-
Data Memory Address Size Address MiDimum
Grade SiDgIe-Precision Double-Precision Valid Delay' Cycle Time
Commercial
J
16 Bits I 64K Words 30 Bits I I Gigaword 35 lOOns
K 16 Bits I 64K Words 30 Bits I I Gigaword 30 90ns
Military S 16 Bits I 64K Words 30 Bits I I Gigaword 45 125ns
T 16 Bits I 64K Words 30 Bits I I Gigaword 35 lOOns
NOTES
Ins, max @ +70"<: commercial, + 125"<: MIL.
'mA maximum, fCLK=max, over full Voo rsnge, @ +70'C commercial,+125'C MIL.
'D=ceramic 48pin DIP, N=plastic 48'pin DIP, P=52contact PLCC.
#of Address
Registers
16
16
16
16
Total # of
Registers
30
30
30
30
ADSP-1401/ADSP-1402 PROGRAM SEQUENCERS
C1ock!oAddre MiDimum
Prosram Valid Delay' Cycle Time
Model Addre Size Comm MIL Comm MIL
ADSpI402 16 Bits I 64K Words K=l7" (Note 5) K=5Ons (Note 5)
ADSpI401 16 Bits I 64K Words J=35 S=45 J=90ns S=110no
K=25 T=35 K=70ns T=90ns
NOTES
Ins, max @ + 70"<: commercial, + 125"<: MIL.
'mA miX, feLK =max, over full V DO range, @ + 70'C commercial, + 125"<: MIL.
'D=ceramic 48'pin DIP, N=plastic 48pin DIP, P=52contsct PLCC.
'Preliminary specification.
'Contact factory.
3-4 MICROCODED SUPPORT COMPONENTS
Number of
IDD
,
interrupts Comm MIL
10 (Note 5) (Note S)
10 75 100
Package Logic
IDDl Options' Process Type
75mA D,N,P CMOS TTL
75mA D,N,P CMOS TTL
100mA D CMOS TTL
100mA D CMOS TTL
No. of Packa .. Logic
Pins Option.' Proce Type
84 G CMOS TTL
48 D,N CMOS TTL
52 P
",ANALOG
WDEVICES
FEATURES
16-Blt Microcode Addressing Capability
LookAhead Pipeline
Extensive Interrupt Processing. With Ten OnChip
Interrupt Vectors
70ns Cycle Time; 25ns ClocktoAddress Delay
64-Word RAM for Storing:
Subroutine Linkage
Jump Addresses
Counters
Status Register
375mW Maximum Power Dissipation with
CMOS Technology
48-Pin Ceramic or Plastic DIP and
52Lead Plastic Leaded Chip Carrier
GENERAL DESCRIPTION
The ADSP1401 is a highspeed microprogram controller op-
timized for the demanding sequencing tasks found in digital
signal processors and general purpose computers. In addition to
high speed (2Sns clocktoaddress delay) and large addressing
range (64K of progrsm memory), this WordSlice@ component
has unique features that mske it highly versatile:
on-chip storage and control of ten prioritized and
maskable interrupts
four decrementing event counters
absolute, relative and indirect addressing capability
download capability (writeable control store) and
a dynamically configurable 64-word RAM.
The ADSP1401 microprogram sequencer's main task is to
provide the appropriate microprogram addressing to support
programming requirements (e.g., looping, jumping, branching,
subroutines, condition testing and interrupts). An internal Look
Ahead pipeline, controlled by both phases of the clock, allows
the ADSP1401 to satisfy these requirements at very high speed.
During each micro.instruction, the ADSp1401 monitors the
conditions and instructions to determine the next tnicroprogrsm
address. This address can come from one of several sources: the
stack, the jump address space in the RAM, the data port, the
interrupt vectors, or the microprogrsm counter. An extensive
set of conditional instructions are also available, including jumps,
branches, subroutines, interrupts, and writeable control store.
LookAhead i. a trademark of AIIIIioI Devices,loc.
WordSlice i. a reliotered trademark of Analol Deviceo, Inc.
Word-Slice
Program Sequencer
ADSP-1401 I
The ADSPl40I's internal 64-word RAM is userconfigurable
into three regions; subroutine stack, register stack and indirect
jump address space. The subroutine stack is used for linking
interrupts and subroutines and, during their execution, allow
storage of system states. The register stack allows association of
unique jump addresses with various levels of interrupts and
subroutines (both local and global stacks are provided). Indirect
jump capability is also supported, addressing for which is provided
at the data port.
Interrupts are handled entirely on chip. The ADSPI401's internal
interrupt control logic includes registers for eight external (user)
interrupt vectors, a mask register, and a priority decoder. Two
additional vectors are reserved for internallygenerated interrupts
resulting from counter underflow and stack limit violation. A
stack limit violation is caused by stack overflow, underflow or
collision. A mechanism is provided for recovering from stack viola
tions.
The ADSPl40I's four decrementing 16bit counters are used to
track loops and events. These counters generate a signal when
negative. This negative condition is used by several conditional
instructions and can also trigger an internal interrupt.
MICROCODED SUPPORT COMPONENTS 3-5
EXTERNAL
INTERRUPTS
(EXIR . ,)
INSTRUCTION
n,.,)
FLAG
Figure 1. ADSp1401 Block Diagram
ADDRESSING MODES
Direct: both absolute and relative
Indirect: from internal RAM
HARDWARE FEATURES
Instruction Port
Bidirectional Oata Port
Four Input Address Multiplexer
Three Stack Pointers
Four Event Counters
Condition Flag
Eight Prioritized and Maskable U aer Interrupts
ITR Pin:
Trap
Three-State
Reset
INSTRUCTION TYPES
Jumps and Branches
Stack Operations
Status Register Operations
Counter Operations
Interrupt Control
Relative Address Width Controls
Instruction Hold Control
Writeable Control Store
Dedicated Counter Underflow Interrupt
Dedicated Stack Overflow Interrupt
3-6 MICROCODED SUPPORT COMPONENTS
ADSP.1401 PIN ASSIGNMENTS
YIS - Yo
EXIR._1
CLK
FLAG
TTR
VDD
GND
Description
The 7 bit microinstruction controlling the
AOSPl401.
Output bus which provides addresaes to the micro-
program memory.
Bidirectional Oata bus for transferring data to or
from the AOSp1401.
Four external interrupt request lines. Note that in
ternal circuitry supports 8 interrupts with the aid of
an external 2 to I multiplexer.
External clock input
An input used for conditional instructions. Its
source is usually a condition multiplexer.
A multipurpoae pin accommodating traps, output
disable and react.
+ S Voltsupply.
Ground.
1.0 ARCHITECTURE
1.1 Look-Ahead Pipeline
Logically, the Look-Ahead pipeline is split into two halves: the
f1l'St, located at the instruction and data ports; and the second,
located at the address port. Each half of the pipeline (input vs.
output) has a transparent latch which operates out of phase with
the other; the address latch is transparent during the f1l'St half
of the cycle (clock HI), while the input latches (instruction and
data) are transparent during the second half of the cycle (clock
LO). This complementary arrangement allows new instructions
to be decoded (in preparation for the following cycle) while the
program address for the current cycle is held steady.
1.2 Instruction Port
The instruction port receives 7-bit instructions defming the next
operation to perform from microcode. The ADSP-I401 has a
built-in Look-Ahead pipeline latch, eliminating the need for an
external microcode latch to hold instructions. This implementation
has the further benefit of allowing instruction "look-ahead"; the
sequencer is able to decode the next instruction during execution
of the current cycle. During the "look-ahead" period, the sequencer
precalculates the next address, allowing its output as early as
possible in the next cycle.
External instructions are internally latched during clock HI, and
passed directly to the instruction decoder during clock LO
(transparent phase); thus, implementing the fll'st half of the
Look-Ahead pipeline latch.
The use of the instruction hold mode (see: Instruction Set De-
scription, 2.7; and Instruction Hold Control, appendix 4.1)
allows an instruction to be held in the instruction latch for
execution over several cycles (freeing microcode for use by other
devices).
1.3 Address Port and Multiplexer Sources
The address port provides 16-bit program addresses with three-
state drivers designed for driving large microcode memories.
Addresses come from a four-to-one microprogram address mul-
tiplexer. Between the multiplexer and output port is a transparent
latch which is transparent during clock HI and latched during
clock LO, permitting addresses to be output as early as possible
during phase one (clock HI) while holding the address constant
during phase two (clock LO) - implementing the second half of
the Look-Ahead pipeline latch.
Inputs to the microprogram address multiplexer are the:
16-Bit Program Counter
16-Bit Adder
Interrupt Vector File and
Internal 64-Word RAM.
Addressing Modes
The ADSP-I401 supports two addressing modes: direct and
indirect. The direct addressing mode uses the internal adder to
generate either absolute addresses from the data port (without
modification) or relative addresses from the program counter
(with or without extension: see Status Register, 1.4.4). The
indirect addressing mode uses the lower order bits at the data
port to access the contents of internal RAM for output.
ADSP-1401
Output Drivers
The address port output drivers are always active unless placed
in the high-impedance state by the IDLE instruction or appro-
priately asserting the TTR pin (see TTR Pin, 1.7). This allows
other devices to supply microcode addresses, which is particularly
useful in multi-tasking or context switching applications where
several ADSP-I40ls may be sharing common microcode
memory.
1.3.1 Program Counter
The program counter (PC) consists of a 16-bit incrementing
counter. For most instructions, the PC is incremented by the
end of the cycle (post-increment) as follows:
PC < = output address + I.
1.3.2 Adder and Width Control
For absolute jumps, data from the data port is passed unchanged
through the adder directly to the microprogram address port.
For relative jumps, a twos complement offset is supplied from
the data port and added with the 1 6 ~ b i t PC. Since the PC normally
points to the next instruction, the jump distance is (offset + I)
from the jump instruction. See Status Register (1.4.4) for more
details.
The width control block permits microcode width to be reduced
in systems not requiting full, 16-bit jump distances. Internal
width control logic sign-extends reduced offsets of 8- and 12-bits
to full 16-bit precision, accommodating jumps in either direction
(positive or negative displacement).
1.3.3 Interrupt Vector File
Ten prioritized interrupt vectors may be stored in the interrupt
vector file. The associated interrupts are internally latched and
may be individually masked or entirely disabled by the "Disable
Interrupts" (DISIR) instruction. The highest priority interrupt
vector displaces the usual address on the next cycle following its
detection. See Interrupts (1.4.3) for more details.
1.3.4 Intemal RAM
Any of the 64 words of RAM may be output on the address
port. Four distinct address sources may access the RAM:
Local Stack Pointer
Global Stack Pointer
Subroutine Stack Pointer and
Lower Order Data Port Bits.
The use of internal RAM and its various address sources are
described in section 1.4.2.
1.4 Bidirectional Data Port
The 16-bit bidirectional data port (Dls_o) supplies direct or
indirect jump addresses and permits loading or dumping of all
internal registers. The input data latch freezes incoming data
(for counter or register writes executed during that cycle) during
the first half-cycle (clock HI) and is transparent for the remainder
of the cycle. The output data driver asserts output data only
during the first half-cycle of a data output instruction and is
independent of the address port drivers. This complementary
1/0 arrangement permits data to be output from the sequencer
(as in a read register instruction) during the first half-cycle
while accommodating external data setups (for the next cycle)
during the second half-cycle.
MICROCODED SUPPORT COMPONENTS 3-7
Direct addressing via the data port may be either relative or
absolute. For indirect addressing, the six LS data bits (Ds_o)
are used to address internal RAM, containing the desired jump
address (see Internal RAM, 1.4.2).
1.4.1 Counters
Four independent l6-bit counters are provided for maintaining
loops and event tracking. These counters hold twos complement
values that may be decremented or preloaded through dedicated
instructions. The sign bit associated with the most recently used
counter, prior to its decrement, is always saved in the status
register (SRI)' Simultaneously, the sign bit is also made available
to control various conditional instructions or for asserting the
lowest priority interrupt, IRo, reserved for counter underflow
(see: Instruction Set Description, 2.0; and Interrupts, 1.4.3).
Note that interrupt IRo is primarily used for ending writeable
control store downloads (see Instruction Set Description - WCS,
2.7). Use of IRo in the context of a "Decrement Counter and
Interrupt on Underflow" operation represents the worst case
instruction and flag setup times because of the additional overhead
in processing the interrupt after determining whether the counter
was underflowed. These setup times are specified two ways:
1. all conditions and
2. IRo masked.
The source of SIGN (applied to the condition test) depends
upon the type of instruction used (see Instruction Set Description,
2.1). Two possibilities exist:
I. If an explicit counter is selected, then the sign applied is that
of the counter, prior to the decrement.
2. If no counter is selected, then the sign applied is implicitly
that of the status register, SRI'
1.4.2 Internal RAM
The ADSP-I40I's internal 64-word RAM implements two distinct
stacks: a Subroutine Stack (SS) and a Register Stack (RS). The
subroutine stack has a dedicated, Subroutine Stack Pointer
(SSP), while the register stack shares two pointers: the Local
Stack Pointer (LSP) and the Global Stack Pointer (GSP). The
three stack pointers are each held in 6-bit, preloadable, upldown
counters.
Upon reset, (TTR pin held HI for three cycles, see TTR Pin,
1. 7) the SSP is initialized to 0 (top of RAM). The RS pointers
(LSP and GSP) are typically configured as shown in Figure 2
using the "Write RSP" instruction (WRRSP). The SSP pushes
down while the RS pointers push up. Selection of the active RS
pointer (LSP or GSP) is made in the status register.
Stack overflow detection is provided via a stack limit register to
protect software integrity and allow stack expansion (see In-
struction Set Description - SLRIVP, 2.5).
Each RS pointer may be explicitly initialized by performing the
"Write RS Pointer" (WRRSP) instruction. The LSP should be
located above the GSP, allowing the local stack to grow upwards
as the level of nested subroutines increases. Finally, indirect
jump address space (as needed) should be reserved below the
global stack.
The sequencer will generate a stack underflow interrupt whenever
RAM location zero is popped. This facility may be used in
support of stack paging. IV 9 should be masked if not using
stack paging, allowing location zero to be used as the first stack
location without interrupting. When using paged stacking, location
zero must be reserved as an underflow buffer to avoid a subsequent
3-8 MICROCODED SUPPORT COMPONENTS
stack POP (which may otherwise occur, depending upon the
next instruction) prior to the interrupt routine saving the stack.
00
01
02
xx
33
34
35
36
31
3.
39
3A
3.
3C
3D
3.
3F
TOPOFRAM
UNDERFLOW BUFFER






INITIALIZED
FOR
INDIRECT
ADDRESSING
{ASNEEDEOJ
BOTTOM OF RAM
~ SSP
1 (PUSH)
_ SLR
t (PUSH)
LSP
f (PUSH)
---- GSP
Figure 2. Typical RAM Initialization
Register Stack Pointers (LSP and GSP)
Upon entering a routine, up to four jump addresses may be
pushed onto the register stack. A Push onto the register stack
first decrements the RS pointer (either LSP or GSP, depending
upon the status register) and then writes the appropriate data to
RAM. A Pop from the register stack first reads the RAM location
and then increments the RS pointer (LSP or GSP).
Four registers are available within context of any routine which
are addressed relative to the stack pointer (LSP or GSP) by
the two LSBs of the relevant instruction. For example, the
instruction:
IF CONDITION, JMP R2
a c c e s ~ e s the location (LSP + 2 or GSP + 2) in RAM as the condi-
tional address source. Prior to exiting a routine, local or global
registers can be effectively removed from the RS by the "ADD i
TO RSP" (AIRSP) instruction (see Instruction Set Description,
2.2).
Often, the same set of jump addresses are used by several different
routines. The GSP is available for addressing these common
registers - conserving RAM space and eliminating repeated
stack pushes and pops. Global registers can be pushed, popped,
and used by conditional instructions in the same way that local
registers are handled. In addition, the GSP can itself be pushed
and popped tolfrom the subroutine stack, allowing different
routines to access different subsets of the global stack area.
Subroutine Stack Pointer (SSP)
A Push onto the SS (jump subroutine or interrupt) first increments
the SSP and then writes the return address to RAM. A pop
from the SS first reads the return location and then decrements
the SSP, effectively removing the data from the stack (although
the data remains in RAM). For interrupts, the return address is
the one that would have been output in the cycle when the
interrupt vector was output. For subroutine jumps, the return
address is the instruction immediately following the subroutine
call. For further information, see: Return from Interrupt with
Pending Interrupt, appendix 4.2; and the Instruction Set De-
scription, 2.0.
The subroutine stack can also be used to save key program
parameters such as the status register, GSP, or counter values.
After entering a new routine, critical parameters from the calling
routine are pushed onto the stack, thus freeing the associated
hardware for use by the new routine. Prior to the end of the
routine, the original parameters are restored with their former
values for continued use by the calling routine.
The Stack Usage Example (appendix 4.3) illustrates the state of
RAM after three subroutine calls.
Stack Limit Register and Stack Owrjlqw
The preloadable Stack Limit Register (SLR) and associated
circuitry warns the user of impending stack overflows, permitting
stack overflow recovery. The highest priority interrupt, IR" is
assigned to stack overflow, although it may be masked. A stack
overflow interrupt will occur under any of the following three cir-
cumstances:
a push causing the SSP to increment to the value in the
stack limit register
a pop from SS location 00 (underflow)
a push causing the RS pointer (LSP or GSP) to decre-
ment to the value in the stack limit register + 3.
The three location buffer between the SLR and the RS pointer
allows for three extra pushes that may occur (in a worst case)
prior to entering the stack overflow service routine. These pushes
would be:
1. the push causing the initial overflow
2. a possible push operation while IV 9 is output and
3. the IR, return address push.
See: Interrupts, 1.4.3; and Three Stack Pushes on Stack Overflow
(appendix 4.2.5) for more details.
The SLR is only 4-bits wide and is compared to the 4 MS bits
of the 6-bit RAM address. Therefore, stack limits may only be
set at integer multiples of 2
2
, i.e., RAM locations 0, 4, 8, 12,
. , 60. The SLR is right-filled the additional two bits with
zeros or ones, depending upon the direction of the push being
performed ('00' for SS pushes and 'U' for RS pushes, see In-
struction Set Description - SLRIVP, 2.S). In the cycle following
a stack overflow, the highest priority interrupt vector IRV9 (also
used for trapping; see TTR Pin, 1.7) is output. To determine
the cause of this interrupt, both SS and RS pointers must be
tested in the first several cycles of the service routine. Prior to
returning from the overflow interrupt routine, the SLRIVP
instruction must be executed, to clear the calling IR, from the
interrupt latch.
1.4.3 interrupti
The ADSP-I401 processes eight externsl and two internal inter-
rupts. All external interrupts are level sensitive (positive logic:
see IR Latch, this section) and are processed by the interrupt
10gic block. The block eLlments (see Figure 4) are comprised of
an interrupt de-multiplexcr followed by an interrupt latch, masking
I. and priority decoder for selecting the most urgent interrupt
( I ~ having the hiahest priority, and IRa the lowest), and special
OIIe-shot to override the address multiplexer with the interrupt
ADSP-1401
vector (IV 9-0) on the cycle following the interrupt request.
The external interrupts (IRs_I) may be used for any purpose,
however, unused inputs IIIIISt not be left floating (i.e., tie them
to logic LO so as to preclude the associated interrupt). Two
additional interrupts which are internal are reserved for stack
overflow - IR, (see Stack Limit Register and Stack Overflow,
1.4.2) and counter underflow - IRa (see Counters, 1.4.1). See
Counters (1.4.1) for implications of using IRa for other than
writable control store downloading.
Interrupt vectors are always output (aasuming interrupts are
enabled and the associated interrupt is not masked) on the cycle
immediately following the acceptance of the interrupt request.
Contextual saves (stacking and storing) should be made im-
mediately upon entering the interrupt service routine and restored
immediately prior to its exit.
Up to four external interrupts may be connected directly to the
external interrupt pins, EXIR._1t and are treated as interrupts
IRs_s, respectively. Lower priority interrupts, IR._1t must be
masked out in this case.
Up to eight external interrupts may be accommodated using
time-division multiplexing. An external 2:1 multiplexer reduces
the eight externsl interrupts to two groups of four (see Figure
3). An internsl de-multip1exer automatically restores the external
interrupts back to eight.
The interrupt vector file may be directly read and written via
the data bus with the aid of the Interrupt Vector Pointer (see
Instruction Set Description, Interrupts, 2.S).
IROB
IRQ7
IRQe
IRQ5
IRQ4
IRQ3
IR02
IRQl
74F257
QUAD 2:1
MUX
lY
2Y
3Y
4Y
ADSPI401
SEQUENCER
CLOCK _____ ..... _________ ..1
Figure 3. Expanding External Interrupts
IR Latch
Interrupt requests IRs_s are latched during the first half-cycle
(clock lfi), while IR._I are latched during the second half-cycle
(clock LO). Once latched, externsl interrupt requests are held
until processed, even if the externsl request signal goes away.
This latching technique allows removal of externsl interrupt
sources after they have been recognized by the sequencer.
Latched user interrupt requests (IRs-I) are held until: i) the
interrupt is processed and a "Return from Interrupt" (RTNIR)
instruction is executed; ii) the interrupt service routine executes
a ''Clear Current Interrupt" instruction (allowing nested inter-
rupts); or, iii) a "Clear All Interrupts" instruction is executed.
Reserved interrupts (IR, and IRa) are cleared from the interrupt
latch by utilizing the SLRIVP and CLRS instructions, respectively.
See Internal IR Control Logic (1.4.3) for details.
The user may byps6S the interrupt latch with the "Select Trans-
parent Interrupts" (STIR) instruction (setting status register bit
SRo). In the traneparent mode, the interrupting device must
assert the interrupt request until the interrupt service routine
resets the request source.
MICROCODED SUPPORT COMPONENTS 3-9
EXIR4-'
TRAP-----.-_.
INTERRUPT
VECTOR
FILE
(lVIOI

(lROI
TO ADDRESS PORT
SIGNISR11
Q
PRIORITY
DECODER
IRVP IRO
10
INTERRUPT IN
PROGRESS (lRIPI
Figure 4. Internal Interrupt Control Logic
IRMask
All ten interrupts may be independently masked using status
register bits SR15 _6 (corresponding to interrupts Setting
a particular mask bit prevents the interrupt from being executed.
Note that the status register may be read or written via the Data
port, and also pushed and popped to/from the subroutine stack,
allowing nesting and servicing of interrupts in any desired order
(see: Internal IR Control Logic, 1.4.3; and Status Register,
1.4.4).
Two instructions allow bitwise clearing or setting of the interrupt
mask. "IR Mask Bit Clear" (IRMBC) will clear those mask bits
for which the corresponding data bits (015_6, as applied to
are set, while "IR Mask Bit Set" (IRMBS) will set those
mask bits for which the corresponding data bits are set. In both
cases, zeros in the data field will preserve the corresponding
mask bit. See Instruction Set Description - Status Register, 2.3.
IR Priorily Decoder
Unmasked interrupts are passed to the priority decoder which
determines the most urgent, valid interrupt and generates an
internal Interrupt'Request Signal (IRS). The corresponding
vector is then fetched from the interrupt vector file and passed
to the address port.
Minimum IR Servicing Requirements
Interrupt vectors are output on the cycle following the acceptance
of an interrupt request. Interrupt jumps differ from subroutine
jumps in that subroutine jumps push the return address in the
same cycle as the jump address is output, whereas interrupt
return addresses are not pushed until the folluwing cycle. This is
3-10 MICROCODED SUPPORT COMPONENTS
because the instruction executing while the interrupt vector is
output may be utilizing RAM and must complete its execution
prior to pushing the interrupt return address. Thus, the PC
(interrupt return address) is pushed automatically in the first
cycle of the interrupt service routine, i.e., the cycle folluwing the
interrupt request acceptance.
For this reason, the first instruction of any interrupt service
routine is always ignored; it must be a no-op (CONT). Note that
a minimum interrupt service routine would be a CONT followed
by a RTNIR.
lmernallR Control Logic
The interrupt enable bit of the status register, SR2, must be set
for interrupt servicing to occur. Interrupt servicing may be
inhibited by clearing this bit, although external interrupt
will continue to be latched.
Only one interrupt is ever active at a time. Additional interrupts
are "locked out" by an internal "Interrupt In Progress" signal
(IRIP) during interrupt servicing (except for TRAP), although
they continue to be latched. The IRIP signal is automatically
reset upon the "Return from Interrupt" (RTNIR) instruction
which pops the return address from the subroutine stack to the
PC.
Normally, multiple interrupts are accumulated in the interrupt
latch. Whenever a valid interrupt is pending, the internal signal
"Interrupt Request" (IRQ) is asserted. Upon each RTNIR, the
highest priority, unmasked, pending interrupt is serviced.
Nested interrupts are supported with two instructions: "Clear
Current Interrupt" (CCIR) or "Clear All Interrupts" (CAIR).
The CCIR instruction clears the IRIP signal and interrupt latch
bit for the interrupt in progress. This action re-enables inter-
rupting, relegating the interrupt in progress to a subroutine
status. If an external interrupt is pending, the associated IR
vector will be output on the cycle following CCIR. To cancel all
pending interrupt requests, the CAIR instruction clears the
IRIP signal and the entire interrupt latch.
Normally, it is good practice to convert interrupts to subroutines.
This can be done by executing the "Clear Current Interrupt"
(CCIR) instruction (resetting IRIP) and should be done as early
as possible in the interrupt service routine. There are two reasons
for changing the status of an interrupt to that of a subroutine.
Firstly, if IRIP is allowed to remain active throughout the interrupt
service routine, then the occurrence of either internal interrupt
(stack overflow or counter underflow, IR9 or IRo, respectively)
will remain undetected until the current interrupt concludes;
the user will be unaware of these interrupt requests.
When using the TRAP capability (see TTR Pin, 1.7), there is a
second reason to clear IRIP. Because TRAP must have the
highest priority, interrupt ~ (when invoked by a TRAP request)
is not locked out by IRIP. This allows TRAP to displace an
interrupt in progress, but also means that upon completion of
the trap service routine, IRIP will be cleared by the RTNIR
instruction; re-enabling interrupting in spite of the incomplete
interrupt which TRAP displaced.
Either of these instructions (CCIR or CAIR) require an "extra"
cycle before a pending interrupt vector may be output. A typical
scenario being an interrupt in progress, IR" (containing a CCIR
instruction), with a interrupt pending, IRm:
CCIR Example
.. Code lutruction OutpUt
Location Esecutina Addres. Comments
n IR.Routine n+1 IR,. Pending
n+1 CCIR n+2 ClearIRIP
n+2 IR.Routine IVm IR,. Recognized
IVm IR,. Routine IVm+1 ...
1.4.4 Status Register
The ADSP-1401 has a 16-bit status register for storing various
operational modes. The ten MS bits of this register (SR1S_ 6)
comprise the interrupt mask for interrupts IR9_
o
, respectively.
The remaining six LS bits (SRs_o) control the operational modes
as shown below.
Bit#
SR"
Sa.
SR, .
SR,
SR,
SRI
SR,
Statui Rasiotar Bit Auipmenla
FIIIICtion HVLO
IR, Mask Bit
IR,MaskBit
Relative Jump Width Selectinn:
'00' = Iii-bit relative address width
'OI'=Sbit width
'IO'=IHC Mode (S.bit width)
'11' = 12bit width
Select GSP/LSP
EnablclDisable Interrupts
Set/Clear Sign Bit
Select Transparent/Latched Interrupto
ADSP-1401
The status register can be directly read and written via the data
port and also pushed and popped to/from the subroutine stack.
In addition, status register bits SR1s_6 (the interrupt mask) may
be bitwise cleared or set with dedicated instructions. See: In-
struction Set Description - Status Register, 2.3; and Interrupts
- IR Mask, 1.4.3.
1.5 Clock
The input clock employs both HI and LO levels to control the
various transparent latches throughout the device. Generally,
the clock should be symmetric; however, in some instances the
clock may be stretched during the second half-cycle (LO) to
accommodate unusual circumstances such as a cache memory
miss (see: TTR Pin - Trap, 1.7).
1.6 External Flag
The external flag input may be used to control conditional in-
structions. FLAG is latched similarly to instructions (latched
during clock HI and transparent during clock LO), but requires
less setup time. Two instructions make explicit use of FLAG as
their condition (JPCOF and JPCNF), while others employ a
condition mode selection (UNCONDITIONAL, NOT FLAG,
FLAG, or SIGN; see Instruction Set Description, 2.0) to be
specified as part of their opcode.
1.7 TTR Pin (Trap, Three-State and Reset)
The Trap, Three-State and Reset pin (TTR) is a time multiplexed,
three-purpose pin used to
provide program trap capability
control the address port output drivers and
reset the ADSP-1401.
If the TTR pin is held HI for an entire cycle, the RESET sequence
begins and TTR must be held HI for at least two more complete
cycles (RESET requires three cycles to complete). If trap and
threestate control capabilities are also needed, the combination
of the 1401's internal circuits and the external circuitry shown
in Figure 5 can be used to effectively timemultiplex the TTR
pin.
74F257
2.1 y
MUX
SElB elK
CLOCK ________ .... _______ -'
Figure 5. External Logic for TTR Pin
Trap
For a trap to occur, the TTR pin must be asserted during clock
LO only. The primary reason to invoke a trap is in support of
cache memory systems, or in case of system emergencies. Cache
memory systems generally utilize a large microcode memory
space, of which only a small area (that currently under execution)
is comprised of high.speed RAM (the balance consisting of
slower, less costly memory). The high-speed RAM is directly
accessible by the sequencer, whereas the bulk of (slow) memory
is usually accessible indirectly (via a cache memory controller
which controls downloads of code to the cache memory area).
MICROCODED SUPPORT COMPONENTS 3-11
In a cache-based system, microcode is generally executed from
the high-speed cache. If an access is attempted to code not
resident in the cache area, the cache memory controller must
detect the discrepancy and generate an exception to the access (a
"cache miss"). Then, the missing code segment must be down-
loaded to the cache memory area (see: Instruction Set Description
- Writeable Control Store, 2.7).
When a cache miss occurs, the cache memory control logic
asserts the TTR pin while stretching the system clock LO.
Upon detecting the trap request, the sequencer immediately
generates the highest priority interrupt, IR9, replacing the current
address (that causing the cache miss). The cache miss address is
pushed on the subroutine stack and popped after the interrupt
service routine has reloaded the cache area with the missing
code segment.
Note: Trap requests which occur on the first cycle of an interrupt
service routine are not recognized. The ADSP-I40 I always executes
a CONT instruction in this cycle, and ignores its instruction
port and therefore trap requests as well.
The trap interrupt differs from the standard interrupt protocol
in three ways:
1. The interrupt vector, IV 9, is output asynchronously, i.e., it
occurs tTRAD after asserting the Trap signal and must occur
before the next cycle! To accomplish this, a clock stretch
cycle may be needed to allow enough time to fetch the new
instruction.
2. The current address is pushed onto the SS for later restoration
(after the cache miss is resolved), whereas standard interrupts
push the current address + 1.
3. Trap interrupts cannot be masked or disabled. Note that if
IR9 is also used for stack overflow and underflow, the service
routine must discriminate which actually occurred.
Caution: because trapping is asynchronous, spikes on the TTR
pin wider than 3ns during clock LO may initiate inadvertent
trapping.
2.0 INSTRUCTION SET DESCRIPTION
The instruction set is divided into seven categories pertaining to
generic operation (see data sheet outline or Mnemonics and
Opcodes, 4.5).
Several instructions employ two instruction bits (I I and 10) to
specify a counter (C3-0) and/or a local register (R3_0, relative to
the RSP) as arguments. Nine of the conditional instructions use
another two instruction bits (13 and Iv to select one of the four
condition modes:
'00'
'01'
'10'
'1I'
UNCONDITIONAL
NOT FLAG
FLAG
SIGN
The sign bit of the status register, SR" may also be used to
(implicitly or explicitly) store an external condition. This is
useful if the condition results from an operation performed in
the middle of a loop, but is not tested until the end; the loop is
exited with an "If Sign: Jump" instruction. Recall that any
subsequent counter operations will overwrite SRI'
2.1 Jump and Branch Instructions
Jump and branch instructions provide flow control of microcode
execution, offering three-way branches, jumps, subroutine calls,
returns, and addressing mode selection (see Figure 6). These
3-12 MICROCODED SUPPORT COMPONENTS
Three-State
The address port is placed in a high-impedance state when the
TTR pin is HI during clock HI and LO during clock LO. The
TTR signal is latched during clock LO and transparent during
clock HI. This facilitates full cycle, three-state control. (Note
that the IDLE instruction can also place the address port in a
high-impedance state.)
Reset
The TTR pin may be used to initialize the ADSP-I40 I by asserting
it (HI for both clock phases) for at least three full cycles. Use of
the reset operation alone does not require the multiplexing
described above. However, if the trap and/or three-state controls
are also needed, they must not occur in the same cycle (this
would be an abnormal situation), as this constitutes a reset. The
RESET signal forces a zero output address, places the data port
in the high-impedance state, and resets internal registers as
follows:
Sequencer Status after RESET Operation
Parameter
Program Counter
Subroutine Stsclt Pointer (SSP)
Loca1 Stsclt Pointer (LSP)
Global Stsclt Pointer (GSP)
Stack Umit Register (SLR)
RAM Data
Counters

Interrupt Vector File
Interrupt Vector Pointer (IVP)
SR
S
_
4
SRl
SR2
SRI
SRo
Writeable Control Store Mode
NOTE:
Reaet Condition
..eocte Location 0000'6
RAM Location 00'0
Undefmed
Undcflned
RAM Location 3210
NoChaage
NoChaage
All Bits to '0' (Uamaskcd)
NoChaage
Undefmed
'00' (I6-Bit Relative Offsets)
'0' (LSP Selected)
'0' (Interrupts Disabled)
'0' (Sign Bit Cleared)
'0' (Latched Interrupt Mode)
Qearcd
The first instruction (mic:rocode location 000016) mUlt be a "CONT".
instructions support conditional control, allowing addressing
from the register stack, the data port, or the indirect jump
address space in the RAM. Generally, they are of the form:
If Condition: Do Operation; Else, Continue.
JPCOF IF FLAG: JUMP PC
The address is not incremented while the flag is at a logic HI,
i.e., PC< =PC. If the flag is LO, the next address is (PC + I).
JPCNF IF NOT FLAG: JUMP PC
The address is not incremented while the flag is at a logic LO,
i.e., PC< =PC. If the flag is HI, the next address is (PC + I).
ITWO IF CONDITION: JUMPPC+2
If the condition specifled is met, this instruction causes the next
sequential microprogram address to be skipped. This instruction
allows single instruction bypassing or interleaving without need
to provide explicit addresaing.
JDA IF CONDITION: JUMP DATA, ABSOLUTE
If the specifled condition is met, this instruction causes a jump
to the absolute address at the data port. If the condition is not
met, the next sequential instruction will be executed.
ADSP-1401
16

16
17
F TRUE

FALSE TRUE
18 18
tJ
17
18
19
JPCOF
DATA=40 FOR ABS 22 FOR REL DATA=13
16 16
17 17
18 40 18
JDA.JDR
JPCNF
RAM (13)=40
40
JDI
20
16
17
18
Ci<=CI-1
JTWO
DATA = 10
10
Ci<=RI
JDRST
RSP=26,1=2, RAM (28)=R2=4O RSP=26,1=3, RAM (29)=R3=12, DATA=40 FOR ABS .. 22 FOR REL.

::
17
S. TRUE
FALSE
18 C3<=C3-1
16
17
18 40
JRC JRS JSA,JSR
SSP=37, RAM (37)=40
RSP=26, 1=2, RAM (28)=R2=40, DATA =83
16 DATA = 75

16 17

18 75 40
83
WAIT CO<=CO-l
FOR F PC<=PC+l
FLAG TRUE
FALSE
RTN
C2<=C2-1
BRANCH WCS
Figure 6. Instruction Flow Charts
JDR IF CONDITION: JUMPOATA, RELATIVE
If the condition specified is met, the address at the data port
will be added to the PC and output (jump distance is offset plus
one). The offset width is determined by the address width selection
(8, 12, or l6-bits). If the condition is not met, the next sequential
instruction will be executed.
JDI IF CONDITION: JUMPOATA, INDIRECT
If the condition specified is met, this instruction will output the
address stored in the RAM address given by bits 0 5_0 of the
data port. If the condition is not met, the next sequential instruction
will be executed.
JDRST IF SIGN OF (4: JUMP OAT A, (4< = Ri ;
ELSE"Ci< = C.-l
This instruction fIrSt tests the sign of the counter, C If negative,
the address at the data port is output and the counter is re-initialized
(reset) with the data in the register pointed to by (aSP + i). If
the sign is positive, the counter is decremented and the next
sequential address is output. The register and counter use the
same subscript, i.
JRC IF CONDITION: JUMP R;. (CONO <F SIGN)
If the condition specified is met, output the address in RAM at
the location (RSP+i), where i is given by 11- 0 of the instruction.
The selected condition may not be SIGN, as this is the JRS
instruction. The PC may be pushed on the register stack and
referenced as a register thus allowiDg a "jump to stack" instruction
which is useful for looping.
JRS IFSIGNOF(4:JUMPR.,C.<=C.-l;
ELSE,(4< =Ci-l
This instruction fIrSt tests the sign of counter, C . If negative,
output the address in RAM at location (RSP + i). If the sign is
positive, the next sequential microprogram address is output.
The counter is always decremented after the test.
jSA IF CONDITION: JUMP SUBROUTINE,
ABSOLUTE
If the condition specified is met, the 16-bit absolute address at
the data port is output and the PC will be pushed onto the
subroutine stack. If the condition is not met, the next sequential
instruction will be executed.
MICROCOOED SUPPORT COMPONENTS
JSR IF CONDITION: IUMPSUBROUTINE,
RELATIVE
If the condition specified is met, the address at the data port is
added to the PC and output (jump distance is offset plus one)
and the PC is pushed onto the subroutine stack. The offset
width is determined by the address width selection (8, 12, or
16-bits). If the condition is not met, the next sequential instruction
will be executed.
RTN IF CONDITION: RETURN FROM
SUBROUTINE
This instruction is used to return from subroutines. If the condition
specified is met, the subroutine stack is POPped, which outputs
the return address and decrements the SSP. If the condition is
not met, the next sequential instruction will be executed.
BRANCH IF SIGN OFCI: JUMP Rio Ci< =Ci -I;
ELSE,IFCONDITION:
IUMPDATA,Ci<=Ci-l;
ELSE, Ci< =Ci -I (COND'" SIGN)
This instruction implements a three-way branch with the address
source from the data port, register Rio or the PC. The instruction
first tests the sign bit of the counter Ci; if negative, the output
address is given by R;, i.e., RSP+i. If the sign was not true,
but the specified condition is true, the address source is the data
port. If the sign was not true and the condition is not met, the
next sequential instruction is executed.
The counter and the register use the same subscript value i.
The counter is always decremented. Note that this instruction
uses only absolute data addresses; relative addressing is not
availsble with the three-way branch instruction.
2.2 Stack Operations
Subroutine Stack
Subroutine Stack Pointer (SSP) instructions are used for main
taining the subroutine stack. These instructions may also be
used to upload or download the entire RAM for examination,
stack expansion or context switches.
PSDSS PUSHDATAONTOSS
Increments the stack pointer and then loads the RAM location
specified by the SSP with the data at the data port.
PPSSD POP SS TO DATA PORT
Transfers the contents of the stack location given by the stack
pointer to the data port and decrements the stack pointer.
wassp WRITE SSP
Loads the SSP with bits D5_0 of the data port.
RDSSP READ SSP
Read the 6-bit subroutine stack pointer. This allows the value of
the stack pointer to be saved or examined. Bits D5_0 of the data
port correspond to bits S"() of the SSP. The 10 MSB's of the
data port ( D I 5 _ ~ are undefined.
DSSP DECREMENT SSP
Decrements the stack pointer without reading.
Register Stack
Register Stack Pointer (RSP) instructions are used to upload
and download the entire RAM for initialization, examination, or
3-14 MICROCODED SUPPORT COMPONENTS
context switchinJ and to maintain the RAM space allocated to
local and global jump registers. As previously discussed, register
stack instructions refer to either the Local Stack Pointer (LSP)
or the Global Stack Pointer (GSp), depending upon the status
register (SR3). If SR3 is LO, register stack instructions pertain
to the LSP. If SR, is HI, register stack instructions pertain to
the GSP.
SGSP SELECTGSP
Select the Global Register Stack Pointer. Set Status bit SR,
(HI).
SLSP SELECT LSP
Select the Local Register Stack Pointer. C1ear Status bit SR3
(LO).
RDRSP READRSP
Transfers the RSP to the data port bits D5_0 for examination OJ
storage. The 10 MSBs ( D I 5 _ ~ of the D port are undefined.
WRRSP WRITERSP
Preload the selected RSP (LSP or GSp) with bits D5_0 of the
data port.
PSPC PUSHPCONTORS
Decrements the RSP and writes the PC to the register stack.
This instruction may be used to set up a IRC loop (IF
CONDITION: JUMP R;=PC).
PSGSP PUSH GSPONTO SS
Increment the SSP and write the GSP onto the subroutine
stack. .
PPGSP POP GSPFROM SS
Write the subroutine stack to the GSP and decrement the SSP.
PSDRS PUSH DATA ONTO RS
Decrement the RSP and then write the data at the data port
into the location specified by the updated RSP.
PPRSD POPRS TO DATA PORT
Transfers RAM data pointed to by the RSP to the data port and
then increments the RSP.
AlRSP ADDiTORSP
Add i to the register stack pointer. Note that i = 0, 1, 2, !Jr 3 in
this instruction corresponds to 4, 1,2, or 3, reapectively. This
instruction effectively removes up to four registers from the
stack.
SlRSP SUBTRACT ONE FROM RSP
Subtract 1 from the RSP without a write. This instruction is
used to modify the RSP without explicitly reloading it.
S4RSP SUBTRACT FOUR FROM RSP
Subtract four from the RSP without a write. This instruction
may be used to modify the RSP without explicitly reloading it.
2.3 Status Register OperalioDl
The status register bits, SR
I5
_
0
, contain ten mask bits, SR
IS
_
6
,
for masking interrupts IR,_o, and six control bits, SR5_
0
(sec
Bidirectional Data Port, 1.4). The entire status register can be
read or written via the data port, or pushed or popped to/from
the subroutine stack. Upon RESET, the entire status register is
initialized to zero.
RDSR READSR
The entire status register (SRI5_0) is output over the data port
(D15_0)'
WRSR WRITESR
Write the data port (DI5_0) to the status register (SRI5_0).
PSSR PUSH SRONTO SS
Increment the SSP and then write the status register to the
subroutine stack.
PPSR POP SRFROM SS
The top of the subroutine stack is wrirten into the status register,
and then the SSP is decremented.
2.4 Counter Operations
Counters may be pushed and popped to/from the subroutine
stack or loaded directly from the data port. The counters may
be read externally by pushing the counters onto the subroutine
stack then popping the subroutine stack to the data port. The
device has four counters, denoted 4, which are indexed by the
two LSBs of the instruction.
If a jump is required after N events (until sign), the counter
should be loaded with two less than the number of events desired
(N - 2). If a jump is required for N events (while sign), the
counter is loaded with 2
15
+ N - 2 = 800016 + N - 2.
Care must be taken when using the counter underflow interrupt
(IRa, see 1.4.3) to clear the sign bit before the IRa mask bit is
cleared.
WRCNTR WRITECi
Write to the selected counter, 4, from the data port.
CLRS CLEAR SIGN BIT
Clear status register bit SRI'
SETS SET SIGN BIT
Set status register bit SRI'
PSCNTR PUSH CI ONTO SS
Increment the SSP and write the specified counter onto the
subroutine stack.
PPCNTR
Transfer the data from the subroutine stack to the counter
specified by the instruction, then decrement the SSP.
DCCNTR DECREMENT 4
Unconditionally decrement counter 4.
IFCDEC IF CONDITION: DECREMENT Co
Decrement counter Co on condition. If the sign condition is
selected, the sign is taken from the status register bit SRI> rather
ADSP-1401
than from the counter sign (which normally provides the sign
condition).
Normally, if the counter underflow interrupt (IRa) is enabled, it
is activated by the counter sign bit going HI. However, iflFCDEC
is used to decrement Co, the IRa interrupt is activated by the
SRI bit, rather than the sign bit of Co. Since the SRI bit goe$
HI only after Co has underflowed, IFCDEC must be executed
once more after the Co underflow to generate the IRa interrupt.
Alternatively, the pre10aded value of Co may be reduced by one.
2.S Interrupt Control
Detailed interrupt operation is described in the Interrupts section
(1.4.3). Here, specific interrupt operations such as interrupt
clearing, IRV readlwrite, interrupt mask manipulation, etc., are
described.
CCIR CLEAR CURRENT INTERRUPT
Allows nesting of user interrupts IRs_Ion subsequent instructions
by clearing both the interrupt latch bit currently being serviced
and the interrupt in progress signal (IRIp), re-enabling interrupts.
If an external interrupt is pending, the associated IR vector
will not be output until the cycle following CCIR. Internal
interrupts ( ~ and IRa) are IIOt cleared by CCIR and must be
explicitly cleared through the SLRIVP and CLRS instructions,
respectively.
CAIR CLEAR ALL INTERRUPTS
Clears external interrupt latches IRs- I> and re-enables the interrupt
interface (IRIP cleared LO). The next sequential instruction
will be executed prior to the jump to a pending interrupt. Internal
interrupts ( I ~ and IRa) are IIOt cleared by CAIR and must be
explicitly c1eared through the SLRIVP and CLRS instructions,
respectively.
RTNIR RETURN FROM INTERRUPT
Clears the current interrupt latch for IRs- I> re-enables interrupts
(IRIP cleared LO), and pops the return address from the sub-
routine stack. The next sequential instruction will be executed
prior to the jump to a pending interrupt routine. Internal interrupts
are IIOt cleared and the ~ and IRQ interrupt latches must be
cleared explicitly through the SLRIVP and CLRS instructions,
respectively.
RDIV READ IRV AND INCREMENTIVP
Outputs the interrupt vector currently pointed to by IVP to the
data port and then increments the IVP. Interrupts should be
disabled when writing or reading interrupt vectors.
WRIV WRITE IRV AND INCREMENT IVP
Writes the interrupt vector currently pointed to by the IVP
from the data port and then increments the IVP. Interrupts
should be disabled when writing or reading interrupt vectors.
IRMBC IR MASK BITWISE CLEAR
Allows selected IR mask bits to be cleared. Data port bits D15_6
are applied to status register bits SR1S-6 (corresponding to
mask bits for I ~ _ o ) . Those data bits which are HI will clear
the mask bit, while those data bits which are LO will leave the
mask bit intact. Data port bits Ds -0 are ignored.
MICROCODED SUPPORT COMPONENTS 3-15
IllMBS IR MASK BITWISE SET
Allows selected IR mask bits to be set. Data port bits D1,_6 are
applied to status register bits SR1,_6 (corresponding to mask
bits for IR._o). Those data bits which are HI will set the mask
bit, while those data bits which are LO will leave the mask bit
intact. Data port bits D,_o are ignored.
DISIR DISABLE INTERRUPTS
Disables the execution of all further interrupts by clearing the
enable interrupt flas (SRv. External interrupts continue to be
latched.
NAIR ENABLE INTERRUPTS
Enables execution of interrupts by setting the enable interrupt
flag (SRz).
SUR SELECT LATCHED INTERRUPTS
Places the interrupt request latches in the latched mode for
interrupts IRs_I (SRo LO). Interrupts are latched if they are
valid at the appropriate clock edge. Interrupts IRs_, are latched
at the positive going clock edge while I ~ _ I are latched at the
negative going clock edge.
STIR SELECT TRANSPARENT INTERRUPTS
Places the interrupt request latches in the transparent mode
(SRo HI) for interrupts IRs_I. The interrupt request is only
valid while the external interrupt inputs are high. Interrupts are
still processed on the next cycle, so long as they meet the minimum
interrupt setup specification. Note that selecting transpareot
interrupting will clear any pending interrupts stored in the
interrupt latch.
SLRIVP WRITE SLR WITH D,_z,
ANDIVPWlTHD
ls
_
lz
Loads the 4-bit stack limit register (SLR) and the 4-bit interrupt
vector pointer (IVP) from the data port. This instruction also
clears the stack ovuflow interrupt request IR,.
For stack overflow detection, the active 60bit stack pointer
(SSP, LSP or GSp) is compared to a 60bit word comprised of
the 4-bit SLR (MSBs) and the two LSBs determined by the
instruction type, as follows:
'00' for subroutine stack push (PSDSS); or,
'11' for register stack push (PSDRS).
For example, if a stack limit of 3610 and positioning of the IVP
at IRV7 is desired, the value 'Oll1xxxxxxl00lxx' is provided at
the data port. Note that the SLR and IVP cannot be resd.
The interrupt vector pointer (IVP) addresses the vector file for
resding or writing interrupt vectors. To write interrupt vectors
IRV9_0, the IVP must first be initialized by SLRIVP. The
WRIV instruction (see above) is then used to write the interrupt
vector pointed to by the IVP, which is then incremented
automatically.
2.6 Relative AcIcIren Width Controls
The width control instructions allow reduction of microcode
when Jump Data Relative and Jump Subroutine Relative in
structions need less than the full, 160bit range. Use these in
structions to sign extend the 8, 12 or 160bit wide jump data
presented at the data port. The jump width may be selected by
the explicit instructions or by directly setting the status register
bits SRS_ 4 as described below. Any of these three instructions
3-16 MICROCODED SUPPORT COMPONENTS
will reset the Instruction Hold Control mode (see Misc. Instruc
tions - IHC, 2.7).
Note that selection of 8-bit width can be made with or without
IHC. For all relative jumps, the jump distance is the offset + 1.
REL16 SELECT 160BITRELATIVEJUMPS
Select the 160bit relative jump. This adds DI,_o at the data port
to the PC to obtain the jump address. The status bits SR'_4 are
set to '00'.
REL12 SELECT 12BIT RELATIVE JUMPS
Selects the jump data from DI1_
0
The offset is sign-e:xtended
allowing relative jumps in the range +2047 to -2048. The
status bits SR
S
_
4
are set to '11'.
REL8 SELECT8BITRELATIVEJUMPS
Selects the jump data from ~ -0. The offset is sign-e:xtended
allowing relative jumps in the range + 127 to - 128. The status
bits SR'_4 are set to '01'.
2.7 MiBceUaneoua lnatructions
CONT CONTINUE
Increment and outpUt the next location in microcode memory
without any other changes. Allows straight line microcode
execution.
IDLE DISABLE OUTPUTS AND JUMP PC
Places the address port into the high.impedance state, inhibiting
program counter (PC) increments. Useful in applications where
multiple sequencers share a common microcode address bus.
This instruction causes the ADSpI401 to behave as if the clock
had stopped. The IDLE instruction may be latched internally
by using IHC, freeing microcode for use by another device.
External interrupt requests must be inhibited during IDLE. If
interrupts are not inhibited, the ADSPI401 will attempt to
process an interrupt that goes active. However, it will be unable
to outpUt an interrupt vector because the IDLE instruction
places the address port in the highimpedance state; more im
portantly, it will set its IRIP flag, which will inhibit further
interrupt processing even after the IDLE state is exited.
Interrupts can be inhibited using the interrupt mask or the
DISIR instruction. While inhibited, interrupt requests will still
be latched in the interrupt latch.
DlC ENABLE INSTRUCTION HOLD CONTROL
Sets SRS_4 to '10' and redefines the function of IRI to allow a
subsequent instruction to be held for repeated execution, regardless
of the instruction port. Use of the IHC mode requires that the
mask bit for IRI be set. See Instruction Hold Control, appendix
4.1 for more details.
While in the IHC mode, asserting IRI HI (prior to the second
balf-cycle of any instruction) will hold that instruction and
disable all interrupts (although they continue to be latched)
until IRI is brought LO again (again, prior to the second balf-cycle
of any instruction).
It is recommended that IR. be dedicated to control of the IHC
mode (if needed). However, if it must also be used for subsequent
interrupting, then the CAIR instruction should be executed
before unmasking IR I (to clear the interrupt request resulting
from use of IR. as the IHC control).
Use of IHC is constrained to 8-bit relative addressing (see Relative
Address Width Controls, 2.6) and clearing IHC is accomplished
by executing any of the relative address width control instructions
(changing status register bits SRs_4).
WCS WRITE CONTROL STORE
Provides sequential addressing during microcode downloads to a
RAM based microcode store. The instruction may be interpreted
as:
JUMP DATA;
IF FLAG: DECREMENT Co AND CONTINUE UNTIL
INTERRUPTED.
Upon initiation of the WCS instruction, the sequencer outputs
the address found at the data port (that of the first instruction
to be downloaded). The external flag is then used to gate sub-
sequent sequential addressing for the download and decrementing
of counter Co. This action continues until an interrupt is detected
(from either a Co underflow, externally or the chip is RESET).
Instructions at the instruction port are Ignored during WCS,
until the interrupt or reset occurs.
The external flag allows synchronization of an external memory
with the sequencer. FLAG should be asserted HI as each new
J.l.Code word is made available for writing to ,..code memory.
Notes on Using a Writeable Control Store:
If a counter interrupt is desired, counter Co must be in-
itialized with two less than the length of microcode seg-
ment to be downloaded.
If counter interrupting is to be used to exit the WCS
mode, IRVo should be unmasked and initialized with the
address of the instruction to be executed upon WCS com-
pletion (see Interrupts, 1.4.3 for timing).
Since interrupting is used to exit the WCS mode, the last
address downloaded is pushed onto the SS stack as an in-
terrupt return address. However, because it is not actually
a return address, the SS should be popped immediately
by decrementing the SSP (DSSP) to clear it of this last
address.
Since FLAG is used to gate the download, it should not
become active until after the WCS instruction is executed.
See application note "Writeable Control Store using the
ADSP-1401."
ADSP-1401
3.0 SPECIFICATIONS
This section describes the ADSP-1401's performance parameters.
The Specifications Table lists the device's relevant electrical and
switching characteristics, while Figure 7 presents the corres-
ponding timing diagram.
. ...
CLOCK f------1 I
1 I
1 --I... I --11---'. I

'""""::;:jT--7,I
OUTPUT ADDRESS ;-1 ___ +I..JX 1 1 ><=J
-I t.., I-- I -j 1-... I
OUTPUT DATA I 1 c:::::I::i 'n. I I
--....I toDD I-- --I
I I

1 ---I 1-"" I --11--', I

1 1 I-;;;;;M 1 -I t-- '. I


ADDRESS PORT 1 I,J 1 1 'I
IDLE-TO-THREE I I '------.!
STATE 1 ---I '"u t--I --t I-- I
TTRPINFOR I I 1
THREE-STATE 1-1 ___ .!J
1
I. --j 'n" I I
ADDRESS PORT : 1 I ), c::::::J
l-i""t-" --I '" I-- 1
CLOCK I 1 I I
ISTRETCHED) I I
I I \. I,
TTRPINIJI
FORTRAP 1 I -I I-- 'm" I
OUTPUT ADDRESS 1V9 I
i--'m,,----I --l." I--
Figure 7. ADSP-1401 Timing Diagram
HIGH IMPEDANCE
Figure 8. Three-State Reference Levels
ORDERING INFORMATION
Temperature Package
Part Number Range Package Outline
ADSP-1401JN Oto + 70C 48-Pin Plastic DIP N-48A
ADSP-1401KN Oto + 70C 48-Pin Plastic DIP N-48A
ADSP-1401JP Oto + 70C 52-LeadPLCC P-52
ADSP-1401KP Oto + 70C 52-LeadPLCC P-52
ADSP-1401JD Oto + 70C 48-Pin Ceramic DIP D-48A
ADSP-1401KD Oto + 70C 48-Pin Ceramic DIP D-48A
ADSP-1401SD - 55C to + 125C 48-Pin Ceramic DIP D-48A
ADSP-1401TD - 55C to + 125C 48-Pin Ceramic DIP D-48A
ADSP-1401SD/883B - 55C to + 125C 48-Pin Ceramic DIP D-48A
ADSP-1401TD/883B -55Cto + 125C 48-Pin Ceramic DIP D-48A
MICROCODED SUPPORT COMPONENTS 3-17
------. --_. -------------
SPECIFICATIONS
1
RECOMMENDED OPERATING CONDITIONS
Parameter
Voo
Supply Voltage
TAMB
Ambient Operating Temp.
ELECTRICAL CHARACTERISTI CS
Parameter
VIH
Hi-Level Input Voltage
VIHC
Clock Input Hi-Level Input Voltage
VIL
Lo-Level Input Voltage
VOH Hi-Level Output Voltage
VOL
Lo-Level Output Voltage
IIH
H i ~ L e v e l Input Current, All Inputs
IlL
Lo-Level Input Current, All Inputs
10ZH
Three-State Leakage Current
10ZL
Three-State Leakage Current
100
Supply Current
100
Quiescent Supply Current
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ....
Input Voltage . . . . . . . . . . . . .
Output Voltage Swing ........ .
Operating Temperature Range (Ambient) .
Storage Temperature Range ...
Lead Temperature (10 Seconds)
ESD SENSITMTY
Test
Conditions
Voo = max
Voo=max
Voo = min
Voo=min,loH= -lmA
Voo=min,loL = 3mA
Voo = max, VIN=5V
Voo=max, VIN=OV
Voo = max, VIN=max
Voo = max, VIN=O
max clock rate, TTL inputs
V
IN
= 2.4V
-O.3V to 7V
-0.3V to Voo
-0.3V to Voo
- 55C to + 125C
-65C to + 150C
...... 300C
J&KGrades
Min Max
4.75 5.25
0 70
J&KGrades
Min Max
2.0
3.0
0.8
2.4
0.6
10
10
50
50
90
50
The ADSP-I401 features proprietary input protection circuitry. Per Method 3015 of MIL-STD-883,
the ADSPI40 I has been classified asa Class I device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance degra-
dation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and
discharge without detection. Unused devices must be stored in conductive foam or shunts, and the
foam should be discharged to the destination socket before devices are removed. For further informa-
tion on ESD precautions, refer to Analog Devices' ESD Prevtllltion Manual.
3-18 MICROCODED SUPPORT COMPONENTS
S&TGrades
2
Min Max Unit
4.5 5.5 V
-55 125 C
S&TGrades
2
Min Max Unit
2.0 V
3.5 V
0.8 V
2.4 V
0.6 V
10 fLA
10
J.LA
50 fLA
50
fLA
115 mA
65 mA
WARNING! ~
~ ~ ~
ADSP-1401
SWITCHING CHARACTERISTICS
3
JGrade KGrade SGrade
2
Parameter Min Max Min Max Min Max Min
tHI
Clock HI 50 40 60 50
tw ClockLO 40 30 50 40
tiS
Instruction Setup Time 36 30 45 40
tDS
Data Setup Time 10
*
IS IS
tlH
Input Signal Hold Time 3
* * *
tAD
Address Delay4 (C = 50pF) 35 25 45
tAH
Address Hold Time 3
*
1 1
toDD
Output Data Delay (C = 30pF) 50 35 60
toms
Output Data Disable Time 20 15 25
tlFSM
Input Flag Setup Time (IRO masked) IS 10 20 15
tlFSU
Input Flag Setup Time
(no constraints) 30 26 35 30
t
urRS
Upper Interrupts (IRs_s) Setup Time 30 25 35 30
tLlRS
Lower Interrupts (IR4_1) Setup Time 20 IS 25 20
tTSS
Three-State (TTR) Setup Time 10
*
15 IS
tTSOV
Three-State (TTR) Overlap Time
(With Trap) 13 13 5
tTSE
Three-State (TTR) Disable Delay 20 IS 25
tlOu
IDLE-to-Three-State Disable Delay 20 15 25
tTROV
Trap (TTR) Overlap Time
(With Three-State) 10 8 10
tTRAD
Trap (TTR) to Address Delay 60 45 70
NOTES
*Specifications same as J grade.
I All specifications are over the recommended operating conditions.
's and T grade parts are available processed and tested in accordance with MILSTD883B. The processing and test methods used
for S/883B and T/883B versions of the ADSPI401 can be found in Analog Devices' Military Databook.
'Input levels are GND and 3.0V. Rise times are Sns. Input timing reference levels and output reference levels are l.SV
except for three-state reference levels, which are shown in Figure 8. For capacitive loads greater than lOOpF,
we recommend the use of external buffers.
'Address delays may be derated from the specified 50pF test loading shown in Figure 12 by adding 7ns/SOpF for
increased capacitive loading,
Specifications subject to change without notice.
10L
Voo
TO
OUTPUT 0-.... -4( +l.SV
INPUT o - _ ~ _ "
PIN
3pF
Voo
TGrade
2
Max
35
45
20
5
20
20
10
55
OUTPUT
Figure 9. Equivalent Input
Circuit
Figure 10. Normal Load for
ac Measurements
Figure 11. EquivalentOutput
Circuit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MICROCODED SUPPORT COMPONENTS 3-19
4.0 APPENDICES
4.1 Instruction HolcI Control (lHC)
The IHC function allows extema1 microcode width to be reduced
by allowing the 1401's microcode field to be shared with another
device. This sharing is accomplished by temporarily latching an
instruction that is used repetitively within the ADSP-14O 1 and
re-directing its microcode to a different device. Control of the
latching is accomplished by the IHC instruction, which re-assigns
the function of interrupt signal IR" becoming the latchlun1atch
control line.
To use this mode, execute the IHC instruction, which sets
status register bits SRS_4 to '10'. Interrupt line IRI now controls
the instruction hold mode (not interrupt), so IRI must be masked.
The shared signal, IRs (recall, IRs_s and IR._1 share the same
pins), is still used normally, since it is active during clock low.
To initiate an instruction hold, execute the instruction to be
repeated, while asserting IRl (HI) prior to the clock falling edge
of the same cycle. For so long as IRl is kept high (on the falling
edge of the clock), the instruction will repeat. All interrupts are
automatically disabled while the instruction is held.
When IRI is needed for interrupts (instead of controlling the
instruction hold mode) the IHC mode may be disabled by:
executing one of the relative jump width control instructions;
or, by changing status register bits SRS_4 directly. Prior to
unmasking IRh execute the CAIR (clear all interrupts) instruction
to clear the interrupt latch.
4.2 ProcrammiIII Examples
The following examples are given to illustrate some fme points
of programming the ADSP-1401.
4.2.1 Jump Register (See Figure 13a)
In this example, three jump registers (R3_1) are loaded with
external data and one CRo) is loaded with the program counter,
enabling a jump to the top-of-stack.
Current Instruction Output
Address ElIecuted AcIdreu Comments RSP
20 PSDRS 21 PushR3 S7
21 PSDRS 22 PushR2 S6
22 PSDRS 23 PushRl SS
23 PSPC 24 Push PC (Ro = 24) S4
24 Start of Loop . . . 2S
30
31 JRCCRo) 32/24 Cond. Jump to
Rol=24
32124
4.2.2 Return from Interrupt with Pending Interrupt (See Figure
13b)
This example shows the program flow when two interrupts
occur in the same cycle or an interrupt is latched while another
interrupt is being executed. The "Return from Interrupt" in-
struction CR TNIR) will execute one instruction of the mainline
routine before servicing a pending interrupt since interrupts are
not re-enabled until the end of the cycle. Here, IV 7 = 60 and
IV3=21.
3-20 MICROCODED SUPPORT COMPONENTS
COz:Z15+6
23
PUSH PC
24
,
LOOP
31 TRUE .TlMES
FALSE
32
..
... ./1," 1R7
V-; ItOUnNE

A. JUMP REGISTER I. PENDING INTERRUPT ON fITNIR
61 SUBRTN
..

93
13 ..
14 Y4
: SAVE
: IR7RounNE
..
IR6
: RounNE
1& j REStORE
1& , --.........., 128
29
c INTERRUPTONRTN D. INTERRUPTUINNOGLOBALREGS
150 IRfIOUTINE
CONT
PUSHea 150 (PUSHa91
IOVRFLI 87. .A 151
.. 0
,
.
,
SUBROUnNE
VIRI!
PUSH: !
E. THREEPUSHESONOVAFL
..
flTNlfI :
.. .
.. RTN
F INTERRUPT ON JUMP SUBROUTINE
Figure 13. Programming Examples
Current Instruction Output
Address &ecuted Addre .. Comments
89 90
90 91 Interrupts 17 & 13 valid.
91 60 IV7output. Instruction 91
still executed.
60 CONT 61 92 is pushed on stack.
61 62
81 RTNIR 92 92 popped and interrupts
re-enabled.
92 21 IV 3 output. Instruction 92
still executed.
21 CONT 22 93 pushed on stack.
22 23
28 RTNIR 93 93 is popped from stack.
93
4.2.3 Interrupt on a Return from Subroutine (See Figure 13c)
If an interrupt occurs on a subroutine return, no instructions in
the main program are executed prior to servicing the interrupt
routine. Here, IVs=20.
Current Instruction Outpnt
Addres. ElIecuted Addre .. Comments
91 92
92 JSR 6S Jump to 6S. 93 pushed.
6S 66 IRs becomes valid.
66 RTN 20 IVs addressoutput.93
popped.
20 CONT 21 93 pushed.
29 RTNIR 93 93 popped.
93
4.2.4 Interrupt Routine usina Global Registers (See Figure
13d)
Current Instruction Output
Address mecuted Address Comments
12 13 Mainline ...
13 14 IR7 occurs here.
14 CONT 93 OutputIV7.
93 PSSR 94 Push status register.
94 PSCNTR(C3) 95 Save previous values . . .
95 PSCNTR(C1) 96
96 PSGSP 97
97 WRSR 98 Write new values ...
98 WRCNTR(C3) 99
99 WRCNTR(C1) 100
100 WRRSP 101
101 102 Begin interrupt servicing . .
123 124 End of interrupt service
routine.
124 PPGSP 125 Pop in reverse order of
pushes ..
125 PPCNTR(C1) 126
126 PPCNTR(C3) 127
127 PPSR 128
128 RTNIR 15 Jump back to mainline.
15 16
4.2.5 Three Stack Pushes on Stack Overflow (See Figure Be)
The four register buffer between the subroutine stack and the
register stack will be filled with three values whenever the stack
push that caused the overflow is followed by another instruction
that causes a stack push. The second stack push occurs since
the instruction that is interrupted (the second stack push) must
complete internally to preserve the correct state of the ADSP-1401
after the interrupt. The third push occurs to provide the return
address to the main program. The sequence is illustrated below.
Assume that the address of the stack overflow service routine
(IV9) is at 150.
Current Instruction Output
Address mec:uted Address Comments
86 87
87 PSCNTR(Co) 88 The push causes a stack
overflow.
88 PSCNTR(C1) 150 The interrupted instruc-
tion executes.
150 CONT 151 89 is pushed onto the stack.
151
4.2.6 Interrupt on Jump Subroutine Instruction (See Figure
13f)
Current Instruction Output
Address mecuted Address Comments
86 87 Interrupt occurs to loca-
tion 150
87 JSA(4O) 150
150 CONT 151 40 Pushed on stack
160
161 RTNIR 40 Return from interrupt
40 41
ADSP-1401
4.3 Use of RAM by Multiple Subroutines
This diagram (Figure 14) shows the state of RAM after three
nested subroutine calls.
Prior to the first subroutine call, the RSP was used to preload
the bottom portion of the RAM with indirect jump addresses.
Next, global jump registers were preloaded. In the mainline
program, ouly global jump registers are used.
SUBROUTINE
STACK
f-----=----\ t-- SUBROUTINE#1
f-----"'-----\ 1-- SUBMOUTINE#2
r- SUIIl'IOUTINEIl
{ '" - ,",""u,,,..,
t'"'"ou".,,,


Figure 14. RAM Status after Subroutine Calls
The instruction calling the first subroutine pushes the return
address of the main program onto the subroutine stack. The
values of counters 1 and 3 are also pushed onto the stack to free
counters 1 and 3 for use in subroutine # 1. The GSP is saved
since different routines will require different GSPs. Similarly,
the status register of the main program is saved. As shown,
routine # 1 uses both global and local jump registers. It selects
the GSP or LSP at the appropriate times in the routine by executing
SGSP or SLSP instructions.
Routine #2 saves the return address, some counters, and the
GSP for routine # 1. Since no local registers are used in routine
#2, none are loaded.
Routine #3 saves the return address and the status register.
Since the GSP and counters are not used in this routine, they
are not saved. After the new status register is loaded (selecting
the LSP), local registers are pushed onto the stack.
4.4 Bus Drive Considerations with the WordSlice Family
The various members of Analog Devices' Word-Slice family are
designed with high-speed drivers on all output pins. This capability
means that large peak currents may pass through the ground
and V DO pins when all the bus lines are simultaneously charging
their load capacitance from LO to HI, or vice versa.
To calculate the peak current for a typic:a1 family member (such
as the ADSp1401 Program Sequencer), we assume that all
output drivers are switching from a HI to a LO state. From a
MICROCOOED SUPPORT COMPONENTS 3-21
fall time and capacitance measurement, we can determine that
the peak current in each driver is:
Ipcak =CIoo,rAV/At,
where AV/At is the initial slew rate.
In the case of the program sequencer, for an external load capaci-
tance of SOpF and a measured slew rate of 0.6V/ns, the peak
current will be about 3OmA. Since there are 16 such drivers, the
total peak current may ,pproach 480mA!
4.5 MnemoDics and Opcodes
Opcode bits "ii" select the relevant register (R3_ 0) and/or counter
(C3_ 0). Opcode bits u cc" select the condition to be applied:
'00' UNCONDITIONAL
'or NOT FLAG
'10' FLAG
'11' SIGN
The SIGN condition is precluded from instructions prefixed
with "*".
MaemODic Opcode 0._,,) Description
Jump and Branch Ins .... c!io ... :
JPCOF 001 0101 IF FLAG: JUMP PC (self)
JPCNF 011 0101 IF NOT FLAG: JUMP PC
(self)
JTWO IOlecOI IFCOND:JUMPPC+2(skip)
JDA III cell IF COND: JUMP DATA,
ABSOLUTE
JDR III eeOI IF COND: JUMP DATA,
RELATIVE
JDI 101 eclO IF COND: JUMP DATA,
INDIRECT
JDRST 100 lli i IF SIGN OF C,: JUMP DATA,
C.<=R,; ELSE, C,<=C.-I
'JRC 110 eei i IF COND: JUMP R,
JRS 110 lli i IF SIGN OF C,: JUMP R"
C,<=C,-I
JSA III eeOO IF COND: JUMP SUB,
ABSOLUTE
JSR III ee 10 IF COND: JUMP SUB,
RELATIVE
RTN 101 cell IF COND; RETURN FROM
SUB
'BRANCH 100 eci i IF SIGN OF C,: JUMP R,;
ELSE, C,<=C,-I, IF COND:
Stack Operations:
Sub .... ri .. Slack
PSDSS 001 1110
PPSSD 011 11 JO
WRSSP 000 1110
RDSSP 010 1100
DSSP 000 00 I 0
R.,uler Slack
SGSP 0000111
SLSP 0000110
RDRSP 0101111
WRRSP 000 II 00
PSPC 0100011
PSGSP 0000101
PPGSP 000 0 I 00
PSDRS 0011111
PPRSD 011 1111
AIRSP 010 10i i
SIRSP 000 1111
S4RSP 011 1100
JUMP DATA
PUSH DATA ONTO SS
POP SS TO DATA PORT
WRITE SSP
READ SSP
DECREMENT SSP
SELECTGSP
SELECT LSP
READRSP
WRITERSP
PUSH PC ONTO RS
PUSH GSP ONTO SS
POP GSP FROM S8
PUSH DATA ONTO RS
POP RS TO DATA PORT
ADDiTORSP
SUBTRACT I FROM RSP
SUBTRACT 4 FROM RSP
3-22 MICROCODED SUPPORT COMPONENTS
The internal ground and supply lines may undergo a large dis-
turbance during this transition unless the ADSP-1401 is tied to
a solid ground plane and good high frequency deooupling is
used (O.IJAP ceramic between GND and VDD as close as possible
to the device). Otherwise, is it possible that internal data in the
ADSP-I401 may be lost.
SR.
SR,_.
IRoMsskBit
Relative Jump Width Selection:
'00' = 16-bit telstive address width
'01' = 8bit width
'IO'=IHC Mode (8bit width)
'11'= 12bit width
Select GSP/LSP
EnsbleiDissble Interrupts
Set/Clear Sign Bit
Select TransparentILatched Interrupts
Status Register Operations:
RDSR 010 1110 READSR
WRSR 001 1100 WRlTESR
PSSR 0100001 PUSH SR ONTO S8
PPSR 0100010 POP SR FROM S8
Counter Operations:
WRCNTR 011 10ii WRITEC,
CLRS 0010100 CLEAR SIGN BIT
SETS 011 0100 SET SIGN BIT
PSCNTR 000 10i i PUSH C, ONTO SS
PPCNTR 001 10i i POP C, FROM SS
DCCNTR 011 OOi i DECREMENT C.
IPCDEC 101 ceOO IF COND: DECREMENT Co
Interrupt Control:
CCIR 0010001 CLEAR CURRENT
INTERRUPT
CAIR 0000001 CLEAR ALL INTERRUPTS
RTNIR 0000011 RETURN FROM
INTERRUPT
RDiV 010 1101 READ INTERRUPT VECTOR
ANDINCREMENTIVP
WRIV 000 1101 WRITE INTERRUPT
VECTOR AND INCREMENT
IVP
IRMBC 001 0011 IR MASK BITWISE CLEAR
IRMBS 0010010 IR MASK BITWISE SET
DlSIR 001 0110 DISABLE INTERRUPTS
ENAIR 011 0110 ENABLE INTERRUPTS
SLiR 001 0111 SELECT LATCHED
INTERRUPTS
STIR 011 0111 SELECT TRANSPARENT
INTERRUPTS
SLRIVP 001 1101 WRITE SLR< = 0,_2 AND
IVP< = D15 _ 12
Relative Address Width Controls:
RELl6 0100100 SELECT I6-BIT RELATIVE
ADDRESSING
RELI2 010 0111 SELECT 12BIT RELATIVE
ADDRESSING
REL8 010 0110 SELECT aBIT RELATIVE
ADDRESSING
Miscellaneous Inatru.tiob.'
CONT 000 0000
IDLE 001 0000
IHC 0100101
WCS 0100000
CONTINUE
IDLE
ENABLE INSTRUCTION
HOLD CONTROL
WRITE CONTROL STORE
ADSP-1401
ADSP-1401 PIN CONFIGURATIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DIP
D-48A
N-48A
FUNCTION PIN
07
08
09
010
011
012
013
014
015
EXIR1
EXIR2
GNO
EXIR3
EXIR4
TTR
V15
V14
V13
V12
V11
V10
V9
V8
V7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PLCC
P-52
FUNCTION PIN
07 52
08 51
09 50
010 49
011 48
012 47
GNO 46
013 45
014 44
015 43
EXIR1 42
EXIR2 41
GNO 40
EXIR3 39
EXIR4 38
TTR 37
V15 36
V14 35
V13 34
GNO 33
V12 32
V11 31
V10 30
V9 29
V8 28
V7 27
FUNCTION
06
05
04
03
02
01
00
ClK
FLAG
16
15
Voo
14
13
12
11
10
VO
V1
V2
V3
V4
V5
V6
FUNCTION
06
06
04
03
02
01
GNO
00
ClK
FLAG
16
15
Voo
14
13
12
11
10
VO
GNO
V1
V2
V3
V4
V5
V6
MICROCODED SUPPORT COMPONENTS 3-23
----._--------

3-24 MICROCODED SUPPORT COMPONENTS

WDEVICES
FEATURES
16-Bit Microcode Addressing Capability
Look-Ahead Pipeline
Extensive Interrupt Processing with Eleven On-Chip
Interrupt Vectors
Four Event Counters to Support Looping
Absolute, Relative and Indirect Addressing
SOns Cycle Time
64-Word RAM for Storing:
Subroutine Linkage
Jump Addresses
Counters
Status Register
1IJ.m CMOS Technology
84-Pin Grid Array Package
GENERAL DESCRIPTION
The ADSP-140Z Program Sequencer is an instruction-
compatible upgrade to the ADSP-l40l. It can be used with high
speed arithmetic units and provides many features to simplify
the design of microcoded systems. Among the devices it sup-
ports are the ADSP-3Z12 Floating-Point Multiplier, the ADSP-
b
a
'.. FLAG;. FSEL,.

eo"
Word-Slice
Program Sequencer
ADSP-1402 I
Word-Slice Microcoded System with ADSP-1402
3222 Floating-Point ALU and the ADSP-3128A Register File.
The ADSP-1402 is functionally identical to the ADSP-I401, ex-
cept for the changes deseribed in this section. A block diagram
of the ADSP-!402'is shtlwn below. For a detailed description of
the architecture and'instrUction set of the ADSP-1402, see the
W1mt-Sliae User's Manual and the ADSP-1401 Data Sheet.
Yuo
Addreu
Po"
ADSP-1402 Block Diagram
is a trademark of Analog Devices, Inc.
is a registered trademark of Analog Devices, Inc.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
MICROCODED SUPPORT COMPONENTS 3-25
The ADSP-1402 is a high speed microprogram controller opti-
mized for the demanding sequencing tasks found in digital
signal processors and general purpose computers. In addition to
high speed and large addressing range (64K of program mem-
ory), this Word-Slice component has unique features that make
it highly versatile:
On-chip storage and control of ten prioritized and maskable
interrupts plus a nonmaskable trap,
Four decrementing event counters,
Absolute, relative and indirect addressing capability,
Download capability (writeable control store) and
A dynamically reconfigurable 64-word RAM.
The ADSP-1402 microprogram sequencer's main task is to
provide the appropriate microprogram addressing to support
programming requirements, such as looping, jumping, branch-
ing, subroutines, condition testing and interrupts. An internal
Look-Ahead pipeline, controlled by both phases of the clock,
allows the ADSP-1402 to satisfy these requirements at very high
speed.
During each microinstruction, the ADSP-1402 monitors the
conditions and instructions to determine the next microprogram
address. This address can come from one of several sources: the
stack, the jump address space in the on-chip RAM, the data
port, the interrupt vectors or the microprogram counter, In all
cases, the next address is available in a single cycle. An ell:ten- '
sive set of conditional instructions is also "available, including
jumps, branches, subroutines, interrupts and writeable control
store. Eight multiplexed flag inputs can be used as external con-
ditions for these instructions.
The ADSP-1402's internal 64-word RAM is user configurable
into three regions: subroutine stack, register stack and indirect
jump address space. The subroutine stack is used for linking
interrupts and subroutines and, during their execution, allowing
the storage of system states. The register stack can be used to
store sets of jump addresses; each set can be associated with a
particular level of interrupt or subroutine (both local and global
stacks are provided). Indirect jump capability is also supported,
addressing for which is provided at the data port.
Interrupts are handled entirely on chip. The ADSP-1402's inter-
nal interrupt control logic includes registers for eight external
(user) interrupt vectors, a mask register and a priority decoder.
Two additional vectors are reserved for internally generated in-
terrupts resulting from counter underflow and stack limit viola-
tion, and a special vector is provided for the nonmaskable trap
interrupt. A stack limit violation is caused by stack overflow,
underflow or collision. A mechanism is provided for recovering
from stack violations. Trap interrupts have the highest priority
of all interrupts, and the stack limit violation interrupt has the
second highest priority.
The ADSP-1402's four decrementing 16-bit counters are used to
track loops and events. These counters generate a signal when
negative. This negative condition is available to several condi-
tional instructions and can also trigger an internal interrupt.
CHANGES FROM THE ADSP1401
TTR Input
The ADSP-140 I TTR (Trap/Tristate/Reset) input is eliminated
in the ADSp1402. In its place are separate RESET and TRAP
control pins. The tristate function is implemented with the the
IDLE pin as described under Idle and Halt, below.
Reset
The default reset function in the ADSp1402 is similar to that of
the ADSP-1401. While RESET is La and IDLE is HI, the
ADSP-1402 outputs H#OOOO on its address port. When RESET
goes HI, the address port remains at H#OOOO for one clock
cycle (the first cycle of normal operation). As with the ADSP-
140 I, the first ADSP-1402 instruction must be a CaNT
instruction.
The ADSP-1402 also provides an alternate reset function in
which the address port is placed in a high impedance state. If
the IDLE input is asserted La during reset, the address port is
tristated rather than outputting H#OOOO. Asserting IDLE dur-
ing reset does not affect internal operation, only the address
port. When RESET goes HI, the ADSp1402 outputs H#OOOO
for one clock cycle.
Boot (WCS)
The ADSP-1401 and ADSP-1402 implement a WCS (Writeable
Control Store) instruction. This instruction places the ADSP-
1401 or ADSP-1402 in a mode in which an active FLAG input
increments the program counter (PC), decrements the Co
count<:r and outputs the PC to the address port. This operation
is used to synchronize address sequencing for downloading mi-
crocode from a host. The usual way to exit this mode is by an
interrupt, from either an external interrupt or the internal
counter underflow (of Co in this case).
The ADSP-1402 also provides a pin that allows external hard-
~ a r e control of a download. The BOOT input of the ADSP-
1402 controls the operation for downloading microcode in much
the same way as the WCS instruction. The boot operation, al-
though slightly more restricted compared to the WCS operation,
requires no external circuitry.
Note: IDLE must be HI and TRAP must be LO while the
boot function is being used. RESET must be active when
BOOT is asserted and remain active until BOOT is
deasserted.
In the cycle that BOOT is asserted, the ADSP-1402 outputs
H#OOOO on the address port and sets the PC to H#OOOO. When
FLAG
o
is asserted, the PC is incremented and its new value is
output on the address port. The ADSP-1402 remains in this
mode until the BOOT pin is deasserted. Thus, no interrupt is
required to end the download.
The system clock must be stable and RESET must be asserted
for a minimum number of cycles before BOOT is asserted and
after BOOT is deasserted. IDLE must be HI and TRAP must
be LO for the entire time that BOOT is asserted. When BOOT
is active, FLAG
o
is edge-sensitive (therefore, it cannot be as-
serted more than every other cycle). FLAGo must also meet
minimum setup and hold times.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-26 MICROCODED SUPPORT COMPONENTS
Trap
The ADSP-I402 trap function is controlled by the TRAP input.
The TRAP signal must be asserted at least tTS before the next
rising clock edge and must be held at least tm after the rising
clock edge. In addition, TRAP must not change state (HI or
LO) tTS before or tTH after the rising clock edge, and it must
meet a minimum pulse width specification.
The nonmaskable TRAP input on the ADSP-I402 has a dedi-
cated interrupt vector (IV 10) that is separate from the (stack
over/underflow) vector (unlike the ADSP-I40I, in which Trap
and share the same vector). As with the ADSP-I40I, the
TRAP signal may require a clock skip to allow time to fetch a
new instruction. A block diagram of an example circuit for im-
plementing a clock skip is shown in Figure 1. TRAP aborts the
current instruction and pushes its address onto the subroutine
stack.
I
Microcode
Memory
ADSp1402
Interrupt In Progress (IRIP)
The ADSP-I402 has an internal Interrupt In Progress (lIP) bit
that indicates when it is processing an interrupt The
ADSP-I402 also has an internal Trap In Progress (TIP) bit that
indicates when a trap is being processed. The IRIP output flag
is the logical OR of the lIP and TIP bits.
If TIP is set, the CCIR (Clear Current Interrupt) and RTNIR
(Return From Interrupt) instructions reset TIP without affecting
lIP. If TIP is not set, however, then executing one of these in-
structions resets lIP. Executing the CAIR (Clear All Interrupts)
instruction resets both TIP and liP. Thus, unlike in the ADSP
140 1, a trap service routine can be nested inside an interrupt
service routine; the return from the trap service routine will not
eliminate the Interrupt In Progress status.
Flag Inputa
I I

,
The ADSP-I402 has eight external flag inputs (FLAG
7
-o)' These
eight input flags are multiplexed on-chip into one signal that is
equivalent to on the ADSP-I401. Three exter-
nal control. bit. '* of the eight input flags. The multi
flag sjgna/. is'iatched during clock HI and transparent
", 'dUritls:clsck LO. During a Boot or Writeable Control Store op-
: 'eration, the automatically selects FLAG
o
.
, '
Idle alICi'Hali, ' ,
"
:
-
- Y15.0
ADSp1402
Program Sequencer
ClK TRAP
,
-
"
;"', 'fhe'iDSP-l40Z has two controls for stopping internal opera-
, iiQu, One which tristates the address and data ports (IDLE) and
one whiah does not (HALT). Both perform functions similar to
that of the ADSP-I401 IDLE instruction, which is functional
':'"but obsolete 'on the ADSP-I40Z.
Exception

Rest of System
I
ClockOut
Clock Generator
Stop Clock
Figure 1. Example Clock Skip Circuit
External Interrupta
The eight external interrupts of the ADSP-I402 are input on
eight separate pins, EXIRs-l (whereas the eight external inter-
rupts of the ADSP-I401 are time-multiplexed into four inputs).
All external interrupts are latched on the rising edge of the
clock. The ADSP-I402 outputs the interrupt vector address in
the same clock cycle in which the interrupt is latched.
Interrupt masking and enabling in the ADSP-I402 is the same
as in the ADSP-I401. Interrupts on the ADSP-I402 are priori-
tized in descending numerical order; Trap has the highest prior-
ity, has the next highest, and IRa has the lowest.
Note: The IDLE instruction must not be input to the ADSP-
1402 with either IDLE or HALT asserted; otherwise, the
ADSP-I402 will not function properly.
The IDLE pin is useful for implementing multitasking in sys-
tems with multiple sequencers. IDLE removes the ADSP-I402
from the address and data buses, allowing another sequencer to
drive them.
IDLE requires a minimum setup and hold time to the rising
clock edge. When IDLE is asserted, the ADSP-I402 fmishes
executing the current instruction, and then the internal clock of
the ADSP-1402 is stopped, freezing internal operation. At the
next rising edge of the CLK input, both the address port and
the data port are tristated, and the next instruction is latched
but not executed. Fetching and execution of new instructions
are inhibited until IDLE is deasserted. Interrupts are not
latched, and traps are ignored as well. When IDLE is
deasserted, normal operation continues at the next rising clock
edge with the previously latched instruction.
The ADSP1402 HALT input can be used to stretch the inter-
nal ADSP-I402 clock. HALT is primarily intended to imple-
ment wait states or to be used in conjunction with TRAP to
handle exceptions.
This information applies to a product under development. Its characteristics and speCifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless othelWise agreed to in writing.
MICROCODED SUPPORT COMPONENTS 3-27

HALT stops internal operation without tristating the address
and data ports. It halts internal operation at the next rising edge
of the CLK input after HALT is asserted. The address port and
the data port are not updated; both ports maintain the states
current at a time when HALT is asserted. No new instruction is
latched. During HALT, fetching and execution of new instruc-
tions are inhibited. Interrupts are not latched; however, unlike
during IDLE, active TRAP inputs are recognized and pro-
cessed. The ADSP-1402 latches and executes its next instruction
and updates the address and data ports at the next rising clock
edge after HALT is deasserted.
Repeat
The REPEAT input causes the ADSP-1402 to repeat the next
instruction (the one being set up at the same time as REPEAT)
for one clock cycle. This input performs the same function as
the ADSP-1401 IRI input in IHC (Instruction Hold Control)
mode. The ADSP-1402 repeats the instruction as long as
REPEAT stays asserted.
Interrupts cannot be serviced while the REPEAT pin is active
because the ADSP-I402 ignores its instruction port; however,
interrupt requests are still latched. Because TRAP is not
latched, it should not be used while REPEAT is active.
The REPEAT input is dedicated to the repeat function; the
ADSP-1402 has no IHC mode. In the ADSP-1401, the IHC in-
struction activates the IHC mode and selects an 8-bit relative"
jump offset width. For compatibility, the in
ADSP-1402 also selects an 8-bit ju1IlP ciitset:width.(i!he '
same effect as the REL8 instruction) . " ,1' . " '.' > '
Data Port .. " '::' , "
The ADSP-1402 has a full-cycle data port lia!c;'
cycle data port of the ADSP-1401. Instructions that wrlte data
out of the ADSP-1402 drive the bus for a full cycle. Instructiorill
that read data into the ADSP-1402 require data to be valid a "
specified time before and after the clock rising edge. To avoid
bus contention, therefore, an ADSP-I402 instruction that out-
puts data on the data port cannot be followed by an instruction
that reads data from the port; a NOP cycle must occur between
the two instructions.
The data port output drivers are tristated unless a data output is
being performed.
Power and Ground
The ADSP-1402 has nine power pins and nine ground pins.
PIN LIST
Name Type Function
D15- 0
Bidirectional Data Port
Y15-O
Output Address Port
IRIP Output Interrupt in Progress
16-0 Input Instruction Port
EXIR
8
_
1 Input External Interrupts
FLAG
7
_
o
Input Flags
FSEL2-O Input Flag Select
CLK Input Clock
TRAP Input Trap
RESET Input Reset
IDLE Input Idle
REPEAT Input Repeat Instruction
HALT Input " Halt
BOOT
tnpUi,
Boot (WCS) Mode
,,' \;
"
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Analog Devices assumes no obligation regarding future manufacture unless otherwise agreed to in writing.
3-28 MICROCODED SUPPORT COMPONENTS
r.ANALOG
WDEVICES
FEATURES
16-BIt Addr ..... with Higher Precision Options
30ns Address Output Delay @ 11.1 MHz Operation
Look-Ahead Pipeline
Versatile Addressing Hardware:
30 16-Bit Registers
16-BIt ALU with Left/Right Shift lit Carry 110
Comparator
Bit Reverser
Dual Ports
Powerful Single-Cycle Looping Instructions
375mW Maximum Power Dissipation with
CMOS Technology
48-Pin DIP. 52-Lead PLCC
GENERAL INFORMATION
The ADSP-1410 is a fast, flexible address generator optimized
for digital signal/array processors and other high-performance
computers. This low-power CMOS device rapidly generates the
data memory addresses required by routines such as digital
filters, FFTs, matrix operations, and DMAs. With its 16-bit
architecture, registers, dual ports, and speed, this Word-Slice
component improves performance and reduces board space
substantially relative to bit-slice solutions.
The ADSP-1410's architecture features a 16-bit ALU, a com-
parator, and 30 16-bit registers. The registers are organized into
four files: sixteen address (R) registers, six offset (B) registers,
four compare (C) registers, and four initialization (I) registers.
The ADSP-1410 rapidly executes key address generating opera-
tions. In a single instruction cycle, the device can:
output a 16-bit memory address;
modify this memory address; and,
detect when the address value has moved to or beyond a
pre-set boundary and conditionally loop back to the
top of a circular buffer.
Consequently, circular buffers and modulo addressing for data
memories can be implemented without overhead.
The ADSP-1410's IO-bit microcode instructions include com-
mands for looping, register read/writes, internal data transfers,
and logical/shift operations. Instructions are normally supplied
from an external source. However, an internal Alternate In-
struction Register (AIR) can provide the instruction under external
control, allowing microcode to be conserved in many
applications.
Look-Ahead i. a trademark of Analog Device., Inc.
Word"Slice is a registered trademark of Analog Devices, Inc.
Word-Slice
Address Generator
ADSP-1410 I
WORD-8UCE MICROCODED SYSTEM WITH ADSP1410
The ADSP-1410 has a 16-bit address (Y) port for outputting
addresses and a 16-bit data (D) port for I/O between internal
and external registers. Also, an internal path allows external
data, provided via the D port, to serve as an ALU source and/or
to be directly output over the Y port for a DMA capability.
Double-precision (30-bit), single-cycle addressing can be per-
formed by cascading two ADSP-141O's, with the MSB of each
chip's D and Y port dedicated to interchip communication.
Alternatively, a single AG can provide double-precision addresses
at a rate of one per two clock cycles.
The Look-Ahead pipeline eliminates the need for an external
microcode pipeline register by internally latching instructions
and addresses; microcode bits may be directly routed to the
ADSP-1410 from microcode memory. Logically, the Look-Ahead
pipeline is split into two halves: the first, located at the instruction
(and data) port; and the second, located at the address port.
Each half of the pipeline (input vs. output) has a transparent
latch which operates out of phase with the other: the address
latch is transparent during the first half of the cycle (clock HI),
while the input latches (instruction and data) are transparent
during the second half ofthe cycle (clock LO). This complementary
arrangement allows new instructions to be decoded (in preparation
for the following cycle) while the program address for the current
cycle is held steady.
MICROCODED SUPPORT COMPONENTS 3-29
ADSP1410 OVERVIEW
Digital Signal Processing (DSP) and array processing systems
require fast, flexible address generation cir\:uitry. An Address
Generator (AG) supplies the address of a location in data or
coefficient memory. The value residing at the specified address
is fetched and fed to an aritbmetic unit for processing. The AG
must then modify the address pointer in anticipation of the next
data fetch. For algorithms that repetitively loop through data
buffers, the AG may need to compare the address to a buffer
end and conditionally loop back to the top of the buffer. Finally,
to maximize throughput, an AG must perform its addressing
tasks rapidly and without overhead.
With the ADSP-1410, 16-bit pointers to memory are stored in
an address (R) register file. Since an AG must track several
pointers aincurrently, sixteen R registers, denoted R,., are pr0-
vided. Ifwe denote Y as the address port, the operation ''Y - R,."
corresponds to the AG supplying an address from register R,..
After supplying an address, the AG must update the pointer for
the next memory fetch. The updating may be as simple as an
increment but, more generally, involves adding or subtracting
an arbitrary offset value. Also, algorithms generally access several
different offset values. To this end, the AG provides six offset
ADDRESS SOURCES
- Sixteen internal R registers
- External data provided over the 0 port
OFFSET SOURCES
- Six internal B registers
- Data Port
OFFSET OPERATIONS
- Increment
- Decrement
- AddOffset
- Subtract Offset
- Single-Bit LeftlRight
Shifts
(R
n
_ Rn+
1
)
(R,._ R,.-l)
(Rn- R,.+B..,)
(Rn_Rn- B..,)
- Logical Operations (AND, OR, XOR)
CONDITIONAL RE-INITlALIZATION
- Independent InhibitlEnable for each of four
initialization registers
- Conditional AIR execution (used for true
modulo addressing)

- Normal (Pre-Update) Mode (output the address
before update)
- Post-Update Mode (output the address after
update)
PRECISION
- Single chip supplies 16-bit addresses
- Two chips cascaded provide 30-bit addresses
- One chip provides 3O-bit addresses in two
cycles
3-30 MICROCODED SUPPORT COMPONENTS
registers, denoted B .... and can execute in a singJe-cyc:le the core
operation:
Y R,,; R,.+ Bm.
In DSP applications, data arrays are often addressed as cimJIar
buffers. That is, when addressing reaches the buffer end, it
wraps back to the beginning of the buffer. To implement this
looping, the AG compares the supplied address to one of four
compare registers, denoted Cj. If the address has moved to or
beyond the end of the boundary <Ro;;"Cj), the device can
transfer an initialization register value, denoted Ij , to the register
<Ro - Iv; otherwise, it is updated in normal fashion
<Ro-- R,.+Bm). To minimize overhead, the AG can execute
normal updates while also performing conditional re-initializations;
again, in one core operation:
IF (R,.;;"Cj): R,.+- Ij ; ELSE R,.-- R,.+Bm.
Since the above instruction bandies the looping required of
cimJIar buffet: addressing, it is termed a looping instruction. To
a large extent, the ADSP1410's arc:bitecture and instruction set
revolve around efficient implementation of this instruction.
However, many variations of this instruction are supported on
the device and spelled out in the following sections.
ADSP1410 PIN ASSIGNMENTS
PIN NAME DESCRIPTION
DSEL
The address (Y) output port. In single-chip/double-
precision mode, the MSB (YIS) indicates whether
the supplied address is the MSW or LSW (see
Precision Modes). In two-chip/double-precision
mode, the MSB conveys the carry/shift bit from
the Least Significant (LS) to the Most Significant
(MS) chip.
The bi-directional data (D) port. In two-chip/dou-
ble-precision addressing mode, the MSB (DIS) of
this port conveys CMP status from the partner
chip.
The instruction port.
A dual function pin. Looping instructions, which
compare address register values to compare
register values, assert this pin HI to convey
CMP status if i) R;;"C for positive offsets, or
ii) RsC for negative offsets. Logical/Shift in-
structions assert this pin HI to convey the ZERO
status of the result.
Data Select control. Asserting this control HI
causes data set up on the data port to substitute
for the R value specified in the instruction.
AIR Enable Alternate Instruction Register control. Asserting
this control HI causes the device to execute an
instruction stored in the internsl AIR, rather
than the instruction set up on the instruction
port
CLK Clock
Vdd +5 Volt Power Supply
GND Ground
16
0'5-0
INSTRUCTIONS
Figure 1. ADSP-1410 Functional Block Diagram
ADSP-1410
ClK
AIR
ENABLE
MICROCODED SUPPORT COMPONENTS 3-31

ARCHITECTURE
After discussing the architecture of the ADSP-1410, different
operating modes of the ADSP-1410 are detailed, followed by a
description of the ADSP-141O's method of operation: including
timing concerns and instructions. Brief applications information
is then presented, and the data sheet concludes with a section
on MNEMONICS AND OPCODES.
The ADSP-141O's architecture (Figure 1) features four register
fUes, an ALU, a Comparator, an Alternate Instruction Register
(AIR), and a Control register. External interfaces include a 10-
bit instruction port, a 16-bit data (D) and address (Y) ports, a
DSEL (Data Select) control pin, an AIR Enable control pin,
and a status flag.
Instruction Port
The microcode controlling the ADSP-141O is supplied over the
100bit wide INSTRUCTION PORT. The instruction word,
19-0, is latched prior to the instruction decoder during phase one
(clock HI) and is passed during phase two (clock LO). In addition
to the microcode, two dedicated control pins affect the device's
operation: the DSEL pin (see Y Port, D Port, and DSEL Control
Pin); and the AIR Enable pin (see Alternate Instruction Register
and AIR Enable). These pins are considered instruction bits,
and latched as described above.
Y Port, D Port, and DSEL Control Pin
The ADSP-141O has two 16-bit ports: a DATA (D) PORT and
an ADDRESS (Y) PORT. The output drivers of both ports are
three-state disabled unless an instruction specifies an output.
Addresses supplied to external data memory are output over the
unidirectional Y port. The address supplied may come from one
of three sources: an internal address (R) register, the data (D)
port, or the ALU, The DSEL (Data Select) pin controls whether
an R register (DSEL LO) or external data (DSEL HI) is the
address source. The address source can either be directly output
over the Y port, or passed through the ALU for modification
prior to output (see Pre-Update Mode versus Post-Update Mode).
Hardware three-state output control of the Y port is possible
(see note in "Alternate Instruction Register and AIR Enable"
section). Finally, the address being output (direct or modified
source) may be bit-reversed (see Bit Reverser).
The Y port has two modes of operation (see Transparent Mode
versus Latched Mode). In the more commonly used latched
mode, addresses are latched during phase two (clock LO). The
transparent mode disables the output latch and may be used in
conjunction with stopping the clock LO, allowing data to be
passed through (directly, or modified by the ALU) the AG
without performing updates.
Any internal register may be read or written via the ADSP-141O's
D port. Also, external data can be supplied to the chip over this
port for immediate addressing purposes.
No"':
The ADSP-141O may power-up driving the data bus. Caution
should be used to avoid creating a bus contention with other
devices which may be sharing this bus. To prevent bus contention,
the CLK input may be forced LO during power-up (disabling
the output data drivers). During this time, a RESET instruction
should be setup at the instruction port to be executed as the
first operation when the clock starts up.
3--32 MICROCODED SUPPORT COMPONENTS
Registers
The ADSP-1410 has 30 16-bit registers, organized into four
banks. Single-cycle transfers between certain register hanks are
supported.
Sixteen ADDRESS (R) REGISTERS hold memory address
pointers. In the same cycle that a 16-bit R value is output over
the address (Y) port, it may be incremented, decremented,
offset, modified by a logical operation, or left/right shifted by
one bit. The updated value is then written back into the original
R location (pre-update mode), In post-update mode, the address
is output after being modified. Any R value (or data, using
DSEL) may be bit-reversed on output.
Six OFFSET (B) REGISTERS furnish a second operand to the
ALU (the other, provided by an R register or the data bus) for
modifying the address to be output. The B registers are partitioned
into two, user-selectable (see Control Register: B Bank Select)
banks and external data can substitute as an offset value whenever
B3 (bank one) or B7 (bank two) is used (see Table IV).
Four COMPARE (C) REGISTERS supply one source to the on-
chip comparator, whose other source is the address being output.
When an address moves to or beyond a boundary set by the C
value, the CMP flag goes active (HI).
Four INITIALIZATION (I) REGISTERS can-conditional on
the CMP flag going any R value, allowing
overhead-free branches to the top of an addressing loop. Note
that I and C registers are always paired. Conditional re-initializing
of R registers may be independently inhibited for individual I
registers (see Control Register CR3-0)'
ALU and Shifter
The ADSP-1410's 16-BIT ALU performs adds, subtracts, and
logical operations. Usually, one source is an offset (B) register,
while the other is an address (R) register. However, external
data provided via the D port may substitute either for an R
register (under the control of the DSEL pin), or a B register
(using B3 or B7).
For two-chip/double-precision ALU operations, CARRIES into
the MS chip and out of the LS chip (CSm and CSou,) are conveyed
via the YIS pin (see Precision Modes).
The ALU also contains the logic required for single-bit SHIFTS
of a supplied R register. Left shifts are logical, while right shifts
are arithmetic. In two-chip/double-precision shift operations, the
Y 15 pin conveys the shifted bit. In single-precision operation,
the carry/shift status of the device cannot be monitored.
The destination of an AL U or shift result is always the source R
register location specified in the instruction-even if external
data is the source. If the post-update mode is used, the ALU/shift
result is sent directly over the address (Y) port on the current
cycle (in addition to being returned to the source R location).
Altemate Instruction Register and AIR Enable
The ALTERNATE INSTRUCTION REGISTER (AIR) is a
100bit register which may be loaded with any instruction. On
any cycle that the AIR Enable pin is asserted, the device will
execute the instruction held in the AIR, rather than the instruction
set up on the instruction pins (except for the RST instruction).
The AIR's principal purpose is to conserve microcode. One way
to conserve microcode is to load a frequently-used instruction
(e.g., a looping instruction) into the AIR. Then, this instruction
is executed simply by asserting the device's AIR Enable pin-
temporarily suspending the need for external microcode.
The AIR can also conserve microcode in applications using
multiple AGs (e.g., double-precision or high-throughput systems).
If the AGs generally execute identical instructions, external
microcode may be significantly reduced if they share a common
microcode instruction field. During some cycles, however, it
may be crucial for an AG to execute an instruction different
from the common instruction-something which the AIR and
its enable pin allow. For example, a NOP instruction can be
loaded into an AG's AIR; anytime the AIR Enable pin is asserted,
the AG will be selectively "put to sleep" (lIO pins three-state
disabled; no change in internal state).
The AIR register may be read over the data port (D9-<) in a
single cycle. As Table I shows, the AIR may be written via the
data port (D9-<) or the instruction port. If the instruction written
into the AIR is provided via the instruction port, two cycles are
required. This method allows the AIRs of two or more AGs
sharing microcode to be selectively loaded by differentially as-
serting their DSEL pins. Note that if the DSEL pin is LO
during the entire second phase (clock LO) of the LDA instruction,
no AIR loading occurs. This implicitly requires that DSEL be
setup accordingly prior to the start of the LDA instruction, as it
is latched during phase one (clock HI).
INSTRUCTION LOADED INTO THE AIR VIA THE:
DATA PORT INSTRUCTION PORT
l. Execute "Load AIR" instr.
l. Execute "Write AIR" instr. 2. Provide instr. on instr. port
and assert DSEL pin.
Table I. Options for Reading and Writing the AIR
A second method exists for executing the instruction in the
AIR. Looping instructions compare an address (R) value to a
compare (C) value and, if the address has moved to or beyond a
pre-set boundary, the CMP flag goes HI. If CR 10 (see Control
Register and Conditional AIR Execute Mode) is set, a true
comparison causes the device to execute its next instruction
from the AIR (see Table III.) This capability facilitates no-overhead
modulo addressing (see application note: Modulo Addressing).
Note:
The AIRE pin may be used to control the Y port output drivers
by loading a NOP into the AIR register; the AIRE pin becomes
dedicated to three-state control of the Y port. This technique
supports connection of multiple address sources to the same
bus.
Flags and Comparator
The ADSP-1410 has two internal flags-CMP and ZERO-that
share the external CMP/Z pin. The CMP flag, set by the com-
parator, is affected by looping instructions. The ZERO flag is
set whenever a Logical/Shift instruction has a zero result. In
cycles that do not affect the CMP or ZERO flag, the CMP/Z
flag pin defaults LO.
As Table II shows, the CMP flag goes HI whenever the supplied
address moves to or beyond a boundary set by the specified C
register. The address that is compared to the C value is always
the address that is output-even in post-update mode. R, C,
and B values are treated as unsigned integers by the
Comparator.
ADSP-1410
Twos-Complement Offsets
Negative offsets are generally handled by the R_ R - B in-
struction. However, if for some reason the user is interpreting
offset values as negative twos complement numbers, the instruction
R_ R + B will cause the comparator to sense whether R2:C
(when the condition RosC is of interest). The user may account
for this reversal (e.g., by monitoring for the CMP flag going
LO, rather than HI), but looping instructions cannot be fully uti-
lized.
ARITHMETIC OPERATION CMPFLAG HIGH IF:
R" - R" + 1 (YINC instruction) R,,2:<;
R" - R" - 1 (YDEC instruction) R"sC,
R" - R" + Bm (Y ADD instruction) R,,2:C,
R" - R" - Bm (YSUB instruction) R"sC;
Table II. CMP Flag Truth Table
Alternating Offsets
If the microprogram switches between different offsets and the
AG is in the normal, pre-update mode, the comparator logic
may produce seemingly erroneous results because comparisons
are not made until the cycle following the update. In pre-update
mode, when a routine switches between positive and negative
offsets, the comparator will check for wrong condition because
the comparison is not made until the following cycle. The value
in the compare register must anticipate the comparator sense
reversal by one cycle.
Bit Reverser
Addresses can be bit-reversed as they are output, which is useful
in algorithms such as the Fast Fourier Transform. The bit-reverse
mapping is as follows, where K, and Y; denote the i
th
bit of K
(either an address register or the data bus) and Y (the address
port), respectively.
Bit reversal only affects the value that appears on the address
port; it does not affect the value returned to the R register
location. The hardware bit reverser operates only on single-pre-
cision, 16-bit addresses. For details on software reversal of N-
bit (N<16) fields, see the application note: Variable-Width Bit
Reversing.
Control Register
The ADSP-141O's ll-bit CONTROL REGISTER may
be read or written via the device's data port, Dedicated
instructions are used to read or write the entire control register,
or to set and clear individual bits (see Instruction Group 4). On
power-up, the RST instruction clears the control register to aU
zeros automatically.
MICROCODED SUPPORT COMPONENTS 3-33
The following list shows the control register organization. If the
bites) is set (HI), the specified mode is operative.
CR Bit Assignment
3-0 Re-Initialization Mask: For looping instructions, enables
conditional re-initialization ofR registers with I registers.
For example, setting bit 2 of the CR allows 12 to re-in-
itialize the selected R register if the address has moved
to or beyond the boundary set by C2
5-4 Precision Select:
00 = single-precision mode;
01 = double-precision mode, LS chip;
10 = double-precision mode, MS chip;
11 = double-precision mode, single-chip.
6 Transparent Mode: Sets the address (Y) port to the
transparent mode: otherwise, the Y port is latched
during phase two.
7 R Bank Select: Selects the upper eight R registers as
address sources for the YADD and YSUB instructions.
8 B Bank Select: Selects the upper four B registers as
offset sources for all instructions.
9 Post-Update Mode: Sets the post-update mode (addresses
supplied after updating).
10 Conditional AIR Execute: Sets the conditional AIR
mode: allowing looping instructions to (conditional
upon the CMP status going true) be fetched from the
AIR on the next instruction, rather than the instruction
port. Using this mode disables conditional re-initializa-
tion (of R by I on CMP) and forces the default update
ofR.
ADSP-141O OPERATING MODES
The flexibility of the ADSP-1410 is enhanced by several optional
modes of operation. These modes, governed by the control
register, are discussed in detail in this section.
Precision Modes
Typically, the ADSp141O provides single-precision (16-bit)
addresses. If greater addressing range is needed, double-precision
(30-bit) addresses can be supplied. Two double-precision modes
are with two chips cascaded and the other with
a single chip. Specific instructions set these modes. Double-pre-
cision (single or two-chip) bit-reversing is not supported.
Two-C hiplDouble-Precision
(CRs_
4
="01" for LS chip; "10" for MS chip). In this mode,
two ADSP-141O's are cascaded to generate double-precision
addresses at a rate of one per cycle. Each address may be output,
incremented, decremented or modified by an offset value, com-
pared to a double-precision value, and conditionally re-initialized
by a double-precision word. Alternately, double-precision logical/
shift operations may be performed.
The Y and D ports of each chip are restricted to the lower IS
bits, freeing the MSBs of both devices to convey carry/shift and
CMP status, respectively (see Figure 2). For double-precision
adds/subtracts, the LS chip sends carry/borrow status over the
YIS pin; the MS chip uses Y" to accept carry/borrow status
from the LS. For left (right) shifts, the LS (MS) conveys the
shifted bit over the Y 15 pin.
Double-precision, conditional re-initializations are implemented
by dedicating the DIS pin on each device's data port to receive
the CMP status from the other. When performing a looping
3-34 MICROCODED SUPPORT COMPONENTS
instruction, the MS chip generates a valid CMP flag on its
CMP/Z output. For a logical or shift instruction, the CMP/Z
outputs from both the LS and MS chips must be ANDed to
produce a single valid ZERO flag. To ensure that this flag is
valid on the next low-to-high transition of the clock, the output
of the AND gate should be latched as shown in Figure 2. The
ZERO flag is latched on the falling edge of the clock and held
by the latch until the next falling edge.
CMP/Z
CMP/Z (LS)-"1..._"
CLOCK
o
"1"
Q
ZERO FLAG
'F74
RESET
Figure 2. Valid Two-Chip Double-Precision ZERO
(Logical Instructions)
In this mode, all values are IS-bit words. The 30-bit address is
supplied in two IS-bit words over the Y 14-0 pins of the two
devices. Internally, the MS bit of each operand is zeroed prior
to ALU operations, the MSB of the result then becoming the
carry/shift bit. External data provided over the D port must be
segmented with the IS LSBs going to the LS chip and the IS
MSBs to the MS chip.
In two-chip/double-precision mode, both chips may share the
same microcode instruction. The only complication to this sharing
is in differentiallY initializing the MS and LS chips. Internal
logic allows this initialization to be accomplished. BOlh chips are
fed the instruction designating it as the LS chip. The assertion
of DSEL on the intended MS chip during the SETP instruction
reverses the two LS instruction bits (those defining the chip
configuration to the control register), allowing both MS and LS
designations to be performed simultaneously.
Single-ChiplDouble-Precision
(CR
s
_
4
="Il"). In this mode, double-precision (30-bit) addresses
are generated at a rate of one every two cycles. Each address
may be output, incremented or decremented, and compared to a
double-precision compare (C) value. Logical/shift operations are
also supported. Conditional re-initialization with I registers and
the conditional AIR mode are not supported.
LSW operations are executed first, followed by MSW operations
(with the exception of right shifts). Even-numbered R registers
are reserved for LSWs, while odd registers are assumed to be
MSWs. No such restrictions apply to B or C registers; MS or
LS words may be held in any B or C register, but such allocation
must be tracked by the user. After an operation involving LSW
registers, the device stores the carry/shift bit (as appropriate)
needed to complete the double-precision operation. On the next
operation involving MSW registers, this intermediate value is
utilized. Storage of the carry/shift bit occurs only on LSW oper-
ations, except for double-precision right shifting, which starts
with the MSW. If non-addressing operations intervene, the
intermediate value is not disturbed. The comparator will generate
a meaningful CMP signal after each MSW operation.
In this mode, only the 15 LSBs of any register are used. The
LSW and MSW addresses that are supplied are both IS-bit
words. The Y 15 (MSB) pin of the 16-bit address port designates
whether the address is the LSW (= 0) or MSW (= I), and may
be used to control an external mux. Note that the MSB of values
provided via the data (D) port is not meaningful in this mode.
Transparent Mode
(CR.; HI). In this mode, the address port is made transparent
during the entire cycle, rather than only phase one. The transparent
mode may also be used in conjunction with stopping the clock
(LO), in which case the entire device behaves asynchronously
and no updates are written internally.
Latched Mode
(CR,; LO). In latched mode, output values are enabled during
phase one and latched at the address (Y) port during phase two.
Use of the latched mode guarantees that outputs remain stable
throughout the current cycle regardless of changes at the in-
struction port. This, in contrast to the transparent mode, in
which such changes may occur quickly enough to alter the
output before cycle end.
Post-Update Mode
(CR9 HI). Addresses are output after the update operation. The
delay between the start of phase one and output of a valid address
is extended in this mode to allow for updating. The addresses
output are equivalent to the values written back into the specified
address (R) register. In this mode, external data may be brought
on chip, modified and output-in a single clock cycle.
Pre-Update Mode
( C ~ LO). This is the normal update mode in which addresses
are output over the address (Y) port prior to update operations
(increment, decrement, offset, shift, and logical)-allowing
addresses to be generated at maximal speed. Note however, that
this mode requires two cycles to bring external data on chip,
modify it, and supply it as an address.
Conditional AIR Execute Mode
(CRIO HI). In this mode, a valid CMP flag on looping instructions
causes the next instruction to be executed from the AIR. The
MODULO ADDRESSING section highlights a particularly
valuable use of this mode.
Note that conditional re-initialization of address registers is
disabled when using the conditional AIR execute mode. The
default (ELSE clause) is performed unconditionally whether or
not the instruction is from the instruction port or the AIR.
(CRIO LO). Conditional AIR execution is disabled. Conditional
re-initialization is fully operational, contingent upon the re-in-
itialization mask (CR
3
_
o
).
Table III summarizes the different ways the CMP status affects
operation of the AG as a function of the conditional AIR execute
mode control bit, CRlO, and the re-initialization mask, CR,_o.
D15
MS1410
Y15 CMP/Z
D15
LS 1410
CMP/Z Y15
Figure 3. Two-Chip/Double Precision Handshaking
ADSP-1410
CRIOLO
CMP
STATUS ~ L O CR.ID CRIOID
LO No Effect No Effect No Effect
m CMP/Zgoes CMP/Zgoes CMP/Zgoes
HI HI; HI;
R,,+- Ij Nextinstr.
executed from
AIR
Table III. Effect of Compare (CMP) Status for Looping
Instructions; Note: j =3-0, the Re-Initialization Mask.
INSTRUCTION SET DESCRIPTION
The ADSP-1410's instruction set is partitioned into six groups,
which are discussed below. First, however, issues spanning
several instruction groups are discussed.
Most of the instruction groups contain instructions using one of
the chip's six offset (B) registers. Without exception, these
instructions have just two bits available for selecting the B register.
Consequently, offset registers are partitioned into two banks.
The upper/lower bank selection is maintained in the control
register (CRg) and is set or cleared by dedicated instructions.
Whenever the "fourth" B register of either bank is specified
(B3 or B7), the ALU's offset source becomes external data (see
Table IV).
CR. & TWOBIT OFFSET
OFFSET (B) SOURCE
REGISTER
FIELD
000 BO
001 Bl
010 B2
xll DataPort*
100 B4
101 BS
1 10 B6
xll DataPort*
Table IV. Offset Value Structure
"Explicit use of DSEL is unnecessary when using B, or Bt offsets; the offset
data is sourced from the data bus by default.
In several instruction groups (see mnemonics and opcodes for
details), address (R) registers are used. In all cases, asserting the
DSEL pin allows external data to be substituted for an R value
as both output and update data.
MICROCODED SUPPORT COMPONENTS 3-35
Two instruction groups (looping and logical/shift) both supply
and update the address. Normally, addresses are supplied prior
to updating (pre-update). In post-update mode however, the
addresses are output after the update operation is performed.
CR9 controls this mode of operation.
For all instructions accessing an offset register, the MS bit of
the three-bit offset register address (B, of Bbb) is fetched from
the control register and is programmed by the SELB instruction.
This is also the case for the Y ADD and YSUB instructions
(group 1) as pertains the MS bit of the four-bit address register
address (R, of Rrrr), programmed by the SELR instruction. In
both cases, it is incumbent upon the programmer to ensure the
appropriate register bank is selected.
The Y port is only driven on output instructions (mnemonic
form Yxxx, see MNEMONICS AND OPCODES). Otherwise,
the Y port defaults to a high-impedance state.
Instruction Group 1: Looping
Instructions in the looping group supply the contents of a selected
address (R) register to the address (Y) port and then overwrite
the R location with an updated value.
All instructions in this group generate an internal CMP status
indicating whether the supplied address has moved to or beyond
the boundary specified by the compare register. This status may
be monitored externally via the CMP/Z pin. Internal to the
chip, the CMP status can i) be ignored, ii) be used to control
re-initialization of the R register value with a selected I register
value (e.g., to restart an addressing loop), or iii) control execution
of an instruction located in the AIR on the next cycle. Individual
control register bits determine which option is enforced (see
Control Register).
YINC Output & IncrementlInit.
Pre-Update Mode: R,,;
IF
THEN
ELSE
Post-Update Mode:

THEN
ELSE
R,,-Ij,
R,,-Rn+l.
Y - R,,+l;
Output an address (R) register on the address (Y) port and
compare it to one of the compare (C) registers. If the address is
less than Cj, the R location is simply updated with an incremented
value. However, if , CMP status goes HI and the R
register is re-initialized with the Ij value, provided the initialization
mask (CR3_ 0) is enabled for Ij' Note that other modes of operation
allow CMP status to be ignored (e.g., the instruction executed is
simply "Y ...... Rn; R" - Rn + 1") or to cause the AIR instruction
to execute on the next cycle.
YDEC Output & Decrement/lnit.
Pre-Update Mode: Y - R,,;
IF (RnsCj):
THEN
ELSE
Post-Update Mode:
IF (YsCj):
THEN
ELSE
Same as above except the R value is decremented instead of
incremented; CMP is valid if the R value is less than or equal to
the C value.
3-36 MICROCOOEO SUPPORT COMPONENTS
YADD Output & Add Offset/Init.
Pre-Update Mode: Y -R,,;
IF
THEN
ELSE
Post-Update Mode:

THEN
ELSE
Same as YINC except the R value is summed with the contents
of a selected offset (B) register.
The R register bank select bit (CR7) is used in both the Y ADD
and YSUB (offset) instructions.
YSUB Output & Subtract Offset/lnit.
Pre-Update Mode: Y -R,,;
IF (RosCj):
THEN
ELSE
Post-Update Mode:
IF (YsC,):
THEN
ELSE
Same as YADD except the selected offset (B) register is subtracted
from the R value.
Instruction Group 2: Register Transfers
Instructions in the register transfer group support internal register
transfers, as well as transfers between internal and external
registers. Internally, any I or B register may be written directly
to any R register. Also, any R register may simultaneously be
output and written directly to a B or C register. For an R-to-R
transfer, the source R register can first be written to a B register,
followed by a write of the B register to an R register on the next
cycle.
Internal registers are read or written externally via the bi-directional
data port. There are explicit instructions to read any of these
registers; however, only the I registers have an explicit Write
instruction. The R, B, and C registers may be written with
external data by executing a transfer instruction (YRTR, YRTB,
and YRTC) and asserting the DSEL pin, substituting the external
data for the designated R value.
YRTR Output & Transfer Addr. Reg. to Self
Y ...... R.
Outputs selected address (R) register over the address (Y) port.
When DSEL is asserted, data port values are output and, in the
same cycle, written into the selected R register.
YRTB Output & Transfer Addr. Reg. to Base Reg.
Y-R,,;Bm ...... R.
Outputs selected R register over the Y port and copies it into a
selected B register. When DSEL is asserted, data port values
are output and, in the same cycle, written into the selected B
register.
YRTC Output & Transfer Addr. Reg. toComp. Reg.
Y ...... R,,;C, ... Rn
Same as above, except that values are written to a C register.
DTI Transfer Data Bus to !nit. Reg.

Loads selected I register from data (D) port.
ITR Transferlnit. Reg. to Addr. Reg.
R,.-I,
Selected R register is loaded from an I register, allowing a
microprogram to restart a loop at any time.
BTR Transfer Base Reg. to Addr. Reg.
R,.-Bm
Loads an R register from a B register. Once in the R register,
the B value may be modified and then returned to the B file
(using a YRTB inatruction). Recall, use of B3 or B7 will access
the data port as the offset source, allowing R registers to be
initialized directly from the data port.
Rm Transfer Addr. Reg. to Data Bus
D..-R,.
Supplies selected R register to data (D) port.
cm Transfer Comp. Reg. to Data Bus
D_C,
Supplies selected C register to data (D) port.
Bm Transfer Base Reg. to Data Bus
D-B
m
Supplies selected B register to data (D) port.
lTD Transfer !nit. Reg. to Data Bus
D_I
j
Supplies selected I register to data (D) port.
Instruction Group 3: LoPeal & Shift
Instructions in the logical/shift group supply a value from a
selected address (R) register to the address (Y) port and then
unconditionally overwrite the selected R location with a modified
version of the output. Modify operations include logical (AND,
OR, and XOR) and shift (one-bit left/right) operations. All
inatructions in this group affect the ZERO flag, which goes HI
if the result of the modification is zero. The ZERO flag status is
available externally over the CMP/Z pin.
YOR Output & Logical OR to Addr. Reg.
Y - R,.; R. - (R.
Selected R register is supplied to the address (Y) port; the specified
R location is then overwritten with the logical OR of the B
register and original R value.
YAND Output & Logical AND to Addr. Reg.
Y - R,.; R. - (R,.AND
Same as above, except that a logical AND is performed.
YXOR Output & Logical XOR to Addr. Reg.
Y_ R.;R,.-
Same as above, except that a logical XOR is performed.
ADSP-1410
YASR Output & Arithmetic Right Shift to Addr. Reg.
Y - R,.; R. - ASR (R,.)
Selected R register is supplied to the address (Y) port; the specified
R location is then overwritten with the original R value arithmeti-
cally shifted right (ASR) by one bit (the MSB is repeated).
YLSL Output & Logical Left Shift to Addr. Reg.
Y - R,.; R,. - LSL (R,.)
Selected R register is supplied to the address (Y) port; the specified
R location is then overwritten with the original R value logically
shifted left (LSL) by one bit (the LSB is zero-filled).
Instruction Group 4: Control Register
Instructions in the control register group reset, read, and write
the entire control register or individual control register bits (see
Control Register).
Note the use of "x" and "pp" to denote values supplied within
the opeode field (see MNEMONICS AND OPCODES). A
positive logic convention is used throughout.
RST Reset Control Reg.
CR-O
Clears the entire control register (CRIO_ O). The RST instruction
has dedicated decoding logic so that it takes precedence even
over the second instruction of a conditional AIR sequence.
DTCR Transfer Data Bus to Control Reg.
CR_D
Writes the entire control register (CR 10-0) from the data port,
D
IO
_
o

CRTD Transfer Control Reg. to Data Bus
D_CR
Outputs the entire control register (CRIO_ O) over the data port,
D
IO
_
o

SETI Set/Clear Conditional lnit. on CMF Flag

Enables conditional re-initialization of an R location, subject to
CMP status (see Control Register). This inatruction loads the x
value into the control register bit specified by jj. Conditional re-
initialization of address registers by the Cjjlljj pair is inhibited if
the corresponding CRjj is cleared.
SETP Set Chip precision
CRs_ ..... pp
Loads a 2-bit code (Pp) into control register bits 5 and 4, specifying
the addressing mode of the device:
00 = single-precision mode;
01 = double-precision mode, LS chip (10 if DSEL);
10 = double-precision mode, MS chip;
II = double-precision mode, single-chip.
If the instruction "SETP, 01" is supplied and the MS chip's
DSEL pin is asserted, the CRS-
4
bits are reversed, i.e., the MS
chip is loaded with "10", not "01" (see Precision Modes). This
is useful if the MS and LS chips share a common instruction
bus.
MICROCODED SUPPORT COMPONENTS 3-37

SETY Set Y Port to TransparentlLatched Mode
CR., ..... x
Uses the LS instruction bit to set the address (Y) port to the
transparent (ID) or latched (LO) mode. This status is maintained
in control register bit 6.
SELR Select Upper/Lower Addr. Reg. Bank
CR7 ... x
The LS bit of this instruction provides the missing Address (R)
register select bit required by the Y ADD and YSUB instructions.
This selection is maintained in control register bit 7.
SELB SeIect Upper/Lower Base Reg. Bank
CRs .... x
The LS bit of this instruction provides the missing B register
select bit required by sll instructions utilizing offset (B) registers.
This selection is maintained in control register bit 8.,
SETU Set Update Mode (PostlPre)
CR,"'x
Setting this bit causes the chip to output address values after
updating them (post-update mode). The LS bit of this instruction
determines the value of control register bit 9.
SETA SetlQearConditionai AIR Execute Mode
CR10"'x
Setting this bit causes Looping instructions-conditional on
CMP status being HI-to execute the following instruction from
the AIR on the next cycle. In this mode, conditional re-initialization
of R by I on CMP is inhibited. The LS bit of this instruction
determines the value of control register bit 10.
Instruction Group 5: AIR Control
Instructions in the AIR group write and read the Alternate
Instruction Register (AIR). The AIR may be written or read
over the data bus in one cycle or written via the instruction port
in two cycles (see Table I). The instruction contained in the
AIR is executed whenever the AIR Ensble pin is asserted or on
the next cycle in the conditional AIR execute mode.
WRA Write AIR with Data Bus
AIR ... D
Write the AIR from the data (D) bus (D9-O>.
RDA Read AIR at Data Bus
D ..... AIR
Read the AIR over the data (D) bus (D9 -O>.
LOA Load AIR from Instruction Port on Next Cycle
(Requires DSEL HI)
AIR_ Instruction Port
This instruction is the first of a two-cycle sequence that loads
the AIR via the instruction port. On the cycle following the
execution of LDA, the instruction at the instruction port is
loaded into the AIR (and not executed). DSEL must be asserted
with the LDA instruction (meeting the same setup and hold
time requirements); otherwise, the AIR is not loaded. In systems
with multiple ADSP-1410s sharing microcode instructions, this
feature sllows you to select particular devices for AIR loading.
3-38 MICROCODED SUPPORT COMPONENTS
Instruction Group 6: Miscellaneous
YDTV Pass Data Bus to Y Port
Y_D
Data (D) port values are supplied directly to the address (Y)
port. Note that internal address (R) registers are not affected by
this instruction.
REV Output Addr. Reg. in Bit-Reversed Format
V-YREV (R,,); R" - R,. + Bm
The selected address (R) register is bit reversed at the output
port. The original (unreversed) R value is added to the selected
offset (B) register, and written back into the specifted R location.
Condition testing is not performed. Bit reversing affects only
output data, not register contents.
NOP No Operation
Prevents any changes to the internal conditions of the AG. All
110 pins go to the three-state disable mode.
ADDRESS GENERATOR APPLICATIONS
The ADSP-141O has a wide range of uses in high-speed digital
signal processing and general purpose computer applications. In
particular, this AG can be used in implementing the following:
Circular Data Buffers
- FIR filter tapped delay lines
- Corre1ator delay lines
- Image processing delay lines
- Recirculated data 110 for transient data capture or stimulus
source
Memory Management
- Fast Fourier Transtorm data and twiddle factors
- Matrix computations
Table Look-Ups
Masking and table address mapping with AND/OR and bit
reverse capabilities.
Variable-Width Bit Reversing
The internal bit-reversing multiplexer of the AG accommodates
only full, l6-bit addresses (64K FFTs). For smaller FFTs,
(utilizing a right-justified subset of the l6-bit address field), a
zero-overhead software approach may be employed. The details
of this approach may be found in the application note: "Variable-
Width Bit Reversing with the ADSP-1410 Address Generator."
Essentially, the technique is this: an R register is intialized with
the bit-reversed value of the 16-bit starting address (a "pre-re-
versed" version of the first data point location) and a B register
with the value K'2
16
-
N
, where K is the step size between samples
and N is the order' of the FFT. Now, repeated execution of the
YREV instruction will output the appropriate bit-reversed ad-
dresses; updating the R register each time.
Multi-Tasking Operations
Context switching allowed by large number of on-chip registers
or by instructions allowing all registers to be saved and restored.
16-Bit ALU/Accumulator
By substituting external data for a B register and operating in
post-update mode, ALU operations can be performed at high
speed. ALU sources are the external data and anyone of sixteen
internal R registers. Results are stored on-chip in these R registers.
Two chips may be cascaded for double-precision operations.
Unclocked (Flow-Through) Applications
When operating in transparent and post-update modes with the
DSEL line asserted, the device serves as an unclocked ALU.
Digital Differential Analyzer
- Sine and cosine generation
- Graphics/Line drawing
- Control and guidance
Modulo Addressing
Hardware on the ADSP-14l0 allows the addressing of circular
buffers to be implemented without overhead. The Conditional
re-initialization structure handles the simple case of returning to
the top of a loop.
Some applications require robust modulo addressing of a circular
buffer with an arbitrary starting point, ending point, and increment
between addresses. To implement true modulo addressing with
the ADSP-14l0, consider a buffer of length L. First, Rn is
initialized with the start address n, Bm is initialized with m, a
constant increment or step between addresses, and Bo is initialized
with (L-m), to implement a modulo jump to the beginning of
the buffer. Then a compare register C, is loaded with the value
(n + L - 2m) for pre-update mode, or the value (n + L - m) for
post-update mode. Bit CRIO of the Control Register is set to
enable conditional AIR execution. The instruction "YADD R
n
e, Bm" is then executed repeatedly, from the instruction port.
This outputs Rn and updates it (for pre-update mode - or updates
Rn and then outputs it for post-update mode) by summing it
with the offset Bm. The comparator monitors whether
Rn<o:(n + L - 2m), for pre-update mode, or Rn<o:(n + L - m), for
post-update mode. When such an event occurs, the instruction
in the AIR is executed in the next cycle. This should be the
negative offset instruction "YSUB Rn C, Bo" which updates Rn
with a negative offset of (L - m), causing a modulo L jump
back to the beginning of the buffer. In this fashion, true modulo
addressing can be implemented for arbitrary buffer boundaries
and offsets.
SPECIFICATIONS
The specification tables contain the electrical and switching
characteristics of the ADSP-141O. Figure 7 is the accompanying
timing diagram for the device.
The clock input to the ADSP-141O is a single, two-phase clock
with cycle time: tey.
The setup and hold times for the instruction inputs are tiS and
tm, respectively. Input instructions consist of the 10-bit microcode
instruction, the DSEL control, and the AIRE control: all of
which are latched during phase one (clock HI).
The timing of internal register reads from the data port is specified
by tonD and tnms. Assuming a data output instruction is executing,
the data drivers are activated only during phase one (clock HI).
Therefore, output data becomes valid tonn into phase one (clock
HI) and remains valid for a portion of phase two (clock LO).
tnms specifies how long into phase two the data drivers take to
disable. If data outputs are followed by data inputs, tnms estab-
lishes the timing required to avoid bus contention.
If the device is in the transparent mode, the DSEL pin may be
asserted to open the path between the data port and the address
port. Assuming data is properly setup on the D port, tTAn or
tTAp (for pre- or post-update modes, respectively) specifies the
interval from DSEL assertion to a valid address appearing at the
Y port. Note that changes on the DSEL pin (or any instruction
pin) are not recognized during phase one (clock HI).
ADSP-1410
Latched Mode Parameters have a Sliding Window
Output delays for addresses and the CMP/Z flag depend upon
whether the device is in the pre-update (normal) mode or post-up-
date mode and upon the use of a latches vs. transparent mode
of operation. In the latched mode, a "sliding window" effect is
apparent, resulting from the internal Look-Ahead pipeline (see
Figure 3). The sliding window effect is described to facilitate
IOUTPUT
OUTPUT
tiS DELAY
tiS DELAY
I
1 ~ I I ~ I -,
/ '\
a. Minimum Output Delay b. Minimum Setup Time
Figure 4. Boundary Cases of "Sliding Window" Effect:
Minimum Output vs. Minimum Setup
exact calculation of guaranteed Clock-to-Output delays as a
function of faster or slower instruction setup times. Latched
mode guaranteed Clock-to-Output delays are given as a minimax
pair. The user may vary the output delays within these limits by
adjusting the instruction setup time.
As the instruction setup time is increased beyond the minimum
(tls<o:min[tls]), the corresponding guaranteed Clock-to-Output
delay will be reduced (see Figure 3a) toward its minimum value.
Conversely, as the instruction setup time is reduced toward its
minimum (tiS __ min[tIS]), the corresponding Clock-to-Output
delay will increase (see Figure 3b) toward its maximum value.
The required instruction setup time for the fastest latched output
delay is simply the difference between the minimum and maximum
guaranteed Clock-to-Output specifications plus the minimum
instruction setup time, e.g., an instruction setup time of Imax[tLAnl
-min[tLAnl +min[tlsJJ is required to realize min[tLAnl.
For intermediate cases (in which neither minimax limits apply),
output delays may be calculated by subtracting the actual in-
struction setup time from the sum of the minimum instruction
setup time and the maximum guaranteed Clock-to-Output
specifications, as the following example shows (in which
tlSnun = l5ns and 30ns:StLAn :S35ns):
Actual
tiS
5
10
15
16
17
18
19
20
25
30
etc.
Guaranteed Clock-to-Output Delay
(rnax[tLAnl + min[tIsl - tiS)
nla Invalid (minimum tiS violated)
nla Invalid (minimum tIS violated)
35 Minimum Setup, Maximum Delay
34 Sliding Window Dominant
33 Sliding Window Dominant
32 Sliding Window Dominant
31 Sliding Window Dominant
30 Maximum Usable Setup, Minimum Delay
30 Minimum tLAn Dominant
30 Minimum tLAn Dominant
etc. etc.
Transparent Mode Parameters
The transparent mode of operation is entirely dissociated from
clock edges. Hence, the relevant parameters are referenced to
the instruction becoming valid rather than the clock edge; only
maximum Valid-instruction-to-Output Delay specifications
pertain.
(continued on page 3-42)
MICROCODED SUPPORT COMPONENTS 3-39

SPECIFICATIONS
1
RECOMMENDED OPERATING CONDITIONS
J&KGrades S&TGrades
2
Parameter Min Max Min Max Unit
VDD
Supply Voltage 4.75 5.25 4.5 5.5 V
TAMS
Ambient Operating Temp. 0 70 -55 125 OC
ELECTRICAL CHARACTERISTICS
Test J&KGrades S&TGrades
2
Parameter Conditions Min Max Min Max Unit
VIH
Hi-Level Input Voltage
VIHe
Clock Input Hi-Level Input Voltage
VIL
Lo-Level Input Voltage
VOH Hi-Level Output Voltage
VOL
La-Level Output Voltage
IIH Hi-Level Input Current
IlL
Lo-Level Input Current
IIH Clocks & Control Inputs
Hi-Level Input Current
IlL
Clocks & Control Inputs
Lo-Level Input Current
IozH
Three-State Leakage Current
IozL
ThreeState Leakage Current
IDD
Supply Current
IDD
Quiescent Suppiy Current
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .. . .
Input Voltage . . . . .
Output Voltage Swing.
Load Capacitance . . .
Operating Temperature Range (Ambient) .
Storage Temperature Range . . .
Lead Temperature (10 Seconds)
VDD = max 2.0 2.0 V
VDD=max 3.0 3.5 V
VDD = min 0.8 0.8 V
VDD=min,loH= -lrnA 2.4 2.4 V
VDD=min,loL =3rnA 0.6 0.6 V
VDD=max, VIN=5V 10 10 J.LA
VDD = max, VIN=OV 10 10 J.LA
VDD = max, VIN=5V 10 10 J.LA
VDD=max, VIN=OV 10 10
J.LA
VDD = max, VIN=max 50 50
J.LA
VDD=max, VIN=O 50 50 J.LA
max clock rate, TTL inputs 75 100 rnA
VIN=2.4V 35 50 rnA
ORDERING INFORMATION
-O.3V to 7V
-O.3V to Voo
-O.3V to Voo
..... 200pF
- 55C to + 125C
- 65C to + 150C
. . . . .. 300C
Part Number
ADSP14IOJN
ADSP1410KN
ADSP14IOJP
ADSP-14IOKP
ADSP-1410JD
ADSP-14IOKD
ADSP-14IOSD
ADSP-14IOTD
ADSP-14IOSDI883B
ADSP-14IOTDI883B
Temperature
Range Package
Oto +70'C 48-Pin Plastic DIP
Oto + 70'C 48-Pin Plastic DIP
Oto +70'C 52-Lead PLCC
Oto +70'C 52-Lead PLCC
Oto +70'C 48-Pin Ceramic DIP
Oto + 70'C 48-Pin Ceramic DIP
- 55'C to + 125'C 48-Pin Ceramic DIP
- 55'C to + l25'C 48-Pin Ceramic DIP
- 55'C to + l25'C 48-Pin Ceramic DIP
- 55'C to + l25'C 48-Pin Ceramic DIP
ESDSENSITIVITY ______________________ _
Package
Outline
N48A
N48A
P-52
P-52
D-48A
D-48A
D-48A
D-48A
D-48A
D-48A
The ADSP-1410 features proprietary input protection circuitry. Per Method 3015 of MIL-STD883,
the ADSP -1410 has been classified as a Class 1 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance degra-
dation. Charges as high as 4000 volts readily accumulate on the human body and test equipment and
discharge without detection. Unused devices must be stored in conductive foam or shunts, and the
foam should be discharged to the destination socket before devices are removed. For further informa-
tion on ESD precautions, refer to Analog Devices' ESD Prevention Manual.
WARNING! 0
~ ~ D E V I C E
3-40 MICROCODED SUPPORT COMPONENTS
SWITCHING CHARACTERISTICS
3
ADSP-1410
JGnde KGrade sGrade' TGrade'
Puameter Min Mal: Min Mal: Min Mal: Min Mal: Vllit
t,s Instruc:tion Setup Time 20 15 30 2C!
ns
t'H
Instruc:tion Hold Time 5 4 5 4 ns
leY
instruction Cycle Time 100 90 125 100 ns
I,DS Inpul Dats Setup Time 10 10 10 10 ns
I'DH
Input Oats Hold Time 5 5 6 6 ns
toDD
Gusranteed C1ock-ta-Dats Delay' 35 55 30 50 45 70 40 60 ns
IDENA
Output Dats Enable Time' 30 50 25 45 40 65 35 55 ns
tDDIS
Output Dats Disable Time 20 20 25 20 ns
tAD'S
Output Address Disable Time 30 25 45 40 ns
Latched Mode,
Gusranteed CIock-to-Output Delays:
tUn
Pre-Update Address Delay' 35 45 30 35 40 55 35 45 ns
lLFn
Pre-UpdateCMP/Z Flag Delay'
(C=25pF) 45 55 35 45 60 75 45 60 ns
tu.
Post-Update Address Delay' 35 60 30 50 40 75 35 55 ns
lLFp
Post-UpdateCMP/ZFlagDelay'
(C=25pF) 45 70 35 55 60 95 45 75 ns
Transparent Mode,
Valid-Instruction-to-Output Delays:
tTAa
Pre-Update Address Delay 50 45 65 55 ns
tTFn
Pre-UpdateCMP/ZFIagDelay
(C=25pF) 65 55 90 70 os
lTAp
Post-Update Address Delay 75 65 95 80 os
tTF
Post-UpdateCMP/Z Flag Delay
(C=25pF) 90 75 115 95 os
Supplementsl Parameters for
Double-Chip/Double-Precision Operstioo
6
:
leSD
Valid Instruction-to-Carry/Shift
Output Delay 65 57 80 72 os
less
Carry/Shift Input Setup Time 35 28 40 35 os
lMSD
Carry/Shift Input to Valid MS
Address (Post-Update Only) 45 40 55 48 os
Icz", Valid Instructioo toMS CMP/Z
(Compare) Flag Delay 115 105 120 115 os
Icz,
Clock High toCMP/Z (Compare)
lovalid Delay 4 4 4 4 os
Icz",
Valid Instructioo toCMP/Z (Zero)
F1agDelay 80 70 85 80 os
tliD
Instructioo Iovalid to CMP/Z (Zero)
Iovalid Delay 10 10 10 10 ns
NOTES
I All speciru:ataonsareover the recommended operanng COndttIODS.
'S and T grade pons OR available processed and , .. led 1ft acoordance with MIL-STD-883B_ Tbe processlDg and lesl melhod. used for S/883B and T/883B vernon.
oflbe ADSP-1410 can be found in Analog Dev,ces' Mlluary Produc" Darabook_
Jlnpu[ leveisareGND and 3V. Rise tUlleSare Sos. Input [IDUng reference levels and output tuwngrefercnce levels are I.SV For capaCltlve loads greater than
l00pF J we recommend the use of external buffers.
4lnstructiOil setups beyond the clock W penod (moo the prevlOUS cycle)will not be recognized, regardless oflatched ortransparent mode, as the Instructlon
Ialch isd/tuoys froaen during clock HI. Also, lbeclock HI penod muS! always exceed lbe guaranleed Clock-Io-OurputIDala delay
sMllumum speaf1C8tions pertain to ntaXlDlUD1 usable instruction setups, while maXImum specificanons pertalIl toabsoJute muumum Instruction setups
SeedISCU8Slon of''sliding window" under SpeaflCabon._
'The Instruction Cycle Tune, tey, does not apply to DCDP operation. Clock HI and LO relanonsiups for [)cDP operation are descnbed In the Specifications
tex.tunderDCDPPanuneters: tHI is denved from theteSD, tess, tMSD,and tIS parameters,and themequahty, L O ~ t I S ' must also hold
SpecifICations subJeCt to change without notICe.
Yoo
Y
TO
OUTPUT o--.-4(
PIN
INPUT 0--.--4-..
OUTPUT
3pF
10.
100
Figure 6. Equlvslent
Input Circuits
Figure 6. Equlvslent
Output Circuits
Figure 7. Normal Losd
for ae Measurement
+1.5Y
MICROCODED SUPPORT COMPONENTS 3-41
(continud from page 3-39)
Data Output Parameten
Data output parameters are independent of operating modes.
Data drivers are asserted only during phase one (clock HI). The
guaranteed Clock-to-Data Delay is, again, subject to the sliding
window phenomenon; the minimax specifications pertain to
maximum usable and absolute minimum instruction setup times,
respectively.
The carry/shift output delay, teSD, is referenced to the valid
instruction, while the carry/shift setup time, tess, is referenced
to the clock falling edge. Together, they comprise the minimum
time required from the valid instruction to the falling edge of
the clock. Therefore, the sum of the carry/shift 110 operations
(teSD + tess) less the instruction setup time, tIS, defines the
minimum clock HI period; tHI2:(tcsD + tess) - tIS, as referenced
in footnote 6 of the switching characteristics table. The clock
LO duration must accommodate the instruction setup time;
tL02:t[S'
Double-ChiplDouble-Precision Parameten
The double-chip/double-precision (DCDP) mode of operation
utilizes the Y IS pin to commute the interchip carrylborrow/shift
information, and DIS, the CMP/Z status (see Figure 2).
Post-Update DCDP
Because post-update DCDP operation of the ADSP-1410 requires
calculation of the address prior to its output, the additional
parameter for the MS word output delay, tMSD, is necessary in
specifying this mode. In post-update DCDP mode, tMSD supplants
tess for Clock HI determination; tH[2:(tCSD + tMSD) - tIS,
Pre-Update DCDP
Normally, (as is the case with any pre-update operation) pre-update
DCDP operations have only to output the previously calculated
resnlt. because the carry/shift output delay is asyn-
chronous, the clock cycle time becomes a function of how soon
the instruction is valid; increasing DCDP instruction setups
decreases the required clock cycle time.
SINGLECHIP TIMING PARAMETERS:
CLOCK
INSTRUCTION
:-
tey
I
_I
, t,s I I I
: 1--, i+-t'H


, I
OUTPUT DATA i I' ___ _
(+-: .... : toms 1- :
: I I
LATCHED ADDRESS ! i >r-
Itt=i I I tADIS I
"...-I I 1---,
LATCHED CMPIZ FLAG ! ViJ\7
........ l'"""F."""1 N::A
, I t LF" I

TRANSPARENT ADDRESS i >r--
I tTA I
I
TRANSPARENT CMP/Z FLAG
I tTFIC I
,- -I
Figure 8. Timing Diagram
DCDP
CLOCK
:_tLO--l.- tH,-toI :
DCDP I I lk.---t--
INSTRUCTION @(I I i
-It,s/-:: I
! -+-1
110 &&Xfjj.i,)OO 1: N:L:Cf::.
i -+I tess 1.0- I
DCDP MS ADDRESS I
DELAY (FOR POST-
UPDATE MODE ONLY' ___ ,....._
: --: tMSO f- :