DesignCon 2003 TecForum I2C Bus Overview January 27 2003

Philips Semiconductors
Jean Marc Irazabal Technical Marketing Manager for I2C Devices Steve Blozis International Product Manager for I2C Devices

 1st Hour

Agenda

Serial Bus Overview I2C Theory Of Operation 2nd Hour Overcoming Previous Limitations I2C Development Tools and Evaluation Board 3rd Hour SMBus and IPMI Overview I2C Device Overview I2C Patent and Legal Information Q&A
Slide speaker notes are included in AN10216 I2C Manual
DesignCon 2003 TecForum I2C Bus Overview
2

st 1

Hour

DesignCon 2003 TecForum I2C Bus Overview

Serial Bus Overview

DesignCon 2003 TecForum I2C Bus Overview
4

Co

m m un ic

at io

ns

Co

er m nsu

Au

tive o tom

IEEE1394
SERIAL BUSES

UART SPI
DesignCon 2003 TecForum I2C Bus Overview

In du st

ria l
5

General concept for Serial communications

SCL SDA
Parallel to Serial Shift Register select 3 select 2 select 1 READ or WRITE?

enable R/W

Shift Reg# // to Ser.

enable R/W

Shift Reg# // to Ser.

enable R/W

Shift Reg# // to Ser.

DATA

MASTER

SLAVE 1

SLAVE 2

SLAVE 3

A point to point communication does not require a Select control signal An asynchronous communication does not have a Clock signal Data, Select and R/W signals can share the same line, depending on the protocol Notice that Slave 1 cannot communicate with Slave 2 or 3 (except via the master) Only the master can start communicating. Slaves can only speak when spoken to
DesignCon 2003 TecForum I2C Bus Overview
6

Typical Signaling Characteristics

LVTTL RS422/485 PECL LVPECL LVDS I2C I2C SMBus 1394 I2C GTL+

CML
LVT LVC 5V 3.3 V 2.5 V GTL GTLP

DesignCon 2003 TecForum I2C Bus Overview

Transmission Standards
2500 Data Transfer Rate (Mbps) 655 400
GTLP BTL ETL CML

1394.a

35 10

LVD ECL S =RS-6 /PEC 4 L/LV 4 PEC L

General Purpose 1 Logic

RS-422 RS-485

0.1
I2C RS-232 RS-423

0.5

10

100 Cable Length (meters)

1000

Backplane Length (meters) DesignCon 2003 TecForum I2C Bus Overview

Speed of various connectivity methods (bits/sec)

CAN (1 Wire) I2C (Industrial, and SMBus) SPI CAN (fault tolerant) I2C CAN (high speed) I2C High Speed mode USB (1.1) SCSI (parallel bus) Fast SCSI Ultra SCSI-3 Firewire / IEEE1394 Hi-Speed USB (2.0) 33 kHz (typ) 100 kHz 110 kHz (original speed) 125 kHz 400 kHz 1 MHz 3.4 MHz 1.5 MHz or 12 MHz 40 MHz 8-80 MHz 18-160 MHz 400 MHz 480 MHz

DesignCon 2003 TecForum I2C Bus Overview

Bus characteristics compared

Bus IC I2C w ith buffer I C high speed
2 2

Data rate (bits / sec) 400k 400k 3.4M 33k 5k 125k 1M 1.5M 1.5/12M 480M 100 to 400M+

Length (meters) 2 100 0.5 100 10km 500 40 3 25 72

Length limiting factor w iring capacitance propagation delays w iring capacitance total capacitance propagation delays cable specs 5 cables linking 6 nodes (5m cable node to node) 16 hops, 4.5M each

Nodes Typ.number 20 any 5 32 100 2 127 63

Node number limiting factor 400pF max no limit 100pF max load resistance and transceiver current drive bus specs bus and hub specs 6-bit address

CAN 1 w ire CAN differential USB (low -speed, 1.1) USB (full -speed, 1.1) Hi-Speed USB (2.0) IEEE-1394

DesignCon 2003 TecForum I2C Bus Overview

10

What is UART?
(Universal Asynchronous Receiver Transmitter) Communication standard implemented in the 60s. Simple, universal, well understood and well supported. Slow speed communication standard: up to 1 Mbits/s Asynchronous means that the data clock is not included in the data: Sender and Receiver must agree on timing parameters in advance. Start and Stop bits indicates the data to be sent Parity information can also be sent
0 Start bit 1 2 3 4 5 6 7 Stop bit Parity Information
11

8 Bit Data

DesignCon 2003 TecForum I2C Bus Overview

UART - Applications
Server Server Processor Processor Digital tt Datacom Datacom r r controller controller x x

Public / Private LAN application Telephone / Internet Network Serial Interface

Analog or Digital

t rModem Modem x

WAN application

Parallel Interface tt Modem Modemrr xx

Client Client Processor Processor tt Datacom rr Datacom controller xx controller

Serial Interface

Appliance Terminals Entertainment Home Security

Cash register

Display
Micro Micro Data contr. contr. UART
Address

Robotics Automotive Cellular Medical

12

Memory Memory

Interface to Server

DUART DUART SC28L92 SC28L92

Bar code reader 2 DesignCon 2003 TecForum I C Bus Overview Printer

What is SPI?
Serial Peripheral Interface (SPI) is a 4-wire full-duplex synchronous serial data link:
SCLK: Serial Clock MOSI: Master Out Slave In - Data from Master to Slave MISO: Master In Slave Out - Data from Slave to Master SS: Slave Select

Originally developed by Motorola Used for connecting peripherals to each other and to microprocessors Shift register that serially transmits data to other SPI devices Actually a 3 + n wire interface with n = number of devices Only one master active at a time Various Speed transfers (function of the system clock)
DesignCon 2003 TecForum I2C Bus Overview
13

SPI - How are the connected devices recognized?

SCLK MOSI MISO SS 1 SS 2 SS 3 MASTER SCLK MOSI MISO SS SCLK MOSI MISO SS SCLK MOSI MISO SS SLAVE 1

SLAVE 2

SLAVE 3

Simple transfer scheme, 8 or 16 bits Allows many devices to use SPI through the addition of a shift register Full duplex communications Number of wires proportional to the number of devices in the bus
DesignCon 2003 TecForum I2C Bus Overview
14

What is CAN ? (Controller Area Network)

Proposed by Bosch with automotive applications in mind (and promoted by CIA - of Germany - for industrial applications) Relatively complex coding of the messages Relatively accurate and (usually) fixed timing All modules participate in every communication Content-oriented (message) addressing scheme

Filter

Frame

Filter

DesignCon 2003 TecForum I2C Bus Overview

15

CAN protocol
Start Of Frame Identifier Remote Transmission Request Identifier Extension Data Length Code Data Cyclic Redundancy Check Acknowledge End Of Frame Intermission Frame Space

Very intelligent controller requested to generate such protocol

DesignCon 2003 TecForum I2C Bus Overview
16

CAN Bus Advantages

Accepted standard for Automotive and industrial applications
interfacing between various vendors easier to implement

Freedom to select suitable hardware

differential or 1 wire bus

Secure communications, high Level of error detection

15 bit CRC messages (Cyclic Redundancy Check) Reporting / logging Faulty devices can disconnect themselves Low latency time Configuration flexibility

High degree of EMC immunity (when using Si-On-Insulator technology)

DesignCon 2003 TecForum I2C Bus Overview
17

What is USB ? (Universal Serial Bus)

Originally a standard for connecting PCs to peripherals Defined by Intel, Microsoft, Intended to replace the large number of legacy ports in the PC Single master (= Host) system with up to 127 peripherals Simple plug and play; no need to open the PC Standardized plugs, ports, cables Has over 99% penetration on all new PCs Adapting to new requirements for flexibility of Host function
New Hardware/Software allows dynamic exchanging of Host/Slave roles PC is no longer the only system Host. Can be a camera or a printer.

DesignCon 2003 TecForum I2C Bus Overview

18

USB Topology (original concept, USB1.1, USB2.0)

Host One PC host per system Provides power to peripherals Hub Provides ports for connecting more peripheral devices. Provides power, terminations External supply or Bus Powered Device, Interfaces and Endpoints Device is a collection of data interface(s) Interface is a collection of endpoints (data channels) Endpoint associated with FIFO(s) for data I/O interfacing
DesignCon 2003 TecForum I2C Bus Overview

Monitor Host PC
5m

5m

5m 5m

Hub
5m

Device

19

USB Bus Advantages

Hot pluggable, no need to open cabinets Automatic configuration Up to 127 devices can be connected together Push for USB to become THE standard on PCs
standard for iMac, supported by Windows, now on > 99%of PCs

Interfaces (bridges) to other communication channels exist

USB to serial port (serial port vanishing from laptops) USB to IrDA or to Ethernet

Extreme volumes force down IC and hardware prices Protocol is evolving fast

DesignCon 2003 TecForum I2C Bus Overview

20

Versions of USB specification

USB 1.1 Established, large PC peripheral markets Well controlled hardware, special 4-pin plugs/sockets 12MBits/sec (normal) or 1.5Mbits/sec (low speed) data rate USB 2.0 Challenging IEEE1394/Firewire for video possibilities 480 MHz clock for Hi-Speed means its real UHF transmission Hi-Speed option needs more complex chip hardware and software Hi-Speed component prices about x 2 compared to full speed

USB OTG (On The Go) Supplement New hardware - smaller 5-pin plugs/sockets Lower power (reduced or no bus-powering)
DesignCon 2003 TecForum I2C Bus Overview
21

What is IEEE1394 ?
A bus standard devised to handle the high data throughput requirements of MPEG-2 and DVD
Video requires constant transfer rates with guaranteed bandwidth Data rates 100, 200, 400 Mbits/sec and looking to 3.2 Gb/s

Also known as Firewire bus (registered trademark of Apple) Automatically re-configures itself as each device is added
True plug & play Hot-plugging of devices allowed

Up to 63 devices, 4.5 m cable hops, with max. 16 hops Bandwidth guaranteed

DesignCon 2003 TecForum I2C Bus Overview

22

1394 Topology

Physical layer Analog interface to the cable Simple repeater Performs bus arbitration

Link layer
Assembles and dis-assembles bus packets Handles response and acknowledgment functions

Host controller
DesignCon 2003 TecForum I2C Bus Overview

Implements higher levels of the protocol

23

What is I2C ? (Inter-IC)

Originally, bus defined by Philips providing a simple way to talk between ICs by using a minimum number of pins A set of specifications to build a simple universal bus guaranteeing compatibility of parts (ICs) from different manufacturers:
Simple Hardware standards Simple Software protocol standard

No specific wiring or connectors - most often its just PCB tracks Has become a recognised standard throughout our industry and is used now by ALL major IC manufacturers
DesignCon 2003 TecForum I2C Bus Overview
24

I2C Bus - Software

Simple procedures that allow communication to start, to achieve data transfer, and to stop
Described in the Philips protocol (rules) Message serial data format is very simple Often generated by simple software in general purpose micro Dedicated peripheral devices contain a complete interface Multi-master capable with arbitration feature

Each IC on the bus is identified by its own address code

Address has to be unique

The master IC that initiates communication provides the clock signal (SCL)
There is a maximum clock frequency but NO MINIMUM SPEED
DesignCon 2003 TecForum I2C Bus Overview

25

How are the connected devices recognized?

Master device polls used a specific unique identification or addresses that the designer has included in the system Devices with Master capability can identify themselves to other specific Master devices and advise their own specific address and functionality
Allows designers to build plug and play systems Bus speed can be different for each device, only a maximum limit

Only two devices exchange data during one conversation

DesignCon 2003 TecForum I2C Bus Overview

26

Pros and Cons of the different buses

UART
Well Known Cost effective Simple

CAN
Secure Fast

USB
Fast Plug&Play HW Simple Low cost

SPI
Fast Universally accepted Low cost Large Portfolio

I2C
Simple Well known Universally accepted Plug&Play Large portfolio Cost effective

Limited functionality Point to Point

Complex Automotive oriented Limited portfolio Expensive firmware

Powerful master No Plug&Play required HW No Plug&Play SW - Specific drivers required No fixed standard

Limited speed

DesignCon 2003 TecForum I2C Bus Overview

27

2 IC

Theory Of Operation
28

DesignCon 2003 TecForum I2C Bus Overview

I2C Introduction
I2C bus = Inter-IC bus Bus developed by Philips in the 80s Simple bi-directional 2-wire bus:
serial data (SDA) serial clock (SCL)

Has become a worldwide industry standard and used by all major IC manufacturers Multi-master capable bus with arbitration feature Master-Slave communication; Two-device only communication Each IC on the bus is identified by its own address code The slave can be a:
receiver-only device transmitter with the capability to both receive and send data
DesignCon 2003 TecForum I2C Bus Overview
29

I2C by the numbers

Standard-Mode
Bit Rate (kbits/s) Max Cap Load (pF) Rise time (ns) Spike Filtered (ns) Address Bits
Rise Time

Fast-Mode
0 to 400 400 300 50 7 and 10

High-SpeedMode
0 to 1700 400 160 10 7 and 10 0 to 3400 100 80

0 to 100 400 1000 N/A 7 and 10

VDD VIH 0.7xVDD

VIL VOL GND

DesignCon 2003 TecForum I2C Bus Overview

0.3xVDD 0.4 V @ 3 mA Sink Current

30

I2C Hardware architecture

Pull-up resistors Typical value 2 k to 10 k

SCL

Open Drain structure (or Open Collector) for both SCL and SDA

10 pF Max

DesignCon 2003 TecForum I2C Bus Overview

31

START/STOP conditions
Data on SDA must be stable when SCL is High

Exceptions are the START and STOP conditions

DesignCon 2003 TecForum I2C Bus Overview

32

I2C Address, Basics

controller SCL SDA I/O A/D D/A LCD RTC controller II

1010 0 1 1 1010A2A1A0R/W
Fixed Hardware Selectable Each device is addressed individually by software

A0 A1 A2

EEPROM

New devices or functions can be easily clipped on to an existing bus!

Unique address per device: fully fixed or with a programmable part through hardware pin(s). Programmable pins mean that several same devices can share the same bus Address allocation coordinated by the I2C-bus committee 112 different types of devices max with the 7-bit format (others reserved)
DesignCon 2003 TecForum I2C Bus Overview
33

I2C Address, 7-bit and 10-bit formats

The 1st byte after START determines the Slave to be addressed Some exceptions to the rule: General Call address: all devices are addressed : 0000 000 + R/W = 0 10-bit slave addressing : 1111 0XX + R/W = X 7-bit addressing S

X X X X X X X R/W A
The 7 bits

DATA Only one device will acknowledge

10-bit addressing S

1 1 1 1 0 X X R/W A1 X X X X X X X X A2 DATA
XX = the 2 MSBs The 8 remaining More than one device can Only one device will bits acknowledge acknowledge

DesignCon 2003 TecForum I2C Bus Overview

34

I2C Read and Write Operations (1)

Write to a Slave device
< n data bytes > A data data A P S slave address S slave address WW A A data data A A P Master transmitter
SDA SCL

Slave receiver

0 = Write

Each byte is acknowledged by the slave device

The master is a MASTER - TRANSMITTER: it transmits both Clock and Data during the all communication

Read from a Slave device

<
S slave address R A

n data bytes >

A data A P

SCL

data

receiver
SDA

transmitter

1 = Read

Each byte is acknowledged by the master device (except the last one, just before the STOP condition)

The master is a MASTER TRANSMITTER then MASTER - RECEIVER: it transmits Clock all the time it sends slave address data and then becomes a receiver
DesignCon 2003 TecForum I2C Bus Overview
35

I2C Read and Write Operations (2)

Combined Write and Read
< n data bytes > A data data A Sr Sr slave address R
A

<

m data bytes >

data A data A P

S slave address S slave address W W A A data data A A P

0 = Write

Each byte is acknowledged by the slave device

Combined Read and Write

<
S slave address R A

n data bytes >

A data A

1 = Read Each byte is acknowledged by the master device (except the last one, just before the STOP condition)
< m data bytes > A data data A P

data

S addressW WA Adata data Sr slave slave address A P A P

Each byte is 0 = Write Each byte is acknowledged acknowledged by the master device by the slave device (except the last one, just before the Re-START condition) DesignCon 2003 TecForum I2C Bus Overview

1 = Read

36

Acknowledge; Clock Stretching

Acknowledge Done on the 9th clock pulse and is mandatory Transmitter releases the SDA line Receiver pulls down the SDA line (SCL must be HIGH) Transfer is aborted if no acknowledge
No acknowledge
Acknowledge

Clock Stretching
- Slave device can hold the CLOCK line LOW when performing other functions - Master can slow down the clock to accommodate slow slaves
DesignCon 2003 TecForum I2C Bus Overview
37

I2C Protocol - Clock Synchronization

Master 1 CLK 1 Vdd Master 2 CLK 2

SCL

1 2

4 3

LOW period determined by the longest clock LOW period HIGH period determined by shortest clock HIGH period
DesignCon 2003 TecForum I2C Bus Overview
38

I2C Protocol - Arbitration

Two or more masters may generate a START condition at the same time Arbitration is done on SDA while SCL is HIGH - Slaves are not involved

Master 1 loses arbitration DATA1 SDA

Start command

DesignCon 2003 TecForum I2C Bus Overview

39

What do I need to drive the I2C bus?

Slave 1 Slave 2 Slave 3 Slave 4

Master
I2C BUS

There are 3 basic ways to drive the I2C bus:

1) With a Microcontroller with on-chip I2C Interface Bit oriented - CPU is interrupted after every bit transmission (Example: 87LPC76x) Byte oriented - CPU can be interrupted after every byte transmission (Example: 87C552) 2) With ANY microcontroller: 'Bit Banging
The I2C protocol can be emulated bit by bit via any bi-directional open drain port

3) With a microcontroller in conjunction with bus controller like the PCF8584 or PCA9564 parallel to I2C bus interface IC
DesignCon 2003 TecForum I2C Bus Overview
40

Pull-up Resistor calculation

DC Approach - Static Load Worst Case scenario: maximum current load that the output transistor can handle 3 mA . This gives us the minimum pull-up resistor value Vdd min - 0.4 V R= With Vdd = 5V (min 4.5 V), Rmin = 1.3 k 3 mA AC Approach - Dynamic load maximum value of the rise time: 1s for Standard-mode (100 kHz) 0.3 s for Fast-mode (400 kHz) Dynamic load is defined by: device output capacitances (number of devices) trace, wiring
DesignCon 2003 TecForum I2C Bus Overview

V(t) = VDD (1-e -t /RC ) Rising time defined between 30% and 70% Trise = 0.847.RC
41

I2C Bus recovery

Typical case is when masters fails when doing a read operation in a slave SDA line is then non usable anymore because of the Slave-Transmitter mode. Methods to recover the SDA line are: Reset the slave device (assuming the device has a Reset pin) Use a bus recovery sequence to leave the Slave-Transmitter mode Bus recovery sequence is done as following: 1 - Send 9 clock pulses on SCL line 2 - Ask the master to keep SDA High until the Slave-Transmitter releases the SDA line to perform the ACK operation 3 - Keeping SDA High during the ACK means that the Master-Receiver does not acknowledge the previous byte receive 4 - The Slave-Transmitter then goes in an idle state 5 - The master then sends a STOP command initializing completely the bus
42

DesignCon 2003 TecForum I2C Bus Overview

I2C Protocol Summary

START STOP DATA HIGH to LOW transition on SDA while SCL is HIGH LOW to HIGH transition on SDA while SCL is HIGH 8-bit word, MSB first (Address, Control, Data) - must be stable when SCL is HIGH - can change only when SCL is LOW - number of bytes transmitted is unrestricted - done on each 9th clock pulse during the HIGH period - the transmitter releases the bus - SDA HIGH - the receiver pulls DOWN the bus line - SDA LOW - Generated by the master(s) - Maximum speed specified but NO minimum speed - A receiver can hold SCL LOW when performing another function (transmitter in a Wait state) - A master can slow down the clock for slow devices - Master can start a transfer only if the bus is free - Several masters can start a transfer at the same time - Arbitration is done on SDA line - Master that lost the arbitration must stop sending data

ACKNOWLEDGE

CLOCK

ARBITRATION

DesignCon 2003 TecForum I2C Bus Overview

43

I2C Summary - Advantages

Simple Hardware standard Simple protocol standard Easy to add / remove functions or devices (hardware and software) Easy to upgrade applications Simpler PCB: Only 2 traces required to communicate between devices Very convenient for monitoring applications Fast enough for all Human Interfaces applications Displays, Switches, Keyboards Control, Alarm systems Large number of different I2C devices in the semiconductors business Well known and robust bus
DesignCon 2003 TecForum I2C Bus Overview
44

nd 2

Hour

DesignCon 2003 TecForum I2C Bus Overview

45

Overcoming Previous Limitations

DesignCon 2003 TecForum I2C Bus Overview
46

How to solve I2C address conflicts?

I2C protocol limitation: when a device does not have its I2C address programmable (fixed), only one same device can be plugged in the same bus

An I2C multiplexer can be used to get rid of this limitation

It allows to split dynamically the main I2C in several sub-branches in order to talk to one device at a time It is programmable through I2C so no additional pins are required for control More than one multiplexer can be plugged in the same I2C bus Products
# of Channels 2 4 8 Standard PCA9540 PCA9546 PCA9548 w/Interrupt Logic PCA9542/43 PCA9544/45
47

DesignCon 2003 TecForum I2C Bus Overview

I2C Multiplexers: Address Deconflict

I2C EEPROM 1 I2C EEPROM 2

MASTER

Same I2C devices with same address

I2C EEPROM 1

I2C EEPROM 2

I2C MULTIPLEXER
MASTER

The multiplexer allows to address 1 device then the other one

DesignCon 2003 TecForum I2C Bus Overview
48

How to go beyond I2C max cap load?

I2C protocol limitation: the maximum capacitive load in a bus is 400 pF. If the load is higher AC parameters will be violated.

An I2C multiplexer can be used to get rid of this limitation

It allows to split dynamically the main I2C in several sub-branches in order to divide the bus capacitive load It is programmable through I2C so no additional pins are required for control More than one multiplexer can be plugged in the same I2C bus LIMITATION: All the sub-branches cannot be addressed at the same time Products:
# of Channels 2 4 8 Standard PCA9540 PCA9546 PCA9548 w/Interrupt Logic PCA9542/43 PCA9544/45

DesignCon 2003 TecForum I2C Bus Overview

49

I2C Multiplexers: Capacitive load split

500 pF
MASTER

I2C bus

200 pF

I2C bus 2 I2C bus 3

200 pF

300 pF
MASTER

I2C MULTIPLEXER

300 pF

100 pF

I2C bus 1

The multiplexer splits the bus in two downstream 200 pF busses + 100 pF upstream
DesignCon 2003 TecForum I2C Bus Overview
50

Practical case: Multi-card application

The following example shows how to build an application where: Four identical control cards are used (same devices, same I2Caddress) Devices in each card are controlled through I2C Each card monitors and controls some digital information Digital information is: 1) Interrupt signals (Alarm monitoring) 2) Reset signals (device initialization, Alarm Reset) Each card generates an Interrupt when one (or more) device generates an Interrupt (Alarm condition detected) The master can handle only one Interrupt signal for all the application

DesignCon 2003 TecForum I2C Bus Overview

51

I2C Multiplexers: Multi-card Application

- Cards are identical - One card is selected / controlled at a time - PCA9544 collects Interrupt
I2C bus 0 Card 0 Card 1 Card 2 Card 3 0 1 I2C bus 1 I2C bus 2 I2C bus 3 1 Reset Reset Alarm 1 Alarm 1 Int Int Reset Sub System Int

PCA 9544 MASTER

INT INT0 INT1 INT2 INT3

PCA 0 95540
1 INT

Interrupt signals are collected into one signal DesignCon 2003 TecForum I2C Bus Overview

52

How to accommodate different I2C logic levels in the same bus?

I2C protocol: Due to the open drain structure of the bus, voltage level in the bus is fixed by the voltage connected to the pull-up resistor. If different voltage levels are required (e.g., master core at 1.8 V, legacy I2C bus at 5 V and new devices at 3.3 V), voltage level translators need to be used

An I2C switch can be used to accommodate those different voltage levels.

It allows to split dynamically the main I2C in several sub-branches and allow different supply voltages to be connected to the pull up resistors PCA devices are programmable through I2C bus so no additional pin is required to control which channel is active More than one channel can be active at the same time so the master does not have to remember which branch it has to address (broadcast) More than one switch can be plugged in the same I2C bus
DesignCon 2003 TecForum I2C Bus Overview
53

I2C Switches: Voltage Level Shifting

I2C device I2C device I2C device I2C device I2C device 1 2 3 4 5 Devices supplied by 3.3V and not 5.0 V tolerant

Devices supplied by 5V MASTER I2C bus

Products
# Channels 1 GTL2002 PCA9540 PCA9542/43 PCA9546 PCA9544/45 GTL2010 PCA9548 GTL2000 X X Int

I2C device I2C device I2C device 1 2 3

2 4 5 8 11

MASTER

I2C SWITCH

I2C device I2C device 4 5

5V bus 3.3V bus

DesignCon 2003 TecForum I2C Bus Overview

54

How to increase reliability of an I2C bus? (Slave devices)

I2C protocol: If one device does not work properly and hangs the bus, then no device can be addressed anymore until the rogue device is separated from the bus or reset.

An I2C switch can be used to split the I2C bus in several branches that can be isolated if the bus hangs up.
Switches allow the main I2C to be split dynamically in several sub-branches that can be: active all the time deactivated if one device of a particular branch hangs the bus When a malfunctioning sub-branch has been isolated, the other sub branches are still available It is programmable through I2C so no additional pin is required to control it More than one switch can be plugged in the same I2C bus
DesignCon 2003 TecForum I2C Bus Overview
55

Isolate I2C hanging segment(s)

Device 1 Device 2 MASTER PCA 9548 Device 3 Device 4 Device 5
RESET

Device 6 Device 7 Device 8

DesignCon 2003 TecForum I2C Bus Overview

56

Isolate hanging segments Discrete stand alone solution

P82 B96 SEGMENT 1

MASTER

P82 B96

SEGMENT 2

P82 B96

SEGMENT 3

A bus buffer isolates the branch (capacitive isolation) Its power supply is controlled by a bus sensor SDA and SCL are sensed and the sensor generates a timeout when the bus stays low Bus buffer is Hi-Z when power supply is off.
DesignCon 2003 TecForum I2C Bus Overview
57

How to increase reliability of an I2C bus? (Master devices)

I2C protocol: If the master does not work properly , reliability of the systems will decrease since monitoring or control of critical parameters are not possible anymore (voltage, temperature, cooling system)

An I2C demultiplexer can be used to switch from one failing master to its backup.
It allows to have 2 independent masters to control the bus without any fault or system corruption failed master completely isolated from the bus I2C bus is initialized by the demultiplexer before switching from one master to the other one It is programmable through I2C so no additional pin is required to control it More than one demultiplexer can be plugged in the same I2C bus
DesignCon 2003 TecForum I2C Bus Overview
58

Isolate failing master

MAIN MASTER
2C I2

Slave
SDA SCL

Demux BACKUP MASTER

Main I2C bus

Slave

Main Master control the I2C bus When it fails, backup master asks to take control of the bus Previous master is then isolated by the multiplexer Downstream bus is initialized (all devices waiting for START condition) Switch to the new master is done Products
Device PCA9541 # of upstream channels 2
59

DesignCon 2003 TecForum I2C Bus Overview

How to go beyond I2C max cap load?

I2C protocol limitation: the maximum capacitive load in a bus is 400 pF. If the load is higher AC parameters will be violated.

An I2C bus repeater or an I2C hub can be used to get rid of this limitation
It allows to double the I2C max capacitive load (repeater) or to make it 5 times higher (hub = 5 repeaters) Multi-master capable, voltage level translation All channels can be active at the same time Limitation: Repeater/hub cannot be used in series Products:
Device PCA9515 PC9516 # of repeaters 1 5 # of ENABLE pins 1 4
60

DesignCon 2003 TecForum I2C Bus Overview

I2C Bus repeater (PCA9515) and Hub (PCA9516)

Master

PCA 9515

Hub Hub 1 1

PCA 9516

Hub 2 Hub Hub 3 3 Hub 4 Hub Hub 5 5

DesignCon 2003 TecForum I2C Bus Overview

61

How to scale the I2C bus by adding 400 pF segments?

Some applications require architecture enhancements where one or several isolated I2C hubs need to be added with the capability of hub to hub communication

An expandable I2C hub can be used to easily upgrade this type of application
It allows to expand the numbers of hubs without any limit Multi-master capable, voltage level translation All channels can be active at the same time (4 channels per expandable hub can be individually disabled) Products:
Device PCA9518 # of repeaters 5 # of ENABLE pins 4
62

DesignCon 2003 TecForum I2C Bus Overview

PCA9518 Applications
Hub 4 Hub 3 Hub 2 Hub 1 Master Master Hub 12 Hub 11 Hub 10 Hub Hub 9 9
DesignCon 2003 TecForum I2C Bus Overview

Hub 8 PCA 9518 PCA 9518 Hub 7 Hub 6 Hub 5

I2C Inter Device I2C bus

Non used Hub PCA 9518 PCA 9518 Hub 15 Hub 14 Hub 13
63

How to accommodate 100 kHz and 400 kHz devices in the same I2C bus?
I2C protocol limitation: in an application where 100 kHz and 400 kHz devices (masters and/or slaves) are present in the same bus, the lowest frequency must be used to guarantee a safe behavior.

An I2C bus repeater can be used to isolate 100 kHz from 400 kHz devices when a 400 kHz communication is required
It allows to easily upgrade applications where legacy 100 kHz I2C devices share bus access with newer 400 kHz I2C devices Each side of the repeater can work with different logic voltage levels Products:

Device # of repeaters # of ENABLE pins PCA9515 1 1 DesignCon 2003 TecForum I2C Bus Overview

64

PCA9515 - Application Example

400 kHz slave devices
3.3 V SCL1 SDA1 ENABLE OPTIONAL 5.0 V SCL0 SDA0

100 kHz slave devices

MASTER 1 400 kHz

MASTER 2 100 kHz

Master 1 works at 400 kHz and can access 100 & 400 kHz slaves at their maximum speed (100 kHz only for 100 kHz devices) Master 2 works at only 100 kHz PCA9515 is disabled (ENABLE = 0) when Master 1 sends commands at 400 kHz
DesignCon 2003 TecForum I2C Bus Overview
65

How to live insert?

I2C protocol limitation: in an application where the I2C bus is active, it was not designed for insertion of new devices.

An I2C hot swap bus buffer can be used to detect bus idle condition isolate capacitance, and prevent glitching SDA & SCL when inserting new cards into an active backplane.
Repeaters work with the same logic level on each side except the PCA9512 which works with 3.3 V and 5 V logic voltage levels at the same time Products:
Device PCA9511 PCA9512 PCA9513 PCA9514 # of repeaters 1 1 1 1 # of ENABLE pins 1 0 1 1
66

DesignCon 2003 TecForum I2C Bus Overview

I2C Hot Swap Bus Buffer

PLUG SCL0 SCL1

SDA0 READY

SDA1

Card is plugged on the system - Buffer is on Hi-Z state Bus buffer checks the activity on the main I2C bus When the bus is idle, upstream and downstream buses are connected Ready signal informs that both buses are connected together
DesignCon 2003 TecForum I2C Bus Overview
67

How to send I2C commands through long cables?

I2C limitation: due to the bus 400 pF maximum capacitive load limit, sending commands over wire (80 pF/m) long distances is hard to achieve

An I2C bus extender can be used

It has high drive outputs Possible distances range from 50 meters at 85 kHz to 1km at 31 kHz over twisted-pair phone cables. Up to 400 kHz over short distances. Others applications: Multi-point applications: link applications, factory applications I2C opto-electrical isolation Infra-red or radio links Products:
Device P82B715 P82B96
DesignCon 2003 TecForum I2C Bus Overview
68

How to use a micro-controller without I2C bus or how to develop a dual master application with a single micro-controller?
Some micro-controllers integrates an I2C port, others dont

An I2C bus controller can be used to interface with the micro-controllers parallel port
It generates the I2C commands with the instructions from the micro controllers parallel port (8-bits) It receives the I2C data from the bus and send them to the micro-controller It converts by software any device with a parallel port to an I2C device

DesignCon 2003 TecForum I2C Bus Overview

69

Parallel Bus to I2C Bus Controller

Master without I2C interface

Master

PCA 9564

SDA SCL

Multi-Master capability or 2 isolated I2C bus with the same device

Master

PCA 9564

SDA1 SCL1 SDA2 SCL2

Max I2C freq 90 kHz 360 kHz Clock source External Internal Parallel interface Slow Fast
70

Products
Voltage range PCF8584 4.5 - 5.5V PCA9564 2.3 - 3.6V w/5V tolerance

DesignCon 2003 TecForum I2C Bus Overview

Development Tools and Evaluation Board Overview

DesignCon 2003 TecForum I2C Bus Overview
71

Purpose of the Development Tool and I2C Evaluation Board To provide a low cost platform that allows Field Application Engineers, designers and educators to easily test and demonstrate I2C devices in a platform that allows multiple operations to be performed in a setting similar to a real system environment.

DesignCon 2003 TecForum I2C Bus Overview

72

I2C 2002-1A Evaluation Board Kit

FEATURES - Converts Personal Computer parallel port to I2C bus master - Simple to use graphical interface for I2C commands - Win-I2CNT software compatible with Windows 95, 98, ME, NT, XP and 2000 - Order kits at www.demoboard.com
DesignCon 2003 TecForum I2C Bus Overview
73

Evaluation Board 2002-1A Kit Overview

PC -Win95/98/2000/NT/XP Parallel Port CD - ROM I2C 2002-1A Evaluation Kit I2C Cable

Win-I2CNT Win-I2CNT Software Software

Port Adapter Card

I2CPORT v2 Port I2CPORT v2 Adapter Card

I2C Cable

USB Adapter Card

USB Cable 9V Power Supply I2 I2 C C2002-1A 2002-1 Evaluation EvaluationBoard(s) Board(s)

I2C Cable 9V Power Supply I2 C2002-1A 2002-1 Evaluation I2 C EvaluationBoard(s) Board(s)

USB Cable

DesignCon 2003 TecForum I2C Bus Overview

74

I2CPORT v2 Adapter Card

The Win-I2CNT adapter connects to the standard DB-25 on any PC It can be powered by the PC or by the evaluation board

I2C 2Kbit EEPROM To the PC parallel port

To the I2C Evaluation Board I2C bus signals

Jumper JP2 I2C Voltage Selection (Bus voltage) Open = 3.3 V bus Closed = 5.0 V bus DesignCon 2003 TecForum I2C Bus Overview
75

Evaluation Board I2C 2002-1A Overview

SCL/SDA 1 Main I2C Bus I2C 2002-1A Evaluation Board 1

PCA9550

PCA9551

PCA9554

PCA9543

PCA9555

PCA9561

PCA9515

P82B96

PCA9501

PCF8582

RJ11
LM75A LM75A

3 3 3

USB A SCL1/SDA1 9V
REGULATORS

SCL2/SDA2

USB B SCL0/SDA0

3.3 V 5.0 V

12 I2C devices on the evaluation board 2 evaluation boards can be daisy chained without any address conflict Boards cascadable through I2C connectors, RJ11 phone cable or USB cable On board regulators
DesignCon 2003 TecForum I2C Bus Overview
76

Starting the Software

Clicking on the Win- I2CNT icon will start the software and will give the following window
Working Window Selection
Open the device specific screen 2 modes for the clock. Slow is adequate for slow ports and to solve some potential compatibility issue

Open the Universal modes screen

I2C Indicates the clock (SCL) frequency Indicates that I2C communications can start If problem, message WIN-I2C hardware not detected displayed Action: check Adapter Card DesignCon 2003 TecForum I2C Bus Overview

Help Hints

Parallel Port

77

Device I/O Expanders PCA9501

GPIO register value GPIO value GPIO address EEPROM address
Selected byte information

GPIO Read / Write Options

GPIO programming

Auto Write Feature

Write Time Byte 8BH or 13910

EEPROM Read / Write Options Set the all EEPROM to the same value DesignCon 2003 TecForum I2C Bus Overview

EEPROM programming
78

Device Multiplexers/Switches PCA9543

Device address Control Register Value Read / Write Operation Channel Selection

Interrupt Status

Auto Write Feature

DesignCon 2003 TecForum I2C Bus Overview

79

Device LED Drivers/Blinkers PCA9551

LED drivers states Register values Device address Auto Write Feature Read / Write Operation Frequencies and duty cycles programming DesignCon 2003 TecForum I2C Bus Overview
80

Device I/O Expanders PCA9554

Auto Write Feature Output Register Read / Write Operation (all registers)

Device address Input Register Configuratio n Register Polarity Register Register Programming Read / Write Operation (specific register)

DesignCon 2003 TecForum I2C Bus Overview

81

Device I/O Expanders PCA9555

Auto Write Feature Polarity Registers Input Registers Read / Write Operation (all registers)

Device Address Register Programming Configuration Registers Read / Write Operation (specific Register) Output Registers

DesignCon 2003 TecForum I2C Bus Overview

82

Device Non-Volatile Registers PCA9561

Device Address

EEPROMs Read / Write Operation MUX_IN Read Operation Data (EEPROM, MUX_IN) Multiplexing

Note: MUX_IN, MUX_SELECT and WP pins are not controlled by the Software
DesignCon 2003 TecForum I2C Bus Overview
83

Device Thermal Management LM75A

Auto Write Feature Read / Write Operation (all registers) Temperature monitoring

Device address

Read / Write Operation (specific register)

Device modes

Temperature Monitoring Programming frequency DesignCon 2003 TecForum I2C Bus Overview

Start Monitoring
84

Device EEPROM 256 x 8 (2K) PCA9515

Bus repeater - No software to control it Buffered I2C connector available Enable Control pin accessible

Control window and operating scheme same as PCA9501s 2KBit EEPROM

P82B96
Bus buffer - No software to control it I2C can come from the Port Adapter + USB Adapter through the USB cable I2C can be sent through RJ11 and USB cables to others boards 5.0 V and 9.0 V power supplies
DesignCon 2003 TecForum I2C Bus Overview
85

Universal Receiver / Transmitter Screen

Commands Programming

I2C sequencing parameters

Sequencer Send Sequence selected programming message DesignCon 2003 TecForum I2C Bus Overview

Programmable delay between the messages

86

How to program the Universal Screen?

Length of the messages is variable: 20 instructions max 5 different messages can be programmed First START and STOP instructions can not be removed I2C Re-Start Command S key I2C Write Command W key I2C Read Command R key Add an Instruction Insert key Remove an Instruction Delete key Data: 0 to 9 + A to F keys
DesignCon 2003 TecForum I2C Bus Overview
87

Some others interesting Features

I2C clock frequency can be modified (Options Menu). Acknowledge can be ignored for stand alone experiment (Options Menu). Universal Transmitter/Receiver program can be saved in a file. Device specific screens are different depending on the selected device. All the options are usually covered in those screens. Good tool to learn how the devices work and test all the features. Possibility to build some small applications by connecting the devices together through the headers.

DesignCon 2003 TecForum I2C Bus Overview

88

How To Obtain the New Evaluation Kit

The I2C 2002-1A Evaluation Board Kit consists of the: I2C 2002-1A Evaluation Board I2CPort v2 Adapter Card for the PC parallel port 4-wire connector cable USB Adapter Card (no USB cable included) 9 V power supply CD-ROM with operating instructions and Win-I2CNT software on that provides easy to use PC graphical interface specific to the I2C devices on the evaluation board but also with general purpose mode for all other I2C devices.

Purchase the I2C 2002-1A Evaluation Board Kit at www.demoboard.com

DesignCon 2003 TecForum I2C Bus Overview
89

rd 3

Hour

DesignCon 2003 TecForum I2C Bus Overview

90

Comparison of 2 I C with SMBus

DesignCon 2003 TecForum I2C Bus Overview
91

Some words on SMBus

Protocol derived from the I2C bus Original purpose: define the communication link between: an intelligent battery a charger a microcontroller Most recent specification: Version 2.0 Include a low power version and a normal power version can be found at: www.SMBus.org Some minor differences between I2C and SMBus: Electrical Timing Operating modes
DesignCon 2003 TecForum I2C Bus Overview
92

I2C Bus Vs SMBus - Electrical Differences

Low Power version of the SMBus Specification only The SMBus specification can be found on SMBus web site at www.SMBus.org
DesignCon 2003 TecForum I2C Bus Overview
93

I2C Bus Vs SMBus - Timing and operating modes Differences

Timing: Minimum clock frequency = 10 kHz Maximum clock frequency = 100 kHz Clock timeout = 35 ms Operating modes slaves must acknowledge their address all the time (mechanism to detect a removable devices presence)

DesignCon 2003 TecForum I2C Bus Overview

94

Intelligent Platform Management Interface (IPMI)

DesignCon 2003 TecForum I2C Bus Overview
95

Intelligent Platform Management Interface

Intel initiative in conjunction with hp, NEC and Dell Initiative consists of three specifications: IPMI for software extensions Intelligent Platform Management Bus (IPMB) for intra-chassis (in side the box) extensions Inter Chassis Management Bus (ICMB) for inter-chassis (outside of the box) extensions Needed since as the complexity of systems increase, MTBF decreases Defines a standardized, abstracted, message-based interface to intelligent platform management hardware. Defines standardized records for describing platform management devices and their characteristics. Provides a self monitoring capability increasing reliability of the systems
DesignCon 2003 TecForum I2C Bus Overview
96

Intelligent Platform Management Interface

IPMI Provides a self monitoring capability increasing reliability of the systems Monitor server physical health characteristics : temperatures voltages fans chassis intrusion General system management: automatic alerting automatic system shutdown and re-start remote re-start power control More information www.intel.com/design/servers/ipmi/ipmi.htm
DesignCon 2003 TecForum I2C Bus Overview
97

Intelligent Platform Management Bus

Standardized bus and protocol for extending management control, monitoring, and event delivery within the chassis: I2C based Multi-master Simple Request/Response Protocol Uses IPMI Command sets Supports non-IPMI devices Physically I2C but write only (master capable devices), hot swap not required. Enables the Baseboard Management Controller (BMC) to accept IPMI request messages from other management controllers in the system. Allows non-intelligent devices as well as management controllers on the bus. BMC serves as a controller to give system software access to IPMB
DesignCon 2003 TecForum I2C Bus Overview
98

IPMI Details
Defines a standardized interface to intelligent platform management hardware Prediction and early monitoring of hardware failures Diagnosis of hardware problems Automatic recovery and restoration measures after failure Permanent availability management Facilitate management and recovery Autonomous Management Functions: Monitoring, Event Logging, Platform Inventory, Remote Recovery Implemented using Autonomous Management Hardware: designed for Microcontrollers based implementations Hardware implementation is isolated from software implementation New sensors and events can then be added without any software changes
DesignCon 2003 TecForum I2C Bus Overview

99

Overall IPMI Architecture

ICMB

IPMB

BMC

DesignCon 2003 TecForum I2C Bus Overview

100

Where IPMI is being used

DesignCon 2003 TecForum I2C Bus Overview
101

Intel Server Management

Servers today run mission-critical applications. There is literally no time for downtime. That is why Intel created Intel Server Management a set of hardware and software technologies built right into most Intel sever boards that monitors and diagnoses server health. Intel Server Management helps give you and your customers more server uptime, increased peace of mind, lower support costs, and new revenue opportunities. More information:
program.intel.com/shared/products/servers/boards/server_management
DesignCon 2003 TecForum I2C Bus Overview
102

PICMG
PICMG (PCI Industrial Computer Manufacturers Group) is a consortium of over 600 companies who collaboratively develop open specifications for high performance telecommunications and industrial computing applications. PICMG specifications include CompactPCI for Eurocard, rackmount applications and PCI/ISA for passive backplane, standard format cards. Recently, PICMG announced it was beginning development of a new series of specifications, called AdvancedTCA, for next-generation telecommunications equipment, with a new form factor and based on switched fabric architectures More information - www.picmg.org

DesignCon 2003 TecForum I2C Bus Overview

103

Use of IPMI within PICMG

Known as cPCI cPCI
AdvancedTCA

Specification PICMG 2.0 PICMG 2.9 PICMG 3.x

Based on NA IPMI 1.0 IPMI 1.5

Comments No IPMB Single hot swap IPMB optional Dual redundant hot swap IPMB mandatory

PICMG 2.0: CompactPCI Core PICMG 2.9: System Management PICMG 3.0: AdvancedTCA Core 3.1 Ethernet Star (1000BX and XAUI) FC-PH links mixed with 1000BX 3.2 InfiniBand Star & Mesh 3.3 StarFabric 3.4 PCI Express
DesignCon 2003 TecForum I2C Bus Overview
104

Managed ATCA Board Example

PCA9511

PCA9511

Dual, redundant -48VDC power distribution to each card w. high current, bladed power connector High frequency differential data connectors Robust keying block Two alignment pins Robust, redundant system management 8U x 280mm card size 1.2 (6HP) pitch Flexible rear I/O connector area

DesignCon 2003 TecForum I2C Bus Overview

105

Managed ATCA Shelf: Example 1

PCA9511 PCA9511 PCA9511 PCA9511

PCA9511 PCA9511

PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511 PCA9511

DesignCon 2003 TecForum I2C Bus Overview

106

VME
Motorola, Mostek and Signetics cooperated to define the standard Mechanical standard based on the Eurocard format. Large body of mechanical hardware readily available Pin and socket connector scheme is more resilient to mechanical wear than older printed circuit board edge connectors. Hundreds of component manufacturers support applications such as industrial controls, military, telecommunications, office automation and instrumentation systems.
DesignCon 2003 TecForum I2C Bus Overview

www.vita.com
107

Use of IPMI in VME Architecture

New VME draft standard indirectly calls for IPMI over I2C for the system management protocol since there was nothing to be gained by reinventing a different form of system management for VME. The only change from the PICMG 2.9 system management specification is to redefine the backplane pins used for the I2C bus and to redefine the capacitance that a VME board can present on the I2C bus. The pin change was required because the VME backplane connectors are different from cPCI. The capacitance change was required because cPCI can have a maximum of 8 slots and VME can have a maximum of 21 slots. System Management for VME Draft Standard VITA 38 200x Draft 0.5 9 May 02 draft at www.vita.com/vso/draftstd/vita38.d0.5.pdf
DesignCon 2003 TecForum I2C Bus Overview
108

2 IC

Device Overview
109

DesignCon 2003 TecForum I2C Bus Overview

I2C Device Categories

TV Reception Radio Reception Audio Processing Infrared Control DTMF LCD display control Clocks/timers General Purpose I/O LED display control Bus Extension/Control A/D and D/A Converters EEPROM/RAM Hardware Monitors Microcontroller

DesignCon 2003 TecForum I2C Bus Overview

110

I2C Product Characteristics

Package Offerings Typically DIP, SO, SSOP, QSOP, TSSOP or HVQFN packages Frequency Range Typically 100 kHz operation Newer devices operating up to 400 kHz Graphic devices up to 3.4 MHz Operating Supply Voltage Range 2.5 to 5.5 V or 2.8 to 5.5 V Newer devices at 2.3 to 5.5 V or 3.0 to 3.6 V with 5 V tolerance Operating temperature range Typically -40 to +85 C Some 0 to +70 C Hardware address pins Typically three (AO, A1, A2) are provided to allow up to eight of the identical device on the same I2C bus but sometimes due to pin limitations there are fewer address pins
DesignCon 2003 TecForum I2C Bus Overview
111

TV Reception
The SAA56xx family of microcontrollers are a derivative of the Philips industry-standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system, OSD and incorporate an integrated Data Capture and display function for either Teletext or Closed Caption. Additional features over the SAA55xx family have been included, e.g. 100/120 Hz (2H/2V only) display timing modes, two page operation (50/60 Hz mode for 16:9, 4:3), higher frequency microcontroller, increased character storage, more 80C51 peripherals and a larger Display memory. For CC operation, only a 50/60 Hz display option is available. Byte level IC-bus up to 400 kHz dual port I/O
DesignCon 2003 TecForum I2C Bus Overview
112

Radio Reception
The TEA6845H is a single IC with car radio tuner for AM and FM intended for microcontroller tuning with the ICbus. It provides the following functions:

AM double conversion receiver for LW, MW and SW (31 m, 41 m and 49 m bands) with IF1 = 10.7 MHz and IF2 = 450 kHz FM single conversion receiver with integrated image rejection for IF = 10.7 MHz capable of selecting US FM, US weather, Europe FM, East Europe FM and Japan FM bands.
DesignCon 2003 TecForum I2C Bus Overview
113

Audio Processing
The SAA7740H is a functionspecific digital signal processor. The device is capable of performing processing for listening-environments such as equalization, hall-effects, reverberation, surround-sound and digital volume/balance control. The SAA7740H can also be reconfigured (in a dual and quad filter mode) so that it can be used as a digital filter with programmable characteristics. The SAA7740H realizes most functions directly in hardware. The flexibility exists in the possibility to download function parameters, correction coefficients and various configurations from a host microcontroller. The parameters can be passed in real time and all functions can be switched on simultaneously. The SAA7740H accepts 2 digital stereo signals in the I2S-bus format at audio sampling frequency (fast ) and provides 2 digital stereo outputs.
DesignCon 2003 TecForum I2C Bus Overview
114

DTMF/Modem/Musical Tone Generators

Modem and musical tone generation Telephone tone dialing DTMF > Dual Tone Multiple Frequency Low baud rate modem
DesignCon 2003 TecForum I2C Bus Overview
115

I2C LCD Display Driver

LCD Display Control Display size: 2 line by 12 characters + 120 icons DDRAM CGRAM Sequencer CGROM Bias voltage Voltage generator multiplier Control logic SDA SCL

Row driver

Supply

Column driver

The LCD Display driver is a complex device and is an example of how "complete" a system an I2C chip can be it generates the LCD voltages, adjusts the contrast, temperature compensates, stores the messages, has CGROM and RAM etc etc.
DesignCon 2003 TecForum I2C Bus Overview
116

I2C LCD Segment Driver

LCD Segment Control Display sizes 1 x 24 2 x 40 single chip: 4 x 40 ... 16 x 24

Control logic SDA SCL RAM

Supply

Bias voltage generator

Sequencer

Backplane drivers

Segment drivers

The LCD Segment driver is a less complex LCD driver (e.g., just a segment driver).
DesignCon 2003 TecForum I2C Bus Overview
117

I2C Light Sensor

The TSL2550 sensor converts the intensity of ambient light into digital signals that, in turn, can be used to control the backlighting of display screens found in portable equipment, such as laptops, cell phones, PDAs, camcorders, and GPS systems. The device can also be used to monitor and control commercial and residential lighting conditions. By allowing display brightness to be adjusted to ambient conditions, the sensor is expected to bring about a significant reduction in the power dissipation of portables. The TSL2550 all-silicon sensor combines two photodetectors, with one of the detectors sensitive to both visible and infrared light and the other sensitive only to IR light. The photodetectorss output is converted to a digital format, in which form the information can be used to approximate the response of the human eye to ambient light conditions sans the IR element, which the eye cannot perceive.
DesignCon 2003 TecForum I2C Bus Overview
118

I2C Real Time Clock/Calendar

Real-Time Clock / Calendar 32kHz Counters: s, min, h, day, month, year Oscillator / prescaler

Real time clocks and event counters count the passage of time and act as a chronometer They are used in applications such as:

Alarm-, TimerRegisters (240 Byte RAM 8583)

POR I2C-bus interface SDA SCL

periodic alarms for safety applications system energy conservation time and date stamp for point of sales terminals or bank machines

Interrupt

Sub address decoder

DesignCon 2003 TecForum I2C Bus Overview

119

I2C General Purpose I/O Expanders

General Purpose I/O Supply POR SDA SCL I2C-bus interface Interrupt Input/ output stages alternative analog input configurations

Sub address decoder

Transfers keyboard, ACPI Power switch, keypad, switch or other inputs to microcontroller via I2C bus Expand microcontroller via I2C bus where I/O can be located near the source or on various cards Use outputs to drive LEDs, sensors, fans, enable and other input pins, relays and timers Quasi outputs can be used as Input or Output without the use of a configuration register.
DesignCon 2003 TecForum I2C Bus Overview
120

Latches

Quasi Output I2C I/O Expanders - Registers

To program the outputs
S Address W A OUTPUT DATA A P

Multiple writes are possible during the same communication Multiple reads are possible during the same communication

To read input values

S Address R A INPUT DATA A P

Important to know
At power-up, all the I/Os are HIGH; Only a current source to VDD is active An additional strong pull-up resistors allows fast rising edges I/Os should be HIGH before using them as Inputs
DesignCon 2003 TecForum I2C Bus Overview
121

Blank

DesignCon 2003 TecForum I2C Bus Overview

122

True Output I2C I/O Expanders - Registers

To configure the device
S S Address Address W W A A 03H 02H A A CONFIG DATA POLARITY DATA A A P

No need to access Configuration and Polarity registers once programmed

To program the outputs

S Address W A 01H A OUTPUT DATA A P

Multiple writes are possible during the same communication

To read input values

S Address W A 00H A S Address R A INPUT DATA A P

Multiple reads are possible during the same communication

DesignCon 2003 TecForum I2C Bus Overview
123

True Output I2C I/O Expanders - Example

Input Reg# 1 1 0 0 0 1 0 1 Read Polarity Reg# 0 0 0 1 1 1 0 0 Read/ Write Config Reg# 1 0 0 0 1 1 1 0 Read/ Write Output Reg# X 1 0 1 X X X 1 Read/ Write I/Os
124

1 1 0 1 1 0 0 1

DesignCon 2003 TecForum I2C Bus Overview

Signal monitoring and/or Control

Advantages of I2C
Easy to implement (Hardware and Software) Extend microcontroller: I/Os can be located near the source or on various cards Save GPIOs in the microcontroller Only 2 wires needed, independently of the numbers of signals Signal(s) can be far from the masters Fast enough to control keyboards Simplify the PCB layout Devices exist in the market and are massively used

DesignCon 2003 TecForum I2C Bus Overview

125

Signal monitoring and/or Control

Proposed devices
# of Outputs Interrupt and POR POR and 2K EEPROM Interrupt, POR and 2K EEPROM

Quasi Output (20-25 ma sink and 100 uA source) 8 PCF8574/74A PCA9500/58 PCA9501 16 PCF8575/75C -

# of Outputs

Reset and POR

Interrupt and POR

True Output (20-25 ma sink and 10 mA source) 8 PCA9556/57 PCA9534/54/54A 16 PCA9535/55

Advantages
Number of I/O scalable Programmable I2C address allowing more than one device in the bus Interrupt output to monitor changes in the inputs Software controlling the device(s) easy to implement
DesignCon 2003 TecForum I2C Bus Overview
126

I2C LED Dimmers and Blinkers

Supply POR SDA SCL Sub address decoder I2C-bus interface alternative analog input configurations Reset Input/ output stages

I2C/SMBus is not tied up by sending repeated transmissions to turn LEDs on and then off to blink LEDs. Frees up the micros timer Continues to blink LEDs even when no longer connected to bus master Can be used to cycle relays and timers Higher frequency rate allows LEDs to be dimmed by varying the duty cycle for Red/Green/Blue color mixing applications.
DesignCon 2003 TecForum I2C Bus Overview
127

Oscillator

I2C LED Blinkers and Dimmers

Frequency Duty Cycle 0 (00H) 40 Hz 100 % 0 (00H) 160 Hz 0%
256 - PWM0 256

255 (FFH) 6.4 s 0.4 % 255 (FFH) 1.6 s 99.6 % Blinkers Dimmers

0 Input 0 0 0 0 0 Register(s) 0 0 0 0 0 PWM0 0 0 0 0 0 0 0 PSC0 0 0 0 0

Frequency Duty Cycle

PWM0 256

ON
PSC0 + 1 160 PWM1 256

OFF
PSC0 + 1 40 256 - PWM1 256

ON

OFF

0 PWM1 0 0 0 0 0 0 0 PSC1

ON
PSC1 + 1 160

OFF
PSC1 + 1 40

ON
ON = OFF =

OFF ON
LED ON LED OFF

0 0Selector 0 0 LED

ON, OFF, BR1, BR2

128

DesignCon 2003 TecForum I2C Bus Overview

I2C Blinkers and Dimmers - Programming

To program the 2 blinking rates
S Address W A PSC0 pointer PSC1 A A PSC0 PWM1 A A P PWM0 A

PSC0 pointer = 01H for 2, 4 and 8-bit devices PSC0 pointer = 02H for the 16-bit devices

To program the drivers

S Address W A LED SEL0 pointer LEDSEL2 A A LEDSEL0 LEDSEL3 A A P LEDSEL1 A

LEDSEL0 pointer = 05H for 2, 4 and 8-bit devices LEDSEL0 pointer = 06H for the 16-bit devices Only the 16-bit devices have 4 LED selector registers (8-bit devices have 2 registers, 2 and 4-bit devices have only one)
DesignCon 2003 TecForum I2C Bus Overview
129

Using I2C for visual status

Use LEDs to give visual interpretation of a specific action: alarm status (using different blinking rates) battery charging status 1st approach: I2C GPIOs Advantage: Simple programming Easy to implement Inconvenient: Need to continually send ON/OFF commands through I2C 1 microcontrollers timer required to perform the task I2C bus can be tied up by commands if many LEDs to be controlled Blinking is lost if the I2C bus hangs 2nd approach: I2C LED Blinkers Advantage: One time programmable (frequency, duty cycle) Internal oscillator Easy to implement Device does not need I2C bus once programmed and turned on
DesignCon 2003 TecForum I2C Bus Overview
130

Using I2C for visual status

Products:
# of Outputs 2 4 8 16 Reset and POR PCA9550 PCA9553 PCA9551 PCA9552

LED Blinkers
Blinking between 40 times a second to once every 6.4 seconds

# of Outputs 2 4 8 16

Reset and POR PCA9530 PCA9533 PCA9531 PCA9532

LED Dimmers
Blinking between 160 times a second to once every 1.6 seconds. Can be used for dimming/brightness or PWM for stepper motor control

DesignCon 2003 TecForum I2C Bus Overview

131

I2C DIP Switches

MUX Select Pin I2C Bus EEPROM Non MUX Output Pin Hardware Output Pins Mux

Hardware Input Pins

Non-volatile EEPROM retains values when the device is powered down Used for Speed Step notebook processor voltage changes when on AC/battery power or when in deep sleep mode Also used as replacement for jumpers or DIP switches since there is no requirement to open the equipment cabinet to modify the jumpers/DIP switch settings
DesignCon 2003 TecForum I2C Bus Overview
132

I2C Dip Switches

I2C Bus Write Protect

Mux Select

I2C INTERFACE / EEPROM Control

Mode Selection

0 0 0 0

0EEPROM 0 0 0 0 0EEPROM 0 0 1 0 0EEPROM 0 0 2 0 0EEPROM 0 0 3 0

0 0 0 0

MUX

0HARDWARE 0 0 0 Value 0 0

PCA9561
6 Bits
DesignCon 2003 TecForum I2C Bus Overview
133

I2C DIP Switches - PCA9561

To program the 4 EEPROMS
S Address W A A 00H EEPROM 2 A A EEPROM 0 EEPROM 3 A A EEPROM 1 P A

To read the 4 EEPROMS

S Address W A 00H EEPROM 1 A A S Address A R A EEPROM 0 A P A

EEPROM 2

EEPROM 3

To read the Hardware value

S Address W A FFH A S Address R A HW VALUE A P

To select the mode

S Address W A FXH A P
134

DesignCon 2003 TecForum I2C Bus Overview

I2C Multiplexers
I2C Bus I2C Controller
OFF

I2C Bus 0 I2C Bus 1 Interrupt 0 Interrupt 1

Interrupt Out

FEATURES -Fan out main I2C/SMBus to multiple channels -Select off or individual downstream channel -I2C/SMBus commands used to select channel -Power On Reset (POR) opens all channels -Interrupt logic provides flag to master for system monitoring.

KEY POINTS -Many specialized devices have only one I2C address and sometimes many are needed in the same system. -Multiplexers allow the master to communicate to one downstream channel at a time but dont isolate the bus capacitance -Other Applications include sub-branch isolation.

DesignCon 2003 TecForum I2C Bus Overview

135

I2C Switches
I2C Bus Reset Interrupt Out
OFF

I2C Bus 0 I2C Bus 1 Interrupt 0 Interrupt 1

I2C Controller

OFF

Switches allow the master to communicate to one channel or multiple downstream channels at a time Switches dont isolate the bus capacitance Other Applications include: sub-branch isolation and I2C/SMBus level shifting (1.8, 2.5, 3.3 or 5.0 V)
DesignCon 2003 TecForum I2C Bus Overview
136

I2C Multiplexers & Switches Programming

To connect the upstream channel to the selected downstream channel(s)
S PCA954x Address W A CHANNEL SELECTION A P

Selection is done at the STOP command

To access the downstream devices on the selected channel

S Device Address W A Command A P

Once the downstream channel selection is done, there is no need to access (Write) the PCA954x Multiplexer or Switch The device will keep the configuration until a new configuration is required (New Write operation on the PCA954x)
DesignCon 2003 TecForum I2C Bus Overview
137

I2C 2 to 1 Master Selector

Master 0 I2C Bus Master 1 I2C Bus Interrupt 0 Out Interrupt 1 Out Slave Card I2C Bus

I2C Interrupt In Controller

Interrupt In Reset

Master Selector selects from two I2C/SMBus masters to a single channel I2C/SMBus commands used to select master Interrupt outputs report demultiplexer status Sends 9 clock pulses/stop to clear slaves prior to transferring master
DesignCon 2003 TecForum I2C Bus Overview

138

Master Selector in Multi-Point Application

PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541

DesignCon 2003 TecForum I2C Bus Overview

Master 0

Master 1
139

Master Selector in Point-Point Application

Master 1

Master 1

Master 1

Master 1

PCA9541

PCA9541

PCA9541

PCA9541

Master 0

Master 0

Master 0

Master 0

DesignCon 2003 TecForum I2C Bus Overview

140

I2C Bus Bi-Directional Voltage Level Translation

1.8 V 200 K 1.5 V 1.2 V 1.0 V 5V

GTL2002
GND GREF

VCORE

SREF DREF S1 S2 D1 D2

VCC

CPU I/O

Chipset I/O

Voltage translation between any voltage from 1.0 V to 5.0 V Bi-directional with no direction pin Reference voltage clamps the input voltage with low propagation delay Used for bi-directional translation of I2C buses at 3.3 V and/or 5 V to the processor I2C port at 1.2 V or 1.5 V or any voltage in-between BiCMOS process provides excellent ESD performance
141

DesignCon 2003 TecForum I2C Bus Overview

I2C Bus Repeater and Hub

400 pF

SCL0
400 pF

SCL1 SDA1
400 pF
400 pF

400 pF

SDA0

Enable
I2C Bus Repeater PCA9515

400 pF

400 pF

5-Channel I2C Hub PCA9516

Bi-directional I2C drivers isolate the I2C bus capacitance to each segment. Multi-master capable (e.g., repeater transparent to bus arbitration and contention protocols) with only one repeater delay between segments. Segments can be individually isolated Voltage Level Translation 3.3 V or 5 V voltage levels allowed on the segment
DesignCon 2003 TecForum I2C Bus Overview
142

I2C Hot Swap Bus Buffer

PCA9511 PCA9512 PCA9513 PCA9514

SCL SDA

Allows I/O card insertion into a live backplane without corruption of busses Control circuitry connects card after stop bit or idle occurs on the backplane Bi-directional buffering isolates capacitance, allows 400 pF on either side Rise time accelerator allows use of weaker DC pull-up currents while still meeting rise time requirements SDA and SCL lines are precharged to 1V, minimizing current required to charge chip parasitic capacitance
DesignCon 2003 TecForum I2C Bus Overview
143

I2C Bus Extenders

Note: Schottky diode or Zener clamps may be needed to limit spurious signals on very long wiring

I2C Bus Extender P82B715

KEY POINTS High drive outputs are used to extend the reach of the I2C bus and exceed the 400 pF/system limit. Possible distances range from 50 meters at 85kHz to 1km at 31kHz over twisted-pair phone cable. Bus Buffer has split high drive outputs allowing differential transmission or Dual Bi-Directional Bus Buffer Opto-isolation of the I2C Bus.

P82B96
144

DesignCon 2003 TecForum I2C Bus Overview

Changing I2C bus signals for multi-point applications

3.3/5V 12V 12V Twisted-pair telephone wires, USB or flat ribbon cables
Up to 15V logic levels, Include VCC & GND

SCL 3.3/5 12V

NO LIMIT to the number of connected bus devices ! 3.3V

SDA P82B96
Link parking meters and pay stations

P82B96
SDA/SCL

P82B96
SDA/SCL

P82B96
SDA/SCL

P82B96
SCL SDA

Link vending machines to save cell phone links ------

------

Warehouse pick/pack systems

Factory automation Access/alarm systems Video, LCD & LED display signs Hotel/motel management systems Monitor emergency lighting/exit signs

------

DesignCon 2003 TecForum I2C Bus Overview

145

Changing I2C bus signals for driving long distances

Remote Control Enclosure 3.3 -5V 12V
12V

Long cables
SCL 3.3-5V 12V

SDA P82B96 P82B96

Bi-directional data streams Special logic levels (I2C compatible 5V) I2C currents (3mA)

Simply link the pins for Bi-directional data streams Conventional CMOS logic levels (2-15V) Higher current option, up to 30mA static sink

Twisted-pair telephone wires, Re-combine to bi-directional I2C USB or flat ribbon cables 2V through 12V logic levels Able to send VCC and GND 100 meters at 70kHz NO LIMIT to the number of connected devices ! Convert the logic signal levels back to I2C compatible Hot Swap Protection
146

DesignCon 2003 TecForum I2C Bus Overview

Changing I2C bus signals for Opto-isolation

3.3/5V

Vcc 1

Vcc 2

SCL

SCL 3.3/5V P82B96 SDA

SDA

Bi-directional data streams Special logic levels ( I2C compatible 5V) I2C currents (3mA)

Low cost Optos can be directly driven (10-30mA) VCC 1 = 2 to 12V Higher current option, up to 30mA static sink

4N36 Optos for ~5kHz 6N137 for 100kHz

Re-combined to I2C

I2C compatible levels HCPL-060L for 400 kHz e.g. Vcc 2 = 5V

Controlling equipment on phone lines AC Mains switches, lamp dimmers Isolating medical equipment
147

DesignCon 2003 TecForum I2C Bus Overview

Rise Time Accelerators

The LTC1694-1 is a dual SMBus active pullup designed to enhance data transmission speed and reliability under all specified SMBus loading conditions. The LTC1694-1 is also compatible with the Philips I2C Bus. The LTC1694-1allows multiple device connections or a longer, more capacitive interconnect, without compromising slew rates or bus performance, by supplying a high pull-up current of 2.2 mA to slew the SMBus or I2C lines during positive bus transitions During negative transitions or steady DC levels, the LTC1694-1 sources zero current. External resistors, one on each bus line, trigger the LTC1694-1 during positive bus transitions and set the pull-down current level. These resistors determine the slew rate during negative bus transitions and the logic low DC level.
DesignCon 2003 TecForum I2C Bus Overview
148

Parallel Bus to I2C Bus Controller

I2C Bus
Operation Control Control
Bus Buffer

Chip Enable Write Strobe Read Strobe Reset Address Inputs Interrupt Request Data (8-bits)

Controls all the I2C bus specific sequences, protocol, arbitration and timing Serves as an interface between most standard parallel-bus microcontrollers/ microprocessors and the serial I2C bus. Allows the parallel bus system to communicate with the I2C bus
DesignCon 2003 TecForum I2C Bus Overview
149

Microcontroller

I2C Interface

Digital Potentiometers
DS1846 nonvolatile (NV) tripotentiometer, memory, and MicroMonitor. The DS1846 is a highly integrated chip that combines three linear-taper potentiometers, 256 bytes of EEPROM memory, and a MicroMonitor. The part communicates over the industry-standard 2-wire interface and is available in a 20-pin TSSOP. The DS1846 is optimized for use in a variety of embedded systems where microprocessor supervisory, NV storage, and control of analog functions are required. Common applications include gigabit transceiver modules, portable instrumentation, PDAs, cell phones, and a variety of personal multimedia products.
DesignCon 2003 TecForum I2C Bus Overview
150

Analog to Digital Converter

Supply POR Oscillator, intern / extern + + + + + Sub address decoder Analog reference +

INT SDA SCL

Interrupt I2C-bus interface ADC / DAC

These devices translate between digital information communicated via the I2C bus and analog information measured by a voltage. Analog to digital conversion is used for measurement of the size of a physical quantity (temperature, pressure ), proportional control or transformation of physical amplitudes into numerical values for calculation. Digital to analog conversion is used for creation of particular control voltages to control DC motors or LCD contrast.
151

4 channel Analog to Digital 1 channel Digital to Analog

DesignCon 2003 TecForum I2C Bus Overview

Blank

DesignCon 2003 TecForum I2C Bus Overview

152

I2C Serial CMOS RAM/EEPROMs

EEPROM

Standard Sizes
128 x 8-byte (1 kbit) 256 x 8-byte (2 kbit) 512 x 8-byte (4 kbit) 1024 x 8-byte (8 kbit) 2048 x 8-byte (16 kbit) 4096 x 8-byte (32 kbit) 8192 x 8-byte (64 kbit) 16384 x 8-byte (128 kbit) 32768 x 8-byte (256 kbit) 65536 x 8-byte (512 kbit) 24C01 24C02 24C04 24C08 24C16 24C32 24C64 24C128 24C256 24C512

RAM
Address pointer

Address pointer POR

POR I2C-bus interface

Supply SDA SCL

256 Byte RAM

256 I2C-bus Byte Sub address interface Sub decoder E2PROM address decoder Sub address decoder

IC bus is used to read and write information to and from the memory Electrically Erasable Programmable Read Only Memory 1,000,000 write cycles, unlimited read cycles 10 year data retention
DesignCon 2003 TecForum I2C Bus Overview
153

I2C Hardware Monitors

Remote Sensor

Digital Temperature Sensor and Thermal I2C Temperature Monitor NE1617A NE1618 Watchdog LM75A I2C Temperature and Voltage Monitor(Heceta4) NE1619

Sense temperature and/or monitor voltage via IC Remote sensor can be internal to microprocessor
DesignCon 2003 TecForum I2C Bus Overview
154

I2C Microcontroller
Ports 0, 1, 2, 3 8K ISP 512B 768B IAP Data SRAM Flash EEPROM Timer 0/1 16-bit

Analog Comparators

The master can be either a bus controller or controller and provides the brains behind the I2C bus operation. A bus controller adds I2C bus capability to a regular controller without I2C, or to add more I2C ports to controllers already equipped with an I2C port such as the: P87LPC76x 100 kHz I2C P89C55x 100 kHz I2C P89C65x 100 kHz I2C P89C66x 100 kHz I2C P89LPC932 400 kHz I2C
155

600% Accelerated C51 Core Keypad/ Pattern Match Interrupt Internal 2.5% 7.3728 MHz RC Oscillator

Power Management, RTC, WDT, power-on-reset, brownout detect 32xPLL 16-bit PWM CCU Enh. UART I2C SPI

Microcontrollers with Multiple Serial ports can convert from: I2C to UART/RS232 LPC76x, 89C66x and 89LPC9xx I2C to SPI - P87C51MX and 89LPC9xx family I2C to CAN - 8 bit P87C591 and 16 bit PXA-C37
DesignCon 2003 TecForum I2C Bus Overview

2 IC

Patent and Legal Information

156

DesignCon 2003 TecForum I2C Bus Overview

I2C Patent Information

The I2C bus is protected by patents held by Philips. Licensed IC manufacturers that sell devices incorporating the technology already have secured the rights to use these devices, relieving the burden from the purchaser. A license is required for implementing an I2C interface on a chip (IC, ASIC, FPGA, etc). It is Philips's position that all chips that can talk to the I2C bus must be licensed. It doesnt matter how this interface is implemented. The licensed manufacturer may use its own know how, purchased IP cores, or whatever. This also applies to FPGAs. However, since the FPGAs are programmed by the user, the user is considered a company that builds an I2C-IC and would need to obtain the license from Philips. Apply for a license or text of the Philips I2C Standard License Agreement
US and Canadian companies: contact Mr. Piotrowski ([email protected]) All other companies: contact Mr. Hesselmann ([email protected]) DesignCon 2003 TecForum I2C Bus Overview
157

Questions And Answers

Philips Semiconductors
Specialty Logic Product Line Booth 836 Download AN10126-01 I2C Manual for speaker notes for this presentation
DesignCon 2003 TecForum I2C Bus Overview
158