Introduction to ASIC Design 1.
BIT & BIT_VECTOR
2-level logic (0, 1).
Examples SIGNAL x: BIT; -- x is declared as a one-digit signal of type BIT. SIGNAL y: BIT_VECTOR (3 DOWNTO 0); -- y is a 4-bit vector, with the leftmost bit being the MSB. SIGNAL w: BIT_VECTOR (0 TO 7); -- w is an 8-bit vector, with the rightmost bit being the MSB. Based on the signals above, the following assignments would be legal (to assign a value to a signal, the <= operator must be used): x <= '1'; -- x is a single-bit signal (as specified above), whose value is -- '1'. Notice that single quotes (' ') are used for a single bit. y <= "0111"; -- y is a 4-bit signal (as specified above), whose value is "0111" -- (MSB='0'). Notice that double quotes (" ") are used for -- vectors. w <= "01110001"; -- w is an 8-bit signal, whose value is "01110001" (MSB='1'). 2. STD_LOGIC (and STD_LOGIC_VECTOR) 8-valued logic system introduced in the IEEE 1164 standard X Forcing Unknown 0 Forcing Low 1 Forcing High Z High impedance W Weak unknown L Weak low H Weak high Dont care Examples: SIGNAL x: STD_LOGIC; -- x is declared as a one-digit (scalar) signal of type STD_LOGIC. (synthesizable unknown) (synthesizable logic 1) (synthesizable logic 0) (synthesizable tri-state buffer)
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VHDL Data Types SIGNAL y: STD_LOGIC_VECTOR (3 DOWNTO 0) := "0001"; -- y is declared as a 4-bit vector, with the leftmost bit being -- the MSB. The initial value (optional) of y is "0001". Notice -- that the ":=" operator is used to establish the initial value. 3. STD_ULOGIC (STD_ULOGIC_VECTOR) 9-level logic system introduced in the IEEE 1164 standard (U, X, 0, 1, Z, W, L, H, ).
4. BOOLEAN: True, False. 5. INTEGER: 32-bit integers (from 2,147,483,647 to 2,147,483,647).
6. NATURAL: Non-negative integers (from 0 to 2,147,483,647). 7. REAL: Real numbers ranging from 1.0E38 to 1.0E38. Not synthesizable.
8. Physical literals: Used to inform physical quantities, like time, voltage, etc. Useful in simulations. Not synthesizable. 9. Character literals: Single ASCII character or a string of such characters. Not synthesizable. 10. SIGNED and UNSIGNED: data types defined in the std_logic_arith package of the ieee library. They have the appearance of STD_LOGIC_VECTOR, but accept arithmetic operations, which are typical of INTEGER data types (SIGNED and UNSIGNED will be discussed in detail in section 3.6). 11. Collective Examples x0 <= '0'; -- bit, std_logic, or std_ulogic value '0' x1 <= "00011111"; -- bit_vector, std_logic_vector, -- std_ulogic_vector, signed, or unsigned
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Introduction to ASIC Design x2 <= "0001_1111"; -- underscore allowed to ease visualization x3 <= "101111" -- binary representation of decimal 47 x4 <= B"101111" -- binary representation of decimal 47 x5 <= O"57" -- octal representation of decimal 47 x6 <= X"2F" -- hexadecimal representation of decimal 47 n <= 1200; -- integer m <= 1_200; -- integer, underscore allowed IF ready THEN... -- Boolean, executed if ready=TRUE y <= 1.2E-5; -- real, not synthesizable q <= d after 10 ns; -- physical, not synthesizable 12. Legal and illegal operations between data of different types SIGNAL a: BIT; SIGNAL b: BIT_VECTOR(7 DOWNTO 0); SIGNAL c: STD_LOGIC; SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL e: INTEGER RANGE 0 TO 255; ... a <= b(5); -- legal (same scalar type: BIT) b(0) <= a; -- legal (same scalar type: BIT) c <= d(5); -- legal (same scalar type: STD_LOGIC) d(0) <= c; -- legal (same scalar type: STD_LOGIC)
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VHDL Data Types a <= c; -- illegal (type mismatch: BIT x STD_LOGIC) b <= d; -- illegal (type mismatch: BIT_VECTOR x -- STD_LOGIC_VECTOR) e <= b; -- illegal (type mismatch: INTEGER x BIT_VECTOR) e <= d; -- illegal (type mismatch: INTEGER x -- STD_LOGIC_VECTOR) 13. User-Defined Data Types Two categories of user defined data types are shown below: integer and enumerated. TYPE integer IS RANGE -2147483647 TO +2147483647; -- This is indeed the pre-defined type INTEGER. TYPE natural IS RANGE 0 TO +2147483647; -- This is indeed the pre-defined type NATURAL. TYPE my_integer IS RANGE -32 TO 32; -- A user-defined subset of integers. TYPE student_grade IS RANGE 0 TO 100; -- A user-defined subset of integers or naturals. -- User-defined enumerated types: TYPE bit IS ('0', '1'); -- This is indeed the pre-defined type BIT TYPE my_logic IS ('0', '1', 'Z'); -- A user-defined subset of std_logic. TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT; -- This is indeed the pre-defined type BIT_VECTOR. -- RANGE <> is used to indicate that the range is unconstrained. -- NATURAL RANGE <>, on the other hand, indicates that the only -- restriction is that the range must fall within the NATURAL -- range. TYPE state IS (idle, forward, backward, stop); -- An enumerated data type, typical of finite state machines. TYPE color IS (red, green, blue, white); -- Another enumerated data type.
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Introduction to ASIC Design
14. Subtypes A SUBTYPE is a TYPE with a constraint. The subtypes below were derived from the types presented in the previous examples. SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH; -- As expected, NATURAL is a subtype (subset) of INTEGER. SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z'; -- Recall that STD_LOGIC=('X','0','1','Z','W','L','H','-'). -- Therefore, my_logic=('0','1','Z'). SUBTYPE my_color IS color RANGE red TO blue; -- Since color=(red, green, blue, white), then -- my_color=(red, green, blue). SUBTYPE small_integer IS INTEGER RANGE -32 TO 32; -- A subtype of INTEGER. 15. Legal and illegal operations between types and subtypes SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1'; SIGNAL a: BIT; SIGNAL b: STD_LOGIC; SIGNAL c: my_logic; ... b <= a; --illegal (type mismatch: BIT versus STD_LOGIC) b <= c; --legal (same "base" type: STD_LOGIC) 16. Arrays Arrays are collections of objects of the same type. Example: 1Dx1D array TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array SIGNAL x: matrix; -- 1Dx1D signal
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VHDL Data Types Example: Another 1Dx1D array. TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); -- 1Dx1D Array Example: 2D array TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array Example: Array initialization. ... :="0001"; -- for 1D array ... :=('0','0','0','1') -- for 1D array ... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or -- 2D array 17. Legal and illegal array assignments. The assignments in this example are based on the following type definitions and signal declarations: TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array TYPE array1 IS ARRAY (0 TO 3) OF row; -- 1Dx1D array TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0); -- 1Dx1D TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D array SIGNAL x: row; SIGNAL y: array1; SIGNAL v: array2; SIGNAL w: array3; --------- Legal scalar assignments: --------------The scalar (single bit) assignments below are all legal because the "base" (scalar) type is STD_LOGIC for all signals (x,y,v,w).
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Introduction to ASIC Design
x(0) <= y(1)(2); -- notice two pairs of parenthesis -- (y is 1Dx1D) x(1) <= v(2)(3); -- two pairs of parenthesis (v is 1Dx1D) x(2) <= w(2,1); -- a single pair of parenthesis (w is 2D) y(1)(1) <= x(6); y(2)(0) <= v(0)(0); y(0)(0) <= w(3,3); w(1,1) <= x(7); w(3,0) <= v(0)(3); -------------------- Vector assignments: --------------------x <= y(0); -- legal (same data types: ROW) x <= v(1); -- illegal (type mismatch: ROW x STD_LOGIC_VECTOR) x <= w(2); -- illegal (w must have 2D index) x <= w(2, 2 DOWNTO 0); -- illegal (type mismatch: ROW x STD_LOGIC) v(0) <= w(2, 2 DOWNTO 0); -- illegal (mismatch: STD_LOGIC_VECTOR x STD_LOGIC) v(0) <= w(2); -- illegal (w must have 2D index) y(1) <= v(3); -- illegal (type mismatch: ROW x STD_LOGIC_VECTOR) y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0); -- legal (same type, same size) v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0); -- legal (same type, -- same size) w(1, 5 DOWNTO 1) <= v(2)(4 DOWNTO 0); -- illegal (type mismatch)
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VHDL Data Types 18. Records Records are similar to arrays, with the only difference that they contain objects of different types. Example TYPE birthday IS RECORD day: INTEGER RANGE 1 TO 31; month: month_name; END RECORD; 19. Signed and Unsigned Data Types These types are defined in the std_logic_arith package of the ieee library. Their syntax is illustrated in the examples below. Examples SIGNAL x: SIGNED (7 DOWNTO 0); SIGNAL y: UNSIGNED (0 TO 3);
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