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Architecture of PIC16C74A

Fig 17.2 Basic Architecture of PIC 16C74A The basic architecture of PIC16C74A is shown in fig 17.2. The architecture consists of Program memory, file registers and RAM, ALU and CPU registers. It should be noted that the program Counter is 13 - bit and the program memory is organised as 14 - bit word. Hence the program Memory capacity is 8k x 14 bit. Each instruction of PIC 16C74A is 14 - bit long. The various CPU registers are discussed here. CPU registers (registers commonly used by the CPU) W, the working register, is used by many instructions as the source of an operand. This is similar to accumulator in 8051. It may also serve as the destination for the result of the instruction execution. It is an 8 - bit register. STATUS Register The STATUS register is a 8-bit register that stores the status of the processor. This also stores carry, zero and digit carry bits. STATUS - address 03H, 83H C = Carry bit DC = Digit carry (same as auxiliary carry) Z = Zero bit NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode RP0- Register bank select bit used in conjunction with direct addressing mode. FSR Register (File Selection Register, address = 04H, 84H) FSR is an 8-bit register used as data memory address pointer. This is used in indirect addressing mode.

INDF Register (INDirect through FSR, address = 00H, 80H) INDF is not a physical register. Accessing INDF access is the location pointed to by FSR in indirect addressing mode. PCL Register (Program Counter Low Byte, address = 02H, 82H) PCL is actually the lower 8-bits of the 13-bit program counter. This is a both readable and Program Counter Stack An independent 8-level stack is used for the program counter. As the program counter is 13bit, the stack is organized as 8x13bit registers. When an interrupt occurs, the program counter is pushed onto the stack. When the interrupt is being serviced, other interrupts remain disabled. Hence, other 7 registers of the stack can be used for subroutine calls within an interrupt service routine or within the mainline program. Port Structure and Pin Configuration of PIC 16C74A PIC 16C74A has 5 I/O Ports. Each port is a bidirectional I/O port. In addition, they have the following alternate functions.

Fig. Pin configuration of PIC 16C74A

Instruction Set: The instruction set for PIC16C74A consists of only 35 instructions. Some of these instructions are byte oriented instructions and some are bit oriented instructions. The byte oriented instructions that require two parameters (For example, movf f, F(W)) expect the f to be replaced by the name of a special purpose register (e.g., PORTA) or the name of a RAM variable (e.g., NUM1), which serves as the source of the operand. 'f' stands for file register. The F(W) parameter is the destination of the result of the operation. It should be replaced by: F, if the destination is to be the source register. W, if the destination is to be the working register (i.e., Accumulator or W register). The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here 'f' is to be replaced by the name of a special purpose register or the name of a RAM variable. The 'b' parameter is to be replaced by a bit number ranging from 0 to 7. For example: Z equ 2 btfsc STATUS, Z Z has been equated to 2. Here, the instruction will test the Z bit of the STATUS register and will skip the next instruction if Z bit is clear. The literal instructions require an operand having a known value (e.g., 0AH) or a label that represents a known value. For example: NUM equ 0AH ; movlw NUM ; Assigns 0AH to the label NUM ( a constant ) will move 0AH to the W register.

Every instruction fits in a single 14-bit word. In addition, every instruction also executes in a single cycle, unless it changes the content of the Program Counter. These features are due to the fact that PIC micro controller has been designed on the principles of RISC (Reduced Instruction Set Computer) architecture. Instruction set: Mnemonics bcf f, b bsf f, b clrw Description Clear bit b of register f Set bit b of register f Clear working register W Instruction Cycles 1 1 1

Encoding of instruction: As has been discussed, each instruction is of 14-bit long. These 14-bits contain both op-code and the operand. Some examples of instruction encoding are shown here. Example-1: bcf f, b Clear 'b' bit of register 'f'

Operands: Encoding:

0 f 127 0b7

The instruction is executed in one instruction cycle, i.e., 4 clock cycles. The activities in various clock cycles are as follows.

Discussion on I/O ports of PIC16C74A: PIC16C74A has five I/O ports. Port-B, Port-C and Port-D have 8 pins each. Port-A and PortE have 6 and 3 pins respectively. Each port has bidirectional digital I/O capability. In addition, these I/O ports are multiplexed with alternate functions for the peripheral devices on the microcontroller. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port latch has a corresponding TRIS (Tri-state Enable) register for configuring the port either as an input or as an output. The port pins are designated by the alphabet R, followed by the respective port (viz. A, B, C, D or E) and the pin number. For example, Port-A pins are named as RA0, RA1, etc. Port-A Port-A pins RA0-RA3 and RA5 are similar. These pins function (alternate function) as analog inputs to the analog-to-digital converter.

Fig 19.1 RA0-RA3 and RA5 pin of Port-A The structure of Port-A pins RA0-RA3 and RA5 is shown in the figure. TRISA register decides whether the port-pin is configured as an input or as an output (digital) pin. Setting a TRISA register bit puts the corresponding output driver in high impedance mode. In this mode, the pin can be used as a digital or analog input. Clearing a bit in the TRISA register puts the contents of the data latch on the selected pins, i.e., the pin functions as a digital output. Pins RA0-RA and RA5 have current sourcing capability of 25mA.

The alternate function of RA4 pin is Timer-0 clock input (T0CKI). RA4 pin is an open drain pin and hence requires external pull-up when configured as output pin. It is shown in the following figure.

Fig 19.2 RA4 pin Configuration Configuration of Port-A pins Example : Set RA0-RA3 as outputs and RA4 - RA5 as inputs. bcf STATUS, RP0 ; clrf PORTA ; bsf STATUS, RP0 ; movlw 30H ; movwf TRISA ; Port-B Port-B is an 8-bit bidirectional I/O port. The data direction in Port-B is controlled by TRISB register. Setting a bit in TRISB register puts the corresponding output in high impedance input mode. When a bit in TRISB is made zero, the corresponding pin in Port-B outputs the content of the latch (output mode). Each port pin has a weak internal pull-up that can be enabled by clearing bit of OPTION register (bit-7). When a pin is configured in the output mode, the weak pull-up is automatically turned off. Internal pull-up is used so that we can directly drive a device from the pins. Fig 19.3 Pins RB0-RB3 of Port-B Select Bank-0 Clears the data latch Select Bank-1 W 03H ( data direction ) Set RA0-RA3 as outputs, RA4-RA5 as inputs

Overview of Timer Modules : PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0 and Timer-2 are 8-bit timers. Timer-1 is a 16-bit timer. Each timer module can generate an interrupt on timer overflow. Timer-0 Overview: The timer-0 module is a simple 8-bit UP counter. The clock source can be either the internal clock (fosc /4) or an external clock. When the clock source is external, the Timer-0 module can be programmed to increment on either the rising or falling clock edge. Timer-0 module has a programmable pre-scaler option. This pre-scaler can be assigned either to Timer-0 or the Watch dog timer, but not to both. The Timer-0 Counter sets a flag T0IF (Timer-0 Interrupt Flag) when it overflows and can cause an interrupt at that time if that interrupt source has been enabled, (T0IE = 1), i.e., timer0 interrupt enable bit = 1. OPTION Register Configuration : Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock source. The following OPTION register configuration is for clock source = fosc /4 and no Watchdog timer.

Timer-0 use without pre-scalar Internal clock source of f osc /4. (External clock source, if selected, can be applied at RA4/TOCKI input at PORTA). The following diagram shows the timer use without the prescaler.

Fig 20.1 Timer - 0 operation without prescaler

Timer-0 use with pre-scalar: The pre-scalar can be used either with the Timer-0 module or with the Watchdog timer. The pre-scalar is available for Timer-0 if the pre-scalar assignment bit PSA in the OPTION register is 0. Pre-scalar is a programmable divide by n counter that divides the available clock by a pre-specified number before applying to the Timer-0 counter.

Fig 20.2 Timer - 0 with prescaler

Timer - 1 Module Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000H to FFFFH and rolls over to 0000H. The TMR1 interrupt, if enabled, is generated on overflow, which sets the interrupt flag bit TMR1IF (bit-0 of PIR1 register). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (bit-0 of the PIE1 register). The operating and control modes of Timer1 are determined by the special purpose register T1CON. Various bits of T1CON register are given as follows:-

T1CON Register TMR1 ON : TMR1CS : Timer1 ON bit 0 = stops Timer 1; 1 = Enables Timer 1 Timer 1 Clock source Select Bit ;1 = External Clock (RCO/T1OSO/T1CKI) ) : Timer 1 External Clock Input

0 = Internal Clock ( Synchronization Bit (Valid if TMR1CS = 1)

1 - Do not synchronize 0 - Synchronize T1OSCEN: Oscillator enable control bit 1 = Oscillator is enabled 0 = Oscillator is shut off

Timer 1 Input Clock Prescaler

Select bits T1CKPS1 T1CKPS0 1 1 1 0 0 1 0 0

Prescaler Value 1:8 1:4 1:2 1:1

Fig 21.2

Operation of Timer 1

Timer 1 can operate in one of the two modes

As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in every instruction cycle. The timer 1 clock source is . Since the internal clock is selected, the timer is always synchronized and there is no further need of synchronization. As a counter (TMR1CS = 1). In the counter mode, external clock input from the pin RCO/T1CKI is selected.

Timer 2 Overview

Fig 21.3 Schematic diagram showing operation of Timer 2 Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be used as the PWM time base for PWM mode of capture compare PWM (CCP) modules. The TMR2 register is readable and writable and is cleared on device reset. The input clock ( ) has a pre-scaler option of 1:1, 1:4 or 1:16 which is selected by bit 0 and bit 1 of T2CON register respectively. The Timer 2 module has an 8bit period register (PR2). Timer-2 increments from 00H until it is equal to PR2 and then resets to 00H on the next clock cycle. PR2 is a readable and writable register. PR2 is initailised to FFH on reset. The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to generate a TMR2 interrupt by setting TMR2IF.

Fig 21.4 The T2CON Register Capture / Compare /PWM (CCP) Modules: PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit register (two 8-bit registers) and can operate in one of the three modes, viz., 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The details of the two modules (CCP1 and CCp2) are given as follows. CCP1 Module: CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1 Module. CCP2 Module:

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CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and CCPR2H (high byte). The CCP1CON register controls the operation of CCP2 Module. Both CCP1 and CCP2 modules are identical in operation with the exception of the operation of special event trigger. The following table shows the timer resources for the CCP Mode. CCP Mode Capture Compare Timer Used Timer 1 Timer 1

PWM Timer 2 CCP1CON Register (Address 17H ) CCP2CON Register is exactly similar to CCP1CON register. CCP2CON Register address is 1DH. CCP1CON controls CCP module1 where as CCP2CON controls CCP Module2.

Bit 5-4: CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Capture mode. In PWM Mode, these bits are the two Lsbs of the PWM duty cycle. The eight Msbs are found in CCPR1. Thus the PWM mode operates in 10-bit mode. Bit 3-0: CCP1M3:CCP1MO (CCP1 Mode select bits) 0000=Capture/Compare/PWM Mode off 0100=Capture mode, every falling edge 0101=Capture mode, every rising edge 0110=Capture mode, every 4 th rising edge 0111=Capture mode, every 16 th rising edge 1000=Compare mode, set output on match (CCP1IF bit is set) 1001=Compare mode, clear output on match (CCP1IF bit is set) 1010=Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin unaffected) 1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets Tmr1; CCP2 resets TMR1 and starts A/D conversion if A/D module is Enabled) 11XX=PWM mode. Capture Mode (CCP1): Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L register pair in response to an event occurring on RC2/CCP1 pin. Capture Mode for CCP2 is exactly similar to that of CCP1. An event on RC2/CCP1 pin is defined as follows:

Every falling edge Every rising edge. Every 4 th rising edge.

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Every 16 th rising edge.

As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register. Schematic diagram for capture mode of operation

Fig 22.1 Capture operation

Required condition for capture mode: 1. RC2/CCP1 pin should be configured as an input by setting TRISC (bit 2). 2. Timer 1 should be operated from the internal clock (fosc/4), i.e., timer mode or in synchronized counter mode. Compare Mode (CCP1) Compare mode for CCP2 is similar to that of CCP1, except that in special event trigger mode, CCP1 resets TMR1 only, whereas CCP2 resets TMR1 and starts A/D conversion if A/D module is enabled. In compare mode, the 16-bit CCPR1 register value is compared against TMR1 register pair (TMR1H and TMR1L) value. When a match occurs, the RC2/CCP1 pin is driven high or driven low or remains unchanged as decided by CCP1CON<3:0> bits.

Fig 22.2 Compare Operation Required conditions for compare mode 1. RC2/CCP1 pin must be configured as an output by clearing TRISC<2> bit. 2. Timer-1 should be operated in timer mode (i.e., internal clock source of fosc/4) or in synchronized counter mode. In software interrupt mode, CCP1IF bit is set but CCP1 pin in unaffected. As shown in the figure, in special event trigger mode, both CCP1 and CCP2 intiates an A/D conversion. PWM mode (CCP1) Both CCP1 and CCP2 have similar operation in PWM mode. Here we will

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discuss PWM with respect to CCP1. In PWM mode, the CCP1 pin produces upto a 10-bit resolution Pulse Width Modulation (PWM) output. RC2/CCP1 pin should be configured in the uotput mode by clearing TRISC<2> bit. The schematic block diagram of CCP1 module in PWM mode is shown in the figure.

Fig 22.3 PWM Operation It can be noted that PR2 (Period Register, 8 bit) decides the PWM period where CCPR1L (8bits) and CCP1CON <5:4> (2-bits) decide the PWM duty cycle. When TMR2 equals PR2, the SR latch is set and RC2/CCP1 pin is pulled high. In the same time, TMR2 is cleared and the duty cycle value available in CCPR1L is latched to CCPR1H. CCPR1H, CCP1CON <5:4> decide the duty cycle and when this 10-bit ewquals the TMR2+2 prescaler or Q-bits, the SR latch is set and RC2/CCP1 pin is driven low.

A PWM output as shown has a time period. The time for which the output stays high is called duty cycle. PWM Period The PWM period is specified by writing to PR2 register. The PWM period can be calculated using the following formula: PWM period = [( PR 2) + 1] 4 T osc (TMR2 prescale value) PWM frequency = 1/ PWM period When TMR2 is equal to PR2, the following events occur on the next increment cycle.

TMR2 is cleared the CCP1 pin is set (if PWM duty cycle is 0

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The PWM duty cycle is latched from CCPR1L into CCPR1H

ADC Module An analog-to-digital converter (ADC) converts an analog signal into an equivalent digital number. PIC 16C74A has an inbuilt ADC with the following features

8-bit conversion 8 analog input channels An analog multiplexer A sample and hold circuit for signal on the selected input channel Alternative clock sources for carrying out conversion Adjustable sampling rate Choice of an internal or external reference voltage Interrupt to microcontroller on end of conversion

Port A and Port E pins are used for analog inputs/reference voltage for ADC. In A/D conversion, the input analog voltage is digitized and an equivalent digital output is generated as shown in the figure.

Port-A pins (Alternate functions) RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/Vref RA4/TOCKI RA5/ /AN4 port. can be used as analog input-0 can be used as analog input-1 can be used as analog input-2 can be used as analog input-3 or analog reference voltage clock input to Timer-0 can be used for analog input 4 or slave select for the synchronized serial

Port-E pins (Alternate functions) RE0/ RE1/ RE2/ /AN5 - can be used as analog input-5 /AN6 - can be used as analog input-6 /AN7 - can be used as analog input-7

PIC microcontroller has internal sample and hold circuit. The input signal should be stable across the capacitor before the conversion is initiated.

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Fig 23.2 Sample and Hold Circuit After waiting for the sampling time, a conversion can be initiated. The ADC Circuit will open the sampling switch and carry out the conversion of the input voltage as it was at the moment of opening of the switch. Upon completion of the conversion, the sampling switch is again closed and VHold once again tracks VSource. Using the A/D Converter Registers ADCON1, TRISA, and TRISE must be initialized to select the reference voltage and input channels. The first step selects the ADC clock from among the four choices (fosc/2, fosc/8, fosc/32, and RC). The constraint for selcting clock frequency is that the ADC clock period must be 1.6micro seconds or greater. The A/D module has 3registers. These registers are:

A/D result register (ADRES) A/D control register 0 (ADCON 0) A/D control register 1 (ADCON 1)

The ADCON0 register, which is shown below, controls the operation of A/D module.

Fig 23.3 ADCON0 register Bit 7-6 - A/D Clock select bits ADCS1:ADCS0 00 = fosc/2 01 = fosc/8 10 = fosc/32 11 = fRC- clock derived from an internal RC oscillator Bit 5-3 - A/D Channel Select CHS2:CHS0 000 - Channel 0 - AN0 001 - Channel 1 - AN1 010 - Channel 2 - AN2 011 - Channel 3 - AN3 100 - Channel 4 - AN4 101 - Channel 5 - AN5 110 - Channel 6 - AN6 111 - Channel 7 - AN7 Bit 2 - A/D conversion status bit

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GO / if A/D Converter is enabled (ie. ADON = 1) then If GO / = 1, A/D conversion is in progress (setting this bit starts A/D conversion) If GO / = 0, A/D conversion is not in progress (This bit is automatically cleared by hardware when A/D conversion is complete) Bit1 - Unimplemented Bit 0 - ADON: A/D On bit 1. A/D Converter module is ON 2. A/D Converter module is OFF ADCON1 Register This register specifies the analog inputs

PCFG2:PCFG0 RA0 000 001 010 011 100 101 11X A A A A A A

Fig 23.4 ADCON1 register RA1 RA2 RA5 RA3 RE0 A A A A A A A A A A D D A A A A D D A VREF A VREF A VREF A A D D D D

RE1 A A D D D D

RE2 A A D D D D

VREF VDD RA3 VDD RA3 VDD RA3 -

D D D D D D D D Fig 23.5 PCFG2:PCFG0 = A/D Port configuration control bits A = Analog input D = Digital I/O

Fig 23.6 Schematic diagram of A/D convertor analog inputs and reference voltage Steps for A/D conversion 1. Configure A/D module Configure analog inputs/voltage reference and digital I/O (ADCON1)

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Select A/D Channel (ADCON0) Select A/D Conversion Clock (ADCON0) Turn on A/D Module (ADCON0)

2. Configure A/D Interrupt (Optional)

Clear ADIF bit in PIR1 register Set ADIE bit in PIE1 register Set GIE bit

3. Wait for required acquisition time 4. Start Conversion - set GO/ bit (ADCON0) bit or by waiting

5. Wait for A/D conversion to complete, by either polling GO/ for the A/D interrupt 6. Read A/D result registers (ADRES). Clear ADIF if required.

I2C Communication in PIC Microcontroller I 2C stands for Inter-Integrated circuit. I 2C communication is a two wire bi-directional interface for connecting one or more master processors with one or more slave devices, such as an EEPROM, ADC, RAM, LCD display, DAC, etc. I 2C interface requires two open drain I/O pins, viz. SDA (Serial Data) and SCL (Serial Clock). The reason for open drain connection is that the data transfer is bi-directional and any of the devices connected to the I 2C bus can drive the data line (SDA). The serial clock line (SCL) is usually driven by the master. Since SDA and SCL pins are open drain pins, external pull-up resistances are required for operation of I 2C bus. A typical I2C bus showing the connection of multi-master and multi-slave configuration is shown in the following figure.

Fig 26.1 Multimaster Multislave Connection Some conventions are followed in I2C communication. Let us assume that there is one master and one slave and 8-data bits are sent. We will initially assume that the master is the transmitter and the slave is the receiver. The clock is driven by the master. On receiving 8bits, an acknowledgement bit is driven by the receiver on SDA line. The acknowledgement bit is usually Low (0). The following diagram shows the data communication pattern having 8 data bits and one acknowledgement bit.

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Fig 26.2 Timing diagram for data transfer The following features are to be noted 1. SDA line transmits/ receives data bits. MSB is sent first. 2. Data in SDA line is stable during clock (SCL) high. A new bit is initiated at the negative clock transition after a specified hold time. 3. Serial clock (SCL) is driven by the master. 4. An acknowledgement bit (0) is driven by the receiver after the end of reception. If the receiver does not acknowledge, SDA line remains high (1). I2C bus transfer consists of a number of byte transfers within a START condition and either another START condition or a STOP condition. During the idle state when no data transfer is taking place, both SDA and SCL lines are released by all the devices and remains high. When a master wants to initiate a data transfer, it pulls SDA low followed by SCL being pulled low. This is called START condition. Similarly, when the processor wants to terminate the data transfer it first releases SCL (SCL becomes high) and then SDA. This is called a STOP condition. START and STOP conditions are shown in the diagram as follows.

Fig 26.3 Timing diagram for START and STOP Conditions START and STOP conditions are unique and they never happen within a data transfer. Data Communication Protocol: In I2C communication both 7-bit and 10-bit slave addressing are possible. In 7-bit addressing mode 128 slaves can be interfaced with a single master. Similarly, in 10-bit addressing mode, 1024 slaves can be interfaced with the master. We will discuss here 7-bit addressing mode only. 10-bit addressing mode is similar to 7-bit addressing except from the fact that the number of address bits is more. Following a 'start' condition, the master sends a 7-bit address of the slave on SDA line. The MSB is sent first. After sending 7-bit address of the slave peripheral, a R/ (8th bit) bit is sent by the master. If R/ bit is '0', the following byte (after the acknowledgement bit) is written by the master to the addressed slave peripheral. If R/ =1, the following byte (after the acknowledgement bit) has to be read from the slave by the master. After sending the 7-bit address of the slave, the master sends the address (usually 8 bit) of the internal register of the slave wherefrom the data has to be read or written to. The subsequent access is automatically directed to the next address of the internal register. The following diagrams give the general format to write and read from several peripheral internal registers. Fig 26.4 Data transfer protocol for writing to a slave device

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R/ (Read / Write) bit indicates whether the data is to be written by the master or read by the master. If R/ is 1, the subsequent data are to be read by the master. If R/ = 0, the subsequent data are to be written by the master to the addressed slave. It has to be noted that the slave address is sent first, following a 'start' condition. The addressed slave responds by acknowledging and gets ready for data transfer. If data has to be read from a specific address of the slave device, the master sends the 7-bit address of the slave first following a 'start' condition. R/ bit is sent as 'low'. The addressed slave acknowledges by pulling the ACK line low. The master then sends the 8-bit internal address of the slave from which data has to be read. The slave acknowledges. Since R/ bit was initially 0, the master is in the write mode. To change this to read mode, the 'start' condition is again generated followed by 7-bit address of the slave with R/ = 1. The slave acknowledges. The slave then sends data from previously specified internal address to the master. The master acknowledges by pulling ACK bit low. The data transfer stops when the master does not acknowledge the data reception and a 'stop' condition is generated.