Higher Institute for Applied Science and Technology
Department of Communication Engineering
Quartus II MegaFunctions:
Lpm_mux,inv,xor
FPGA Laboratory
Massaken Barzeh
Damascus, Syria
Prepared by
Ali Deeb & Hasan Ahmad
Supervisor: Eng. Hisham Saadaldin
27 April 2013, Third Semester
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Abstract
In This Homework , we firstly deploy frequency divider to test 4:1 bit lpm_mux. Then we build
the multiplexer using lpm_inv and lpm_xor.
Table of Contents
1 Introduction .............................................................................................................................................. 11
.................................................................................................................................................................... 11
2 Project 1: Test Circuit for a 4 bit to 1 lpm_Mux ...................................................................................... 11
2.1 Frequency divider using lpm_counter: ................................................................................................. 11
[Link] diagram forTest Circuit ................................................................................................................. 12
[Link] Simulation ........................................................................................................................... 12
2.4 Timing simulation ................................................................................................................................. 13
3 Multiplexer design using lpm_inv and lpm_xor ...................................................................................... 13
3.1 Block diagram ....................................................................................................................................... 13
3.2 Functional Simulation ........................................................................................................................... 14
3.2.1 Timing Simulation ............................................................................................................................. 14
Figure 1:Circuit Schematic ......................................................................................................................... 11
Figure [Link] Mux Truth table ...................................................................................................................... 11
Figure 7:project 2 Block Diagram .............................................................................................................. 13
Figure 8:Functional Simulation .................................................................................................................. 14
Figure 9 :Timing simulation. ...................................................................................................................... 14
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1 Introduction
The basic function of a multiplexer: combining multiple inputs into a single data stream. A multiplexer of
2n inputs has n select lines, which are used to select which input line to send to the output. Figure 2 shows
the truth table of 4:1 Mux .And Figure 1 shows the corresponding circuit schematic.
In Section two we will use the predefined lpm_mux megafunction .While in section 3 we will use the
lpm_inv and lpm_xor.
Figure [Link] Mux Truth table
Figure 1:Circuit Schematic
2 Project 1: Test Circuit for a 4 bit to 1 lpm_Mux
In the first lab session we have designed a 4:1 Mux using 2:1 Mux .In order to test the circuit we
have programmed the DE1 baord at first, then we Manually changed the values of the switches
and observed the output on LEDS. In This section we build a Test circuit in which 4 signals with
different frequencies are generated at the input ports. Hence The output frequency of the mux
indicates the selected signal.
2.1 Frequency divider using lpm_counter:
To provide the different frequencies, we design frequency divider. We will use the lpm_counter to divide
the 10ns clock into 4 clocks
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[Link] diagram forTest Circuit
Figure 3:Block diagram of Test circuit
[Link] Simulation
Functional simulates the behavior of flattened netlists (connectivity of the design) extracted from the
design files. That means that it doesnt take into account the processing and the transmission time.
Figure 4:Project1_functional Simulation
We clearly see how the output frequency(the selected signal) is consistent with the truth table.
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2.4 Timing simulation
Timing uses a fully compiled netlist that includes estimated or actual timing information to test
both the logical operation and the timing of your design in the target device.
The timing simulation indicates that we have a delay of the order of 14 ns
3 Multiplexer design using lpm_inv and lpm_xor
To use lpm_inv and lpm_xor in a small project we rebuilt the previous.4to1 mux.
3.1 Block diagram
Figure 5:project 2 Block Diagram
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3.2 Functional Simulation
Figure 6:Functional Simulation
The functional simulation is consistent with the truth table which indicates the validity of our schematic.
3.2.1 Timing Simulation
Figure 7 :Timing simulation.
The figure indicates that there is a delay of the order of 22ns but its a long time so we probably havent
calculated the time delay properly.
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