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The Programmable Logic Data Book April 1998

, XILINX, XACT, XC2064, XC3090, XC4005, XC-DS501, FPGA Architect, FPGA Foundry, NeoCAD, NeoCAD EPIC, NeoCAD PRISM, NeoROUTE, Plus Logic, Plustran, P+, Timing Wizard, and TRACE are registered trademarks of Xilinx, Inc. , all XC-prex product designations, XACTstep, XACTstep Advanced, XACTstep Foundry, XACT-Floorplanner, XACT-Performance, XAPP, XAM, X-BLOX, X-BLOX plus, XChecker, XDM, XDS, XEPLD, XPP, XSI, Foundation Series, BITA, Congurable Logic Cell, CLC, Dual Block, FastCLK, FastCONNECT, FastFLASH, FastMap, HardWire, LCA, Logic Cell, LogiCore, LogicProfessor, MicroVia, PLUSASM, PowerGuide, PowerMaze, Select-RAM, SMARTswitch, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Spartan, Spartan-XL and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company and The Programmable Gate Array Company are service marks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx devices and products are protected under one or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822;

4,750,155; 4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,853,626; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135; 5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238; 5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181; 5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153; 5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189; 5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021; 5,450,022; 5,453,706; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707; 5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608; 5,500,609; 5,502,000; 5,502,440; RE 34,363, RE 34,444, and RE 34,808. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx ofcer is prohibited. Copyright 1998 Xilinx, Inc. All Rights Reserved.

The Programmable Logic Data Book

Xilinx Home Page (WWW): XDOCS E-mail Document Server: Application Service Centers North America Hotline: http://www.xilinx.com/ (Answers Database, File Download) [email protected] send E-mail with help in the header 1-408-879-5199 (USA, Xilinx headquarters) 1-800-255-7778 (North America) 1-408-879-4442 (FAX) [email protected] (44) 1932-820821 (44) 1932-828522 [email protected] (33) 1-3463-0100 (33) 1-3463-0959 [email protected] (49) 89-93088-130 (49) 89-93088-188 [email protected] (81) 3-3297-9163 (81) 3-3297-0067 [email protected] (82) 2-761-4277 (82) 2-761-4278 [email protected] (85) 2-2424-5200 (85) 2-2424-7159 [email protected] 1-800-624-4782 www.xilinx.com

Email: United Kingdom Hotline: Fax: Email: France Hotline: Fax: Email: Germany Hotline: Fax: Email: Japan Hotline: Fax: Email: Korea Hotline: Fax: Email: Hong Kong Hotline: Fax: Email: Software Authorization and Licensing: On-Line Authorization:

2100 Logic Drive San Jose, California 95124 United States of America Telephone: (408) 559-7778 Fax: (408) 559-7114

On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1998 Data Book, and thank you for your interest in Xilinx products and services. As the inventor of Field Programmable Gate Array technology and the worlds leading supplier of programmable logic, we would like to pledge our continuing commitment to providing you, our users, with the best possible integrated circuit components, development systems, and technical and sales support. Over the past year, we have substantially enhanced our product line with the introduction of the XC4000XL, XC4000XV, and Spartan series of FPGAs, as well as XH3 FpgASIC Hardwire technology. We have continued to enhance our leading-edge products with new speed grades and improved pricing. The Alliance and Foundation series products have set a new standard for functionality and ease-of-use in programmable logic development systems. You can expect this pace of innovation to continue, and even increase, as we maintain our leadership role in bringing leading-edge programmable logic solutions to the market. We look forward to satisfying all of your programmable logic needs.

Sincerely,

Wim Roelandts Chief Executive Ofcer

Section Titles

1 2 3 4 5 6 7 8 9

Introduction Development System Products and CORE Solutions Products CPLD Products FPGA Products SPROM Products 3V Products HardWire FpgASIC Products High-Reliability and QML Military Products Programming Support

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Table of Contents

Introduction
An Introduction to Xilinx Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Development System Products and CORE Solutions Products

Development Systems: Products Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Development Systems: Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 CORE Solutions Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13

CPLD Products
XC9500 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 XC9500 In-System Programmable CPLD Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 XC9536 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 XC9572 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 XC95108 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 XC95144 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 XC95216 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 XC95288 In-System Programmable CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

FPGA Products
XC4000E and XC4000X Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 XC4000E and XC4000X Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . 4-5 XC4000XV Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-155 XC4000XLT Family Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-175 Spartan and Spartan-XL Families Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-187 Spartan and Spartan-XL Families Field Programmable Gate Arrays . . . . . . . . . . . . . . . 4-189 XC5200 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-243 XC5200 Series Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-247

XC3000 Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-319 XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L). . . . . . . . . . 4-321

SPROM Products
XC1701L (3.3V), XC1701 (5.0V) and XC17512L (3.3V) Serial Configuration PROMs . . . 5-1 XC1700E Family of Serial Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Spartan and Spartan-XL Families of Serial Configuration PROMs . . . . . . . . . . . . . . . . . 5-23

3V Products
3.3 V and Mixed Voltage Compatible Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1

HardWire FpgASIC Products

Xilinx HardWire FpgASIC Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1

High-Reliability and QML Military Products

High-Reliability and QML Military Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 XC4000X Series High-Reliability Field Programmable Gate Arrays . . . . . . . . . . . . . . . . 8-7 XC4000E High-Reliability Series Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 XC4000E High-Reliability Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . 8-11

Programming Support
HW-130 Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1

Packages and Thermal Characteristics

Packages and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

Testing, Quality, and Reliability

Quality Assurance and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1

Technical Support and Services

Technical Support And Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1

Product Technical Information

XC3000, XC4000, and XC5200: A Technical Overview for the First-Time User . . . . . . . 13-5 Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 I/O Characteristics of the XL FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 XC4000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 XC3000 Series Technical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 FPGA Configuration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 Configuring Mixed FPGA Daisy Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39 Configuration Issues: Power-up, Volatility, Security, Battery Back-up . . . . . . . . . . . . . 13-41 Dynamic Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-45 Metastable Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-47 Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-50 Overshoot and Undershoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51 Boundary Scan in XC4000 and XC5200 Series Devices . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52

Index
Book Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1

Introduction

1 2 3 4 5 6 7 8 9

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Introduction Table of Contents

An Introduction to Xilinx Products

About this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Book Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Logic vs. Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Faster Design and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shortest Time-to-Market . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Field Programmable Gate Arrays (FPGAs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Complex Programmable Logic Devices (CPLDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HardWire devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC3000 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spartan Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC5200 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9500 Series Product Selection Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-1 1-1 1-2 1-2 1-3 1-3 1-3 1-3 1-3 1-4 1-4 1-4 1-4 1-5 1-5 1-5 1-6 1-6 1-7 1-7 1-8

An Introduction to Xilinx Products

1 1*

November 10, 1997

About this Book

This Data Book provides a snapshot in time in its listing of IC devices and development system software available from Xilinx as of late 1997. New devices, speed grades, package types and development system products are continually being added to the Xilinx product portfolio. Users are encouraged to contact their local Xilinx sales representative and consult the WebLINX World Wide Web site and the quarterly XCELL newsletter for the latest information regarding new product availability. This book covers the current XC4000E/EX/XL, XC4000XV, XC4000XLT, Spartan, XC5200, XC3000A/L, XC3100A/L, XC9500, XC1700D/L and XC1701L. The product specications for several older Xilinx FPGA families are not included in this Data Book. This does not imply that these products are no longer available. However, for new designs, users are encouraged to use the newer products described in this book, which offer better performance at lower cost than the older technologies. Product specications for the older products are available at WebLINX, the Xilinx site on the World Wide Web, or through your local Xilinx sales representative.

Chapter 2 contains a discussion of the overall design methodology when using Xilinx programmable logic and descriptions of Xilinx development system products. This chapter is placed at the beginning of the book since these development tools are needed to design with any of the Xilinx programmable logic devices. Chapter 3 contains the product descriptions for the Xilinx Complex Programmable Logic Device (CPLD) products, including the XC9000 series. Chapter 4 includes the product descriptions for the Xilinx static-memory-based Field Programmable Gate Array (FPGA) products, including the XC3000, XC4000, XC5000, and Spartan series. Chapter 5 holds the product descriptions for the XC1701L and XC1700D families of Serial PROM devices. These Serial PROMs provide a convenient, low-cost means of storing conguration programs for the SRAM-based FPGAs described in Chapter 4. Chapter 6 is an overview of Xilinx components appropriate for 3.3 V and mixed-voltage systems. This chapter will refer you back to the appropriate product descriptions in the earlier chapters. Chapter 7 contains a brief overview of the HardWire product line. Detailed product specications are available in separate Xilinx data sheets. Chapter 8 is an overview of Xilinx High-Reliability/Military products. Detailed product specications are available in separate Xilinx data sheets. Chapter 9 describes the HW130 device programmer for the XC170X series of Serial PROMs and the XC9500 series of CPLDs. Chapter 10 contains a description of all the physical packages for the various IC products, including information about the thermal characteristics of those packages. Chapter 11 discusses the testing, quality, and reliability of Xilinx component products. Chapter 12 includes a listing of all the technical support facilities provided by Xilinx. Chapter 13 contains additional information about Xilinx components that is not provided in the product specications of the earlier chapters. This includes some additional electrical parameters that are not in the product specications because they are not part of the manufacturing test program for the particular device, but may be of interest to the user. Also included in this chapter is a discussion of the 1-1

Data Sheet Categories

In order to provide the most up-to-date information, some component products included in this book may not have been fully characterized at the time of publication. In these cases, the AC and DC characteristics included in the data sheets will be marked as Advance or Preliminary information. (Not withstanding the denitions of such terms, all specications are subject to change without notice.) These designations have the following meaning: Advance Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, but not for nal production. Preliminary Based on preliminary characterization. Changes are possible, but not expected. Final (unmarked) Specications not identied as either Advance or Preliminary are to be considered nal.

Data Book Contents

Chapter 1 is a general overview of the Xilinx product line, and is recommended reading for designers who are new to the eld of high-density programmable logic.

November 10, 1997

An Introduction to Xilinx Products

JTAG boundary test scan logic found in several Xilinx component families. The nal two sections contain an index to the topics included in this Data Book and a listing of Xilinx sales ofces, sales representatives, and distributors.

About the Company

Xilinx, Inc., offers the industrys broadest selection of programmable logic devices. With 1997 revenues of over $560 million, Xilinx is the worlds largest supplier of programmable logic, and the market leader in Field Programmable Gate Arrays (FPGAs). Xilinx was founded in 1984, based on the revolutionary idea of combining the logic density and versatility of gate arrays with the time-to-market advantages and convenience of user-programmable standard parts. One year later, Xilinx introduced the worlds rst Field Programmable Gate Array. Since then, through a combination of architectural and manufacturing process improvements, the company has continually increased device performance, in terms of capacity, speed, and ease-of-use, while lowering costs. In 1992, Xilinx expanded its product line to include advanced Complex Programmable Logic Devices (CPLDs). For the user, CPLDs are an attractive complement to FPGAs, offering simpler design software and more predictable timing.

As the market leader in one of the fastest growing segments of the semiconductor industry, Xilinx strategy is to focus its resources on creating new ICs and development system software, providing world-class technical support, developing markets, and building a diverse customer base across a broad range of geographic and end-use application segments. The company has avoided the large capital commitment and overhead burden associated with sole ownership and operation of a wafer fabrication facility. Instead, Xilinx has established alliances with several high-volume, state-of-the-art CMOS IC manufacturers. Using standard, high-volume processes assures low manufacturing costs, produces programmable logic devices with well-established reliability, and provides for early access to advances in CMOS processing technology. Xilinx headquarters are located in San Jose, California. The company markets its products worldwide through a network of direct sales ofces, manufacturers representatives, and distributors (as listed in the back of this book). The company has representatives and distributors in over 38 countries.

Product Line Overview

Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) can be used in virtually any digital logic system. Over 50 million Xilinx components have been used in a wide variety of end-equipment applications, ranging from supercomputers to hand-held

1-2

November 10, 1997

instruments, from central ofce switches to centrifuges, and from missile guidance systems to guitar synthesizers. Xilinx achieved its leading position through a continuing commitment to provide a complete product solution. This encompasses a focus on all three critical areas of the high-density programmable solution triangle: components (silicon), software, and service (Figure 2).

one-third of its lifetime potential prot. With mask-programmed gate arrays, design iterations can easily add that much time, and more, to a product schedule. Once the decision has been made to use Xilinx programmable logic, a choice must be made from a number of product families, device options, and product types. The information in the product selection matrices that follow can help guide that selection; detailed product specications are available in subsequent chapters of this book. Since many component products are available in common packages with common footprints, designs often can be migrated to higher or lower density devices, or even across some product families, without any printed circuit board changes. Design ideas, represented in text or schematic format, are converted into a conguration data le for an FPGA or CPLD device using the Xilinx XACTstep development software running on a PC or workstation.

Programmable Logic vs. Gate Arrays

Xilinx programmable logic devices provide the benets of high integration levels without the risks or expenses of semi-custom and custom IC development. Some of the benets of programmable logic versus mask-programmed gate arrays are briey discussed below.

Faster Design and Verication

Xilinx FPGAs and CPLDs can be designed and veried quickly while the same process requires several weeks with gate arrays. There are no non-recurring engineering (NRE) costs, no test vectors to generate, and no delay while waiting for prototypes to be manufactured.

Component Products
Xilinx offers the broadest line of programmable logic devices available today, with hundreds of products featuring various combinations of architectures, logic densities, package types, and speed grades in commercial, industrial, and military grades. This breadth of product offerings allows the selection of the programmable logic device that is best suited for the target application. Xilinx programmable logic offerings include several families of reprogrammable FPGAs and FLASH-memory-based CPLDs (Figure 3). HardWire devices are mask-programmed versions of the reprogrammable FPGAs, and provide a transparent, no-risk migration path to lower-cost devices for high-volume, stable designs. Additionally, a family of Serial PROM devices is available to store conguration programs for the reprogrammable FPGA devices. Many devices are available in military temperature range

Design Changes without Penalty

Because the devices are software-congured and user-programmed, modications are much less risky and can be made anytime - in a manner of minutes or hours, as opposed to the weeks it would take with a gate array. This results in signicant cost savings in design and production.

Shortest Time-to-Market
When designing with Xilinx programmable logic, time-to-market is measured in days or a few weeks, not the months often required when using gate arrays. A study by market research rm McKinsey & Co. concluded that a six-month delay in getting to market can cost a product

Optimized circuits/architectures
SO

Powerful but easy

Highest performance/densities
LI

Integrated across families Seamless integration into customer CAE system

Deep submicron processes Unmatched quality and reliability

S E RV I C E Global world class sales/distribution support Global world class technical support: FAEs/support center/on-line/internet Global world class manufacturing: quality/capacity/delivery
X5955

Figure 2: The Xilinx Programmable Solution Triangle

November 10, 1997

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An Introduction to Xilinx Products

and/or MIL-STD-883B versions, for high-reliability and military applications.

Complex Programmable Logic Devices (CPLDs)

Designers more comfortable with the speed, design simplicity, and predictability of PALs may prefer CPLD devices. Conceptually, CPLDs consist of multiple PAL-like function blocks that can be interconnected through a switch matrix (Figure 5). The XC9000 CPLD series features 5V in-system programmable FLASH technology, and, like most of the FPGA families, includes built-in JTAG boundary scan test logic.

Field Programmable Gate Arrays (FPGAs)

FPGA devices feature a gate-array-like architecture, with a matrix of logic cells surrounded by a periphery of I/O cells, as diagrammed in Figure 4. Segments of metal interconnect can be linked in an arbitrary manner by programmable switches to form the desired signal nets between the cells. FPGAs combine an abundance of logic gates, registers, and I/Os with fast system speed. Xilinx offers several families of reprogrammable, static-memory-based (SRAM-based) FPGAs, including the XC3000, XC4000, XC5000, and XC6000 series.
ASIC Alternatives
Gate Arrays Custom Highest Density ASIC Tools

HardWire devices
HardWire devices are masked-programmed versions of the SRAM-based FPGAs. The HardWire products provide an easy, transparent migration path to a cost-reduced device without the engineering burden associated with conventional gate array re-design. The HardWire gate array is architecturally identical to its FPGA counterpart, but the programmable elements in the FPGA are replaced with xed metal connections. The resulting die is considerably smaller, with a correspondingly lower cost. Using proprietary automatic test vector generation software and patented test logic, Xilinx guarantees over 95% fault coverage, while eliminating the need for user-generated test vectors. The mask and test programs are generated automatically by Xilinx from the users existing FPGA design le.

Xilinx Product Line

CPLD ISP PAL Architecture Medium Density Simple Tools

FPGA Programmable Gate Array Architecture High Density ASIC Tools

HardWire Custom Transparent Conversion 100% Tested

Serial PROMs
The XC1700 family features one-time programmable serial PROMs ranging in density from about 18,000 bits to over 260,000 bits. These serial PROMs are an easy-to-use, cost-effective method for storing conguration data for the SRAM-based FPGAs.

PAL Devices Programmable AND/OR Architecture Low Density Simple Tools

X5957

Figure 3: Application-Specic IC Products

PROGRAMMABLE INTERCONNECT

I/O BLOCKS

X1153

LOGIC BLOCKS

Figure 4: FPGA Architecture

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November 10, 1997

I/O

Interconnect Matrix FB FB

I/O

X5956

Figure 5: CPLD Architecture

High-Reliability Devices
Xilinx was the rst company to offer high-reliability FPGAs by introducing MIL-STD-883B qualied XC2000 and XC3000 series devices in 1989. MIL-STD-883B members of the XC4000 FPGA series are currently available, and qualied versions of additional Xilinx families are in development. The product line also includes Standard Microcircuit Drawing (SMD) versions of several families. Some Xilinx devices are available in tested die form through arrangements with manufacturing partners.

forms include the ubiquitous PC and several popular workstations.

Technical Support and Service

Providing global, world-class manufacturing, technical support, and sales/distribution support is an essential foundation of the Xilinx product strategy. Xilinx manufacturing facilities have earned ISO9002 certication, and Xilinx quality and reliability achievements are among the worlds best - not just for programmable logic suppliers, but among all semiconductor companies. Comprehensive technical support facilities include training courses, extensive product documentation and application notes, a quarterly technical newsletter, the WebLINX World Wide Web site, technical support hotlines, and a cadre of Field Application Engineers. Sales support is provided by a worldwide network of representatives and distributors.

Development System Products

Xilinx offers a complete software environment for the implementation of logic designs in Xilinx programmable logic devices. This environment combines powerful technology with a exible, easy-to-use graphical interface to help users achieve the best possible designs, regardless of experience level. The user has a wide range of choices between a fully-automatic implementation and detailed involvement in the layout process. The development system provides all the implementation tools required to design with Xilinx logic devices, including the following: libraries and interfaces for popular schematic editors, logic synthesis tools, and simulators design manager/ow engine module generator map, place, and route compilation software static timing analyzer hardware debugger

Xilinx is committed to an open system approach to front-end design creation, synthesis, and verication. Xilinx devices are supported by the broadest number of EDA vendors and synthesis vendors in the industry. Supported plat-

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An Introduction to Xilinx Products

XC3000 Series Product Selection Matrix

XC3020A/L XC3030A/L XC3042A/L XC3064A/L XC3090A/L XC3120A XC3130A XC3142A XC3164A XC3190A XC3195A XC3142L
3 N/A 2-3 144 480 4 N N 1.5 -2

XC3000 Series

KEY FEATURES

Low Cost/ Low Power

Max Logic Gates (K) 1.5 N/A 1-1.5 64 256 4 N N -6/-8 2 N/A 1.5-2 100 360 4 N N -6/-8 3 N/A 2-3 144 480 4 N N -6/-8 4.5 N/A 3.5-4.5 224 688 4 N N -6/-8 6 N/A 5-6 320 928 4 N N -6/-8 1.5 N/A 1-1.5 64 256 8 N N 8 -09 2 N/A

High Performance

Low Voltage (3.3 V) High Performance

6 7.5 N/A 6.5-7.5 484 1320 8 N N 8 -09 6 N/A 5-6 320 928 4 N N 1.5 -2

3 N/A 2-3 144 480 8 N N 8 -09

4.5 N/A 3.5-4.5 224 688 8 N N 8 -09

DENSITY

Max RAM Bits Typical Gate Range (K) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade

N/A 5-6 320 928 8 N N 8 -09

1.5-2 100 360 8 N N 8 -09

FEATURES

0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02 0.5/0.02

XC4000 Series Product Selection Matrix

XC4028EX/XL XC4036EX/XL XC4005E/XL XC4010E/XL XC4013E/XL XC4020E/XL XC4044XL XC4052XL XC4062XL XC4085XL XC4003E XC4006E XC4008E XC4025E
DEVICES

XC4000 Series

KEY FEATURES

High Density High Performance Select-RAM Memory

System Gate Range* (Logic and RAM) (K) Logic Cells Max Logic Gates, (no RAM) (K) Max RAM Bits (no Logic) CLBs Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 2-5 238 3 3200 100 360 12 Y Y 10 -1 3-9 466 5 6272 196 616 12 Y Y 10 -09 4-12 6-15 7-20 608 770 950 6 8 10 8192 10368 12800 256 324 400 768 936 1120 12 12 12 Y Y Y Y Y Y 10 10 10 -1 -1 -09 10-30 1368 13 18432 576 1536 12 Y Y 10 -09 13-40 1862 20 25088 784 2016 12 Y Y 10 -09 15-45 2432 25 32768 1024 2560 12 Y Y 10 -1 18-50 2432 28 32768 1024 2560 12 Y Y 10 -09 22-65 3078 36 41472 1296 3168 12 Y Y 10 -09 27-80 33-100 40-130 55-180 3800 4598 5472 7448 44 52 62 85 51200 61952 73728 100352 1600 1936 2304 3136 3840 4576 5376 7168 12 12 12 12 Y Y Y Y Y Y Y Y 10 10 10 10 -09 -09 -09 -09

FEATURES

DENSITY

*Maximum System gates assume 20% of CLBs used as RAM

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XC3190L

DEVICES

Spartan Series Product Selection Matrix

KEY FEATURES DEVICES

Spartan Series

XCS05 XCS05-XL

XCS10 XCS10-XL

XCS20 XCS20-XL

XCS30 XCS30-XL

XCS40 XCS40-XL

High Density High Performance Select-RAM Memory Low Cost

FEATURES

DENSITY

*Maximum System gates assume 20% of CLBs used as RAM

XC5200 Series Product Selection Matrix

KEY FEATURES DEVICES

XC5200 Series

XC5202

XC5204

XC5206

XC5210

XC5215

High Density Low Cost Max Logic Gates (K) Max RAM Bits Typical Gate Range (K) CLBs/Logic Cells Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 3 N/A 2-3 64 256 8 Y Y 15 -3 6 N/A 4-6 120 480 8 Y Y 15 -3 10 N/A 6-10 196 784 8 Y Y 15 -3 16 N/A 10-16 324 1296 8 Y Y 15 -3 23 N/A 15-23 484 1936 8 Y Y 15 -3

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FEATURES

DENSITY

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An Introduction to Xilinx Products

XC9500 Series Product Selection Matrix

KEY DENSITY FEATURES DEVICES

CPLD Families

XC9536

XC9572

XC95108

XC95144

XC95216

XC95288

JTAG 5 V ISP 3 V or 5 V I/O Gates (K) Macrocells Flip-Flops Output Drive (mA) JTAG (IEEE 1149.1) Dedicated Arithmetic Quiescent Current (mA) Fastest Speed Grade 0.8 36 36 24 Y N -5 1.6 72 72 24 Y N -7 2.4 108 108 24 Y N 140 -7 3.2 144 144 24 Y N -7 4.8 216 216 24 Y N -10 6.4 288 288 24 Y N -10

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FEATURES

November 10, 1997

Development System Products and CORE Solutions Products

1 2 3 4 5 6 7 8 9

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

Development System Products Table of Contents

Development System Products and CORE Solutions Products

Development Systems: Products Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexible Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx M1 Software Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Increased Design Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M1 Technical Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-1 2-1 2-1 2-1 2-2 2-2 2-2 2-2

Development Systems: Product Descriptions

Development Systems Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Base-Express System with VHDL/Verilog Synthesis (PC) . . . . . . . . . . Foundation Series: Foundation Standard System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Foundation Series: Foundation Express System (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Alliance Base (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series: Alliance Standard (PC or Workstation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alliance Series Options (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-4 2-5 2-6 2-7 2-8 2-10 2-12

CORE Solutions Overview

Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Solutions Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CORE Solutions Data Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LogiCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx CORE Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx PCI Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Xilinx DSP Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring LogiCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AllianceCORE Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AllianceCORE Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquiring AllianceCORE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2-13 2-13 2-13 2-13 2-14 2-14 2-14 2-14 2-14 2-15 2-15

Development Systems: Products Overview

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Product Overview all Xilinx programmable logic devices, featuring the industrys largest FPGA devices.

Introduction
Leading-edge silicon products, state-of-the art software solutions and world-class technical support make up the total solution delivered by Xilinx. The software component of this solution is critical to the success of every design project. Xilinx Software Solutions provide powerful tools which make designing with programmable logic simple. Push button design ows, integrated on-line help, multimedia tutorials, plus high performance automatic and autointeractive tools, help designers achieve optimum results. And the industrys broadest array of programmable logic technology and EDA integration options deliver unparalleled design exibility.

Foundation Series
The Xilinx Foundation Series provides everything required to design a programmable logic device in an easy-to-use environment. This fully integrated tool set allows users to access design entry, synthesis, implementation and simulation tools in a ready-to-use package. Every step in the design process is accomplished using graphical tool bars, icons and pop-up menus supported by interactive tutorials and comprehensive on-line help. The Xilinx Foundation Series features support for standards based HDL design. All congurations support the popular ABEL language, with integrated compilers optimized for each target architecture. HDL congurations include integrated VHDL/Verilog synthesis from Synopsys with tutorials and graphical HDL design entry tools to turn new users into experts quickly and easily.

Product Overview
Xilinx Software Solutions are available in two different product series making it easy for designers to choose the right system for their needs. These two series support the industrys broadest array of programmable logic IC families. This allows users to standardize their design tools for all programmable logic applications and use these tools to realize the benets of the industrys highest performance and density FPGAs and CPLDs. It also makes it easy to migrate designs to new technologies and re-use existing designs in new applications. The Xilinx Foundation Series provides designers with a complete, ready-to-use solution for programmable logic design. The Xilinx Alliance Series provides designers powerful integration of Xilinx design tools with their existing EDA environment.

HDL Congurations
HDL congurations of the Foundation Series contain integrated VHDL/Verilog synthesis and graphical interactive HDL entry tools with the following features: On-line tutorial teaches the art of VHDL design. Xilinx HDL Editor provides color coding, syntax checking and single click error navigation making it easy to create and debug VHDL, Verilog and ABEL designs. Graphical State Machine editor makes the design of simple or complex state machines simple and intuitive. HDL Language Assistant provides libraries of common functions with optimized VHDL, Verilog and ABEL code. FPGA and CPLD specic synthesis and optimization from Synopsys tools produce high-utilization, highperformance results

Flexible Congurations
Xilinx Software Solutions are available in two device congurations giving designers a cost-effective way to match their tools to the design methodologies they require. These congurations are available for both the Foundation and Alliance Series. Base congurations provide push button design ows and support a broad array of FPGA and CPLD devices targeted for low density and high volume applications. Standard congurations combine push button ows with powerful auto-interactive tools. These tools give designers more inuence and control over implementation while maintaining the benets of design automation. Standard congurations include support for

Alliance Series
The Alliance Series provides powerful and integrated design tools for users who require a quality solution for their chosen EDA design solution. With the Alliance Series, users can choose from a wide range of design techniques including schematic capture, module-based design and HDL design solutions. With standard based design interfaces including EDIF, VITAL, VHDL, Verilog and SDF, this series provides maximum exibility, portability, mixed vendor support, and design reuse.

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Development Systems: Products Overview

Quality integration with leading EDA vendors such as ALDEC, Exemplar, Cadence, Mentor Graphics, Model Technology, OrCAD, Synopsys, Synplicity, Veribest and VIEWlogic provide tightly-coupled environments that make it easy to move through the design process and through a mixed EDA vendor ow. The EDA vendors are supported through the Xilinx Alliance Program, insuring high quality tools and accuracy of results. Information on Xilinx Alliance Program vendors can be found on the Xilinx WEB page www.xilinx.com. The Alliance Series includes an enhanced set of easy-touse features including, design manager, ow engine, installation, on-line documentation, and answer database. In addition, the Alliance Series includes a powerful and complete implementation toolset, LogiBLOX (next generation module generation), fully integrated EDA vendor support, and a powerful gate-level optimizer. Also included are new advanced place and route software that has incremental design capabilities and SMARTspecs (a robust timing constraint language). Users can achieve up to 25% performance improvements with no additional elapse time through the use of the Alliance Series Turns Engine. The Turns Engine uses networked workstations to run multiple place and route passes for a single design. This feature is included with the Alliance Series BASE and Standard workstation development systems. The libraries and interface provide Xilinx Unied Library schematic symbols, HDL synthesis libraries, VITAL(VHDL) and Verilog simulation models with timing information and translators through a standard netlist format. All of these tools provide a complete spectrum of high density design methodologies from fully-automatic to hand-crafted and close integration with Xilinx LogiCores and AllianceCore partners.

which delivers push-button design ows and incremental design capabilities. These Xilinx-exclusive capabilities leverage results from previous design iterations to reduce runtimes and shorter design iterations to less than ten minutes. As engineers design complex circuits incrementally, this technology allows them to work in their preferred methodology. M1 Technology also delivers advanced timing driven placeand route capabilities to deliver maximum design performance through push-button ows.

M1 Technical Benets
Maximum Design Performance
M1 technology enables the user to achieve maximum design performance by providing a unique combination of advanced algorithms and interactive tools. Designer productivity is greatly enhanced through use of simple, pushbutton ows and optional auto-interactive tools. Customer testing has shown that M1 technology used with XC4000XL/XV devices results in 70 percent shorter run times, up to a 25 percent performance improvement, and the ability to place and route devices with up to 100 percent utilization with a push-button ow.

Modular Software System

The modular architecture of the Xilinx M1 technology allows rapid delivery of incremental technologies, new features, device support, and versions of its leading software product families. New feature sets can now be released independently resulting in users ability to quickly complete designs without having to re-learn new tools as enhancements are made. The investment Xilinx has made in the M1 technology ensures that the continuous delivery of innovative device architectures and improved software solutions can be done more rapidly, and predictably than previous software versions.

Alliance Series Options

VIEWlogic Workview Ofce Development System options as part of the Alliance Series are intended for users who want the integration of a complete solution with the power to access board and system level design tools. These products include VIEWlogic Workview Ofce schematic capture and simulation tools.

Methodology Flexibility
High-level design methodologies are becoming the methodology choice for the design of complex programmable logic. M1 technology delivers programmable logic specic high-level ows. The ows provide high-quality, high performance optimized results, and afford fast, exible design changes and iterations to match the way engineers design. Designers employ a mixture of graphical and languagebased design entry methods while providing an easy-tolearn environment for Hardware Description Language (HDL) based design. Xilinx recognizes that design environments are variant and, therefore, has created a exible system enabling the customer to choose the best methodology for their environment or design challenge.

Xilinx M1 Software Technology

M1 technology represents Xilinxs next generation software technology. This advanced technology developed as a result of the Xilinx merger with NeoCAD Inc., enables digital system designers to increase design performance, leverage standards-based, high-level design methodologies and quickly receive new software features and device support through Xilinx Foundation Series and Alliance Series software solutions.

Increased Design Performance

The M1 technology provides dramatically improved design performance through advanced place-and-route software

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Development Systems: Product Descriptions

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Development Systems Descriptions

Its simple to order a Xilinx Development System. Just choose a Foundation or Alliance Series and a few options. Give your local Xilinx Sales Office a call for information about our evaluation kits.

Foundation Series
Foundation Base System (PC) Foundation Base-Express System (PC) Foundation Standard System (PC) Foundation Express System (PC)

Alliance Series
Alliance Base (PC or Workstation) Alliance Standard (PC or Workstation)

Alliance Series Options

VIEWlogic Workview Ofce Standard Development System Options (PC)

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Development Systems: Product Descriptions

Foundation Series: Foundation Base System (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Base System provides design entry (schematic and Abel HDL), simulation, and device implementation tools for a broad array of FPGA and CPLD devices targeted for low density and high volume applications.

Package Features - Foundation Base System

Feature CPLD Devices FPGA Devices Libraries and Interface Schematic Editor HDL Editor Graphical State Editor ABEL 6 Entry / Synthesis VHDL Entry / Synthesis Verilog Entry / Synthesis Schematic-centric Synthesis HDL-centric Synthesis Simulator Device Implementation Maintenance2
11/12/97

System Features
Project manager Schematic editor Integrated HDL editor with support for the Abel 6 HDL Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X Up to XC4010E/X - Spartan - XC3x00A/L - XC5200 Up to XC5210 FPGAs

Notes: 1. Spartan, XC3x00A/X, XC4000E/X up to XC4010E/X, and XC5200 up to XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information.

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements: 32 MB RAM, 32-64 MB Virtual Memory CD-ROM drive

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Foundation Series: Foundation Base-Express System with VHDL/Verilog Synthesis (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Express System incorporates advanced synthesis technology from Synopsys, and provides design entry (schematic and HDL), VHDL and Verilog synthesis, simulation, and device implementation tools for a broad array of FPGA and CPLD devices targeted for low density and high volume applications.

Package Features - Foundation Base-Express System

System Features
Project manager Schematic editor Integrated HDL editor with support for VHDL, Verilog, and Abel 6 HDL VHDL and Verilog synthesis, including compilation and optimization Functional and timing simulator EDIF, VHDL (VITAL compliant), and Verilog / SDF design interfaces Device implementation software for Xilinx CPLDs and FPGAs Comprehensive on-line help, on-line documentation, and software tutorials Software maintenance, including hotline support and software updates

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X Up to XC4010E/X - Spartan - XC3x00A/L - XC5200 Up to XC5210 FPGAs

Notes: 1. Spartan, XC3x00A/L, XC4000E/X up to XC4010E/X, and XC5200 up to XC5210. 2. A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information.

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements: 32 MB RAM, 32-64 MB Virtual Memory CD-ROM drive

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Development Systems: Product Descriptions

Foundation Series: Foundation Standard System (PC)

Overview
The Foundation Series provides a complete, ready-to-use design system for the design of Xilinx programmable logic devices. The Foundation Standard System provides design entry (schematic and Abel HDL), simulation, and device implementation tools for all Xilinx CPLDs and Xilinx FPGAs.

Package Features - Foundation Base System

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

Required Hardware Environment

Windows 95 and Windows NT 4.0 compatible PCs Minimum memory requirements - Small Devices (< 10K gates): 32 MB RAM, 32-64 MB Virtual Memory - Medium Devices (10K to 30K gates): 64 MB RAM, 64-128 MB Virtual Memory - Large Devices (> 30K gates): 128 MB RAM, 128-256 MB Virtual Memory CD-ROM drive

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Foundation Series: Foundation Express System (PC)

Package Features - Foundation Base System

FND FND FND FND BAS STD BSX EXP 1 1

Device Support
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

Required Hardware Environment

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Development Systems: Product Descriptions

Alliance Series: Alliance Base (PC or Workstation)

Overview
Next generation FPGA/CPLD design solutions leveraging Open Systems integration with premier EDA partners for devices up to 10,000 gates.

Libraries and Interfaces

Cadence
Concept schematic libraries and Verilog-XL simulation models Falcon Framework schematic capture library and ModelSim simulation models Leonardo synthesis libraries and interfaces are available from Mentor or Exemplar Logic HDL Design Solutions (VHDL and Verilog) Design Compiler, FPGA Compiler II, FPGA Express, VSS Vital Simulation models DesignWare arithmetic modules

Base System Features:

EDA Libraries & Interfaces Design Manager and Flow Engine LogiBLOX Module Generator Gate Optimizer Complete HDL design methodology support Incremental design capabilities Place and route utilizing SMARTspecs Re-entrant router Multi-pass PAR Timing Analyzer Standard netlist and backannotation (EDIF, SDF, VITAL VHDL and Verilog) Xchecker Hardware Debugger (workstation only)

Mentor

Synopsys

* No libraries required to support FPGA Express

VIEWlogic
Workview Ofce schematic capture library and functional and timing simulation interface Leonardo and Galileo synthesis libraries and interfaces are available from Exemplar Logic Synplify synthesis libraries and interfaces are available from Synplicity ModelSim, V-System HDL simulation libraries and interface

Package Includes:
Alliance Quick Start Guide Alliance Release Document Answer Database Core Technology CD CAE Libraries CD On-line Documentation CD with DynaText browser Hardware Cable Demoboard

Exemplar

Synplicity

Device Support:
CPLDs: - XC9500 FPGAs: - XC4000E/X Up to XC4010E/X - Spartan - XC3x00A/L - XC5200 Up to XC5210 FPGAs

Model Technology

Contact your local EDA sales ofce to purchase these EDA tools.

Support and Updates Include:

Answers Database - http://www.xilinx.com or Answers electronic book included. Hotline Telephone Support Apps FAX and E-Mail Online Documentation World Wide Web Access Technical Newletter Extensive Application Notes Software Updates (for in-maintenance customers) - A period of maintenance is included with new design system licenses, after which annual maintenance contracts may be purchased. Contact your Xilinx sales representative for more information

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Required Hardware Environment (PC)

Required Hardware Environment (Workstation)

Ultra Sparc (or equivalent) - Sun OS 4.1.3 and 4.1.4 - Solaris 2.5 HP715 (or equivalent) - HP-UX 10.2 RS6000 - AIX 4.1.5 (no GUIs) 64 MB RAM (Use additional to increase performance) 64MB min Swap Space Color Monitor

November 25, 1997 (Version 2.0)

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Development Systems: Product Descriptions

Alliance Series: Alliance Standard (PC or Workstation)

Overview
Next generation FPGA/CPLD design solutions leveraging Open Systems integration with premier EDA partners for unlimited gate capacity.

Libraries and Interfaces

Base System Features:

EDA Libraries & Interfaces Design Manager and Flow Engine LogiBLOX Module Generator Gate Optimizer Full HDL design methodology support Incremental design capabilities Place and route utilizing SMARTspecs Re-entrant router Multi-pass PAR Timing Analyzer Standard netlist and backannotation (EDIF, SDF, VITAL VHDL and Verilog) Xchecker Hardware Debugger (workstation only)

Mentor

Synopsys

* No libraries required to support FPGA Express

Package Includes:
Alliance Quick Start Guide Alliance Release Document Answer Database Core Technology CD CAE Libraries CD On-line Documentation CD with DynaText browser Hardware Cable Demoboard

Exemplar

Synplicity

Model Technology

Device Support:
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

Contact your local EDA sales ofce to purchase these EDA tools.

Support and Updates Include:

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November 25, 1997 (Version 2.0)

Required Hardware Environment (PC)

Fully IBM compatible PC486/Pentium - NEC98 supported Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 300 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports Small Devices: (8K or <) XC9536 - XC95108; XC4003E - XC4008E; XC4005XL - XC4008XL - 32 MB RAM (Use additional RAM to increase performance) - 32 -64 MB Virtual Memory Medium Devices: (10K- 28K) XC95144 - XC95216; XC4010E - XC4025E; XC4028EX - XC4036EX; XC4010XL - XC4028XL - 64 MB RAM (Use additional RAM to increase performance) - 64-128 MB Virtual Memory Large Devices: (36K or >) XC4036XL - XC4062XL - 128K RAM (Use additional RAM to increase performance) - 128 - 256 MB Virtual Memory

Required Hardware Environment (Workstation)

Ultra Sparc (or equivalent) - Sun OS 4.1.3 and 4.1.4 - Solaris 2.5 HP715 (or equivalent) - HP-UX 10.2 RS6000 - AIX 4.1.5 (no GUIs) Small Devices: (28K or <) XC4000E; XC4028EX - XC4036EX; XC4005XL - XC4028XL - 64 MB RAM (Use additional RAM to increase performance) - 64MB min Swap Space Large Devices (36K or >) XC4036XL - XC4062XL - 128 MB RAM (Use additional RAM to increase performance) - 128 MB min Swap Space Color Monitor

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Development Systems: Product Descriptions

Alliance Series Options (PC)

Overview
VIEWlogic Workview Ofce schematic capture and gate simulator development system with libraries and interfaces for Xilinx FPGAs and CPLDs.

Support and Updates Include:

Workview Ofce Standard Features:

Workview Ofce schematic editor Workview Ofce gate simulator Libraries and interfaces Hotline support Software maintenance for 90-days

Required Hardware Environment:

Fully IBM compatible PC486/Pentium Windows 95, Windows NT 4.0 - Chinese, Korean and Japanese versions Minimum 500 Mbytes hard-disk space CD-ROM drive VGA display Serial port mouse One parallel and two serial ports 64 Mbytes RAM recommended (increase to improve performance)

Libraries Support:
CPLDs: - XC9500 FPGAs: - XC4000E/X - Spartan - XC3x00A/L - XC5200

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November 25, 1997 (Version 2.0)

CORE Solutions Overview

0 2*

September 5, 1997 (Version 1.0)

Product Overview view) which lists all of the functions available today. This table will be your best guide to locating a specic product. If you don't see what you need, check the AllianceCORE Partner Proles, Areas of Expertise section, for each of our AllianceCORE partners. Our partners will be more than willing to discuss the possibility of producing a core specifically for your needs.

Background
The ASIC core industry has been developing for over a decade. Today there exists a wealth of intellectual property (IP) that is readily available from numerous sources. During this time, however, programmable logic did not have the density or the performance needed to accommodate large IP cores. Today, things have changed considerably. Xilinx is shipping FPGAs like the XL family that have usable densities up to 125,000 gates. Now, not only is the use of pre-dened logic functions in programmable logic a possibility, it is becoming a requirement to meet ever-shrinking product development cycles. As a result, many ASIC core vendors and system designers are beginning to look at using cores for their programmable logic designs. It is for this reason that Xilinx created the CORE Solutions portfolio of products.

Data Book Contents

The contents of the data book are as follows: Introduction - Program Overview - Product Listing by Application Segment LogiCORE Products, sold and supported by Xilinx - Product Overview - PCI - DSP - CORE Generator products AllianceCORE Products, sold and supported by Xilinx' Partners - Program Overview - Products - AllianceCORE Partner Proles LogiBLOX, GUI-based small function generator Reference Designs Sales Ofces, Representatives and Distributors

CORE Solutions Products

CORE Solutions products support four application areas. The application areas are as follows: Standard Bus Interfaces - such as PCI, PCMCIA, USB and Plug-and-Play ISA. DSP Functions - These range from small building blocks such adders, registers and multipliers, to larger system-level functions such as FIR lters and ReedSolomon coders. Telecom and Networking - building blocks for popular communications standards. Base-Level Functions - a broad category of functions used across many application segments. These include the every small parameterizable LogiBLOX macros up through larger functions such as UARTs and DMA controllers.

Ordering Information
To order a copy, request the CORE Solutions Data Book from the Xilinx Literature Department. In the US call 1-800231-3386. For international locations call 1-408-879-5017 or you can send an E-mail request to: [email protected]. An electronic version of the CORE Solutions Data Book (1.2M Adobe Acrobat .pdf format) can also be downloaded from: www.xilinx.com/products/logicore/core_sol.pdf

CORE Solutions Data Book

The goal of the CORE Solutions portfolio of products is to provide cores with the shortest time-to-market and best possible device utilization the programmable logic industry has to offer. Xilinx has published a brand new data book focused entirely on programmable logic cores and related products. Now there is one denitive sourcebook with detailed descriptions of all Xilinx CORE Solutions. When you receive your copy of the CORE Solutions Data Book, become familiar with the Product Listing by Application Segment Table, (reproduced at the end of this over-

LogiCORE Products
LogiCORE products are sold, licensed and supported by Xilinx. They are developed internally by Xilinx or jointly with a partner. The cores that Xilinx provides as LogiCORE products typically fall into one of two categories.The rst are high-performance interface cores that require a thorough understanding and control of the FPGA technology and

September 5, 1997 (Version 1.0)

2-13

CORE Solutions Overview

implementation software in order to achieve the desired performance and complexity. An example of a core in this category is the LogiCORE PCI interface. The second category are cores that benet from a very specialized implementation in the FPGA. An example is the LogiCORE DSP modules that are implemented using a unique algorithm, Distributed Arithmetic. This algorithm ts the lookup-table-based architecture of the FPGA. The result is outstanding performance and device utilization, often more than 10 times better than generic HDL descriptions.

PCI is an extremely high-performance and complex specication that is challenging to meet in any technology. To meet the stringent PCI specication the core is carefully hand-tuned for the targeted architecture. Placement and routing for the critical parts of the core is locked down to ensure that timing can be met every time the core is used. To achieve our goals, the LogiCORE development team is working closely with both the IC and Software teams. As an example of this teamwork, new methodologies for characterizing and modeling our FPGAs have been developed. The result is access to state of the art technology and expertise, that allows you to complete your PCI application in record time. Xilinx has sold over 250 licenses of the LogiCORE PCI interface and has built up solid knowledge about PCI. We are committed, and will continuously develop our PCI products to remain state of the art.

Xilinx CORE Generator

In addition to actual cores, Xilinx is committed to develop enabling design tools and methodologies to facilitate usage of cores with FPGAs. The rst products available in this category are the web-based CORE Generator for PCI and the CORE Generator for DSP (available on CD). This innovative methodology for acquiring and using cores combines the benets of a rm core with predictable performance, and the exibility of system level design, facilitated by behavioral languages such as VHDL and Verilog.

Xilinx DSP Solutions

Using an FPGA to implement high performance DSP functions often allows a radical performance advantage over xed processors while maintaining maximum exibility and the shortest time-to-market. Until now, tools to automate the design process have been lacking and most designs have been completed manually by experienced FPGA designers. With the introduction of Xilinx CORE Generator for DSP, complex parameterized DSP building blocks can be implemented automatically with performance and density equal to or better than a hand-tuned implementation. LogiCORE DSP modules can be used with VHDL-, Verilog- or schematic based design methodologies. Higher level DSP cores are available from our AllianceCORE partners.

In addition, because Xilinx is using the web as a distribution mechanism, you always have access to the latest versions and enhancements of the cores at: www.xilinx.com/products/logicore/logicore.htm The LogiCORE products are customized to t your specic application using an intuitive graphical user interface. Based on your inputs, the tool then generates a proven core with highly predictable timing that can be integrated using any VHDL-, Verilog- or schematic-based design ow. As a result, you can integrate several individually proven cores with given performance into one system on a single FPGA. Because each core is already veried, the time-tomarket benets are maintained for high-complexity FPGAs.

Acquiring LogiCORE Products

LogiCORE products are available from your local Xilinx sales representative similar to other Xilinx software products. Xilinx and your local sales representative will also be your primary source for support of the core, the devices and the design tools. You can also send email questions to: [email protected].

Xilinx PCI Solutions

Xilinx PCI solution includes devices, tools and cores needed to build a cost-effective single-chip PCI system in record time. LogiCORE PCI - the only proven PCI core with predictable timing XC4000E/XL - the industrys fastest FPGAs that allow you to integrate the PCI interface plus 5 to 60 thousand gates of user designed logic HardWire - an automatic migration path to a low-cost chip for volume production CORE Generator - for easy conguration and integration of the LogiCORE PCI module 3rd party Design Centers - with PCI expertise available for special applications and customization of the core

AllianceCORE Overview
The AllianceCORE program is a cooperative effort between Xilinx and independent third-party core developers. It is designed to produce a broad selection of industry-standard solutions dedicated for use in Xilinx programmable logic. Xilinx takes an active role with its partners in the process of productizing AllianceCOREs. This is unique to the AllianceCORE program. Because the process is so involved,

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September 5, 1997 (Version 1.0)

we work closely with our partners to select the right cores rst. This naturally limits the number of partners we can work with at any one time and subsequently the number of available cores. At the same time it raises the quality and usability of the cores that are offered.

tee functionality and compliance. AllianceCOREs originated from either schematic or HDL entry tools.

Core Integration
AllianceCOREs are not just cores, they are complete solutions for system designs. While cores by themselves have value, in many cases it is often not enough to just supply a generic core. You may need additional tools such as system software and prototyping equipment to help you rapidly integrate the core into your design, perform system debug in a real-world environment, and then quickly convert the prototype to a production unit. This is particularly true of complex functions. Many AllianceCORE functions are supported by Xilinxbased demonstration or prototyping boards. Some also have system simulation models or debug software. All of this allows you to evaluate and work with the function before you have to layout your board. These tools are provided by the AllianceCORE partner, usually at additional cost. Descriptions of the support tools available for each core are included in the CORE Solutions Data Book. Complete solutions like these help preserve the value of using programmable logic while minimizing the support burden for the core provider.

AllianceCORE Criteria
A core must meet a minimum set of criteria before it can receive the AllianceCORE label.

Core Selection
The AllianceCORE program looks at cores from a practical point of view. A programmable logic version of a core must have value over an ASIC or standard product version of the same function. It must be cost effective and make sense for use in a programmable device in a production system. If a candidate core does not pass these simple tests, then it does not make sense to invest the effort to convert it to an AllianceCORE module.

Core Qualication
Generic, synthesizable cores offer maximum exibility for users with unique requirements. This is typically the format for cores provided to the ASIC market. With programmable logic, however, this exibility can come at the expense of efciency and performance. It can take a considerable amount of effort to get a specic core to synthesize in a way that meets density and timing requirements. Time spent trying to accomplish this can quickly reduce the time-tomarket advantage of using programmable logic and cores in the rst place. Xilinx is not interested in promoting generic, synthesizable functions as AllianceCOREs. Instead, AllianceCOREs are generally provided as parameterizable black-boxes that allow customization in critical areas. This guarantees that the implementation is optimized for density while still meeting performance, preserving the time-to-market value of programmable logic. Flexibility is provided by allowing you to quickly implement your unique logic on the same device. Source code versions of the cores are also available from the partners at additional cost for those who need ultimate exibility. Announced AllianceCOREs have been implemented and veried in a Xilinx device. They are available immediately for purchase in a Xilinx-specic format. Timing-critical cores designed to adhere to an industry standard also come with appropriate constraints les in order to guaran-

Acquiring AllianceCORE Products

AllianceCORE products are sold and serviced directly by the AllianceCORE partners since they are the experts for their particular products. They are responsible for pricing, licensing terms, delivery and technical support. Contact information for each partner is included in the AllianceCORE Partner Proles section of the CORE Solutions Data Book. If you want additional information about the AllianceCORE program or are interested in becoming a partner, contact Xilinx directly. Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Attn: Mark Bowlby, AllianceCORE Product Manager Phone: +1 408-879-5381 Fax: +1 408-879-4780 E-mail: [email protected] URL: www.xilinx.com/products/logicore /alliance/tblpart.htm

September 5, 1997 (Version 1.0)

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CORE Solutions Overview

Table 1: Product Listing by Application Segment

Check www.xilinx.com/products/logicore/tbls_cores.htm for the latest listing of available Cores

Function Standard Bus Interfaces IIC Two-Wire Serial Interface ISA Plug and Play Interface ISA Interface for JPEG Motion Codec PCI Master/Slave Interfaces 1.2.0 PCI Master/Slave Interfaces 2.0.0 PCMCIA Fax/Modem PCMCIA Library USB - Low-Speed Function Controller USB - Full-Speed Function Controller USB - 3-Port Hub Controller DSP Functions 1s Complement Accumulator, Scaled by 1/2 Adder, Registered Adder, Registered Loadable Adder, Registered Scaled Adder, Registered Serial Adders, Subtractors, Accumulators Comb Filter Correlator, 1-D RAM Based Correlator, 1-D ROM Based Delay Element FIR Filter, 16-Tap, 8-Bit FIR Filter - Serial Distributed Arithmetic FIR Filter - Dual Channel Serial Distributor Arithmetic Integrator Memory - 16-Word Deep Register Look-up Table Memory - 32-Word Deep Register Look-up Table Memory - 16-Word Deep Registered RAM Memory - 32-Word Deep Registered RAM Memory - Registered Synchronous RAM Memory - Registered ROM Multiplier, Constant Coefficient Multiplier, Constant Coefficient (pipelined) Multipliers, Parallel - Area Optimized Multipliers, Parallel - Performance Optimized Parallel to Serial Converter Reed-Solomon Decoder Reed-Solomon Encoder SDA FIR Control Logic Sine/Cosine Square Root Subtracter, Registered Subtracter, Registered Loadable CORE Solution AllianceCORE Reference Design Reference Design LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE Reference Design LogiCORE LogiCORE LogiCORE LogiCORE Reference Design LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceCORE AllianceCORE LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE

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September 5, 1997 (Version 1.0)

Table 1: Product Listing by Application Segment (Continued)

Check www.xilinx.com/products/logicore/tbls_cores.htm for the latest listing of available Cores

Function Time Skew Buffer - Non-Symmetric 16-Deep Time Skew Buffer - Non-Symmetric 32-Deep Time Skew Buffer - Symmetric 16-Deep Transform, DFT Transform, FFT Base-Level Functions 16450 UART 16550A UART with RAM 8250 Asynchronous Communications 8254 Programmable Timer M8255 Programmable Peripheral Interface XF8255 Programmable Peripheral Interface Accumulator Adder/Subtracter Clock Divider Comparator Constant Constant Counter Counter, Loadable Binary Counter, Ultra-Fast Synchronous Counter, Accelerating Loadable Data Register Decoder FIFOs in XC4000 RAM FIFO, High-Performance RAM-Based FIFO, Register-Based Frequency/Phase Comparator for PLL Gates, Simple Harmonic Frequency Synthesizer and FSK Modulator Input/Output Microcontroller, Dynamic Memory (ROM, RAM, Synch-RAM, Dual Port RAM) Multiplexer Multiplexers, Barrel Shifters Multiplexer, Two Input Multiplexer, Three Input Multiplexer, Four Input Pad Pulse-Width Modulation Register Serial Code Conversion between BCD and Binary Shift Register Tristate CORE Solution LogiCORE LogiCORE LogiCORE LogiCORE LogiCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE AllianceCORE LogiBLOX LogiBLOX LogiBLOX LogiBLOX LogiCORE LogiBLOX LogiBLOX Reference Design Reference Design Reference Design LogiBLOX LogiBLOX Reference Design Reference Design Reference Design Reference Design LogiBLOX Reference Design LogiBLOX Reference Design LogiBLOX LogiBLOX Reference Design LogiCORE LogiCORE LogiCORE LogiBLOX Reference Design LogiCORE Reference Design LogiBLOX LogiBLOX

September 5, 1997 (Version 1.0)

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CORE Solutions Overview

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September 5, 1997 (Version 1.0)

CPLD Products

1 2 3 4 5 6 7 8 9

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

CPLD Products Table of Contents

XC9500 Series Table of Contents

1 3*

XC9500 In-System Programmable CPLD Family

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Family Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macrocell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastCONNECT Switch Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin-Locking Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE 1149.1 Boundary-Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Development System Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FastFLASH Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-5 3-5 3-7 3-8 3-10 3-13 3-14 3-15 3-16 3-16 3-16 3-16 3-16 3-17 3-17 3-18 3-19 3-19

XC9536 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9536 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21 3-21 3-21 3-23 3-23 3-23 3-24 3-24 3-25 3-26 3-26 3-27 3-27

XC9572 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC9572 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-29 3-29 3-31 3-31 3-31 3-32 3-32 3-33 3-34 3-35 3-36 3-1

XC9500 Series Table of Contents

Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36

XC95108 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95108 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3-37 3-37 3-39 3-39 3-39 3-40 3-40 3-41 3-42 3-43 3-43 3-44 3-44

XC95144 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95144 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3-45 3-45 3-47 3-47 3-47 3-48 3-48 3-49 3-50 3-51 3-52 3-53 3-53

XC95216 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95216 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 3-55 3-55 3-57 3-57 3-57 3-58 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-64

XC95288 In-System Programmable CPLD

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65

3-2

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operation Conditions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Endurance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 I/O Pins (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC95288 Global, JTAG and Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-67 3-67 3-67 3-68 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-75

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XC9500 Series Table of Contents

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XC9500 In-System Programmable CPLD Family

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Product Information

Features
High-performance - 5 ns pin-to-pin logic delays on all pins - fCNT to 125 MHz Large density range - 36 to 288 macrocells with 800 to 6,400 usable gates 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-5, -7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of multiple XC9500 devices

Family Overview
The XC9500 CPLD family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration. All devices are in-system programmable for a minimum of 10,000 program/erase cycles. Extensive IEEE 1149.1 (JTAG) boundary-scan support is also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 registers, respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. An expanded JTAG instruction set allows version control of programming patterns and in-system debugging. In-system programming throughout the full device operating range and a minimum of 10,000 program/erase cycles provide worry-free recongurations and system eld upgrades. Advanced system features include output slew rate control and user-programmable ground pins to help reduce system noise. I/Os may be congured for 3.3 V or 5 V operation. All outputs provide 24 mA drive.

Architecture Description
Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capability with 36 inputs and 18 outputs. The FastCONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. See Figure 1.

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XC9500 In-System Programmable CPLD Family

3 JTAG Port

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 or 4

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block N Macrocells 1 to 18

X5877

Figure 1: XC9500 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

Table 1: XC9500 Device Family XC9536 36 800 36 5 4.5 4.5 100 100 XC9572 72 1,600 72 7.5 5.5 5.5 125 83 XC95108 108 2,400 108 7.5 5.5 5.5 125 83 XC95144 144 3,200 144 7.5 5.5 5.5 125 83 XC95216 216 4,800 216 10 6.5 6.5 111 67 XC95288 288 6,400 288 15 8.0 8.0 95 56

Macrocells Usable Gates Registers tPD (ns) tSU (ns) tCO (ns) fCNT (MHz) fSYSTEM (MHz)

Note: fCNT = Operating frequency for 16-bit counters

fSYSTEM = Internal operating frequency for general purpose system designs spanning multiple FBs.

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Figure 2: Available Packages and Device I/O Pins (not including dedicated JTAG pins) XC9536 34 34 XC9572 34 69 72 72 XC95108 XC95144 XC95216 XC95288

44-Pin VQFP 44-Pin PLCC 84-Pin PLCC 100-Pin TQFP 100-Pin PQFP 160-Pin PQFP 208-Pin HQFP 352-Pin BGA

69 81 81 108

81 81 133

133 166 166

168 192

Function Block
Each Function Block, as shown in Figure 3, is comprised of 18 independent macrocells, each capable of implementing a combinatorial or registered function. The FB also receives global clock, output enable, and set/reset signals. The FB generates 18 outputs that drive the FastCONNECT switch matrix. These 18 outputs and their corresponding output enable signals also drive the IOB. Logic within the FB is implemented using a sum-of-products representation. Thirty-six inputs provide 72 true and complement signals into the programmable AND-array to form 90 product terms. Any number of these product terms, up to the 90 available, can be allocated to each macrocell by the product term allocator. Each FB (except for the XC9536) supports local feedback paths that allow any number of FB outputs to drive into its own programmable AND-array without going outside the FB. These paths are used for creating very fast counters and state machines where all state registers are within the same FB.

Macrocell 1

Programmable AND-Array From FastCONNECT Switch Matrix

Product Term Allocators

36 18 18 OUT PTOE

To FastCONNECT Switch Matrix

To I/O Blocks

Macrocell 18 1 Global Set/Reset 3 Global Clocks

X5878

Figure 3: XC9500 Function Block

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XC9500 In-System Programmable CPLD Family

Macrocell
Each XC9500 macrocell may be individually congured for a combinatorial or registered function. The macrocell and associated FB logic is shown in Figure 4. Five direct product terms from the AND-array are available for use as primary data inputs (to the OR and XOR gates) to implement combinatorial functions, or as control inputs including clock, set/reset, and output enable. The product term allocator associated with each macrocell selects how the ve direct terms are used. The macrocell register can be congured as a D-type or Ttype ip-op, or it may be bypassed for combinatorial operation. Each register supports both asynchronous set and reset operations. During power-up, all user registers are initialized to the user-dened preload state (default to 0 if unspecied).
Global Set/Reset Global Clocks

Additional Product Terms (from other macrocells)

Product Term Set 1 0 S D/T Q Product Term Allocator

To FastCONNECT Switch Matrix

Product Term Clock Product Term Reset

OUT Product Term OE PTOE To I/O Blocks

Additional Product Terms (from other macrocells)

X5879

Figure 4: XC9500 Macrocell Within Function Block

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All global control signals are available to each individual macrocell, including clock, set/reset, and output enable signals. As shown in Figure 5, the macrocell register clock originates from either of three global clocks or a product

term clock. Both true and complement polarities of a GCK pin can be used within the device. A GSR input is also provided to allow user registers to be set to a user-dened state.

Macrocell Product Term Set

Product Term Clock

S D/T

R Product Term Reset

I/O/GSR

Global Set/Reset

I/O/GCK1 Global Clock 1

I/O/GCK2

Global Clock 2

I/O/GCK3

Global Clock 3

X5880

Figure 5: Macrocell Clock and Set/Reset Capability

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XC9500 In-System Programmable CPLD Family

Product Term Allocator

The product term allocator controls how the ve direct product terms are assigned to each macrocell. For example, all ve direct terms can drive the OR function as shown in Figure 6.
Product Term Allocator

Note that the incremental delay affects only the product terms in other macrocells. The timing of the direct product terms is not changed.
Product Term Allocator

Macrocell Product Term Logic

Product Term Allocator

X5894

Figure 6: Macrocell Logic Using Direct Product Term The product term allocator can re-assign other product terms within the FB to increase the logic capacity of a macrocell beyond ve direct terms. Any macrocell requiring additional product terms can access uncommitted product terms in other macrocells within the FB. Up to 15 product terms can be available to a single macrocell with only a small incremental delay of tPTA, as shown in Figure 7.
Product Term Allocator

Macrocell Logic With 15 P-Terms

X5895

Figure 7: Product Term Allocation With 15 Product Terms

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The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in Figure 8.
Product Term Allocator

In this example, the incremental delay is only 2*tPTA. All 90 product terms are available to any macrocell, with a maximum incremental delay of 8*tPTA.

Macrocell Logic With 2 Product Terms Product Term Allocator

Product Term Allocator

Macrocell Logic With 18 Product Terms

Product Term Allocator

X5896

Figure 8: Product Term Allocation Over Several Macrocells

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XC9500 In-System Programmable CPLD Family

The internal logic of the product term allocator is shown in Figure 9.

From Upper Macrocell To Upper Macrocell

Product Term Allocator

Product Term Set

Global Set/Reset

1 0

S D/T Q Global Clocks Product Term Clock R

Product Term Reset

Global Set/Reset Product Term OE

From Lower Macrocell

To Lower Macrocell

X5881

Figure 9: Product Term Allocator Logic

3-12

November 10, 1997 (Version 2.0)

FastCONNECT Switch Matrix

The FastCONNECT switch matrix connects signals to the FB inputs, as shown in Figure 10. All IOB outputs (corresponding to user pin inputs) and all FB outputs drive the FastCONNECT matrix. Any of these (up to a FB fan-in limit of 36) may be selected, through user programming, to drive each FB with a uniform delay. The FastCONNECT switch matrix is capable of combining multiple internal connections into a single wired-AND output before driving the destination FB. This provides additional logic capability and increases the effective logic fanin of the destination FB without any additional timing delay. This capability is available for internal connections originating from FB outputs only. It is automatically invoked by the development software where applicable.

FastCONNECT Switch Matrix

Function Block

I/O Block (36) D/T Q 18 I/O

Function Block

I/O Block (36) D/T Q I/O 18

Wired-AND Capability

X5882

Figure 10: FastCONNECT Switch Matrix

November 10, 1997 (Version 2.0)

3-13

XC9500 In-System Programmable CPLD Family

I/O Block
The I/O Block (IOB) interfaces between the internal logic and the device user I/O pins. Each IOB includes an input buffer, output driver, output enable selection multiplexer, and user programmable ground control. See Figure 11 for details. The input buffer is compatible with standard 5 V CMOS, 5 V TTL and 3.3 V signal levels. The input buffer uses the internal 5 V voltage supply (VCCINT) to ensure that the input thresholds are constant and do not vary with the VCCIO voltage. The output enable may be generated from one of four options: a product term signal from the macrocell, any of the global OE signals, always 1, or always 0. There are two global output enables for devices with up to 144 macrocells, and four global output enables for devices with 180 or more macrocells. Both polarities of any of the global 3-state control (GTS) pins may be used within the device.

To other Macrocells

VCCINT

I/O Block

To FastCONNECT Switch Matrix

Macrocell

Pull-up Resistor OUT I/O

(Inversion in AND-array) Product Term OE PTOE

UserProgrammable Ground

0 Slew Rate Control

I/O/GTS1 Global OE 1

I/O/GTS2

Global OE 2

I/O/GTS3

Global OE 3

Available in XC95180, XC95216 and XC95288

I/O/GTS3

Global OE 4

X5899

Figure 11: I/O Block and Output Enable Capability

3-14

November 10, 1997 (Version 2.0)

Each output has independent slew rate control. Output edge rates may be slowed down to reduce system noise (with an additional time delay of tSLEW) through programming. See Figure 12. Each IOB provides user programmable ground pin capability. This allows device I/O pins to be congured as additional ground pins. By tying strategically located programmable ground pins to the external ground connection, system noise generated from large numbers of simultaneous switching outputs may be reduced. A control pull-up resistor (typically 10K ohms) is attached to each device I/O pin to prevent them from oating when the device is not in normal user operation. This resistor is active during device programming mode and system power-up. It is also activated for an erased device. The resistor is deactivated during normal operation. The output driver is capable of supplying 24 mA output drive. All output drivers in the device may be congured for either 5 V TTL levels or 3.3 V levels by connecting the device output voltage supply (VCCIO) to a 5 V or 3.3 V
Output Voltage

voltage supply. Figure 13 shows how the XC9500 device can be used in 5 V only and mixed 3.3 V/5 V systems.

Pin-Locking Capability
The capability to lock the user dened pin assignments during design changes depends on the ability of the architecture to adapt to unexpected changes. The XC9500 devices have architectural features that enhance the ability to accept design changes while maintaining the same pinout. The XC9500 architecture provides maximum routing within the FastCONNECT switch matrix, and incorporates a exible Function Block that allows block-wide allocation of available product terms. This provides a high level of condence of maintaining both input and output pin assignments for unexpected design changes. For extensive design changes requiring higher logic capacity than is available in the initially chosen device, the new design may be able to t into a larger pin-compatible device using the same pin assignments. The same board may be used with a higher density device without the expense of board rework.
Output Voltage

Standard Slew-Rated Limited tSLEW 1.5 V Standard

Slew-Rated Limited tSLEW 1.5 V

Time

(a)

(b)

X5900

Figure 12: Output Slew-Rate Control For (a) Rising and (b) Falling Outputs

5 V CMOS 5V 0V 5 V TTL or 3.6 V IN 0V 3.3 V or 3.3 V 0V

5 V CMOS 5V

3.3 V

VCCINT

VCCIO 5 V TTL

0V 5 V TTL or 3.6 V

VCCINT

VCCIO 3.3 V

XC9500 CPLD

~4V OUT 0V 3.3 V

IN 0V or 3.3 V 0V

XC9500 CPLD

3.3 V OUT 0V

GND

(a)

(b)

X5901

Figure 13: XC9500 Devices in (a) 5 V Systems and (b) Mixed 3.3 V/5 V Systems

November 10, 1997 (Version 2.0)

3-15

XC9500 In-System Programmable CPLD Family

In-System Programming
XC9500 devices are programmed in-system via a standard 4-pin JTAG protocol, as shown in Figure 14. In-system programming offers quick and efcient design iterations and eliminates package handling. The Xilinx development system provides the programming data sequence using a Xilinx download cable, a third-party JTAG development system, JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. All I/Os are 3-stated and pulled high by the IOB resistors during in-system programming. If a particular signal must remain low during this time, then a pulldown resistor may be added to the pin.

The TMS and TCK pins have dedicated pull-up resistors as specied by the IEEE 1149.1 standard. Boundary Scan Description Language (BSDL) les for the XC9500 are included in the development system and are avalable on the Xilinx FTP site.

Design Security
XC9500 devices incorporate advanced data security features which fully protect the programming data against unauthorized reading or inadvertent device erasure/reprogramming. Table 2 shows the four different security settings available. The read security bits can be set by the user to prevent the internal programming pattern from being read or copied. Erasing the entire device is the only way to reset the read security bit. The write security bits provide added protection against accidental device erasure or reprogramming when the JTAG pins are subject to noise, such as during system power-up. Once set, the write-protection may be deactivated when the device needs to be reprogrammed with a valid pattern. Table 2: Data Security Options
Read Security Default Read Allowed
Write Security

External Programming
XC9500 devices can also be programmed by the Xilinx HW130 device programmer as well as third-party programmers. This provides the added exibility of using pre-programmed devices during manufacturing, with an in-system programmable option for future enhancements.

Endurance
All XC9500 CPLDs provide a minimum endurance level of 10,000 in-system program/erase cycles. Each device meets all functional, performance, and data retention specications within this endurance limit.

Set Read Inhibited Program/Erase Allowed Read Inhibited Program/Erase Inhibited

X5905

Default Program/Erase Allowed Read Allowed Set Program/Erase Inhibited

IEEE 1149.1 Boundary-Scan (JTAG)

XC9500 devices fully support IEEE 1149.1 boundary-scan (JTAG). EXTEST, SAMPLE/PRELOAD, BYPASS, USERCODE, INTEST, IDCODE, and HIGHZ instructions are supported in each device. For ISP operations, ve additional instructions are added; the ISPEN, FERASE, FPGM, FVFY, and ISPEX instructions are fully compliant extensions of the 1149.1 instruction set.

3-16

November 10, 1997 (Version 2.0)

V CC

GND

(a)

(b)

X5902

Figure 14: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable

Low Power Mode

All XC9500 devices offer a low-power mode for individual macrocells or across all macrocells. This feature allows the device power to be signicantly reduced. Each individual macrocell may be programmed in lowpower mode by the user. Performance-critical parts of the application can remain in standard power mode, while other parts of the application may be programmed for lowpower operation to reduce the overall power dissipation. Macrocells programmed for low-power mode incur additional delay (tLP) in pin-to-pin combinatorial delay as well as register setup time. Product term clock to output and product term output enable delays are unaffected by the macrocell power-setting.

Timing Model
The uniformity of the XC9500 architecture allows a simplied timing model for the entire device. The basic timing model, shown in Figure 15, is valid for macrocell functions that use the direct product terms only, with standard power setting, and standard slew rate setting. Table 3 shows how each of the key timing parameters is affected by the product term allocator (if needed), low-power setting, and slew-limited setting. The product term allocation time depends on the logic span of the macrocell function, which is dened as one less than the maximum number of allocators in the product term path. If only direct product terms are used, then the logic span is 0. The example in Figure 6 shows that up to 15 product terms are available with a span of 1. In the case of Figure 8, the 18 product term function has a span of 2. Detailed timing information may be derived from the full timing model shown in Figure 16. The values and explanations for each parameter are given in the individual device data sheets.

November 10, 1997 (Version 2.0)

3-17

XC9500 In-System Programmable CPLD Family

tSU Combinatorial Logic Combinatorial Logic D/T Q

tCO Propagation Delay = tPD (a) tPSU Combinatorial Logic P-Term Clock Path tPCO Setup Time = tPSU Clock to Out Time = tPCO Internal System Cycle Time = tSYSTEM (d) D/T Q Combinatorial Logic Setup Time = tSU (b) Clock to Out Time = tCO

D/T

(c) All resources within FB using local Feedback

Combinatorial Logic

D/T

Q Combinatorial Logic

Internal Cycle Time = tCNT (e) Setup Time Propagation Delay = tPD + tFBK With Feedback (f)

Figure 15: Basic Timing Model

tF tLF tLOGILP tIN tLOGI tPTCK tGCK tPTSR tGSR tPTTS tGTS Figure 16: Detailed Timing Model S*tPTA tPDI tSLEW

D/T

tOUT

tSUI tCOI tHI

tAOI tRAI

tEN

Power-Up Characteristics
The XC9500 devices are well behaved under all operating conditions. During power-up each XC9500 device employs internal circuitry which keeps the device in the quiescent state until the VCCINT supply voltage is at a safe level (approximately 3.8 V). During this time, all device pins and JTAG pins are disabled and all device outputs are disabled with the IOB pull-up resistors (~ 10K ohms) enabled, as shown in Table 4. When the supply voltage reaches a safe 3-18

level, all user registers become initialized (typically within 100 s for 9536 - 95144, 200 s for 95216 and 300 s for 95288), and the device is immediately available for operation, as shown in Figure 17. If the device is in the erased state (before any user pattern is programmed), the device outputs remain disabled with the IOB pull-up resistors enabled. The JTAG pins are enabled to allow the device to be programmed at any time.

November 10, 1997 (Version 2.0)

If the device is programmed, the device inputs and outputs take on their congured states for normal operation. The JTAG pins are enabled to allow device erasure or boundary-scan tests at any time.

FastFLASH Technology
An advanced CMOS Flash process is used to fabricate all XC9500 devices. Specically developed for Xilinx in-system programmable CPLDs, the FastFLASH process provides high performance logic capability, fast programming times, and endurance of 10,000 program/erase cycles.
VCCINT

Development System Support

The XC9500 CPLD family is fully supported by the development systems available from Xilinx and the Xilinx Alliance Program vendors. The designer can create the design using ABEL, schematics, equations, VHDL, or Verilog in a variety of software front-end tools. The development system can be used to implement the design and generate a JEDEC bitmap which can be used to program the XC9500 device. Each development system includes JTAG download software that can be used to program the devices via the standard JTAG interface and a download cable.

3.8 V (Typ)

0V No Power Quiescent State User Operation Quiescent State No Power

X5904

Initialization of User Registers

Figure 17: Device Behavior During Power-up Table 3: Timing Model Parameters Description Propagation Delay Global Clock Setup Time Global Clock-to-output Product Term Clock Setup Time Product Term Clock-to-output Internal System Cycle Period Parameter tPD tSU tCO tPSU tPCO tSYSTEM Product Term Allocator1 + tPTA * S + tPTA * S + tPTA * S + tPTA * S Macrocell Low-Power Setting + tLP + tLP + tLP + tLP Output Slew-Limited Setting + tSLEW + tSLEW + tSLEW

Note: 1. S = the logic span of the function, as dened in the text. Table 4: XC9500 Device Characteristics Device Circuitry IOB Pull-up Resistors Device Outputs Device Inputs and Clocks Function Block JTAG Controller Quiescent State Enabled Disabled Disabled Disabled Disabled Erased Device Operation Enabled Disabled Disabled Disabled Enabled Valid User Operation Disabled As Configured As Configured As Configured Enabled

November 10, 1997 (Version 2.0)

3-19

XC9500 In-System Programmable CPLD Family

3-20

November 10, 1997 (Version 2.0)

XC9536 In-System Programmable CPLD

0 3*

November 10, 1997 (Version 2.0)

Product Specification

Features
5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz 36 macrocells with 800 usable gates Up to 34 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-5, -6, -7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC and 44-pin VQFP packages

Power Management
Power dissipation can be reduced in the XC9536 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9536 device.

High P
Typical ICC (mA) (50)

erform

ance

(83)

(50)

ower Low P
(30)

Description
The XC9536 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 36V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for the architecture overview.
0 50 Clock Frequency (MHz) 100
X5920

Figure 1: Typical ICC vs. Frequency For XC9536

November 10, 1997 (Version 2.0)

3-21

XC9536 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

X5919

Figure 2: XC9536 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-22

November 10, 1997 (Version 2.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL
Warning:

Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm)

Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260

Units V V V C C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage

Note 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

November 10, 1997 (Version 2.0)

3-23

XC9536 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Test Conditions IOH = -4.0 mA VCC = Min Output high voltage for 3.3 V operation IOH = -3.2 mA VCC = Min Output low voltage for 5 V operation IOL = 24 mA VCC = Min Output low voltage for 3.3 V operation IOL = 10 mA VCC = Min Input leakage current VCC = Max VIN = GND or VCC I/O high-Z leakage current VCC = Max VIN = GND or VCC I/O capacitance VIN = GND f = 1.0 MHz Operating Supply Current VI = GND, No load (low power mode, active) f = 1.0 MHz Min 2.4 2.4 0.5 0.4 10.0 10.0 10.0 30 (Typ) Max Units V V V V A A pF mA

VOL

IIL IIH CIN ICC

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Units Min Max Min Max Min Max Min Max Min Max 5.0 6.0 7.5 10.0 15.0 ns 4.5 4.5 5.5 6.5 8.0 ns 0.0 0.0 0.0 0.0 0.0 ns 4.5 4.5 5.5 6.5 8.0 ns 100 100 83 67 56 MHz 100 100 83 67 56 MHz 0.5 0.5 1.5 2.5 4.0 ns 4.0 4.0 4.0 4.0 4.0 ns 8.5 8.5 9.5 10.5 12.0 ns 6.0 6.0 7.0 10.0 15.0 ns 6.0 6.0 7.0 10.0 15.0 ns 10.5 10.5 13.0 15.5 18.0 ns 10.5 10.5 13.0 15.5 18.0 ns 4.0 4.0 4.0 4.5 5.5 ns

Note: 1. fCNT is the fastest 16-bit counter frequency available.

fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-24

November 10, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max 1.5 2.0 4.0 6.0 2.0 0.0 4.5 1.0 9.0 0.5 4.0 0.5 0.5 6.0 5.0 1.0 9.0 4.5 4.5 1.0 3.5 5.0 1.0 9.0 4.5 4.5 1.0 3.5 4.0 0.5 0.5 6.0 7.5 2.0 10.0 6.0 6.0 1.0 4.0 1.5 2.0 4.0 6.0 2.0 0.0 4.5 1.0 9.0 1.5 3.5 2.0 0.5 6.5 10.0 2.5 11.0 8.5 8.5 1.0 4.5 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 11.0 1.5 5.0 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

November 10, 1997 (Version 2.0)

3-25

XC9536 In-System Programmable CPLD

XC9536 I/O Pins

Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 2 3 5 4 6 8 7 9 11 12 13 14 18 19 20 22 24 VQ44 40 41 43 42 44 2 1 3 5 6 7 8 12 13 14 16 18 BScan Notes Order 105 102 99 [1] 96 93 [1] 90 87 [1] 84 81 78 75 72 69 66 63 60 57 54 Function Block 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 1 44 42 43 40 39 38 37 36 35 34 33 29 28 27 26 25 VQ44 39 38 36 37 34 33 32 31 30 29 28 27 23 22 21 20 19 BScan Notes Order 51 48 45 [1] 42 39 [1] 36 [1] 33 30 27 24 21 18 15 12 9 6 3 0

[1] Global control pin

XC9536 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 23,10,31 VQ44 43 44 1 36 34 33 11 9 24 10 15,35 26 17,4,25

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November 10, 1997 (Version 2.0)

Ordering Information XC9536 -5 PC 44 C

Device Type Speed Temperature Range Number of Pins Package Type
Speed Options -15 -10 -7 -6 -5 15 ns 10 ns 7.5 ns 6 ns 5 ns pin-to-pin delay pin-to-pin delay pin-to-pin delay pin-to-pin delay pin-to-pin delay Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) VQ44 44-Pin Thin Quad Pack (VQFP) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code 15 10 7 6 5 Plastic PLCC PC44 C,I C,I C,I C C1 44 Plastic VQFP VQ44 C,I C,I C,I C C

XC9536

C = Commercial = 0 to +70C, I = Industrial = 40 to 85C Note: 1.Contact factory for availability

November 10, 1997 (Version 2.0)

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XC9536 In-System Programmable CPLD

3-28

November 10, 1997 (Version 2.0)

XC9572 In-System Programmable CPLD

0 3*

October 28, 1997 (Version 2.0)

Product Specification Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz)

Features
7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages

200

erform High P
Typical Icc (ma)

ance

(160)

(125) 100
ower Low P

(100)

(65)

50
Clock Frequency (MHz)

100

Description
The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

Figure 1: Typical ICC vs. Frequency for XC9572

Power Management
Power dissipation can be reduced in the XC9572 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

October 28, 1997 (Version 2.0)

3-29

XC9572 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

X5921

Figure 2: XC9572 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-30

October 28, 1997 (Version 2.0)

Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V C C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Note: 1. Numbers in parenthesis are for industrial temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

October 28, 1997 (Version 2.0)

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XC9572 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

Symbol VOH Parameter Output high voltage for 5 V operation Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL IIH CIN ICC Input leakage current I/O high-Z leakage current I/O capacitance Operating Supply Current (low power mode, active) Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 Max Units V V 2.4 0.5 0.4 10.0 10.0 10.0 65 (Typ) V V A A pF ma

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC9572-7 Min 5.5 0.0 5.5 125 83 1.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 Max 7.5 XC9572-10 Min 6.5 0.0 6.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 XC9572-15 Min 8.0 0.0 8.0 Max 15.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastst 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-32

October 28, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC9572-7 Min Max 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 2.0 0.5 6.5 7.5 2.0 10.0 6.0 2.0 1.0 4.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 XC9572-10 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 XC9572-15 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

October 28, 1997 (Version 2.0)

3-33

XC9572 In-System Programmable CPLD

XC9572 I/O Pins

Function Macrocell Block PC 44 PC 84 PQ 100 TQ 100 BScan Notes Order Function Macrocell Block PC 44 PC 84 PQ 100 TQ 100 BScan Notes Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

1 2 3 4 5 6 7 8 9 35 36 37 38 39 40 42 43 44

4 1 6 7 2 3 11 5 9 13 10 18 20 12 14 23 15 24 63 69 67 68 70 71 76 72 74 75 77 79 80 81 83 82 84

18 15 20 22 16 17 27 19 24 30 25 35 38 29 31 41 32 42 89 96 93 95 97 98 5 99 1 3 6 8 10 11 13 12 14 94

16 13 18 20 14 15 25 17 22 28 23 33 36 27 29 39 30 40 87 94 91 93 95 96 3 97 99 1 4 6 8 9 11 10 12 92

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

[1] [1]

[1]

[2] [1] [1]

[3]

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

11 12 13 14 18 19 20 22 24 25 26 27 28 29 33 34

25 17 31 32 19 34 35 21 26 40 33 41 43 36 37 45 39 46 44 51 52 47 54 55 48 50 57 53 58 61 56 65 62 66

43 34 51 52 37 55 56 39 44 62 54 63 65 57 58 67 60 61 68 66 73 74 69 78 79 70 72 83 76 84 87 80 91 88 92 81

41 32 49 50 35 53 54 37 42 60 52 61 63 55 56 65 58 59 66 64 71 72 67 76 77 68 70 81 74 82 85 78 89 86 90 79

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

Notes: [1] Global control pin

[2] Global control pin GTS1 for PC84, PQ100, and TQ100 [3] Global control pin GTS1 for PC44

3-34

October 28, 1997 (Version 2.0)

XC9572 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21,41 32 10,23,31

PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42, 49,60

PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71, 77,86 4,9,21,26,36,45,48, 75, 82

TQ100 22 23 27 3 4 99 48 45 83 47 5,57,98 26,38,51,88 100,21,31,44,62,69, 75, 84 2,7,19,24,34,43,46, 73, 80

October 28, 1997 (Version 2.0)

3-35

XC9572 In-System Programmable CPLD

Ordering Information XC9572 -7 PQ 100 C

Device Type Speed Temperature Range Number of Pins Package Type

Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7.5 ns pin-to-pin delay

Packaging Options PC44 PC84 PQ100 TQ100 44-Pin Plastic Leaded Chip Carrier (PLCC) 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Quad Flat Pack (TQFP) 0C to 70C 40C to 85C

Temperature Options C I Commercial Industrial

Component Availability
Pins Type Code XC9572 15 10 7 44 Plastic PLCC PC44 C,I C,I C 84 Plastic PLCC PC84 C,I C,I C 100 Plastic PQFP PQ100 C,I C,I C Plastic TQFP TQ100 C,I C,I C

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

3-36

October 28, 1997 (Version 2.0)

XC95108 In-System Programmable CPLD

0 3*

October 28, 1997 (Version 2.0)

Product Specification

Features
7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP and 160-pin PQFP packages

Power Management
Power dissipation can be reduced in the XC95108 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95108 device.

300

H
Typical ICC (mA)

rform igh Pe

ance

(250)

200 (180)
Low Power

(170)

Description
The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

100

50 Clock Frequency (MHz)

100
X5898

Figure 1: Typical ICC vs. Frequency for XC95108

October 28, 1997 (Version 2.0)

3-37

XC95108 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O

FastCONNECT Switch Matrix

Function Block 1 Macrocells 1 to 18

36 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 5 Macrocells 1 to 18

36 18

Function Block 6 Macrocells 1 to 18

X5897

Figure 2: XC95108 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-38

October 28, 1997 (Version 2.0)

Absolute Maximum Ratings

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

October 28, 1997 (Version 2.0)

3-39

XC95108 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95108-7 Min 5.5 0.0 5.5 125 83 1.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 Max 7.5 XC95108-10 XC95108-15 XC95108-20 Min 6.5 0.0 6.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 Min 8.0 0.0 8.0 83 50 4.0 6.0 16.0 20.0 20.0 22.0 22.0 5.5 Max 15.0 Min 10.0 0.0 10.0 Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable.
fCNT is also the Export Control Maximum ip-op toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.

3-40

October 28, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95108-7 Min Max 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 2.0 0.5 6.5 7.5 2.0 10.0 6.0 2.0 1.0 4.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 XC95108-10 XC95108-15 XC95108-20 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 20.0 3.0 11.5 13.0 5.0 1.5 5.5 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 6.5 0.5 9.0 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

October 28, 1997 (Version 2.0)

3-41

XC95108 In-System Programmable CPLD

XC95108 I/O Pins

Function Function BScan BScan Macrocell PC84 PQ100 TQ100 PQ160 Macrocell PC84 PQ100 TQ100 PQ160 Notes Notes Block Block Order Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

1 2 3 4 5 6 7 9 10 11 12 13 71 72 74 75 76 77 79 80 81 82 83 84

15 16 21 17 18 19 20 26 22 24 25 27 29 30 98 99 4 1 3 5 6 9 8 10 11 12 13 14

13 14 19 15 16 17 18 24 20 22 23 25 27 28 96 97 2 99 1 3 4 7 6 8 9 10 11 12

25 21 22 29 23 24 27 26 28 36 30 33 34 35 37 42 44 43 158 154 156 4 159 2 9 6 8 12 11 13 14 15 17 18 19 16

321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216

[1] [1] [1]

[1]

[1] [1]

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

14 15 17 18 19 20 21 23 24 25 26 31 57 58 61 62 63 65 66 67 68 69 70

31 32 36 34 35 37 38 45 39 41 42 43 44 51 83 84 82 87 88 89 91 92 93 95 96 94 97

29 30 34 32 33 35 36 43 37 39 40 41 42 49 81 82 80 85 86 87 89 90 91 93 94 92 95

45 47 49 57 54 56 50 58 59 69 60 62 52 63 64 68 77 74 123 134 135 133 138 139 128 140 142 147 143 144 153 146 148 145 152 155

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

Notes: [1] Global control pin

3-42

October 28, 1997 (Version 2.0)

XC95108 I/O Pins (continued)

Function Function BScan BScan Macrocell PC84 PQ100 TQ100 PQ160 Macrocell PC84 PQ100 TQ100 PQ160 Notes Notes Block Block Order Order

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

32 33 34 35 36 37 39 40 41 43 44

52 54 48 55 56 57 58 60 62 63 65 61 66

50 52 46 53 54 55 56 58 60 61 63 59 64

76 79 82 72 86 88 78 90 92 84 95 97 87 98 101 96 102 89

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

45 46 47 48 50 51 52 53 54 55 56

67 68 75 69 70 72 73 74 76 78 79 81 80

65 66 73 67 68 70 71 72 74 76 77 79 78

91 103 104 116 106 108 105 111 113 107 115 117 112 122 124 129 126 114

51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

XC95108 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND GND GND No connects PC84 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42,49,60 PQ100 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71,77,86 TQ100 PQ160 22 33 23 35 27 42 3 6 4 8 99 159 48 75 45 71 83 136 47 73 5,57,98 10,46,94,157 26,38,51,88 1,41,61,81,121,141 100,21,31,44,62,69,75,84 20,31,40,51,70,80,99 100,110,120,127,137 160 3,5,7,32,38,39,48,53,55,6 5,66,67,83,85,93,109, 118,119,125,130,131, 132,149,150,151

October 28, 1997 (Version 2.0)

3-43

XC95108 In-System Programmable CPLD

Ordering Information XC95108 -7 PQ 160 C

Device Type Temperature Range Number of Pins Speed Package Type

Speed Options - 20 -15 -10 -7 20 ns pin-to-pin delay 15 ns pin-to-pin delay 10 ns pin-to-pin delay 7 ns pin-to-pin delay

Packaging Options PC84 PQ100 TQ100 PQ160 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Quad Flat Pack (TQFP) 160-Pin Plastic Quad Flat Pack (PQFP) 0C to 70C 40C to 85C

Temperature Options C I Commercial Industrial

Component Availability
Pins Type Code 20 15 10 7 84 Plastic PLCC PC84 C,I C,I C,I C 100 Plastic PQFP PQ100 C,I C,I C,I C Plastic TQFP TQ100 C,I C,I C,I C 160 Plastic PQFP PQ160 C,I C,I C,I C

XC95108

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

3-44

October 28, 1997 (Version 2.0)

XC95144 In-System Programmable CPLD

0 3*

November 21, 1997 (Version 3.0)

Preliminary Product Specification Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device.

Features
7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages

600

(480)

Typical ICC (mA)

400

High

man erfor

(320) (300) 200 (160)

er Pow Low

Description
The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

50 Clock Frequency (MHz)

100
X5898B

Figure 1: Typical Icc vs. Frequency for XC95144

Power Management
Power dissipation can be reduced in the XC95144 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

November 21, 1997 (Version 3.0)

3-45

XC95144 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O

FastCONNECT Switch Matrix

Function Block 1 Macrocells 1 to 18

36 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 8 Macrocells 1 to 18

X5922

Figure 2: XC95144 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.

3-46

November 21, 1997 (Version 3.0)

Absolute Maximum Ratings

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

November 21, 1997 (Version 3.0)

3-47

XC95144 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95144-7 Min 5.5 0.0 5.5 125 83 1.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 Preliminary Max 7.5 XC95144-10 XC95144-15 Min 6.5 0.0 6.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 Min 8.0 0.0 8.0 Max 15.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

3-48

November 21, 1997 (Version 3.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95144-7 Min Max 2.5 2.5 4.5 7.0 2.5 0.0 4.0 2.0 10.5 0.5 3.5 2.0 0.5 6.5 7.5 2.0 10.0 6.0 2.0 1.0 4.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 Preliminary 3.5 3.0 0.5 7.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 XC95144-10 XC95144-15 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 4.5 0.5 8.0 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 Units

Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay tSUI Register setup time tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feedback delay Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

November 21, 1997 (Version 3.0)

3-49

XC95144 In-System Programmable CPLD

XC95144 I/O Pins

Function Macrocell Block 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 1 17 1 18 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 TQ 100 11 12 13 14 15 16 17 18 19 20 22 99 1 2 3 4 6 7 8 9 10 PQ 100 13 14 15 16 17 18 19 20 21 22 24 1 3 4 5 6 8 9 10 11 12 PQ BScan Notes 160 Order 25 429 18 426 19 423 27 420 21 417 22 414 32 411 23 408 24 405 34 402 26 399 28 396 38 393 29 390 30 387 39 384 33 381 [1] 378 158 375 159 372 [1] 3 369 5 366 2 363 [1] 4 360 [1] 7 357 6 354 [1] 8 351 [1] 9 348 11 345 12 342 14 339 13 336 15 333 16 330 17 327 324 Function Macrocell Block 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 TQ 100 23 24 25 27 28 29 30 32 33 34 87 89 90 91 92 93 94 95 96 97 PQ 100 25 26 27 29 30 31 32 34 35 36 89 91 92 93 94 95 96 97 98 99 PQ 160 43 35 45 48 36 37 50 42 44 52 47 49 53 54 56 55 57 132 140 147 149 142 143 150 144 145 151 146 148 153 152 154 155 156 BScan Notes Order 321 318 [1] 315 312 309 306 303 300 [1] 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216

Notes: [1] Global control pin.

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are xed.

3-50

November 21, 1997 (Version 3.0)

XC95144 I/O Pins (continued)

Function TQ Macrocell Block 100 5 1 5 2 35 5 3 5 4 5 5 36 5 6 37 5 7 5 8 39 5 9 40 5 10 5 11 41 5 12 42 5 13 5 14 43 5 15 46 5 16 5 17 49 5 18 6 1 6 2 74 6 3 6 4 6 5 76 6 6 77 6 7 6 8 78 6 9 79 6 10 6 11 80 6 12 81 6 13 6 14 82 6 15 85 6 16 6 17 86 6 18 PQ 100 37 38 39 41 42 43 44 45 48 51 76 78 79 80 81 82 83 84 87 88 PQ 160 65 58 66 67 59 60 74 62 63 76 64 68 78 69 72 83 77 117 119 123 122 124 125 126 129 128 133 134 130 135 138 131 139 BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Macrocell Block 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 10 8 11 8 12 8 13 8 14 8 15 8 16 8 17 8 18 TQ 100 50 52 53 54 55 56 58 59 60 61 63 64 65 66 67 68 70 71 72 73 PQ 100 52 54 55 56 57 58 60 61 62 63 65 66 67 68 69 70 72 73 74 75 PQ 160 79 84 85 82 86 87 88 90 89 92 95 91 96 97 93 98 101 105 107 102 103 109 104 106 112 108 111 114 113 115 118 116 BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

November 21, 1997 (Version 3.0)

3-51

XC95144 In-System Programmable CPLD

XC95144 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND TQ100 22 23 27 3 4 1 2 99 48 45 83 47 5, 57, 98 26, 38, 51, 88 100, 21, 31, 44, 62, 69, 75, 84 PQ100 24 25 29 5 6 3 4 1 50 47 85 49 7, 59, 100 28, 40, 53, 90 2, 23, 33, 46, 64, 71, 77, 86 PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10, 46, 94, 157 1, 41, 61, 81, 121, 141 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160

No Connects

3-52

November 21, 1997 (Version 3.0)

Ordering Information XC95144 -7 PQ 160 C

Device Type Temperature Range Number of Pins Speed Package Type

Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7 ns pin-to-pin delay

Packaging Options PQ100 100-Pin Plastic Quad Flat Pack (PQFP) TQ100 100-Pin Very Thin Quad Flat Pack (TQFP) PQ160 160-Pin Plastic Quad Flat Pack (PQFP) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code XC95144 15 10 7 100 Plastic PQFP PQ100 C,I C,I C Plastic TQFP TQ100 C,I C,I C 160 Plastic PQFP PQ160 C,I C,I C

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

November 21, 1997 (Version 3.0)

3-53

XC95144 In-System Programmable CPLD

3-54

November 21, 1997 (Version 3.0)

XC95216 In-System Programmable CPLD

0 3*

October 28, 1997 (Version 2.0)

Product Specification

Features
10 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 216 macrocells with 4800 usable gates Up to 166 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-10 speed grade) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 160-pin PQFP, 352-pin BGA, and 208-pin HQFP packages

Power Management
Power dissipation can be reduced in the XC95216 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95216 device.

600

High P
Typical ICC (mA)

erform

ance

(500)

400 (360)
ower Low P

(340)

Description
The XC95216 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of twelve 36V18 Function Blocks, providing 4,800 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview.

200

50 Clock Frequency (MHz)

100
X5918

Figure 1: Typical ICC vs. Frequency For XC95216

October 28, 1997 (Version 2.0)

3-55

XC95216 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O

FastCONNECT Switch Matrix

Function Block 1 Macrocells 1 to 18

36 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 12 Macrocells 1 to 18

X5917

Figure 2: XC95216 Architecture

Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-56

October 28, 1997 (Version 2.0)

Absolute Maximum Ratings

Recommended Operating Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

October 28, 1997 (Version 2.0)

3-57

XC95216 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95216-10 XC95216-15 XC95216-20 Min 6.5 0.0 6.5 111 67 2.5 4.0 10.5 10.0 10.0 15.5 15.5 4.5 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 Max 10.0 Min 8.0 0.0 8.0 83 50 4.0 6.0 16.0 20.0 20.0 22.0 22.0 5.5 Max 15.0 Min 10.0 0.0 10.0 Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

3-58

October 28, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95216-10 XC95216-15 XC95216-20 Min Max 3.5 3.0 6.0 10.0 3.0 0.0 3.5 2.5 12.0 1.0 3.5 3.0 0.5 7.0 10.0 2.5 11.0 8.5 2.5 1.0 4.5 15.0 3.0 11.5 11.0 3.5 1.5 5.0 3.5 4.5 0.5 8.0 20.0 3.0 11.5 13.0 5.0 1.5 5.5 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 6.5 0.5 9.0 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

October 28, 1997 (Version 2.0)

3-59

XC95216 In-System Programmable CPLD

XC95216 I/O Pins

Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

18 19 21 22 23 24 25 26 27 28 29 30 6 7 8 9 11 12 13 14 15 16 17

22 23 28 25 30 31 32 12 33 34 35 36 37 38 7 8 29 9 10 15 16 17 18 19 20 14 21

M25 M26 N26 N25 P23 P24 R26 G26 R24 T26 T25 T23 V26 U24 E25 G24 P25 F26 H23 K23 K24 J25 L24 K25 L26 H25 M24

645 642 639 636 633 630 627 624 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 546 543 540

[1]

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

32 33 34 35 36 37 38 39 42 43 44 152 153 154 155 156 158 159 2 3 4 5

43 44 39 45 46 47 49 67 50 51 55 56 80 57 198 199 196 200 201 202 205 206 3 4 5 203 6

AA26 Y24 U23 AB25 AA24 Y23 AA23 AD18 AB24 AD25 AD23 AF24 AE12 AE23 D18 A21 B19 B20 C20 B22 B24 C23 E23 C26 E24 D20 F24

537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432

[1]

[1] [1]

[1]

3-60

October 28, 1997 (Version 2.0)

XC95216 I/O Pins (continued)

Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order

5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

45 47 48 49 50 52 53 54 55 56 57 140 142 143 144 145 146 147 148 149 150 151

58 60 41 61 63 64 70 109 71 72 73 74 40 75 180 182 208 185 186 187 188 183 191 192 193 194 169 197

AE22 AE21 W25 AF21 AD19 AE20 AF18 AD1 AE17 AE16 AF16 AE14 Y26 AF14 A12 A13 D22 C14 A15 B15 C15 B14 A16 C16 C17 B18 D9 C19

429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

58 59 60 62 63 64 65 66 67 68 69 126 128 129 130 131 132 133 134 135 138 139

76 77 54 78 82 83 84 91 85 86 87 88 48 89 162 164 143 166 167 170 171 195 173 174 175 178 189 179

AE13 AC13 AE24 AD13 AD12 AC12 AF11 AD8 AE11 AE9 AD9 AC10 AC26 AF7 B5 B6 J1 D8 B7 C10 B9 A20 A9 D11 B11 C12 D15 B12

321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216

October 28, 1997 (Version 2.0)

3-61

XC95216 In-System Programmable CPLD

XC95216 I/O Pins (continued)

Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order Function Macrocell PQ160 HQ208 BG352 Block BScan Notes Order

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

72 74 76 77 78 79 82 83 84 85 86 113 114 115 116 117 118 119 122 123 124 125

95 97 101 99 100 102 103 90 110 111 112 113 62 114 147 148 144 149 150 152 154 168 155 158 159 160 165 161

AD7 AE5 AD4 AC7 AE3 AC5 AD3 AE8 AA4 AB2 AC1 AA2 AC19 AA1 H3 J4 K3 G2 G3 E2 D2 A7 F4 B3 A3 D6 A6 C6

213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108

11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

87 88 89 90 91 92 93 95 96 97 98 101 102 103 104 105 106 107 108 109 111 112

115 116 119 117 118 121 122 107 123 125 126 127 120 128 131 133 106 134 135 136 137 151 138 139 140 145 142 146

Y1 V4 U4 V3 W2 V2 U2 AC3 T2 R4 R3 R2 U3 R1 P1 N2 AD2 N4 N3 M1 M3 F2 M4 L1 L2 G1 L3 H2

105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

3-62

October 28, 1997 (Version 2.0)

XC95216 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10,46,94,157 1,41,61,81,121,141 HQ208 BG352 44 Y24 46 AA24 55 AD23 7 E25 9 F26 3 E23 5 E24 206 C23 98 AD6 94 AF6 176 D12 96 AE6 11, 59, 124, 153, 204 H24, AF23, T1, G4, C22 1, 26, 53, 65, 79, 92, 105, 132, A10, A17, B2, B25, D7, D13, 157, 172, 181, 184 D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 2, 13, 24, 27, 42, 52, 66, 68, 69, A1, A2, A5, A8, A14, A19, A22, 81, 93, 104, 108, 129, 130, 141, A25, A26, B1, B26, C7, E1, E26, 156, 163, 177, 190, 207 H1, H26, N1, P3, P26, V23, W1, W26, AB1, AB4, AB26, AC9, AC17, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF20, AF22, AF25, AF26 A4, A11, A18, A23, A24, B4, B8, B10, B13, B16, B17, B21, B23, C1, C2, C3, C4, C5, C8, C9, C11, C13, C18, C21, C24, C25, D1, D3, D4, D5, D10, D14, D16, D17, D21, D23, D24, D25, D26, E3, E4, F1, F3, F23, F25, G25, J2, J3, J23, J24, J26, K2, K4, L4, L23, L25, M2, M23, N24, P2, R23, R25, T3, T4, T24, U25, V1, V24, V25, W3, W4, W24, Y2, Y3, Y25, AA3, AA25, AB3, AB23, AC2, AC4, AC6, AC11, AC15, AC16, AC18, AC21, AC22, AC23, AC24, AC25, AD5, AD10, AD11, AD14, AD15, AD16, AD17, AD20, AD21, AD22, AD24, AD26, AE2, AE4, AE7, AE10, AE15, AE18, AE19, AF3, AF4, AF9, AF12, AF15

GND

20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160

No Connects

October 28, 1997 (Version 2.0)

3-63

XC95216 In-System Programmable CPLD

Ordering Information XC95216 -10 HQ 208 C

Device Type Temperature Range Number of Pins Speed Package Type

Speed Options - 20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay

Packaging Options PQ160 160-Pin Plastic Quad Flat Pack (PQFP) HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP) BG352 352-Pin Ball Grid Array (BGA) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code XC95216 20 15 10 160 Plastic PQFP PQ160 C,I C C 160 Power QFP HQ208 C,I C C 352 Plastic BGA BG352 C,I C,I C

C = Commercial = 0 to +70C

I = Industrial = 40 to 85C

3-64

October 28, 1997 (Version 2.0)

XC95288 In-System Programmable CPLD

0 3*

November 12, 1997 (Version 2.0)

Preliminary Product Specification MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz)
900

Features
15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz 288 macrocells with 6,400 usable gates Up to 192 user I/O pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant ( -10 speed grade) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 352-pin BGA and 208-pin HQFP packages

Typical ICC (mA)

600 (500)

ance erform High P

(700)

(500)
o Low P w er

300

50 Clock Frequency (MHz)

100
X7131

Figure 1: Typical ICC vs. Frequency For XC95288

Description
The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen 36V18 Function Blocks, providing 6,400 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview.

Power Management
Power dissipation can be reduced in the XC95288 by conguring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specic operating conditions using the following equation: ICC (mA) =

November 12, 1997 (Version 2.0)

3-65

XC95288 In-System Programmable CPLD

3 JTAG Port 1

JTAG Controller

In-System Programming Controller

36 I/O I/O I/O I/O FastCONNECT Switch Matrix 36 18 18

Function Block 1 Macrocells 1 to 18

Function Block 2 Macrocells 1 to 18

I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2

36 18

Function Block 3 Macrocells 1 to 18

36 18

Function Block 4 Macrocells 1 to 18

36 18

Function Block 16 Macrocells 1 to 18

X5924

Figure 2: XC95288 Architecture

Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly

3-66

November 12, 1997 (Version 2.0)

Absolute Maximum Ratings

Recommended Operation Conditions

Symbol VCCINT VCCIO VIL VIH VO Parameter

Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0

Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO

Units V V V V V V

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

Endurance Characteristics
Symbol tDR NPE Parameter Data Retention Program/Erase Cycles Min 20 10,000 Max Units Years Cycles

November 12, 1997 (Version 2.0)

3-67

XC95288 In-System Programmable CPLD

DC Characteristics Over Recommended Operating Conditions

AC Characteristics
Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95288-15 XC95288-20 Min 8.0 0.0 8.0 95 56 4.0 4.0 12.0 15.0 15.0 18.0 18.0 5.5 83 50 4.0 6.0 16.0 20.0 20.0 22.0 22.0 5.5 Max 15.0 Min 10.0 0.0 10.0 Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns

3-68

November 12, 1997 (Version 2.0)

VTEST R1 Device Output R2 CL

Output Type

VCCIO 5.0 V 3.3 V

VTEST 5.0 V 3.3 V

R1 160 260

R2 120 360

CL 35 pF 35 pF
X5906

Figure 3: AC Load Circuit

Internal Timing Parameters

Symbol Parameter XC95288-15 XC95288-20 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 4.5 0.5 8.0 15.0 3.0 11.5 11.0 3.5 1.5 5.0 20.0 3.0 11.5 13.0 5.0 1.5 5.5 3.5 6.5 0.5 9.0 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note: 3. tPTA is multiplied by the span of the function as dened in the family data sheet.

November 12, 1997 (Version 2.0)

3-69

XC95288 In-System Programmable CPLD

XC95288 I/O Pins

Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 32 33 34 35 36 37 15 16 17 18 19 20 21 22 23 25 N26 P25 P23 P24 R26 R25 R24 R23 T26 T25 T23 V26 K23 K24 J25 L24 K25 L25 L26 M23 M24 M25 M26 N25 BScan Notes Order 861 858 855 852 849 846 843 840 837 834 831 828 825 822 819 816 813 810 807 804 801 798 795 792 789 786 783 780 777 774 771 768 765 762 759 756 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 38 39 40 41 43 44 45 46 47 48 3 4 5 6 7 8 9 10 12 14 U24 U23 Y26 W25 AA26 Y25 Y24 AA25 AB25 AA24 Y23 AC26 E23 C26 E24 F24 E25 D26 G24 F25 F26 H23 G26 H25 BScan Notes Order 753 750 747 744 741 738 735 732 729 726 [1] 723 720 717 714 [1] 711 708 705 702 699 696 [1] 693 690 687 [1] 684 681 678 [1] 675 672 669 666 [1] 663 660 657 654 651 648

Notes: [1] Global control pin

Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are xed.

3-70

November 12, 1997 (Version 2.0)

XC95288 I/O Pins (continued)

Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Note: Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 49 50 51 54 55 56 57 58 60 61 197 198 199 200 201 202 203 205 206 208 AA23 AB24 AD25 AE24 AD23 AC22 AF24 AD22 AE23 AE22 AE21 AF21 C19 D18 A21 B20 C20 B21 B22 C21 D20 B24 C23 D22 BScan Notes Order 645 642 639 636 633 630 627 624 [1] 621 618 615 612 609 606 603 600 597 594 591 588 585 582 579 576 573 570 567 564 561 558 555 552 549 [1] 546 543 540 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 62 63 64 66 67 69 70 71 72 73 186 187 188 189 191 192 193 194 195 196 AC19 AD19 AE20 AC18 AD18 AE19 AD17 AE18 AF18 AE17 AE16 AF16 A15 B15 C15 D15 A16 B16 C16 B17 C17 B18 A20 B19 BScan Notes Order 537 534 531 528 525 522 519 516 513 510 507 504 501 498 495 492 489 486 483 480 477 474 471 468 465 462 459 456 453 450 447 444 441 438 435 432

[1] Global control pin

November 12, 1997 (Version 2.0)

3-71

XC95288 In-System Programmable CPLD

XC95288 I/O Pins (continued)

Function Block 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 74 75 76 77 78 80 82 83 84 85 86 170 171 173 174 175 178 179 180 182 183 185 AE14 AF14 AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 AE11 AE9 C10 B9 A9 D11 B11 A11 C12 B12 A12 A13 B14 C14 BScan Notes Order 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324 Function Block 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 87 88 89 90 91 95 97 99 100 101 102 158 159 160 161 162 164 165 166 167 168 169 BScan Notes Order 321 AD9 318 AC10 315 312 AF7 309 AE8 306 303 AD8 300 AE7 297 AD7 294 AE5 291 AC7 288 285 AE3 282 AD4 279 276 AC5 273 270 267 B3 264 A3 261 258 D6 255 C6 252 249 B5 246 A4 243 B6 240 A6 237 D8 234 231 B7 228 A7 225 222 D9 219 216

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XC95288 I/O Pins (continued)

Function Block 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 103 106 107 109 110 111 112 113 114 115 116 144 145 146 147 148 149 150 151 152 154 155 AD3 AD2 AC3 AD1 AA4 AA3 AB2 AC1 AA2 AA1 Y1 V4 K3 G1 H2 H3 J4 F1 G2 G3 F2 E2 D2 F4 BScan Notes Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Block 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Macrocell HQ208 BG352 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 117 118 119 120 121 122 123 125 126 127 128 131 133 134 135 136 137 138 139 140 142 143 V3 W2 U4 U3 V2 V1 U2 T2 R4 R3 R2 R1 P1 N2 N4 N3 M1 M2 M3 M4 L1 L2 L3 J1 BScan Notes Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0

November 12, 1997 (Version 2.0)

3-73

XC95288 In-System Programmable CPLD

XC95288 Global, JTAG and Power Pins

Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5 V BG352 Y24 AA24 AD23 E25 F26 E23 E24 C23 AD6 AF6 D12 AE6 J23, V24, AF23, AC15, AF15, AD11, AD5, Y3, T1, J3, G4, D5, D10, B13, D17, C22, H24 1, 26, 53, 65, 79, 92, 105, 132, A10, A17, B2, B25, D7, D13, 157, 172, 181, 184 D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 2, 13, 24, 27, 42, 52, 68, 81, 93, A1, A2, A5, A8, A14, A19, A22, 104,108, 129, 130, 141, 156, A25, A26, B1, B26, C7, C9, C13, 163, 177, 190, 207 C18, D24, E1, E26, H1, H26, K4, N1, N24, P3, P26, V23, W1, W4, W26, AB1, AB4, AB26, AC9, AD10, AD14, AD15, AD20, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 A18, A23, A24, B4, B8, B10, B23, C1, C2, C3, C4, C5, C8, C11, C24, C25, D1, D3, D4, D14, D16, D21, D23, D25, E3, E4, F3, F23, G25, J2, J24, J26, K2, L4, L23, P2, T3, T4, T24, U25, V25, W3, W24, Y2, AB3, AB23, AC2, AC4, AC6, AC11, AC16, AC17, AC21, AC23, AC24, AC25, AD16, AD21, AD24, AD26, AE2, AE4, AE10, AE15, AF3, AF4, AF9, AF20 HQ208 44 46 55 7 9 3 5 206 98 94 176 96 11, 59, 124, 153, 204

VCCIO 3.3 V/5 V

GND

No Connects

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November 12, 1997 (Version 2.0)

Ordering Information XC95288 -15 HQ 208 C

Device Type Speed Temperature Range Number of Pins Package Type

Speed Options - 20 20 ns pin-to-pin delay -15 15 ns pin-to-pin delay

Packaging Options HQ208 208-Pin Heat Sink Quad Flat Pack (HQFP) BG352 352-Pin Plastic Ball Grid Array (BGA) Temperature Options C I Commercial Industrial 0C to 70C 40C to 85C

Component Availability
Pins Type Code XC95288 20 15 208 Plastic HQFP HQ C,I C 352 Plastic BGA BG C,I C
I = Industrial = 40 to 85C

C = Commercial = 0 to +70C

November 12, 1997 (Version 2.0)

3-75

XC95288 In-System Programmable CPLD

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November 12, 1997 (Version 2.0)

FPGA Products

1 2 3 4 5 6 7 8 9

10 Packages and Thermal Characteristics 11 Testing, Quality, and Reliability 12 Technical Support and Services 13 Product Technical Information 14 Index

FPGA Products Table of Contents

XC4000E and XC4000X Series Table of Contents

1 4*

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E and XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Versions Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional XC4000X Series Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Taking Advantage of Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E and XC4000X Series Compared to the XC4000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improvements in XC4000E and XC4000X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Improvements in XC4000X Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configurable Logic Blocks (CLBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latches (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Set/Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Inputs and Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using FPGA Flip-Flops and Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Function Generators as RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast Carry Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output Blocks (IOBs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IOB Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other IOB Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-State Buffer Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wide Edge Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Chip Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnect Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLB Routing Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Switch Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-Length Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Double-Length Lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quad Lines (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Longlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Direct Interconnect (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octal I/O Routing (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000E only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Nets and Buffers (XC4000X only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4-5 4-5 4-5 4-6 4-6 4-7 4-7 4-8 4-9 4-9 4-9 4-9 4-10 4-10 4-10 4-10 4-11 4-11 4-11 4-11 4-11 4-11 4-18 4-21 4-21 4-24 4-26 4-27 4-27 4-27 4-28 4-28 4-29 4-29 4-29 4-30 4-30 4-32 4-32 4-32 4-33 4-33 4-33 4-36 4-36 4-38 4-40

4-1

XC4000E and XC4000X Series Table of Contents

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Including Boundary Scan in a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Avoiding Inadvertent Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Address lines in XC4000 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting CCLK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Stream Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cyclic Redundancy Check (CRC) for Configuration and Readback . . . . . . . . . . . . . . . . . . . . . . Configuration Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Memory Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delaying Configuration After Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of User I/O After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release of Global Set/Reset After DONE Goes High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Through the Boundary Scan Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Violating the Maximum High and Low Time Specification for the Readback Clock . . . . . . . . . . Readback with the XChecker Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E/EX/XL Program Readback Switching Characteristic Guidelines . . . . . . . . . . . . . . . . Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Address lines in XC4000 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes (XC4000E/EX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Modes (XC4000XL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave and Peripheral Modes(All) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Additional Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-40 4-43 4-43 4-45 4-45 4-45 4-46 4-46 4-46 4-47 4-47 4-47 4-47 4-47 4-49 4-49 4-50 4-51 4-51 4-52 4-52 4-52 4-55 4-55 4-55 4-55 4-55 4-56 4-57 4-57 4-57 4-57 4-57 4-57 4-58 4-61 4-61 4-62 4-63 4-63 4-65 4-67 4-67 4-67 4-69 4-69 4-69 4-69 4-70 4-70 4-70 4-70 4-70 4-71 4-72 4-73

4-2

XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . XC4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . XC4000XL Pin-to-Pin Output Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitive Load Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Pin-to-Pin Input Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL Global Low Skew Clock, Set-Up and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL . . . . . XC4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL . . . . . XC4000XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000XL IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX DC Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . XC4000EX Longline and Wide Decoder Timing Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines . XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics . . . . . . . . . . . . . XC4000EX Pin-to-Pin Output Parameter Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Output MUX, Clock to Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Output Level and Slew Rate Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Pin-to-Pin Input Parameter Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Global Early Clock, Set-Up and Hold for IFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Global Early Clock, Set-Up and Hold for FCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX Input Threshold Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX IOB Input Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000EX IOB Input Switching Characteristic Guidelines (Continued) . . . . . . . . . . . . . . . . . . . XC4000EX IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Global Buffer Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Horizontal Longline Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . XC4000E Wide Decoder Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . . . . . . . . . XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . XC4000E CLB Level-Sensitive RAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) . . . . . . . . . . . . . . . . XC4000E IOB Input Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E IOB Output Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines . . . . . . . . . . . . . . . . . . . Device-Specific Pinout Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4003E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4005E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4006E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4008E Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4010E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-76 4-76 4-77 4-78 4-79 4-79 4-80 4-81 IOB Input 4-82 4-83 4-84 4-84 4-84 4-84 4-85 4-86 4-86 4-87 4-89 4-89 4-90 4-91 4-92 4-92 4-92 4-93 4-93 4-93 4-93 4-94 4-95 4-96 4-97 4-97 4-97 4-97 4-98 4-98 4-99 4-100 4-101 4-104 4-104 4-105 4-106 4-107 4-108 4-110 4-112 4-113 4-113 4-114 4-115 4-117 4-118

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XC4000E and XC4000X Series Table of Contents

Pin Locations for XC4013E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4020E/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4025E, XC4028EX/XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4036EX/XL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4044XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4052XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4062XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Locations for XC4085XL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User I/O Per Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-120 4-123 4-125 4-128 4-131 4-135 4-139 4-143 4-151 4-153 4-154

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XC4000E and XC4000X Series Field Programmable Gate Arrays

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Product Specification

XC4000E and XC4000X Series Features

Note: XC4000 Series devices described in this data sheet include the XC4000E family and XC4000X Series. XC4000X Series devices described in this data sheet include the XC4000EX and XC4000XL families. Separate data sheets are available for two other Families in the XC4000X series, the XC4000XLT and XC4000XV. This information does not apply to the older Xilinx families: XC4000, XC4000A, XC4000D, XC4000H, or XC4000L. For information on these devices, see the Xilinx WEBLINX at http://www.xilinx.com. System featured Field-Programmable Gate Arrays - Select-RAMTM memory: on-chip ultra-fast RAM with - synchronous write option - dual-port RAM option - Fully PCI compliant (speed grades -2 and faster) - Abundant ip-ops - Flexible function generators - Dedicated high-speed carry logic - Wide edge decoders on each edge - Hierarchy of interconnect lines - Internal 3-state bus capability - 8 global low-skew clock or signal distribution networks System Performance beyond 80 MHz Flexible Array Architecture Low Power Segmented Routing Architecture Systems-Oriented Features - IEEE 1149.1-compatible boundary scan logic support - Individually programmable output slew rate - Programmable input pull-up or pull-down resistors - 12-mA sink current per XC4000E output Congured by Loading Binary File - Unlimited reprogrammability Readback Capability - Program verication - Internal node observability Backward Compatible with XC4000 Devices Development System runs on most common computer platforms - Interfaces to popular design environments - Fully automatic mapping, placement and routing - Interactive design editor for design optimization

Low-Voltage Versions Available

Low-Voltage Devices Function at 3.0 - 3.6 Volts XC4000XL: High Performance Low-Voltage Versions of XC4000EX devices

Additional XC4000X Series Features

Highest Performance 3.3 V XC4000XL Highest Capacity Over 180,000 Usable Gates 5V tolerant I/Os on XC4000XL 0.35 SRAM process for XC4000XL Additional Routing Over XC4000E - almost twice the routing capacity for high-density designs Buffered Interconnect for Maximum Speed New Latch Capability in Congurable Logic Blocks Improved VersaRingTM I/O Interconnect for Better Fixed Pinout Flexibility 12-mA Sink Current Per XC4000X Output Flexible New High-Speed Clock Network - 8 additional Early Buffers for shorter clock delays - Virtually unlimited number of clock signals Optional Multiplexer or 2-input Function Generator on Device Outputs 4 Additional Address Bits in Master Parallel Conguration Mode XC4000XLT devices, optimized for PCI applications, are available. The XC4000XV Family offers the highest density with 0.25 micron 2.5 volt technology.

Introduction
XC4000 Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benets of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of thirteen years of FPGA design experience and feedback from thousands of customers, these FPGAs combine architectural versatility, on-chip Select-RAM memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. The XC4000E and XC4000X Series currently have 20 members, as shown in Table 2.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Note: All functionality in low-voltage families is the same as in the corresponding 5-Volt family, except where numerical references are made to timing or power. Table 2: XC4000E and XC4000X Series Field Programmable Gate Arrays Logic Cells 152 238 466 608 770 950 1368 1862 2432 2432 3078 3800 4598 5472 7448 Max Logic Max. RAM Gates Bits (No RAM) (No Logic) 1,600 2,048 3,000 3,200 5,000 6,272 6,000 8,192 8,000 10,368 10,000 12,800 13,000 18,432 20,000 25,088 25,000 32,768 28,000 32,768 36,000 41,472 44,000 51,200 52,000 61,952 62,000 73,728 85,000 100,352 Typical Gate Range (Logic and RAM)* 1,000 - 3,000 2,000 - 5,000 3,000 - 9,000 4,000 - 12,000 6,000 - 15,000 7,000 - 20,000 10,000 - 30,000 13,000 - 40,000 15,000 - 45,000 18,000 - 50,000 22,000 - 65,000 27,000 - 80,000 33,000 - 100,000 40,000 - 130,000 55,000 - 180,000 CLB Matrix 8x8 10 x 10 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 28 x 28 32 x 32 32 x 32 36 x 36 40 x 40 44 x 44 48 x 48 56 x 56 Total CLBs 64 100 196 256 324 400 576 784 1,024 1,024 1,296 1,600 1,936 2,304 3,136 Number of Max. Flip-Flops User I/O 256 64 360 80 616 112 768 128 936 144 1,120 160 1,536 192 2,016 224 2,560 256 2,560 256 3,168 288 3,840 320 4,576 352 5,376 384 7,168 448

Device XC4002XL XC4003E XC4005E/XL XC4006E XC4008E XC4010E/XL XC4013E/XL XC4020E/XL XC4025E XC4028EX/XL XC4036EX/XL XC4044XL XC4052XL XC4062XL XC4085XL

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Description
XC4000 Series devices are implemented with a regular, exible, programmable architecture of Congurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable Input/Output Blocks (IOBs). They have generous routing resources to accommodate the most complex interconnect patterns. The devices are customized by loading conguration data into internal memory cells. The FPGA can either actively read its conguration data from an external serial or byteparallel PROM (master modes), or the conguration data can be written into the FPGA from an external device (slave and peripheral modes). XC4000 Series FPGAs are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, oorplanning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and readback of the conguration bit stream. Because Xilinx FPGAs can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hardware must be adapted to different user applications.

FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per month. For lowest high-volume unit cost, a design can rst be implemented in the XC4000E or XC4000X, then migrated to one of Xilinx compatible HardWire mask-programmed devices.

Taking Advantage of Reconguration

FPGA devices can be recongured to change logic function while resident in the system. This capability gives the system designer a new degree of freedom not available with any other type of logic. Hardware can be changed as easily as software. Design updates or modications are easy, and can be made to products already in the eld. An FPGA can even be recongured dynamically to perform different functions at different times. Recongurable logic can be used to implement system self-diagnostics, create systems capable of being recongured for different environments or operations, or implement multi-purpose hardware for a given application. As an added benet, using recongurable FPGA devices simplies hardware design and debugging and shortens product time-to-market.

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XC4000E and XC4000X Series Compared to the XC4000

For readers already familiar with the XC4000 family of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000 Series devices are listed in this section. The biggest advantages of XC4000E and XC4000X devices are signicantly increased system speed, greater capacity, and new architectural features, particularly Select-RAM memory. The XC4000X devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. Any XC4000E device is pinout- and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device. However, since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device. XC4000X Series devices are not bitstream-compatible with equivalent array size devices in the XC4000 or XC4000E families. However, equivalent array size devices, such as the XC4025, XC4025E, XC4028EX, and XC4028XL, are pinout-compatible.

much as 50% from XC4000 values. See Fast Carry Logic on page 4-18 for more information. Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes The RAM in any CLB can be congured for synchronous, edge-triggered, write operation. The read operation is not affected by this change to an edge-triggered write. Dual-Port RAM A separate option converts the 16x2 RAM in any CLB into a 16x1 dual-port RAM with simultaneous Read/Write. The function generators in each CLB can be congured as either level-sensitive (asynchronous) single-port RAM, edge-triggered (synchronous) single-port RAM, edge-triggered (synchronous) dual-port RAM, or as combinatorial logic. Congurable RAM Content The RAM content can now be loaded at conguration time, so that the RAM starts up with user-dened data. H Function Generator In current XC4000 Series devices, the H function generator is more versatile than in the original XC4000. Its inputs can come not only from the F and G function generators but also from up to three of the four control input lines. The H function generator can thus be totally or partially independent of the other two function generators, increasing the maximum capacity of the device. IOB Clock Enable The two ip-ops in each IOB have a common clock enable input, which through conguration can be activated individually for the input or output ip-op or both. This clock enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the IOBs more versatile, and avoids the need for clock gating. Output Drivers The output pull-up structure defaults to a TTL-like totempole. This driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below Vcc, just like the XC4000 family outputs. Alternatively, XC4000 Series devices can be globally congured with CMOS outputs, with p-channel pull-up transistors pulling to Vcc. Also, the congurable pull-up resistor in the XC4000 Series is a pchannel transistor that pulls to Vcc, whereas in the original XC4000 family it is an n-channel transistor that pulls to a voltage one transistor threshold below Vcc.

Improvements in XC4000E and XC4000X

Increased System Speed XC4000E and XC4000X devices can run at synchronous system clock rates of up to 80 MHz, and internal performance can exceed 150 MHz. This increase in performance over the previous families stems from improvements in both device processing and system architecture. XC4000 Series devices use a sub-micron multi-layer metal process. In addition, many architectural improvements have been made, as described below. The XC4000XL family is a high performance 3.3V family based on 0.35 SRAM technology and supports system speeds to 80 MHz. PCI Compliance XC4000 Series -2 and faster speed grades are fully PCI compliant. XC4000E and XC4000X devices can be used to implement a one-chip PCI solution. Carry Logic The speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carry chain through a single CLB (TBYP), have improved by as

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Input Thresholds The input thresholds of 5V devices can be globally congured for either TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like XC2000 and XC3000 inputs. The two global adjustments of input threshold and output level are independent of each other. The XC4000XL family has an input threshold of 1.6V, compatible with both 3.3V CMOS and TTL levels. Global Signal Access to Logic There is additional access from global clocks to the F and G function generator inputs. Conguration Pin Pull-Up Resistors During conguration, the three mode pins, M0, M1, and M2, have weak pull-up resistors. For the most popular conguration mode, Slave Serial, the mode pins can thus be left unconnected. The three mode inputs can be individually congured with or without weak pull-up or pull-down resistors after conguration. The PROGRAM input pin has a permanent weak pull-up. Soft Start-up Like the XC3000A, XC4000 Series devices have Soft Start-up. When the conguration process is nished and the device starts up, the rst activation of the outputs is automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. Immediately after start-up, the slew rate of the individual outputs is, as in the XC4000 family, determined by the individual conguration option. XC4000 and XC4000A Compatibility Existing XC4000 bitstreams can be used to congure an XC4000E device. XC4000A bitstreams must be recompiled for use with the XC4000E due to improved routing resources, although the devices are pin-for-pin compatible.

Additional Improvements in XC4000X Only

Increased Routing New interconnect in the XC4000X includes twenty-two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs. The twelve Quad Lines in each CLB row and column include optional repowering buffers for maximum speed. Additional highperformance routing near the IOBs enhances pin exibility. Faster Input and Output A fast, dedicated early clock sourced by global clock buffers is available for the IOBs. To ensure synchronization with the regular global clocks, a Fast Capture latch driven by the early clock is available. The input data can be initially loaded into the Fast Capture latch with the early clock, then transferred to the input ip-op or latch with the low-skew global clock. A programmable delay on the input can be used to avoid hold-time requirements. See IOB Input Signals on page 4-21 for more information. Latch Capability in CLBs Storage elements in the XC4000X CLB can be congured as either ip-ops or latches. This capability makes the FPGA highly synthesis-compatible. IOB Output MUX From Output Clock A multiplexer in the IOB allows the output clock to select either the output data or the IOB clock enable as the output to the pad. Thus, two different data signals can share a single output pad, effectively doubling the number of device outputs without requiring a larger, more expensive package. This multiplexer can also be congured as an ANDgate to implement a very fast pin-to-pin path. See IOB Output Signals on page 4-24 for more information. Additional Address Bits Larger devices require more bits of conguration data. A daisy chain of several large XC4000X devices may require a PROM that cannot be addressed by the eighteen address bits supported in the XC4000E. The XC4000X Series therefore extends the addressing in Master Parallel conguration mode to 22 bits.

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Detailed Functional Description

XC4000 Series devices achieve high speed through advanced semiconductor technology and improved architecture. The XC4000E and XC4000X support system clock rates of up to 80 MHz and internal performance in excess of 150 MHz. Compared to older Xilinx FPGA families, XC4000 Series devices are more powerful. They offer onchip edge-triggered and dual-port RAM, clock enables on I/ O ip-ops, and wide-input decoders. They are more versatile in many applications, especially those involving RAM. Design cycles are faster due to a combination of increased routing resources and more sophisticated software.

Each CLB contains two storage elements that can be used to store the function generator outputs. However, the storage elements and function generators can also be used independently. These storage elements can be congured as ip-ops in both XC4000E and XC4000X devices; in the XC4000X they can optionally be congured as latches. DIN can be used as a direct input to either of the two storage elements. H1 can drive the other through the H function generator. Function generator outputs can also drive two outputs independent of the storage element outputs. This versatility increases logic capacity and simplies routing. Thirteen CLB inputs and four CLB outputs provide access to the function generators and storage elements. These inputs and outputs connect to the programmable interconnect resources outside the block.

Basic Building Blocks

Xilinx user-programmable gate arrays include two major congurable elements: congurable logic blocks (CLBs) and input/output blocks (IOBs). CLBs provide the functional elements for constructing the users logic. IOBs provide the interface between the package pins and internal signal lines.

Function Generators
Four independent inputs are provided to each of two function generators (F1 - F4 and G1 - G4). These function generators, with outputs labeled F and G, are each capable of implementing any arbitrarily dened Boolean function of four inputs. The function generators are implemented as memory look-up tables. The propagation delay is therefore independent of the function implemented. A third function generator, labeled H, can implement any Boolean function of its three inputs. Two of these inputs can optionally be the F and G functional generator outputs. Alternatively, one or both of these inputs can come from outside the CLB (H2, H0). The third input must come from outside the block (H1). Signals from the function generators can exit the CLB on two outputs. F or H can be connected to the X output. G or H can be connected to the Y output. A CLB can be used to implement any of the following functions: any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables1 any single function of ve variables any function of four variables together with some functions of six variables some functions of up to nine variables.

Three other types of circuits are also available: 3-State buffers (TBUFs) driving horizontal longlines are associated with each CLB. Wide edge decoders are available around the periphery of each device. An on-chip oscillator is provided.

Programmable interconnect resources provide routing paths to connect the inputs and outputs of these congurable elements to the appropriate networks. The functionality of each circuit block is customized during conguration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA. Each of these available circuits is described in this section.

Congurable Logic Blocks (CLBs)

Congurable Logic Blocks implement most of the logic in an FPGA. The principal CLB elements are shown in Figure 2. Two 4-input function generators (F and G) offer unrestricted versatility. Most combinatorial logic functions need four or fewer inputs. However, a third function generator (H) is provided. The H function generator has three inputs. Either zero, one, or two of these inputs can be the outputs of F and G; the other input(s) are from outside the CLB. The CLB can, therefore, implement certain functions of up to nine variables, like parity check or expandableidentity comparison of two sets of four inputs.

Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators signicantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This exibility improves cell usage.

1. When three separate functions are generated, one of the function outputs must be captured in a ip-op internal to the CLB. Only two unregistered function generator outputs are available from the CLB.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

C1 C4

D IN /H 2

SR/H 0

G4 G3 G2 G1 LOGIC FUNCTION OF H' F', G', AND H1 F4 F3 F2 F1 LOGIC FUNCTION F' OF F1-F4 DIN F' G' H' LOGIC FUNCTION G' OF G1-G4 DIN F' G' H'

S/R CONTROL D SD

Bypass YQ Q

EC G' H' RD 1 Y S/R CONTROL D SD Q Bypass XQ

EC K (CLOCK) H' F' Multiplexer Controlled by Configuration Program RD 1 X

X6692

Figure 2: Simplied Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)

Flip-Flops
The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial results or other incoming data in one or two ip-ops, and connect their outputs to the interconnect network as well. The two edge-triggered D-type ip-ops have common clock (K) and clock enable (EC) inputs. Either or both clock inputs can also be permanently enabled. Storage element functionality is described in Table 3.

Clock Enable
The clock enable signal (EC) is active High. The EC pin is shared by both storage elements. If left unconnected for either, the clock enable for that storage element defaults to the active state. EC is not invertible within the CLB. Table 3: CLB Storage Element Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop K X X __/ 0 1 0 X EC X X 1* X 1* 1* 0 SR X 1 0* 0* 0* 0* 0* D X X D X X D X Q SR SR D Q Q D Q

Latches (XC4000X only)

The CLB storage elements can also be congured as latches. The two latches have common clock (K) and clock enable (EC) inputs. Storage element functionality is described in Table 3.

Clock Input
Each ip-op can be triggered on either the rising or falling clock edge. The clock pin is shared by both storage elements. However, the clock is individually invertible for each storage element. Any inverter placed on the clock input is automatically absorbed into the CLB.

Latch Both
Legend: X __/ SR 0* 1*

Dont care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

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Set/Reset
An asynchronous storage element input (SR) can be congured as either set or reset. This conguration option determines the state in which each ip-op becomes operational after conguration. It also determines the effect of a Global Set/Reset pulse during normal operation, and the effect of a pulse on the SR pin of the CLB. All three set/ reset functions for any single ip-op are controlled by the same conguration data bit. The set/reset state can be independently specied for each ip-op. This input can also be independently disabled for either ip-op. The set/reset state is specied by using the INIT attribute, or by placing the appropriate set or reset ip-op library symbol. SR is active High. It is not invertible within the CLB.

Two fast feed-through paths are available, as shown in Figure 2. A two-to-one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs. This bypass is sometimes used by the automated router to repower internal signals.

Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4 in Figure 2) into the four internal control signals (H1, DIN/ H2, SR/H0, and EC). Any of these inputs can drive any of the four internal control signals. When the logic function is enabled, the four inputs are: EC Enable Clock SR/H0 Asynchronous Set/Reset or H function generator Input 0 DIN/H2 Direct In or H function generator Input 2 H1 H function generator Input 1.

Global Set/Reset
A separate Global Set/Reset line (not shown in Figure 2) sets or clears each storage element during power-up, reconguration, or when a dedicated Reset net is driven active. This global net (GSR) does not compete with other routing resources; it uses a dedicated distribution network. Each ip-op is congured as either globally set or reset in the same way that the local set/reset (SR) is specied. Therefore, if a ip-op is set by SR, it is also set by GSR. Similarly, a reset ip-op is reset by both SR and GSR.
STARTUP PAD IBUF GSR GTS Q2 Q3 Q1Q4 CLK DONEIN
X5260

When the memory function is enabled, the four inputs are: EC Enable Clock WE Write Enable D0 Data Input to F and/or G function generator D1 Data input to G function generator (16x1 and 16x2 modes) or 5th Address bit (32x1 mode).

Using FPGA Flip-Flops and Latches

The abundance of ip-ops in the XC4000 Series invites pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the results through pipeline ip-ops. This method should be seriously considered wherever throughput is more important than latency. To include a CLB ip-op, place the appropriate library symbol. For example, FDCE is a D-type ip-op with clock enable and asynchronous clear. The corresponding latch symbol (for the XC4000X only) is called LDCE. In XC4000 Series devices, registers or shift registers generators from performing task. This ability increases devices. the ip ops can be used as without blocking the function a different, perhaps unrelated the functional capacity of the

Figure 3: Schematic Symbols for Global Set/Reset GSR can be driven from any user-programmable pin as a global reset input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GSR pin of the STARTUP symbol. (See Figure 3.) A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global Set/Reset signal. Alternatively, GSR can be driven from any internal node.

The CLB setup time is specied between the function generator inputs and the clock input K. Therefore, the specied CLB ip-op setup time includes the delay through the function generator.

Using Function Generators as RAM

Optional modes for each CLB make the memory look-up tables in the F and G function generators usable as an array of Read/Write memory cells. Available modes are level-sensitive (similar to the XC4000/A/H families), edgetriggered, and dual-port edge-triggered. Depending on the

Data Inputs and Outputs

The source of a storage element data input is programmable. It is driven by any of the functions F, G, and H, or by the Direct In (DIN) block input. The ip-ops or latches drive the XQ and YQ CLB outputs.

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selected mode, a single CLB can be congured as either a 16x2, 32x1, or 16x1 bit array. Supported CLB memory congurations and timing modes for single- and dual-port modes are shown in Table 4. XC4000 Series devices are the rst programmable logic devices with edge-triggered (synchronous) and dual-port RAM accessible to the user. Edge-triggered RAM simplies system timing. Dual-port RAM doubles the effective throughput of FIFO applications. These features can be individually programmed in any XC4000 Series CLB. Advantages of On-Chip and Edge-Triggered RAM The on-chip RAM is extremely fast. The read access time is the same as the logic delay. The write access time is slightly slower. Both access times are much faster than any off-chip solution, because they avoid I/O delays. Edge-triggered RAM, also called synchronous RAM, is a feature never before available in a Field Programmable Gate Array. The simplicity of designing with edge-triggered RAM, and the markedly higher achievable performance, add up to a signicant improvement over existing devices with on-chip RAM. Three application notes are available from Xilinx that discuss edge-triggered RAM: XC4000E Edge-Triggered and Dual-Port RAM Capability, Implementing FIFOs in XC4000E RAM, and Synchronous and Asynchronous FIFO Designs. All three application notes apply to both XC4000E and XC4000X RAM. Table 4: Supported RAM Modes 16 x 1 16 x 2 32 x 1 EdgeTriggered Timing LevelSensitive Timing

Level-Sensitive (Asynchronous): an external WE signal acts as the write strobe.

The selected timing mode applies to both function generators within a CLB when both are congured as RAM. The number of read ports is also programmable: Single Port: each function generator has a common read and write port Dual Port: both function generators are congured together as a single 16x1 dual-port RAM with one write port and two read ports. Simultaneous read and write operations to the same or different addresses are supported.

RAM conguration options are selected by placing the appropriate library symbol. Choosing a RAM Conguration Mode The appropriate choice of RAM mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design process. Recommended usage is shown in Table 5. The difference between level-sensitive, edge-triggered, and dual-port RAM is only in the write operation. Read operation and timing is identical for all modes of operation. Table 5: RAM Mode Selection LevelSensitive Use for New Designs? Size (16x1, Registered) Simultaneous Read/Write Relative Performance No 1/2 CLB No X EdgeTriggered Yes 1/2 CLB No 2X Dual-Port EdgeTriggered Yes 1 CLB Yes 2X (4X effective)

Single-Port Dual-Port

RAM Conguration Options The function generators in any CLB can be congured as RAM arrays in the following sizes: Two 16x1 RAMs: two data inputs and two data outputs with identical or, if preferred, different addressing for each RAM One 32x1 RAM: one data input and one data output.

RAM Inputs and Outputs The F1-F4 and G1-G4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. The functionality of the CLB control signals changes when the function generators are congured as RAM. The DIN/ H2, H1, and SR/H0 lines become the two data inputs (D0, D1) and the Write Enable (WE) input for the 16x2 memory. When the 32x1 conguration is selected, D1 acts as the fth address bit and D0 is the data input. The contents of the memory cell(s) being addressed are available at the F and G function-generator outputs. They can exit the CLB through its X and Y outputs, or can be captured in the CLB ip-op(s).

One F or G function generator can be congured as a 16x1 RAM while the other function generators are used to implement any function of up to 5 inputs. Additionally, the XC4000 Series RAM may have either of two timing modes: Edge-Triggered (Synchronous): data written by the designated edge of the CLB clock. WE acts as a true clock enable.

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Conguring the CLB function generators as Read/Write memory does not affect the functionality of the other portions of the CLB, with the exception of the redenition of the control signals. In 16x2 and 16x1 modes, the H function generator can be used to implement Boolean functions of F, G, and D1, and the D ip-ops can latch the F, G, H, or D0 signals. Single-Port Edge-Triggered Mode Edge-triggered (synchronous) RAM simplies timing requirements. XC4000 Series edge-triggered RAM timing operates like writing to a data register. Data and address are presented. The register is enabled for writing by a logic High on the write enable input, WE. Then a rising or falling clock edge loads the data into the register, as shown in Figure 4.
TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

edge of WCLK latches the address, input data, and WE signals. An internal write pulse is generated that performs the write. See Figure 5 and Figure 6 for block diagrams of a CLB congured as 16x2 and 32x1 edge-triggered, singleport RAM. The relationships between CLB pins and RAM inputs and outputs for single-port, edge-triggered mode are shown in Table 6. The Write Clock input (WCLK) can be congured as active on either the rising edge (default) or the falling edge. It uses the same CLB pin (K) used to clock the CLB ip-ops, but it can be independently inverted. Consequently, the RAM output can optionally be registered within the same CLB either by the same clock edge as the RAM, or by the opposite edge of this clock. The sense of WCLK applies to both function generators in the CLB when both are congured as RAM. The WE pin is active-High and is not invertible within the CLB. Note: The pulse following the active edge of WCLK (TWPS in Figure 4) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are congured as edge-triggered RAM. Table 6: Single-Port Edge-Triggered RAM Signals

TILO

RAM Signal D A[3:0] A[4] WE WCLK SPO (Data Out)

TWOS OLD

DATA OUT

NEW
X6461

Figure 4:

Edge-Triggered RAM Write Timing

Complex timing relationships between address, data, and write enable signals are not required, and the external write enable pulse becomes a simple clock enable. The active

CLB Pin D0 or D1 (16x2, 16x1), D0 (32x1) F1-F4 or G1-G4 D1 (32x1) WE K F or G

Function Data In Address Address Write Enable Clock Single Port Out (Data Out)

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C1 C4

DIN

WRITE DECODER G1 G4 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

WRITE PULSE

READ ADDRESS

DIN

WRITE DECODER F1 F4 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

K (CLOCK)

WRITE PULSE

READ ADDRESS X6752

Figure 5:

16x2 (or 16x1) Edge-Triggered Single-Port RAM

C1 C4

EC WE D1/A4 D0 EC

DIN

WRITE DECODER G1 G 4 F1 F 4 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

WRITE PULSE

READ ADDRESS H'

DIN

WRITE DECODER 4 4 1 of 16 LATCH ENABLE

16-LATCH ARRAY

MUX

K (CLOCK)

WRITE PULSE

READ ADDRESS X6754

Figure 6: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

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Dual-Port Edge-Triggered Mode In dual-port mode, both the F and G function generators are used to create a single 16x1 RAM array with one write port and two read ports. The resulting RAM array can be read and written simultaneously at two independent addresses. Simultaneous read and write operations at the same address are also supported. Dual-port mode always has edge-triggered write timing, as shown in Figure 4. Figure 7 shows a simple model of an XC4000 Series CLB congured as dual-port RAM. One address port, labeled A[3:0], supplies both the read and write address for the F function generator. This function generator behaves the same as a 16x1 single-port edge-triggered RAM array. The RAM output, Single Port Out (SPO), appears at the F function generator output. SPO, therefore, reects the data at address A[3:0]. The other address port, labeled DPRA[3:0] for Dual Port Read Address, supplies the read address for the G function generator. The write address for the G function generator, however, comes from the address A[3:0]. The output from this 16x1 RAM array, Dual Port Out (DPO), appears at the G function generator output. DPO, therefore, reects the data at address DPRA[3:0]. Therefore, by using A[3:0] for the write address and DPRA[3:0] for the read address, and reading only the DPO output, a FIFO that can read and write simultaneously is easily generated. Simultaneous access doubles the effective throughput of the FIFO. The relationships between CLB pins and RAM inputs and outputs for dual-port, edge-triggered mode are shown in Table 7. See Figure 8 on page 4-16 for a block diagram of a CLB congured in this mode.
RAM16X1D Primitive DPO (Dual Port Out) WE D DPRA[3:0] WE D AR[3:0] AW[3:0] D Q Registered DPO

Table 7: Dual-Port Edge-Triggered RAM Signals RAM Signal CLB Pin D D0 A[3:0] F1-F4 DPRA[3:0] WE WCLK SPO DPO G1-G4 WE K F G Function Data In Read Address for F, Write Address for F and G Read Address for G Write Enable Clock Single Port Out (addressed by A[3:0]) Dual Port Out (addressed by DPRA[3:0])

Note: The pulse following the active edge of WCLK (TWPS in Figure 4) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even damage to the larger devices if many CLBs are congured as edge-triggered RAM. Single-Port Level-Sensitive Timing Mode Note: Edge-triggered mode is recommended for all new designs. Level-sensitive mode, also called asynchronous mode, is still supported for XC4000 Series backward-compatibility with the XC4000 family. Level-sensitive RAM timing is simple in concept but can be complicated in execution. Data and address signals are presented, then a positive pulse on the write enable pin (WE) performs a write into the RAM at the designated address. As indicated by the level-sensitive label, this RAM acts like a latch. During the WE High pulse, changing the data lines results in new data written to the old address. Changing the address lines while WE is High results in spurious data written to the new addressand possibly at other addresses as well, as the address lines inevitably do not all change simultaneously. The user must generate a carefully timed WE signal. The delay on the WE signal and the address lines must be carefully veried to ensure that WE does not become active until after the address lines have settled, and that WE goes inactive before the address lines change again. The data must be stable before and after the falling edge of WE. In practical terms, WE is usually generated by a 2X clock. If a 2X clock is not available, the falling edge of the system clock can be used. However, there are inherent risks in this approach, since the WE pulse must be guaranteed inactive before the next rising edge of the system clock. Several older application notes are available from Xilinx that discuss the design of level-sensitive RAMs. These application notes include XAPP031, Using the XC4000 RAM Capability, and XAPP042, High-Speed RAM Design in XC4000. However, the edge-triggered RAM available in the XC4000 Series is superior to level-sensitive RAM for almost every application.

G Function Generator

SPO (Single Port Out) WE D A[3:0] AR[3:0] AW[3:0] D Q Registered SPO

F Function Generator

WCLK
X6755

Figure 7: XC4000 Series Dual-Port RAM, Simple Model

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C1 C4

DIN

WRITE DECODER 4 1 of 16 LATCH ENABLE 4

16-LATCH ARRAY

MUX

G1 G4

WRITE PULSE

READ ADDRESS

DIN

WRITE DECODER

16-LATCH ARRAY

MUX

F1 F4

4 1 of 16 LATCH ENABLE WRITE PULSE READ ADDRESS

K (CLOCK)

X6748

Figure 8: 16x1 Edge-Triggered Dual-Port RAM Figure 9 shows the write timing for level-sensitive, singleport RAM. The relationships between CLB pins and RAM inputs and outputs for single-port level-sensitive mode are shown in Table 8. Figure 10 and Figure 11 show block diagrams of a CLB congured as 16x2 and 32x1 level-sensitive, single-port RAM. Initializing RAM at Conguration Both RAM and ROM implementations of the XC4000 Series devices are initialized during conguration. The initial contents are dened via an INIT attribute or property attached to the RAM or ROM symbol, as described in the schematic library guide. If not dened, all RAM contents are initialized to all zeros, by default. RAM initialization occurs only during conguration. The RAM content is not affected by Global Set/Reset. Table 8: Single-Port Level-Sensitive RAM Signals RAM Signal D A[3:0] WE O CLB Pin D0 or D1 F1-F4 or G1-G4 WE F or G Function Data In Address Write Enable Data Out

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T WC ADDRESS

TAS WRITE ENABLE

T WP

T AH

T DS DATA IN REQUIRED

T DH

X6462

Figure 9: Level-Sensitive RAM Write Timing

C1 C4

Enable

DIN

G1 G 4

WRITE DECODER 1 of 16 4

16-LATCH ARRAY

MUX

READ ADDRESS

Enable

DIN

F1 F 4

WRITE DECODER 1 of 16 4

16-LATCH ARRAY

MUX

X6746

READ ADDRESS

Figure 10: 16x2 (or 16x1) Level-Sensitive Single-Port RAM

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C1 C4

D1/A4

Enable

DIN

G1 G4 F1 F4

WRITE DECODER 1 of 16

16-LATCH ARRAY

MUX

4 READ ADDRESS H'

Enable

DIN

WRITE DECODER 1 of 16

16-LATCH ARRAY

MUX

4 READ ADDRESS X6749

Figure 11: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

Fast Carry Logic

Each CLB F and G function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent of normal routing resources. Dedicated fast carry logic greatly increases the efciency and performance of adders, subtractors, accumulators, comparators and counters. It also opens the door to many new applications involving arithmetic operation, where the previous generations of FPGAs were not fast enough or too inefcient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in digital signal processing are two typical applications. The two 4-input function generators can be congured as a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so fast and efcient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal benet at the 32-bit level. This fast carry logic is one of the more signicant features of the XC4000 Series, speeding up arithmetic and counting into the 70 MHz range.

The carry chain in XC4000E devices can run either up or down. At the top and bottom of the columns where there are no CLBs above or below, the carry is propagated to the right. (See Figure 12.) In order to improve speed in the high-capacity XC4000X devices, which can potentially have very long carry chains, the carry chain travels upward only, as shown in Figure 13. Additionally, standard interconnect can be used to route a carry signal in the downward direction. Figure 14 on page 4-20 shows an XC4000E CLB with dedicated fast carry logic. The carry logic in the XC4000X is similar, except that COUT exits at the top only, and the signal CINDOWN does not exist. As shown in Figure 14, the carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function generators, where they are combined with the operands to form the sums. Figure 15 on page 4-21 shows the details of the carry logic for the XC4000E. This diagram shows the contents of the box labeled CARRY LOGIC in Figure 14. The XC4000X carry logic is very similar, but a multiplexer on the passthrough carry chain has been eliminated to reduce delay. Additionally, in the XC4000X the multiplexer on the G4 path has a memory-programmable 0 input, which permits G4 to

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directly connect to COUT. G4 thus becomes an additional high-speed initialization path for carry-in. The dedicated carry logic is discussed in detail in Xilinx document XAPP 013: Using the Dedicated Carry Logic in XC4000. This discussion also applies to XC4000E devices, and to XC4000X devices when the minor logic changes are taken into account. The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.

CLB

X6610

CLB

Figure 13: Available XC4000X Carry Propagation Paths (dotted lines use general interconnect)

CLB

CLB
X6687

Figure 12: Available XC4000E Carry Propagation Paths

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XC4000E and XC4000X Series Field Programmable Gate Arrays

CARRY LOGIC

C OUT

C IN DOWN

D IN

G Y

G CARRY

G3 G G2 DIN H G F G1 EC COUT0 D S/R Q YQ

DIN F CARRY H G F D S/R Q XQ

F3 F F2 F1 H X F

CIN UP

C OUT

S/R

EC X6699

Figure 14: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)

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C OUT M G1 1 0 I G4 0 1 G2 M

G3 C OUT0 M F2 M 1 F1 0 M M M F3 M 0 1 3 1 0 M 0 1 F4 TO FUNCTION GENERATORS

M M 1 0

X2000

C IN UP C IN DOWN

Figure 15: Detail of XC4000E Dedicated Carry Logic

Input/Output Blocks (IOBs)

User-congurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be congured for input, output, or bidirectional signals. Figure 16 shows a simplied block diagram of the XC4000E IOB. A more complete diagram which includes the boundary scan logic of the XC4000E IOB can be found in Figure 41 on page 4-44, in the Boundary Scan section. The XC4000X IOB contains some special features not included in the XC4000E IOB. These features are highlighted in a simplied block diagram found in Figure 17, and discussed throughout this section. When XC4000X special features are discussed, they are clearly identied in the text. Any feature not so identied is present in both XC4000E and XC4000X devices.

The choice is made by placing the appropriate library symbol. For example, IFD is the basic input ip-op (rising edge triggered), and ILD is the basic input latch (transparentHigh). Variations with inverted clocks are available, and some combinations of latches and ip-ops can be implemented in a single IOB, as described in the XACT Libraries Guide. The XC4000E inputs can be globally congured for either TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in the bitstream generation software. There is a slight input hysteresis of about 300mV. The XC4000E output levels are also congurable; the two global adjustments of input threshold and output level are independent. Inputs on the XC4000XL are TTL compatible and 3.3V CMOS compatible. Outputs on the XC4000XL are pulled to the 3.3V positive supply. The inputs of XC4000 Series 5-Volt devices can be driven by the outputs of any 3.3-Volt device, if the 5-Volt inputs are in TTL mode. Supported sources for XC4000 Series device inputs are shown in Table 9.

IOB Input Signals

Two paths, labeled I1 and I2 in Figure 16 and Figure 17, bring input signals into the array. Inputs also connect to an input register that can be programmed as either an edgetriggered ip-op or a level-sensitive latch.

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Slew Rate Control

Passive Pull-Up/ Pull-Down

T Flip-Flop D Out CE Output Clock I1 FlipFlop/ Latch Q D Delay Input Buffer Q Output Buffer Pad

Clock Enable Input Clock

X6704

Figure 16: Simplied Block Diagram of XC4000E IOB

Slew Rate Control T

Passive Pull-Up/ Pull-Down

Output MUX

0 1 Out Flip-Flop D CE Output Clock I1 Flip-Flop/ Latch Q D

Delay Delay

Q Output Buffer Input Buffer Pad

Clock Enable

Fast Capture Latch

Q D Latch G

Input Clock
X5984

Figure 17: Simplied Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)

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Table 9: Supported Sources for XC4000 Series Device Inputs XC4000E/EX XC4000XL Series Inputs Series Inputs 5 V, 5 V, 3.3 V TTL CMOS CMOS Unreli -able Data

Optional Delay Guarantees Zero Hold Time The data input to the register can optionally be delayed by several nanoseconds. With the delay enabled, the setup time of the input ip-op is increased so that normal clock routing does not result in a positive hold-time requirement. A positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. The input ip-op setup time is dened between the data measured at the device I/O pin and the clock input at the IOB (not at the clock pin). Any routing delay from the device clock pin to the clock input of the IOB must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. A short specied setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time requirement. When a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. Sufcient delay eliminates the possibility of a data hold-time requirement at the external pin. The maximum delay is therefore inserted as the default. The XC4000E IOB has a one-tap delay element: either the delay is inserted (default), or it is not. The delay guarantees a zero hold time with respect to clocks routed through any of the XC4000E global clock buffers. (See Global Nets and Buffers (XC4000E only) on page 4-36 for a description of the global clock buffers in the XC4000E.) For a shorter input register setup time, with non-zero hold, attach a NODELAY attribute or property to the ip-op. The XC4000X IOB has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The attributes or properties used to select the desired delay are shown in Table 11. The choices are no added attribute, MEDDELAY, and NODELAY. The default setting, with no added attribute, ensures no hold time with respect to any of the XC4000X clock buffers, including the Global Low-Skew buffers. MEDDELAY ensures no hold time with respect to the Global Early buffers. Inputs with NODELAY may have a positive hold time with respect to all clock buffers. For a description of each of these buffers, see Global Nets and Buffers (XC4000X only) on page 4-38. Table 11: XC4000X IOB Input Delay Element Value full delay (default, no attribute added) MEDDELAY NODELAY When to Use Zero Hold with respect to Global LowSkew Buffer, Global Early Buffer Zero Hold with respect to Global Early Buffer Short Setup, positive Hold time

Source Any device, Vcc = 3.3 V, CMOS outputs XC4000 Series, Vcc = 5 V, TTL outputs Any device, Vcc = 5 V, TTL outputs (Voh 3.7 V) Any device, Vcc = 5 V, CMOS outputs

XC4000XL 5-Volt Tolerant I/Os The I/Os on the XC4000XL are fully 5-volt tolerant even though the VCC is 3.3 volts. This allows 5 V signals to directly connect to the XC4000XL inputs without damage, as shown in Table 9. In addition, the 3.3 volt VCC can be applied before or after 5 volt signals are applied to the I/Os. This makes the XC4000XL immune to power supply sequencing problems. Registered Inputs The I1 and I2 signals that exit the block can each carry either the direct or registered input signal. The input and output storage elements in each IOB have a common clock enable input, which, through conguration, can be activated individually for the input or output ip-op, or both. This clock enable operates exactly like the EC pin on the XC4000 Series CLB. It cannot be inverted within the IOB. The storage element behavior is shown in Table 10. Table 10: Input Register Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop Latch Both
Legend: X __/ SR 0* 1*

Clock X __/ 0 1 0 X

Clock Enable X 1* X 1* 1* 0

D X D X X D X

Q SR D Q Q D Q

Dont care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value)

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Additional Input Latch for Fast Capture (XC4000X only) The XC4000X IOB has an additional optional latch on the input. This latch, as shown in Figure 17, is clocked by the output clock the clock used for the output ip-op rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the very fast capture of input data, which is then synchronized to the internal clock by the IOB ip-op or latch. To use this Fast Capture technique, drive the output clock pin (the Fast Capture latching signal) from the output of one of the Global Early buffers supplied in the XC4000X. The second storage element should be clocked by a Global Low-Skew buffer, to synchronize the incoming data to the internal logic. (See Figure 18.) These special buffers are described in Global Nets and Buffers (XC4000X only) on page 4-38. The Fast Capture latch (FCL) is designed primarily for use with a Global Early buffer. For Fast Capture, a single clock signal is routed through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) The Fast Capture latch is clocked by the Global Early buffer, and the standard IOB ip-op or latch is clocked by the Global Low-Skew buffer. This mode is the safest way to use the Fast Capture latch, because the clock buffers on both storage elements are driven by the same pad. There is no external skew between clock pads to create potential problems. To place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a transparent-Low Fast Capture latch followed by an active-High input ip-op. ILFLX is a transparent-Low Fast Capture latch followed by a transparent-High input latch. Any of the clock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB. If a single BUFG output is used to drive both clock inputs, the software automatically runs the clock through both a Global Low-Skew buffer and a Global Early buffer, and clocks the Fast Capture latch appropriately. Figure 17 on page 4-22 also shows a two-tap delay on the input. By default, if the Fast Capture latch is used, the Xilinx software assumes a Global Early buffer is driving the clock, and selects MEDDELAY to ensure a zero hold time. Select

the desired delay based on the discussion in the previous subsection.

IOB Output Signals

Output signals can be optionally inverted within the IOB, and can pass directly to the pad or be stored in an edgetriggered ip-op. The functionality of this ip-op is shown in Table 12. An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under conguration control, the output (OUT) and output 3-state (T) signals can be inverted. The polarity of these signals is independently congured for each IOB. The 4-mA maximum output current specication of many FPGAs often forces the user to add external buffers, which are especially cumbersome on bidirectional I/O lines. The XC4000E and XC4000EX/XL devices solve many of these problems by providing a guaranteed output sink current of 12 mA. Two adjacent outputs can be interconnected externally to sink up to 24 mA. The XC4000E and XC4000EX/XL FPGAs can thus directly drive buses on a printed circuit board. By default, the output pull-up structure is congured as a TTL-like totem-pole. The High driver is an n-channel pullup transistor, pulling to a voltage one transistor threshold below Vcc. Alternatively, the outputs can be globally congured as CMOS drivers, with p-channel pull-up transistors pulling to Vcc. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programmable. In the XC4000XL, all outputs are pulled to the positive supply rail. Table 12: Output Flip-Flop Functionality (active rising edge is shown) Mode Power-Up or GSR Flip-Flop Clock X X __/ X 0 Clock Enable X 0 1* X X T 0* 0* 0* 1 0* D X X D X X Q SR Q D Z Q

ILFFX
IPAD D Q to internal logic

GF BUFGE IPAD BUFGLS

X9013

CE C

Legend: X __/ SR 0* 1* Z

Dont care Rising edge Set or Reset value. Reset is default. Input is Low or unconnected (default value) Input is High or unconnected (default value) 3-state

Figure 18: Examples Using XC4000X FCL

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Any XC4000 Series 5-Volt device with its outputs congured in TTL mode can drive the inputs of any typical 3.3Volt device. (For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.) Supported destinations for XC4000 Series device outputs are shown in Table 13. An output can be congured as open-drain (open-collector) by placing an OBUFT symbol in a schematic or HDL code, then tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. (See Figure 19.) Table 13: Supported Destinations for XC4000 Series Outputs XC4000 Series Outputs Destination 3.3 V, 5 V, 5 V, CMOS TTL CMOS Any typical device, Vcc = 3.3 V, some1 CMOS-threshold inputs Any device, Vcc = 5 V, TTL-threshold inputs Any device, Vcc = 5 V, Unreliable CMOS-threshold inputs Data
1. Only if destination device has 5-V tolerant inputs

pin pair. For XC4000X devices, additional internal Power/ Ground pin pairs are connected to special Power and Ground planes within the packages, to reduce ground bounce. Therefore, the maximum total capacitive load is 300 pF between each external Power/Ground pin pair. Maximum loading may vary for the low-voltage devices. For slew-rate limited outputs this total is two times larger for each device type: 400 pF for XC4000E devices and 600 pF for XC4000X devices. This maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. This restriction is common to all high-speed digital ICs, and is not particular to Xilinx or the XC4000 Series. XC4000 Series devices have a feature called Soft Startup, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of conguration. When the conguration process is nished and the device starts up, the rst activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is determined by the individual conguration option for each IOB. Global Three-State A separate Global 3-State line (not shown in Figure 16 or Figure 17) forces all FPGA outputs to the high-impedance state, unless boundary scan is enabled and is executing an EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network. GTS can be driven from any user-programmable pin as a global 3-state input. To use this global net, place an input pad and input buffer in the schematic or HDL code, driving the GTS pin of the STARTUP symbol. A specic pin location can be assigned to this input using a LOC attribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after the input buffer to invert the sense of the Global 3-State signal. Using GTS is similar to GSR. See Figure 3 on page 4-11 for details. Alternatively, GTS can be driven from any internal node.

OPAD OBUFT
X6702

Figure 19: Open-Drain Output Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or property to the output buffer or ip-op. For XC4000E devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pF for all package pins between each Power/Ground

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Output Multiplexer/2-Input Function Generator (XC4000X only) As shown in Figure 17 on page 4-22, the output path in the XC4000X IOB contains an additional multiplexer not available in the XC4000E IOB. The multiplexer can also be congured as a 2-input function generator, implementing a pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2 inverted inputs. The logic used to implement these functions is shown in the upper gray area of Figure 17. When congured as a multiplexer, this feature allows two output signals to time-share the same output pad; effectively doubling the number of device outputs without requiring a larger, more expensive package. When the MUX is congured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global Early buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe Driven by a BUFGE buffer, as shown in Figure 20. The critical-path pin-to-pin delay of this circuit is less than 6 nanoseconds. As shown in Figure 17, the IOB input pins Out, Output Clock, and Clock Enable have different delays and different exibilities regarding polarity. Additionally, Output Clock sources are more limited than the other inputs. Therefore, the Xilinx software does not move logic into the IOB function generators unless explicitly directed to do so. The user can specify that the IOB function generator be used, by placing special library symbols beginning with the letter O. For example, a 2-input AND-gate in the IOB function generator is called OAND2. Use the symbol input pin labelled F for the signal on the critical path. This signal is placed on the OK pin the IOB input with the shortest delay to the function generator. Two examples are shown in Figure 21.
IPAD BUFGE F from internal logic OAND2 OPAD FAST
X9019

Other IOB Options

There are a number of other programmable options in the XC4000 Series IOB. Pull-up and Pull-down Resistors Programmable pull-up and pull-down resistors are useful for tying unused pins to Vcc or Ground to minimize power consumption and reduce noise sensitivity. The congurable pull-up resistor is a p-channel transistor that pulls to Vcc. The congurable pull-down resistor is an n-channel transistor that pulls to Ground. The value of these resistors is 50 k 100 k. This high value makes them unsuitable as wired-AND pull-up resistors. The pull-up resistors for most user-programmable IOBs are active during the conguration process. See Table 23 on page 4-59 for a list of pins with pull-ups active before and during conguration. After conguration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default, unused pads are congured with the internal pull-up resistor active. Alternatively, they can be individually congured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULLDOWN library component to the net attached to the pad. Independent Clocks Separate clock signals are provided for the input and output ip-ops. The clock can be independently inverted for each ip-op within the IOB, generating either falling-edge or rising-edge triggered ip-ops. The clock inputs for each IOB are independent, except that in the XC4000X, the Fast Capture latch shares an IOB input with the output clock pin. Early Clock for IOBs (XC4000X only) Special early clocks are available for IOBs. These clocks are sourced by the same sources as the Global Low-Skew buffers, but are separately buffered. They have fewer loads and therefore less delay. The early clock can drive either the IOB output clock or the IOB input clock, or both. The early clock allows fast capture of input data, and fast clockto-output on output data. The Global Early buffers that drive these clocks are described in Global Nets and Buffers (XC4000X only) on page 4-38. Global Set/Reset As with the CLB registers, the Global Set/Reset signal (GSR) can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two ip-ops can be individually congured to set

Figure 20: Fast Pin-to-Pin Path in XC4000X

F OAND2

D0 D1
X6598

OMUX2 O

S0
X6599

Figure 21: AND & MUX Symbols in XC4000X IOB

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or clear on reset and after conguration. Other than the global GSR net, no user-controlled set/reset signal is available to the I/O ip-ops. The choice of set or clear applies to both the initial state of the ip-op and the response to the Global Set/Reset pulse. See Global Set/Reset on page 411 for a description of how to use GSR. JTAG Support Embedded logic attached to the IOBs contains test structures compatible with IEEE Standard 1149.1 for boundary scan testing, permitting easy chip and board-level testing. More information is provided in Boundary Scan on page 4-43.

Standard 3-State Buffer All three pins are used. Place the library element BUFT. Connect the input to the I pin and the output to the O pin. The T pin is an active-High 3-state (i.e. an active-Low enable). Tie the T pin to Ground to implement a standard buffer. Wired-AND with Input on the I Pin The buffer can be used as a Wired-AND. Use the WAND1 library symbol, which is essentially an open-drain buffer. WAND4, WAND8, and WAND16 are also available. See the XACT Libraries Guide for further information. The T pin is internally tied to the I pin. Connect the input to the I pin and the output to the O pin. Connect the outputs of all the WAND1s together and attach a PULLUP symbol. Wired OR-AND The buffer can be congured as a Wired OR-AND. A High level on either input turns off the output. Use the WOR2AND library symbol, which is essentially an opendrain 2-input OR gate. The two input pins are functionally equivalent. Attach the two inputs to the I0 and I1 pins and tie the output to the O pin. Tie the outputs of all the WOR2ANDs together and attach a PULLUP symbol.

Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the array. (See Figure 28 on page 4-31.) These 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. Programmable pull-up resistors attached to these longlines help to implement a wide wired-AND function. The buffer enable is an active-High 3-state (i.e. an activeLow enable), as shown in Table 14. Another 3-state buffer with similar access is located near each I/O block along the right and left edges of the array. (See Figure 34 on page 4-35.) The horizontal longlines driven by the 3-state buffers have a weak keeper at each end. This circuit prevents undened oating levels. However, it is overridden by any driver, even a pull-up resistor. Special longlines running along the perimeter of the array can be used to wire-AND signals coming from nearby IOBs or from internal longlines. These longlines form the wide edge decoders discussed in Wide Edge Decoders on page 4-28.

Three-State Buffer Examples

Figure 22 shows how to use the 3-state buffers to implement a wired-AND function. When all the buffer inputs are High, the pull-up resistor(s) provide the High output. Figure 23 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the buffer 3-state signal. Pay particular attention to the polarity of the T pin when using these buffers in a design. Active-High 3-state (T) is identical to an active-Low output enable, as shown in Table 14. Table 14: Three-State Buffer Functionality IN X IN T 1 0 OUT Z IN

Three-State Buffer Modes

The 3-state buffers can be congured in three modes: Standard 3-state buffer Wired-AND with input on the I pin Wired OR-AND

Z=D

q (D

+D ) q (D +D )
D E F

P U L L

U P

D
WAND1

D C D
WAND1
D

D E D
F

WOR2AND

WOR2AND
X6465

Figure 22: Open-Drain Buffers Implement a Wired-AND Function

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~100 k

Z = DA A + DB B + DC C + DN N

DA BUFT A "Weak Keeper"

DB BUFT B

DC BUFT C

DN BUFT N
X6466

Figure 23: 3-State Buffers Implement a Multiplexer

Wide Edge Decoders

Dedicated decoder circuitry boosts the performance of wide decoding functions. When the address or data eld is wider than the function generator inputs, FPGAs need multi-level decoding and are thus slower than PALs. XC4000 Series CLBs have nine inputs. Any decoder of up to nine inputs is, therefore, compact and fast. However, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. An XC4000 Series FPGA has four programmable decoders located on each edge of the device. The inputs to each decoder are any of the IOB I1 signals on that edge plus one local interconnect per CLB row or column. Each row or column of CLBs provides up to three variables or their compliments., as shown in Figure 24. Each decoder generates a High output (resistor pull-up) when the AND condition of the selected inputs, or their complements, is true. This is analogous to a product term in typical PAL devices. Each of these wired-AND gates is capable of accepting up to 42 inputs on the XC4005E and 72 on the XC4013E. There are up to 96 inputs for each decoder on the XC4028X and 132 on the XC4052X. The decoders may also be split in two when a larger number of narrower decoders are required, for a maximum of 32 decoders per device. The decoder outputs can drive CLB inputs, so they can be combined with other logic to form a PAL-like AND/OR structure. The decoder outputs can also be routed directly to the chip outputs. For fastest speed, the output should be on the same chip edge as the decoder. Very large PALs can be emulated by ORing the decoder outputs in a CLB. This decoding feature covers what has long been considered a weakness of older FPGAs. Users often resorted to external PALs for simple but fast decoding functions. Now, the dedicated decoders in the XC4000 Series device can implement these functions fast and efciently. To use the wide edge decoders, place one or more of the WAND library symbols (WAND1, WAND4, WAND8, WAND16). Attach a DECODE attribute or property to each WAND symbol. Tie the outputs together and attach a PULLUP symbol. Location attributes or properties such as L (left edge) or TR (right half of top edge) should also be used to ensure the correct placement of the decoder inputs.
INTERCONNECT

IOB .I1 A C

IOB .I1 B

C) .....

(A B C) ..... (A B C) ..... (A B C) .....

X2627

Figure 24: XC4000 Series Edge Decoding Example

OSC4
F8M F500K F16K F490 F15
X6703

Figure 25: XC4000 Series Oscillator Symbol

On-Chip Oscillator
XC4000 Series devices include an internal oscillator. This oscillator is used to clock the power-on time-out, for conguration memory clearing, and as the source of CCLK in Master conguration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and temperature. The output frequency falls between 4 and 10 MHz.

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The oscillator output is optionally available after conguration. Any two of four resynchronized taps of a built-in divider are also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as -50% or +25%. These signals can be accessed by placing the OSC4 library element in a schematic or in HDL code (see Figure 25). The oscillator is automatically disabled after conguration if the OSC4 symbol is not used in the design.

Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.

Five interconnect types are distinguished by the relative length of their segments: single-length lines, double-length lines, quad and octal lines (XC4000X only), and longlines. In the XC4000X, direct connects allow fast data ow between adjacent CLBs, and between IOBs and CLBs. Extra routing is included in the IOB pad ring. The XC4000X also includes a ring of octal interconnect lines near the IOBs to improve pin-swapping and routing to locked pins. XC4000E/X devices include two types of global buffers. These global buffers have different properties, and are intended for different purposes. They are discussed in detail later in this section.

Programmable Interconnect
All internal connections are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. A structured, hierarchical matrix of routing resources is provided to achieve efcient automated routing. The XC4000E and XC4000X share a basic interconnect structure. XC4000X devices, however, have additional routing not available in the XC4000E. The extra routing resources allow high utilization in high-capacity devices. All XC4000X-specic routing resources are clearly identied throughout this section. Any resources not identied as XC4000X-specic are present in all XC4000 Series devices. This section describes the varied routing resources available in XC4000 Series devices. The implementation software automatically assigns the appropriate resources based on the density and timing requirements of the design.

CLB Routing Connections

A high-level diagram of the routing resources associated with one CLB is shown in Figure 26. The shaded arrows represent routing present only in XC4000X devices. Table 15 shows how much routing of each type is available in XC4000E and XC4000X CLB arrays. Clearly, very large designs, or designs with a great deal of interconnect, will route more easily in the XC4000X. Smaller XC4000E designs, typically requiring signicantly less interconnect, do not require the additional routing. Figure 28 on page 4-31 is a detailed diagram of both the XC4000E and the XC4000X CLB, with associated routing. The shaded square is the programmable switch matrix, present in both the XC4000E and the XC4000X. The Lshaped shaded area is present only in XC4000X devices. As shown in the gure, the XC4000X block is essentially an XC4000E block with additional routing. CLB inputs and outputs are distributed on all four sides, providing maximum routing exibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algorithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation.

Interconnect Overview
There are several types of interconnect. CLB routing is associated with each row and column of the CLB array. IOB routing forms a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the internal logic blocks.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Quad Single Double Long

CLB

Direct Connect

Long

Quad

Long

Global Clock

Long

Double Single

Global Clock

Carry Direct Chain Connect x5994

Figure 26: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)

Table 15: Routing per CLB in XC4000 Series Devices

es e bl gl

Singles Doubles Quads Longlines Direct Connects Globals Carry Logic Total

XC4000E XC4000X Vertical Horizontal Vertical Horizontal 8 8 8 8 4 4 4 4 0 0 12 12 6 6 10 6 0 0 2 2 4 2 24 0 0 18 8 1 45 0 0 32

Double

Singles Six Pass Transistors Per Switch Matrix Interconnect Point

Double

X6600

Figure 27: Programmable Switch Matrix (PSM)

Programmable Switch Matrices

The horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each switch matrix consists of programmable pass transistors used to establish connections between the lines (see Figure 27). For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix.

Single-Length Lines
Single-length lines provide the greatest interconnect exibility and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associated with each CLB. These lines connect the switching matrices that are located in every row and a column of CLBs. Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 29. Routing connectivity is shown in Figure 28. Single-length lines incur a delay whenever they go through a switching matrix. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one.

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QUAD

DOUBLE

SINGLE

DOUBLE LONG

F4 C4 G4

YQ Y

DIRECT

G1 C1 F1

CLB
K X XQ

G3 C3 F3

FEEDBACK

F2 C2 G2

LONG

Q U AD

LO N G

G LO BA L

LO D N OU G BL E

SI N G LE

LO D O N U G BL E

G D IR LO EC BA T L

FE ED BA C K

Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix

Figure 28: Detail of Programmable Interconnect Associated with XC4000 Series CLB

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XC4000E and XC4000X Series Field Programmable Gate Arrays

CLB

Doubles PSM PSM Singles Doubles

CLB

PSM

CLB

CLB
X6601

CLB

Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs)

X9014

Figure 30: Quad Lines (XC4000X only) and up to two independent outputs. Only one of the independent inputs can be buffered. The place and route software automatically uses the timing requirements of the design to determine whether or not a quad line signal should be buffered. A heavily loaded signal is typically buffered, while a lightly loaded one is not. One scenario is to alternate buffers and pass transistors. This allows both vertical and horizontal quad lines to be buffered at alternating buffered switch matrices. Due to the buffered switch matrices, quad lines are very fast. They provide the fastest available method of routing heavily loaded signals for long distances across the device.

Double-Length Lines
The double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two CLBs before entering a switch matrix. Doublelength lines are grouped in pairs with the switch matrices staggered, so that each line goes through a switch matrix at every other row or column of CLBs (see Figure 29). There are four vertical and four horizontal double-length lines associated with each CLB. These lines provide faster signal routing over intermediate distances, while retaining routing exibility. Double-length lines are connected by way of the programmable switch matrices. Routing connectivity is shown in Figure 28.

Quad Lines (XC4000X only)

XC4000X devices also include twelve vertical and twelve horizontal quad lines per CLB row and column. Quad lines are four times as long as the single-length lines. They are interconnected via buffered switch matrices (shown as diamonds in Figure 28 on page 4-31). Quad lines run past four CLBs before entering a buffered switch matrix. They are grouped in fours, with the buffered switch matrices staggered, so that each line goes through a buffered switch matrix at every fourth CLB location in that row or column. (See Figure 30.) The buffered switch matrixes have four pins, one on each edge. All of the pins are bidirectional. Any pin can drive any or all of the other pins. Each buffered switch matrix contains one buffer and six pass transistors. It resembles the programmable switch matrix shown in Figure 27, with the addition of a programmable buffer. There can be up to two independent inputs

Longlines
Longlines form a grid of metal interconnect segments that run the entire length or width of the array. Longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. In XC4000X devices, quad lines are preferred for critical nets, because the buffered switch matrices make them faster for high fanout nets. Two horizontal longlines per CLB can be driven by 3-state or open-drain drivers (TBUFs). They can therefore implement unidirectional or bidirectional buses, wide multiplexers, or wired-AND functions. (See Three-State Buffers on page 4-27 for more details.) Each horizontal longline driven by TBUFs has either two (XC4000E) or eight (XC4000X) pull-up resistors. To activate these resistors, attach a PULLUP symbol to the longline net. The software automatically activates the appropriate number of pull-ups. There is also a weak keeper at each end of these two horizontal longlines. This circuit pre-

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March 30, 1998 (Version 1.5)

vents undened oating levels. However, it is overridden by any driver, even a pull-up resistor. Each XC4000E longline has a programmable splitter switch at its center, as does each XC4000X longline driven by TBUFs. This switch can separate the line into two independent routing channels, each running half the width or height of the array. Each XC4000X longline not driven by TBUFs has a buffered programmable splitter switch at the 1/4, 1/2, and 3/4 points of the array. Due to the buffering, XC4000X longline performance does not deteriorate with the larger array sizes. If the longline is split, the resulting partial longlines are independent. Routing connectivity of the longlines is shown in Figure 28 on page 4-31.

I/O Routing
XC4000 Series devices have additional routing around the IOB ring. This routing is called a VersaRing. The VersaRing facilitates pin-swapping and redesign without affecting board layout. Included are eight double-length lines spanning two CLBs (four IOBs), and four longlines. Global lines and Wide Edge Decoder lines are provided. XC4000X devices also include eight octal lines. A high-level diagram of the VersaRing is shown in Figure 32. The shaded arrows represent routing present only in XC4000X devices. Figure 34 on page 4-35 is a detailed diagram of the XC4000E and XC4000X VersaRing. The area shown includes two IOBs. There are two IOBs per CLB row or column, therefore this diagram corresponds to the CLB routing diagram shown in Figure 28 on page 4-31. The shaded areas represent routing and routing connections present only in XC4000X devices.

Direct Interconnect (XC4000X only)

The XC4000X offers two direct, efcient and fast connections between adjacent CLBs. These nets facilitate a data ow from the left to the right side of the device, or from the top to the bottom, as shown in Figure 31. Signals routed on the direct interconnect exhibit minimum interconnect propagation delay and use no general routing resources. The direct interconnect is also present between CLBs and adjacent IOBs. Each IOB on the left and top device edges has a direct path to the nearest CLB. Each CLB on the right and bottom edges of the array has a direct path to the nearest two IOBs, since there are two IOBs for each row or column of CLBs. The place and route software uses direct interconnect whenever possible, to maximize routing resources and minimize interconnect delays.

Octal I/O Routing (XC4000X only)

Between the XC4000X CLB array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and xed pinout exibility. (See Figure 33 on page 4-34.) These routing tracks are called octals, because they can be broken every eight CLBs (sixteen IOBs) by a programmable buffer that also functions as a splitter switch. The buffers are staggered, so each line goes through a buffer at every eighth CLB location around the device edge. The octal lines bend around the corners of the device. The lines cross at the corners in such a way that the segment most recently buffered before the turn has the farthest distance to travel before the next buffer, as shown in Figure 33.

IOB

~ ~ ~ ~

IOB

CLB
IOB

CLB

CLB
IOB

IOB

CLB
IOB

CLB

Figure 31: XC4000X Direct Interconnect

March 30, 1998 (Version 1.5)

~ ~ ~ ~
IOB

~ ~ ~ ~ ~ ~ ~ ~
IOB IOB

~ ~ ~ ~
IOB IOB

CLB
IOB

IOB

IOB
X6603

4-33

XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB

WED Quad WED Single Double

INTERCONNECT
Long Direct Connect

IOB
WED

Long

Direct Connect

Edge Double Long Global Octal Decode Clock

X5995

Figure 32: High-Level Routing Diagram of XC4000 Series VersaRing (Left Edge) WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC4000X only)

IOB

Segment with nearest buffer connects to segment with furthest buffer

X9015

Figure 33: XC4000X Octal I/O Routing

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March 30, 1998 (Version 1.5)

QUAD

T O
DOUBLE

SINGLE

C L B A R R A Y

DOUBLE LONG

DECODER

IOB
I1 IK OK T I2 CE O

DIRECT

DECODER

IOB
T OK O CE I2 IK I1

DECODER

LONG
L BA LO G E E G OD ED EC D G N LO

Figure 34: Detail of Programmable Interconnect Associated with XC4000 Series IOB (Left Edge)

March 30, 1998 (Version 1.5)

E BL U O D

L TA C O

Common to XC4000E and XC4000X XC4000X only

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XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB inputs and outputs interface with the octal lines via the single-length interconnect lines. Single-length lines are also used for communication between the octals and double-length lines, quads, and longlines within the CLB array. Segmentation into buffered octals was found to be optimal for distributing signals over long distances around the device.

Two different types of clock buffers are available in the XC4000E: Primary Global Buffers (BUFGP) Secondary Global Buffers (BUFGS)

Global Nets and Buffers

Both the XC4000E and the XC4000X have dedicated global networks. These networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. The global buffers are described in detail in the following sections. The text descriptions and diagrams are summarized in Table 16. The table shows which CLB and IOB clock pins can be sourced by which global buffers. In both XC4000E and XC4000X devices, placement of a library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing requirements of the design. The detailed information in these sections is included only for reference.

Four Primary Global buffers offer the shortest delay and negligible skew. Four Secondary Global buffers have slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater exibility when used to drive non-clock CLB inputs. The Primary Global buffers must be driven by the semidedicated pads. The Secondary Global buffers can be sourced by either semi-dedicated pads or internal nets. Each CLB column has four dedicated vertical Global lines. Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 35. Each corner of the device has one Primary buffer and one Secondary buffer. IOBs along the left and right edges have four vertical global longlines. Top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. A global buffer should be specied for all timing-sensitive global signal distribution. To use a global buffer, place a BUFGP (primary buffer), BUFGS (secondary buffer), or BUFG (either primary or secondary buffer) element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=L attribute or property to a BUFGS symbol to direct that a buffer be placed in one of the two Secondary Global buffers on the left edge of the device, or a LOC=BL to indicate the Secondary Global buffer on the bottom edge of the device, on the left.

Global Nets and Buffers (XC4000E only)

Four vertical longlines in each CLB column are driven exclusively by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of two types of global buffers. The clock pins of every CLB and IOB can also be sourced from local interconnect.

Table 16: Clock Pin Access XC4000E BUFGP All CLBs in Quadrant All CLBs in Device IOBs on Adjacent Vertical Half Edge IOBs on Adjacent Vertical Full Edge IOBs on Adjacent Horizontal Half Edge (Direct) IOBs on Adjacent Horizontal Half Edge (through CLB globals) IOBs on Adjacent Horizontal Full Edge (through CLB globals)
L = Left, R = Right, T = Top, B = Bottom

BUFGS

BUFGLS

XC4000X L&R BUFGE

T&B BUFGE

Local Interconnect

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IOB

locals

BUFGS PGCK1 SGCK1

locals

BUFGP SGCK4 PGCK4

4 BUFGP 4 IOB locals X4 locals IOB Any BUFGS One BUFGP per Global Line locals BUFGS CLB CLB locals CLB CLB

4 BUFGS locals 4

IOB Any BUFGS One BUFGP per Global Line locals BUFGP locals X4 locals IOB

PGCK2 locals locals locals BUFGP locals SGCK2 BUFGS

SGCK3 PGCK3

IOB

X6604

Figure 35: XC4000E Global Net Distribution

BUFGLS

IOB

BUFGLS

GCK1

GCK8 BUFGE BUFGE

GCK7

GCK6

locals

BUFGLS

locals

BUFGE

BUFGLS

CLB

X4
BUFGLS 8

BUFGLS 8

X8 8

BUFGLS

X8 8 BUFGLS 8

locals
4 8 8
CLB CLOCKS (PER COLUMN)

locals

IOB

locals

IOB CLOCKS

CLB CLOCKS (PER COLUMN)

IOB CLOCKS

IOB

locals

locals
IOB IOB CLOCKS CLB CLOCKS (PER COLUMN) CLB CLOCKS (PER COLUMN) IOB CLOCKS

locals
IOB

8 8

locals
BUFGLS 8

locals
8 BUFGLS X8

locals
X4
BUFGLS 8

locals
8 BUFGLS X8
CLB CLB

locals

BUFGLS

locals

BUFGE BUFGE

BUFGE BUFGE GCK4

BUFGLS

GCK2

GCK3 BUFGLS BUFGLS

GCK5 X9018

IOB

Figure 36: XC4000X Global Net Distribution

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Global Nets and Buffers (XC4000X only)

Eight vertical longlines in each CLB column are driven by special global buffers. These longlines are in addition to the vertical longlines used for standard interconnect. The global lines are broken in the center of the array, to allow faster distribution and to minimize skew across the whole array. Each half-column global line has its own buffered multiplexer, as shown in Figure 36. The top and bottom global lines cannot be connected across the center of the device, as this connection might introduce unacceptable skew. The top and bottom halves of the global lines must be separately driven although they can be driven by the same global buffer. The eight global lines in each CLB column can be driven by either of two types of global buffers. They can also be driven by internal logic, because they can be accessed by single, double, and quad lines at the top, bottom, half, and quarter points. Consequently, the number of different clocks that can be used simultaneously in an XC4000X device is very large. There are four global lines feeding the IOBs at the left edge of the device. IOBs along the right edge have eight global lines. There is a single global line along the top and bottom edges with access to the IOBs. All IOB global lines are broken at the center. They cannot be connected across the center of the device, as this connection might introduce unacceptable skew. IOB global lines can be driven from two types of global buffers, or from local interconnect. Alternatively, top and bottom IOBs can be clocked from the global lines in the adjacent CLB column. Two different types of clock buffers are available in the XC4000X: Global Low-Skew Buffers (BUFGLS) Global Early Buffers (BUFGE)

Choosing an XC4000X Clock Buffer The clocking structure of the XC4000X provides a large variety of features. However, it can be simple to use, without understanding all the details. The software automatically handles clocks, along with all other routing, when the appropriate clock buffer is placed in the design. In fact, if a buffer symbol called BUFG is placed, rather than a specic type of buffer, the software even chooses the buffer most appropriate for the design. The detailed information in this section is provided for those users who want a ner level of control over their designs. If ne control is desired, use the following summary and Table 16 on page 4-36 to choose an appropriate clock buffer. The simplest thing to do is to use a Global Low-Skew buffer. If a faster clock path is needed, try a BUFG. The software will rst try to use a Global Low-Skew Buffer. If timing requirements are not met, a faster buffer will automatically be used. If a single quadrant of the chip is sufcient for the clocked logic, and the timing requires a faster clock than the Global Low-Skew buffer, use a Global Early buffer.

Global Low-Skew Buffers Each corner of the XC4000X device has two Global LowSkew buffers. Any of the eight Global Low-Skew buffers can drive any of the eight vertical Global lines in a column of CLBs. In addition, any of the buffers can drive any of the four vertical lines accessing the IOBs on the left edge of the device, and any of the eight vertical lines accessing the IOBs on the right edge of the device. (See Figure 37 on page 4-39.) IOBs at the top and bottom edges of the device are accessed through the vertical Global lines in the CLB array, as in the XC4000E. Any Global Low-Skew buffer can, therefore, access every IOB and CLB in the device. The Global Low-Skew buffers can be driven by either semidedicated pads or internal logic. To use a Global Low-Skew buffer, instantiate a BUFGLS element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGLS be placed in one of the two Global Low-Skew buffers on the top edge of the device, or a LOC=TR to indicate the Global Low-Skew buffer on the top edge of the device, on the right.

Global Low-Skew Buffers are the standard clock buffers. They should be used for most internal clocking, whenever a large portion of the device must be driven. Global Early Buffers are designed to provide a faster clock access, but CLB access is limited to one-fourth of the device. They also facilitate a faster I/O interface. Figure 36 is a conceptual diagram of the global net structure in the XC4000X. Global Early buffers and Global Low-Skew buffers share a single pad. Therefore, the same IPAD symbol can drive one buffer of each type, in parallel. This conguration is particularly useful when using the Fast Capture latches, as described in IOB Input Signals on page 4-21. Paired Global Early and Global Low-Skew buffers share a common input; they cannot be driven by two different signals.

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March 30, 1998 (Version 1.5)

8
IOB IOB

7 6
1
I O B

8
IOB IOB

7 6 CLB CLB
I O B

1
I O B

CLB

I O B

CLB

I O B

CLB

I O B

2 3

IOB

5 4
X6753

2 3

IOB

5 4
X6751

Figure 37: Any BUFGLS (GCK1 - GCK8) Can Drive Any or All Clock Inputs on the Device Global Early Buffers Each corner of the XC4000X device has two Global Early buffers. The primary purpose of the Global Early buffers is to provide an earlier clock access than the potentially heavily-loaded Global Low-Skew buffers. A clock source applied to both buffers will result in the Global Early clock edge occurring several nanoseconds earlier than the Global Low-Skew buffer clock edge, due to the lighter loading. Global Early buffers also facilitate the fast capture of device inputs, using the Fast Capture latches described in IOB Input Signals on page 4-21. For Fast Capture, take a single clock signal, and route it through both a Global Early buffer and a Global Low-Skew buffer. (The two buffers share an input pad.) Use the Global Early buffer to clock the Fast Capture latch, and the Global Low-Skew buffer to clock the normal input ip-op or latch, as shown in Figure 18 on page 4-24. The Global Early buffers can also be used to provide a fast Clock-to-Out on device output pins. However, an early clock in the output ip-op IOB must be taken into consideration when calculating the internal clock speed for the design. The Global Early buffers at the left and right edges of the chip have slightly different capabilities than the ones at the top and bottom. Refer to Figure 38, Figure 39, and Figure 36 on page 4-37 while reading the following explanation. Each Global Early buffer can access the eight vertical Global lines for all CLBs in the quadrant. Therefore, only onefourth of the CLB clock pins can be accessed. This restriction is in large part responsible for the faster speed of the buffers, relative to the Global Low-Skew buffers.

Figure 38: Left and Right BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant or Edge (GCK1 is shown. GCK2, GCK5 and GCK6 are similar.) The left-side Global Early buffers can each drive two of the four vertical lines accessing the IOBs on the entire left edge of the device. The right-side Global Early buffers can each drive two of the eight vertical lines accessing the IOBs on the entire right edge of the device. (See Figure 38.) Each left and right Global Early buffer can also drive half of the IOBs along either the top or bottom edge of the device, using a dedicated line that can only be accessed through the Global Early buffers. The top and bottom Global Early buffers can drive half of the IOBs along either the left or right edge of the device, as shown in Figure 39. They can only access the top and bottom IOBs via the CLB global lines.

8
IOB IOB

7 6

1
I O B

CLB

I O B

CLB

I O B

2 3

IOB

5 4
X6747

Figure 39: Top and Bottom BUFGEs Can Drive Any or All Clock Inputs in Same Quadrant (GCK8 is shown. GCK3, GCK4 and GCK7 are similar.)

March 30, 1998 (Version 1.5)

4-39

XC4000E and XC4000X Series Field Programmable Gate Arrays

The top and bottom Global Early buffers are about 1 ns slower clock to out than the left and right Global Early buffers. The Global Early buffers can be driven by either semi-dedicated pads or internal logic. They share pads with the Global Low-Skew buffers, so a single net can drive both global buffers, as described above. To use a Global Early buffer, place a BUFGE element in a schematic or in HDL code. If desired, attach a LOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute or property to direct that a BUFGE be placed in one of the two Global Early buffers on the top edge of the device, or a LOC=TR to indicate the Global Early buffer on the top edge of the device, on the right.
Vcc

GND Ground and Vcc Ring for I/O Drivers

Vcc

Logic Power Grid

GND

X5422

Power Distribution
Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers, as shown in Figure 40. An independent matrix of Vcc and Ground lines supplies the interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically, a 0.1 F capacitor connected between each Vcc pin and the boards Ground plane will provide adequate decoupling. Output buffers capable of driving/sinking the specied 12 mA loads under specied worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the same direction. It may also be benecial to locate heavily loaded output buffers near the Ground pads. The I/O Block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical.

Figure 40: XC4000 Series Power Distribution

Pin Descriptions
There are three types of pins in the XC4000 Series devices: Permanently dedicated pins User I/O pins that can have special functions Unrestricted user-programmable I/O pins.

Before and during conguration, all outputs not used for the conguration process are 3-stated with a 50 k - 100 k pull-up resistor. After conguration, if an IOB is unused it is congured as an input with a 50 k - 100 k pull-up resistor. XC4000 Series devices have no dedicated Reset input. Any user I/O can be congured to drive the Global Set/ Reset net, GSR. See Global Set/Reset on page 4-11 for more information on GSR. XC4000 Series devices have no Powerdown control input, as the XC3000 and XC2000 families do. The XC3000/ XC2000 Powerdown control also 3-stated all of the device I/O pins. For XC4000 Series devices, use the global 3-state net, GTS, instead. This net 3-states all outputs, but does not place the device in low-power mode. See IOB Output Signals on page 4-24 for more information on GTS. Device pins for XC4000 Series devices are described in Table 17. Pin functions during conguration for each of the seven conguration modes are summarized in Table 23 on page 4-59, in the Conguration Timing section.

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March 30, 1998 (Version 1.5)

Table 17: Pin Descriptions I/O I/O During After Pin Name Cong. Cong. Permanently Dedicated Pins VCC I I

Pin Description

Eight or more (depending on package) connections to the nominal +5 V supply voltage (+3.3 V for low-voltage devices). All must be connected, and each must be decoupled with a 0.01 - 0.1 F capacitor to Ground. Eight or more (depending on package type) connections to Ground. All must be conGND I I nected. During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheral mode. After configuration, CCLK has a weak pull-up resistor and can be selected as the CCLK I or O I Readback Clock. There is no CCLK High or Low time restriction on XC4000 Series devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 4-57 for an explanation of this exception. DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, it indicates the completion of the configuration process. As an input, a Low level on DONE DONE I/O O can be configured to delay the global logic initialization and the enabling of outputs. The optional pull-up resistor is selected as an option in the XACTstep program that creates the configuration bitstream. The resistor is included by default. PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGA finishes the current clear cycle and executes another complete clear cycle, before it PROGRAM I I goes into a WAIT state and releases INIT. The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulled up to Vcc. User I/O Pins That Can Have Special Functions During Peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the FPGA. The same status is also available on D7 in AsynRDY/BUSY O I/O chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, RDY/BUSY is a user-programmable I/O pin. RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High. During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 for XC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK is RCLK O I/O useful for clocked PROMs. It is rarely used during configuration. After configuration, RCLK is a user-programmable I/O pin. As Mode inputs, these pins are sampled after INIT goes High to determine the configuration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1 can be used as a 3-state output. These three pins have no associated input or output registers. I (M0), During configuration, these pins have weak pull-up resistors. For the most popular conM0, M1, M2 I O (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The three I (M2) mode inputs can be individually configured with or without weak pull-up or pull-down resistors. A pull-down resistor value of 4.7 k is recommended. These pins can only be used as inputs or outputs when called out by special schematic definitions. To use these pins, place the library components MD0, MD1, and MD2 instead of the usual pad symbols. Input or output buffers must still be used. If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. TDO O O This pin can be user output only when called out by special schematic definitions. To use this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 17: Pin Descriptions (Continued) I/O I/O During After Cong. Cong.

Pin Name

TDI, TCK, TMS

I/O or I (JTAG)

HDC

I/O

LDC

I/O

INIT

I/O

PGCK1 PGCK4 (XC4000E only)

Weak Pull-up

I or I/O

SGCK1 SGCK4 (XC4000E only)

Weak Pull-up

I or I/O

GCK1 GCK8 (XC4000X only)

Weak Pull-up

I or I/O

CS0, CS1, WS, RS

I/O

A0 - A17

I/O

Pin Description If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs respectively. They come directly from the pads, bypassing the IOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibited once configuration is completed, and these pins become user-programmable I/O. In this case, they must be called out by special schematic definitions. To use these pins, place the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used. High During Configuration (HDC) is driven High until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, HDC is a user-programmable I/O pin. Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin. Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to hold the FPGA in the internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After the I/O go active, INIT is a user-programmable I/O pin. Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O. The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected directly to the input of a BUFGP symbol is automatically placed on one of these pins. Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal skew. These internal global nets can also be driven from internal logic. If not used to drive a global net, any of these pins is a user-programmable I/O pin. The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins. Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Global Early buffer. Each pair of global buffers can also be driven from internal logic, but must share an input signal. If not used to drive a global buffer, any of these pins is a user-programmable I/O. Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol is automatically placed on one of these pins. These four inputs are used in Asynchronous Peripheral mode. The chip is selected when CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A Low on Read Strobe (RS) changes D7 into a status output High if Ready, Low if Busy and drives D0 - D6 High. In Express mode, CS1 is used as a serial-enable signal for daisy-chaining. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable I/O pins. During Master Parallel configuration, these 18 output pins address the configuration EPROM. After configuration, they are user-programmable I/O pins.

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March 30, 1998 (Version 1.5)

Table 17: Pin Descriptions (Continued) I/O I/O During After Cong. Cong.

Pin Description During Master Parallel configuration with an XC4000X master, these 4 output pins add O I/O 4 more bits to address the configuration EPROM. After configuration, they are user-programmable I/O pins. (See Master Parallel Configuration section for additional details.) During Master Parallel and Peripheral configuration, these eight input pins receive conD0 - D7 I I/O figuration data. After configuration, they are user-programmable I/O pins. During Slave Serial or Master Serial configuration, DIN is the serial configuration data DIN I I/O input receiving data on the rising edge of CCLK. During Parallel configuration, DIN is the D0 input. After configuration, DIN is a user-programmable I/O pin. During configuration in any mode but Express mode, DOUT is the serial configuration data output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at the DOUT O I/O DIN input. In Express mode, DOUT is the status output that can drive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices. After configuration, DOUT is a user-programmable I/O pin. Unrestricted User-Programmable I/O Pins These pins can be configured to be input and/or output after configuration is completed. Weak I/O I/O Before configuration is completed, these pins have an internal high-value pull-up resisPull-up tor (25 k - 100 k) that defines the logic level as High.

Pin Name A18 - A21 (XC4000X only)

Boundary Scan
The bed of nails has been the traditional method of testing electronic assemblies. This approach has become less appropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan Standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for I/O and internal logic. This structure is easily implemented with a four-pin interface on any boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two. The XC4000 Series implements IEEE 1149.1-compatible BYPASS, PRELOAD/SAMPLE and EXTEST boundary scan instructions. When the boundary scan conguration option is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pin becomes the dedicated boundary scan output. The details of how to enable this circuitry are covered later in this section. By exercising these input signals, the user can serially load commands and data into these devices to control the driving of their outputs and to examine their inputs. This method is an improvement over bed-of-nails testing. It avoids the need to over-drive device outputs, and it reduces the user interface to four pins. An optional fth pin,

a reset for the control logic, is described in the standard but is not implemented in Xilinx devices. The dedicated on-chip logic implementing the IEEE 1149.1 functions includes a 16-state machine, an instruction register and a number of data registers. The functional details can be found in the IEEE 1149.1 specication and are also discussed in the Xilinx application note XAPP 017: Boundary Scan in XC4000 Devices. Figure 41 on page 4-44 shows a simplied block diagram of the XC4000E Input/Output Block with boundary scan implemented. XC4000X boundary scan logic is identical. Figure 42 on page 4-45 is a diagram of the XC4000 Series boundary scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes. XC4000 Series devices can also be congured through the boundary scan logic. See Readback on page 4-56.

Data Registers
The primary data register is the boundary scan register. For each IOB pin in the FPGA, bonded or not, it includes three bits for In, Out and 3-State Control. Non-IOB pins have appropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundary scan register. Each EXTEST CAPTURE-DR state captures all In, Out, and 3-state pins. The data register also includes the following non-pin bits: TDO.T, and TDO.O, which are always bits 0 and 1 of the data register, respectively, and BSCANT.UPD, which is 4-43

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XC4000E and XC4000X Series Field Programmable Gate Arrays

always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals. The other standard data register is the single ip-op BYPASS register. It synchronizes data being passed through the FPGA to the next downstream boundary scan device. The FPGA provides two additional data registers that can be specied using the BSCAN macro. The FPGA provides

two user pins (BSCAN.SEL1 and BSCAN.SEL2) which are the decodes of two user instructions. For these instructions, two corresponding pins (BSCAN.TDO1 and BSCAN.TDO2) allow user scan data to be shifted out on TDO. The data register clock (BSCAN.DRCK) is available for control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLE is also provided (BSCAN.IDLE).

EXTEST TS INV TS/OE Boundary Scan OUTPUT INVERT OUTPUT M sd Ouput Data O M Ouput Clock OK rd M M S/R INVERT M OUT SEL D EC Q TS - capture TS - update M

SLEW RATE

PULL DOWN

PULL UP

3-State TS

VCC

PAD

Clock Enable

Boundary Scan

O - capture Q - capture O - update

I - capture Boundary Scan I - update sd D DELAY M FLIP-FLOP/LATCH Input Clock IK M INPUT S/R rd EC M INVERT QL Q M M M M Input Data 2 I2

Input Data 1 I1

GLOBAL S/R

X5792

Figure 41: Block Diagram of XC4000E IOB with Boundary Scan (some details not shown). XC4000X Boundary Scan Logic is Identical.

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DATA IN IOB.T 1 0 IOB IOB IOB IOB IOB D Q D sd Q 0 1

IOB

1 0

sd D Q D Q

IOB

IOB LE

IOB

IOB IOB.I 1 0 1 sd D Q D Q

IOB

LE 1 IOB.Q IOB.T 0

IOB

BYPASS REGISTER INSTRUCTION REGISTER

IOB

TDI

M TDO U X

0 1 0 D Q D sd Q 1

1 0 D Q D

sd Q

1 IOB.I 0

DATAOUT SHIFT/ CLOCK DATA CAPTURE REGISTER

UPDATE

EXTEST

X9016

Figure 42: XC4000 Series Boundary Scan Logic

Instruction Set
The XC4000 Series boundary scan instruction set also includes instructions to congure the device and read back the conguration data. The instruction set is coded as shown in Table 18.

Including Boundary Scan in a Schematic

If boundary scan is only to be used during conguration, no special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan pins TDI, TMS, TCK and TDO can be used for user functions after conguration. To indicate that boundary scan remain enabled after conguration, place the BSCAN library symbol and connect the TDI, TMS, TCK and TDO pad symbols to the appropriate pins, as shown in Figure 44. Even if the boundary scan symbol is used in a schematic, the input pins TMS, TCK, and TDI can still be used as inputs to be routed to internal logic. Care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. The simplest way to prevent this is to keep TMS High, and then apply whatever signal is desired to TDI and TCK.

Bit Sequence
The bit sequence within each IOB is: In, Out, 3-State. The input-only M0 and M2 mode pins contribute only the In bit to the boundary scan I/O data register, while the outputonly M1 pin contributes all three bits. The rst two bits in the I/O data register are TDO.T and TDO.O, which can be used for the capture of internal signals. The nal bit is BSCANT.UPD, which can be used to drive an internal net. These locations are primarily used by Xilinx for internal testing. From a cavity-up view of the chip (as shown in XDE or Epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in Figure 43. The device-specic pinout tables for the XC4000 Series include the boundary scan locations for each IOB pin. BSDL (Boundary Scan Description Language) les for XC4000 Series devices are available on the Xilinx FTP site. March 30, 1998 (Version 1.5)

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Table 18: Boundary Scan Instructions Instruction I2 I1 I0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 Test TDO Source Selected EXTEST DR SAMPLE/ DR PRELOAD USER 1 BSCAN. TDO1 USER 2 BSCAN. TDO2 READBACK Readback Data CONFIGURE DOUT Reserved BYPASS Bypass Register I/O Data Source DR Pin/Logic User Logic User Logic Pin/Logic Disabled

Optional IBUF BSCAN TDI TMS TCK From User Logic

TDI TMS TCK TDO1 TDO2 TDO DRCK IDLE SEL1 SEL2

To User Logic

TDO

To User Logic

X2675

Figure 44: Boundary Scan Schematic Example

Conguration
Conguration is the process of loading design-specic programming data into one or more FPGAs to dene the functional operation of the internal blocks and their interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC4000 Series devices use several hundred bits of conguration data per CLB and its associated interconnects. Each conguration bit denes the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design into a netlist le. It automatically partitions, places and routes the logic and generates the conguration data in PROM format.

Bit 0 ( TDO end) Bit 1 Bit 2

TDO.T TDO.O Top-edge IOBs (Right to Left)

Left-edge IOBs (Top to Bottom) MD1.T MD1.O MD1.I MD0.I MD2.I Bottom-edge IOBs (Left to Right)

Special Purpose Pins

Three conguration mode pins (M2, M1, M0) are sampled prior to conguration to determine the conguration mode. After conguration, these pins can be used as auxiliary connections. M2 and M0 can be used as inputs, and M1 can be used as an output. The XACTstep development system does not use these resources unless they are explicitly specied in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of the input or output pad symbol. In XC4000 Series devices, the mode pins have weak pullup resistors during conguration. With all three mode pins High, Slave Serial mode is selected, which is the most popular conguration mode. Therefore, for the most common conguration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistor value can be as high as 100 k.) After conguration, these pins can individually have weak pull-up or pull-down resistors, as specied in the design. A pull-down resistor value of 4.7 k is recommended. These pins are located in the lower left chip corner and are near the readback nets. This location allows convenient routing if compatibility with the XC2000 and XC3000 family conventions of M0/RT, M1/RD is desired.

Right-edge IOBs (Bottom to Top) (TDI end) B SCANT.UPD

X6075

Figure 43:

Boundary Scan Bit Sequence

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken to ensure that at least one of these pins is held constant during conguration. In some applications, a situation may occur where TMS or TCK is driven during conguration. This may cause the device to go into boundary scan mode and disrupt the conguration process. To prevent activation of boundary scan during conguration, do either of the following: TMS: Tie High to put the Test Access Port controller in a benign RESET state TCK: Tie High or Lowdon't toggle this clock input.

For more information regarding boundary scan, refer to the Xilinx Application Note XAPP 017.001, Boundary Scan in XC4000E Devices.

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Conguration Modes
XC4000E devices have six conguration modes. XC4000X devices have the same six modes, plus an additional conguration mode. These modes are selected by a 3-bit input code applied to the M2, M1, and M0 inputs. There are three self-loading Master modes, two Peripheral modes, and a Serial Slave mode, which is used primarily for daisychained devices. The coding for mode selection is shown in Table 19. Table 19: Conguration Modes Mode Master Serial Slave Serial Master Parallel Up Master Parallel Down Peripheral Synchronous* Peripheral Asynchronous Reserved Reserved
Note:

Additional Address lines in XC4000 devices

The XC4000X devices have additional address lines (A18A21) allowing the additional address space required to daisy-chain several large devices. The extra address lines are programmable in XC4000EX devices. By default these address lines are not activated. In the default mode, the devices are compatible with existing XC4000 and XC4000E products. If desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g AddressLines:22). The lines (A18-A21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. Because these pins will initially be pulled high by internal pull-ups, designers using Master Parallel Up mode should use external pull down resistors on pins A18-A21. If Master Parallel Down mode is used external resistors are not necessary. All 22 address lines are always active in Master Parallel modes with XC4000XL devices. The additional address lines behave identically to the lower order address lines. If the Address Lines option in bitgen is set to 18, it will be ignored by the XC4000XL device. The additional address lines (A18-A21) are not available in the PC84 package.

M2 0 1 1

M1 0 1 0

M0 0 1 0

CCLK output input output

output

0 1 0 0

1 0 1 0

1 1 0 1

input output

Data Bit-Serial Bit-Serial Byte-Wide, increment from 00000 Byte-Wide, decrement from 3FFFF Byte-Wide Byte-Wide

Peripheral Modes
The two Peripheral modes accept byte-wide data from a bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes the bytewide data. CCLK can also drive slave devices. In the synchronous mode, an externally supplied clock input to CCLK serializes the data.

* Peripheral Synchronous can be considered bytewide Slave Parallel

A detailed description of each conguration mode, with timing information, is included later in this data sheet. During conguration, some of the I/O pins are used temporarily for the conguration process. All pins used during conguration are shown in Table 23 on page 4-59.

Master Modes
The three Master modes use an internal oscillator to generate a Conguration Clock (CCLK) for driving potential slave devices. They also generate address and timing for external PROM(s) containing the conguration data. Master Parallel (Up or Down) modes generate the CCLK signal and PROM addresses and receive byte parallel data. The data is internally serialized into the FPGA dataframe format. The up and down selection generates starting addresses at either zero or 3FFFF (3FFFFF when 22 address lines are used), for compatibility with different microprocessor addressing conventions. The Master Serial mode generates CCLK and receives the conguration data in serial form from a Xilinx serial-conguration PROM. CCLK speed is selectable as either 1 MHz (default) or 8 MHz. Conguration always starts at the default slow frequency, then can switch to the higher frequency during the rst frame. Frequency tolerance is -50% to +25%.

Slave Serial Mode

In Slave Serial mode, the FPGA receives serial conguration data on the rising edge of CCLK and, after loading its conguration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave devices with identical congurations can be wired with parallel DIN inputs. In this way, multiple devices can be congured simultaneously. Serial Daisy Chain Multiple devices with different congurations can be connected together in a daisy chain, and a single combined bitstream used to congure the chain of slave devices. To congure a daisy chain of devices, wire the CCLK pins of all devices in parallel, as shown in Figure 52 on page 4-61. Connect the DOUT of each device to the DIN of the next. The lead or master FPGA and following slaves each passes resynchronized conguration data coming from a single source. The header data, including the length count,

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XC4000E and XC4000X Series Field Programmable Gate Arrays

is passed through and is captured by each FPGA when it recognizes the 0010 preamble. Following the length-count data, each FPGA outputs a High on DOUT until it has received its required number of data frames. After an FPGA has received its conguration data, it passes on any additional frame start bits and conguration data on DOUT. When the total number of conguration clocks applied after memory initialization equals the value of the 24-bit length count, the FPGAs begin the start-up sequence and become operational together. FPGA I/O are normally released two CCLK cycles after the last conguration bit is received. Figure 48 on page 4-54 shows the startup timing for an XC4000 Series device. The daisy-chained bitstream is not simply a concatenation of the individual bitstreams. The PROM le formatter must be used to combine the bitstreams for a daisy-chained conguration. Multi-Family Daisy Chain All Xilinx FPGAs of the XC2000, XC3000, and XC4000 Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary sequence. There is, however, one limitation. The lead device must belong to the highest family in the chain. If the chain contains XC4000 Series devices, the master normally cannot be an XC2000 or XC3000 device. The reason for this rule is shown in Figure 48 on page 4-54. Since all devices in the chain store the same length count value and generate or receive one common sequence of CCLK pulses, they all recognize length-count match on the same CCLK edge, as indicated on the left edge of Figure 48. The master device then generates additional CCLK pulses until it reaches its nish point F. The different families generate or require different numbers of additional CCLK pulses until they reach F. Not reaching F means that the device does not really nish its conguration, although DONE may have gone High, the outputs became active, and the internal reset was released. For the XC4000 Series device, not reaching F means that readback cannot be ini-

tiated and most boundary scan instructions cannot be used. The user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the nish point F is reached. Timing is controlled using options in the bitstream generation software. XC3000 Master with an XC4000 Series Slave Some designers want to use an inexpensive lead device in peripheral mode and have the more precious I/O pins of the XC4000 Series devices all available for user I/O. Figure 45 provides a solution for that case. This solution requires one CLB, one IOB and pin, and an internal oscillator with a frequency of up to 5 MHz as a clock source. The XC3000 master device must be congured with late Internal Reset, which is the default option. One CLB and one IOB in the lead XC3000-family device are used to generate the additional CCLK pulse required by the XC4000 Series devices. When the lead device removes the internal RESET signal, the 2-bit shift register responds to its clock input and generates an active Low output signal for the duration of the subsequent clock period. An external connection between this output and CCLK thus creates the extra CCLK pulse.

OE/T Reset 0 0 1 0 1 1 0 1 0 1 . etc .

Output Connected to CCLK

Active Low Output Active High Output

X5223

Figure 45: CCLK Generation for XC3000 Master Driving an XC4000 Series Slave

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Setting CCLK Frequency

For Master modes, CCLK can be generated in either of two frequencies. In the default slow mode, the frequency ranges from 0.5 MHz to 1.25 MHz for XC4000E and XC4000EX devices and from 0.6 MHz to 1.8 MHz for XC4000XL devices. In fast CCLK mode, the frequency ranges from 4 MHz to 10 MHz for XC4000EX devices and from 5 MHz to 15 MHz for XC4000XL devices. The frequency is selected by an option when running the bitstream generation software. If an XC4000 Series Master is driving an XC3000- or XC2000-family slave, slow CCLK mode must be used. In addition, an XC4000XL device driving a XC4000E or XC4000EX should use slow mode. Slow mode is the default. Table 20: XC4000 Series Data Stream Formats Data Type Fill Byte Preamble Code Length Count Fill Bits Start Field Data Frame CRC or Constant Field Check Extend Write Cycle Postamble Start-Up Bytes LEGEND: Unshaded Light Dark Once per bitstream Once per data frame Once per device All Other Modes (D0...) 11111111b 0010b COUNT(23:0) 1111b 0b DATA(n-1:0) xxxx (CRC) or 0110b 01111111b xxh

Data Stream Format

The data stream (bitstream) format is identical for all conguration modes. The data stream formats are shown in Table 20. Bit-serial data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the rst bit in each byte assigned to D0. The conguration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator eld of ones. This header is followed by the actual conguration data in frames. The length and number of frames depends on the device type (see Table 21 and Table 22). Each frame begins with a start eld and ends with an error check. A postamble code is required to signal the end of data for a single device. In all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of conguration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams created by the Xilinx software. A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The non-CRC error checking tests for a designated end-of-frame eld for each frame. For CRC error checking, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each frame. The 11-bit CRC check of the last frame of an FPGA includes the last seven data bits. Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes, CCLK and address signals continue to operate externally. The user must detect INIT and initialize a new conguration by pulsing the PROGRAM pin Low or cycling Vcc.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 21: XC4000E Program Data Device Max Logic Gates CLBs (Row x Col.) IOBs Flip-Flops Bits per Frame Frames Program Data PROM Size (bits) XC4003E 3,000 100 (10 x 10) 80 360 126 428 53,936 53,984 XC4005E 5,000 196 (14 x 14) 112 616 166 572 94,960 95,008 XC4006E 6,000 256 (16 x 16) 128 768 186 644 119,792 119,840 XC4008E 8,000 324 (18 x 18) 144 936 206 716 147,504 147,552 XC4010E 10,000 400 (20 x 20) 160 1,120 226 788 178,096 178,144 XC4013E 13,000 576 (24 x 24) 192 1,536 266 932 247,920 247,968 XC4020E 20,000 784 (28 x 28) 224 2,016 306 1,076 329,264 329,312 XC4025E 25,000 1,024 (32 x 32) 256 2,560 346 1,220 422,128 422,176

Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits PROM Size = Program Data + 40 (header) + 8 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.

Table 22: XC4000EX/XL Program Data Device Max Logic Gates CLBs (Row x Column) IOBs Flip-Flops Bits per Frame Frames Program Data PROM Size (bits) XC4005 5,000 196 (14 x 14) 112 616 205 741 151,910 151,960 XC4010 10,000 400 (20 x 20) 160 1,120 277 1,023 283,376 283,424 XC4013 13,000 576 (24 x 24) 192 1,536 325 1,211 393,580 393,632 XC4020 20,000 784 (28 x 28) 224 2,016 373 1,399 521,832 521,880 XC4028 28,000 1,024 (32 x 32) 256 2,560 421 1,587 668,132 668,184 XC4036 36,000 1,296 (36 x 36) 288 3,168 469 1,775 832,480 832,528 XC4044 44,000 1,600 (40 x 40) 320 3,840 517 1,963 1,014,876 1,014,928 XC4052 52,000 1,936 (44 x 44) 352 4,576 565 2,151 1,215,320 1,215,368 XC4062 62,000 2,304 (48 x 48) 384 5,376 613 2,339 1,433,812 1,433,864 XC4085 85,000 3,136 (56 x 56) 448 7,168 709 2,715 1,924,940 1,924,992

Notes: 1. Bits per frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits. Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4. Program data = (bits per frame x number of frames) + 5 postamble bits. PROM size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte. 2. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.t

Cyclic Redundancy Check (CRC) for Conguration and Readback

The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serial bitstream. The result of this calculation is tagged onto the data stream as additional check bits. The receiving system

performs an identical calculation on the bitstream and compares the result with the received checksum. Each data frame of the conguration bitstream has four error bits at the end, as shown in Table 20. If a frame data error is detected during the loading of the FPGA, the conguration process with a potentially corrupted bitstream is terminated. The FPGA pulls the INIT pin Low and goes into a Wait state.

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March 30, 1998 (Version 1.5)

During Readback, 11 bits of the 16-bit checksum are added to the end of the Readback data stream. The checksum is computed using the CRC-16 CCITT polynomial, as shown in Figure 46. The checksum consists of the 11 most signicant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLB outputs should not be included (Read Capture option not used), and if RAM is present, the RAM content must be unchanged. Statistically, one error out of 2048 might go undetected.

Boundary Scan Instructions Available:

VCC >3.5 V Yes

Test M0 Generate One Time-Out Pulse of 16 or 64 ms

PROGRAM = Low Yes

Keep Clearing Configuration Memory

Conguration Sequence
There are four major steps in the XC4000 Series power-up conguration sequence. Conguration Memory Clear Initialization Conguration Start-Up

EXTEST* SAMPLE/PRELOAD Completely Clear BYPASS Configuration Memory CONFIGURE* Once More (* if PROGRAM = High)

~1.3 s per Frame

INIT High? if Master Yes

Master Waits 50 to 250 s Before Sampling Mode Lines

The full process is illustrated in Figure 47.

Sample Mode Lines Master CCLK Goes Active Load One Configuration Data Frame LDC Output = L, HDC Output = H
X6076

Conguration Memory Clear

When power is rst applied or is reapplied to an FPGA, an internal circuit forces initialization of the conguration logic. When Vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of conguration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the low-voltage devices. The delay is four times as long when in Master Modes (M0 Low), to allow ample time for all slaves to reach a stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed and matched in a daisy chain. This delay is applied only on power-up. It is not applied when reconguring an FPGA by pulsing the PROGRAM pin
X2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 X15 X16 15

Frame Error No SAMPLE/PRELOAD BYPASS Configuration memory Full Yes Pass Configuration Data to DOUT

Yes

Pull INIT Low and Stop

CCLK Count Equals Length Count Yes

SERIAL DATA IN

Polynomial: X16 + X15 + X2 + 1

Start-Up Sequence I/O Active

1 1 1 1 1 0 15 14 13 12 11 10 9 8 7 6 5 LAST DATA FRAME CRC CHECKSUM

EXTEST SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK
START BIT

Operational

If Boundary Scan is Selected

Readback Data Stream

X1789

Figure 46: Circuit for Generating CRC-16 Figure 47: Power-up Conguration Sequence

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Low. During this time delay, or as long as the PROGRAM input is asserted, the conguration logic is held in a Conguration Memory Clear state. The conguration-memory frames are consecutively initialized, using the internal oscillator. At the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the conguration frames and then tests the INIT input.

rise time is excessive or poorly dened. As long as PROGRAM is Low, the FPGA keeps clearing its conguration memory. When PROGRAM goes High, the conguration memory is cleared one more time, followed by the beginning of conguration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input automatically forces a Low on the INIT output. The XC4000 Series PROGRAM pin has a permanent weak pull-up. Using an open-collector or open-drain driver to hold INIT Low before the beginning of conguration causes the FPGA to wait after completing the conguration memory clear operation. When INIT is no longer held Low externally, the device determines its conguration mode by capturing its mode pins, and is ready to start the conguration process. A master device waits up to an additional 250 s to make sure that any slaves in the optional daisy chain have seen that INIT is High.

Initialization
During initialization and conguration, user pins HDC, LDC, INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and HDC is held High starting at the initial application of power. The open drain INIT pin is released after the nal initialization pass through the frame addresses. There is a deliberate delay of 50 to 250 s (up to 10% longer for low-voltage devices) before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized as High, the FPGA samples the three mode lines to determine the conguration mode. The appropriate interface lines become active and the conguration preamble and data can be loaded.Conguration The 0010 preamble code indicates that the following 24 bits represent the length count. The length count is the total number of conguration clocks needed to load the complete conguration data. (Four additional conguration clocks are required to complete the conguration process, as discussed below.) After the preamble and the length count have been passed through to all devices in the daisy chain, DOUT is held High to prevent frame start bits from reaching any daisy-chained devices. A specic conguration bit, early in the rst frame of a master device, controls the conguration-clock rate and can increase it by a factor of eight. Therefore, if a fast conguration clock is selected by the bitstream, the slower clock rate is used until this conguration bit is detected. Each frame has a start eld followed by the frame-conguration data bits and a frame error eld. If a frame data error is detected, the FPGA halts loading, and signals the error by pulling the open-drain INIT pin Low. After all conguration frames have been loaded into an FPGA, DOUT again follows the input data so that the remaining data is passed on to the next device.

Start-Up
Start-up is the transition from the conguration process to the intended user operation. This transition involves a change from one clock source to another, and a change from interfacing parallel or serial conguration data where most outputs are 3-stated, to normal operation with I/O pins active in the user-system. Start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the conguration signals, and that the internal ip-ops are released from the global Reset or Set at the right time. Figure 48 describes start-up timing for the three Xilinx families in detail. The conguration modes can use any of the four timing sequences. To access the internal start-up signals, place the STARTUP library symbol. Start-up Timing Different FPGA families have different start-up sequences. The XC2000 family goes through a xed sequence. DONE goes High and the internal global Reset is de-activated one CCLK period after the I/O become active. The XC3000A family offers some exibility. DONE can be programmed to go High one CCLK period before or after the I/O become active. Independent of DONE, the internal global Reset is de-activated one CCLK period before or after the I/O become active. The XC4000 Series offers additional exibility. The three events DONE going High, the internal Set/Reset being de-activated, and the user I/O going active can all occur in any arbitrary sequence. Each of them can occur one CCLK period before or after, or simultaneous with, any of the others. This relative timing is selected by means of software options in the bitstream generation software.

Delaying Conguration After Power-Up

There are two methods of delaying conguration after power-up: put a logic Low on the PROGRAM input, or pull the bidirectional INIT pin Low, using an open-collector (open-drain) driver. (See Figure 47 on page 4-51.) A Low on the PROGRAM input is the more radical approach, and is recommended when the power-supply 4-52

March 30, 1998 (Version 1.5)

The default option, and the most practical one, is for DONE to go High rst, disconnecting the conguration data source and avoiding any contention when the I/Os become active one clock later. Reset/Set is then released another clock period later to make sure that user-operation starts from stable internal conditions. This is the most common sequence, shown with heavy lines in Figure 48, but the designer can modify it to meet particular requirements. Normally, the start-up sequence is controlled by the internal device oscillator output (CCLK), which is asynchronous to the system clock. XC4000 Series offers another start-up clocking option, UCLK_NOSYNC. The three events described above need not be triggered by CCLK. They can, as a conguration option, be triggered by a user clock. This means that the device can wake up in synchronism with the user system. When the UCLK_SYNC option is enabled, the user can externally hold the open-drain DONE output Low, and thus stall all further progress in the start-up sequence until DONE is released and has gone High. This option can be used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully congured before any I/Os go active. If either of these two options is selected, and no user clock is specied in the design or attached to the device, the chip could reach a point where the conguration of the device is complete and the Done pin is asserted, but the outputs do not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply the appropriate user clock. Start-up Sequence The Start-up sequence begins when the conguration memory is full, and the total number of conguration clocks

received since INIT went High equals the loaded value of the length count. The next rising clock edge sets a ip-op Q0, shown in Figure 49. Q0 is the leading bit of a 5-bit shift register. The outputs of this register can be programmed to control three events. The release of the open-drain DONE output The change of conguration-related pins to the user function, activating all IOBs. The termination of the global Set/Reset initialization of all CLB and IOB storage elements. The DONE pin can also be wire-ANDed with DONE pins of other FPGAs or with other external signals, and can then be used as input to bit Q3 of the start-up register. This is called Start-up Timing Synchronous to Done In and is selected by either CCLK_SYNC or UCLK_SYNC. When DONE is not used as an input, the operation is called Start-up Timing Not Synchronous to DONE In, and is selected by either CCLK_NOSYNC or UCLK_NOSYNC. As a conguration option, the start-up control register beyond Q0 can be clocked either by subsequent CCLK pulses or from an on-chip user net called STARTUP.CLK. These signals can be accessed by placing the STARTUP library symbol. Start-up from CCLK If CCLK is used to drive the start-up, Q0 through Q3 provide the timing. Heavy lines in Figure 48 show the default timing, which is compatible with XC2000 and XC3000 devices using early DONE and late Reset. The thin lines indicate all other possible timing options.

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4-53

XC4000E and XC4000X Series Field Programmable Gate Arrays

Length Count Match

CCLK Period

CCLK
F DONE

XC2000

I/O

Global Reset F F = Finished, no more configuration clocks needed Daisy-chain lead device must have latest F Heavy lines describe default timing Global Reset F DONE C1 C2 C3 C4 I/O C2 GSR Active C2 DONE IN F DONE C1, C2 or C3 I/O C3 C4 C3 C4

XC3000

DONE I/O

XC4000E/X
CCLK_NOSYNC

XC4000E/X
CCLK_SYNC

Di
GSR Active

Di+1

Di+1
F

DONE C1 U2 U3 U4 I/O U2 GSR Active U2 DONE IN F DONE C1 U2 I/O U3 U4 U3 U4

XC4000E/X
UCLK_NOSYNC

XC4000E/X
UCLK_SYNC

Di
GSR Active

Di+1

Di+2

Synchronization Uncertainty

Di+1

Di+2

UCLK Period
X9024

Figure 48: Start-up Timing

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March 30, 1998 (Version 1.5)

Start-up from a User Clock (STARTUP.CLK) When, instead of CCLK, a user-supplied start-up clock is selected, Q1 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence.

Release of User I/O After DONE Goes High

By default, the user I/O are released one CCLK cycle after the DONE pin goes High. If CCLK is not clocked after DONE goes High, the outputs remain in their initial state 3-stated, with a 50 k - 100 k pull-up. The delay from DONE High to active user I/O is controlled by an option to the bitstream generation software.

DONE Goes High to Signal End of Conguration

XC4000 Series devices read the expected length count from the bitstream and store it in an internal register. The length count varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during conguration. Two conditions have to be met in order for the DONE pin to go high: the chip's internal memory must be full, and the conguration length count must be met, exactly.

Release of Global Set/Reset After DONE Goes High

By default, Global Set/Reset (GSR) is released two CCLK cycles after the DONE pin goes High. If CCLK is not clocked twice after DONE goes High, all ip-ops are held in their initial set or reset state. The delay from DONE High to GSR inactive is controlled by an option to the bitstream generation software.

Conguration Complete After DONE Goes High

Three full CCLK cycles are required after the DONE pin goes High, as shown in Figure 48 on page 4-54. If CCLK is not clocked three times after DONE goes High, readback cannot be initiated and most boundary scan instructions cannot be used.

This is important because the counter that determines when the length count is met begins with the very rst CCLK, not the rst one after the preamble. Therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the rst CCLK, the internal counter that holds the number of CCLKs will be one ahead of the actual number of data bits read. At the end of conguration, the conguration memory will be full, but the number of bits in the internal counter will not match the expected length count. As a consequence, a Master mode device will continue to send out CCLKs until the internal counter turns over to zero, and then reaches the correct length count a second time. This will take several seconds [224 CCLK period] which is sometimes interpreted as the device not conguring at all. If it is not possible to have the data ready at the time of the rst CCLK, the problem can be avoided by increasing the number in the length count by the appropriate value. The XACT User Guide includes detailed information about manually altering the length count. Note that DONE is an open-drain output and does not go High unless an internal pull-up is activated or an external pull-up is attached. The internal pull-up is activated as the default by the bitstream generation software.

Conguration Through the Boundary Scan Pins

XC4000 Series devices can be congured through the boundary scan pins. The basic procedure is as follows: Power up the FPGA with INIT held Low (or drive the PROGRAM pin Low for more than 300 ns followed by a High while holding INIT Low). Holding INIT Low allows enough time to issue the CONFIG command to the FPGA. The pin can be used as I/O after conguration if a resistor is used to hold INIT Low. Issue the CONFIG command to the TMS input Wait for INIT to go High Sequence the boundary scan Test Access Port to the SHIFT-DR state Toggle TCK to clock data into TDI pin.

The user must account for all TCK clock cycles after INIT goes High, as all of these cycles affect the Length Count compare. For more detailed information, refer to the Xilinx application note XAPP017, Boundary Scan in XC4000 Devices. This application note also applies to XC4000E and XC4000X devices.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Q3 STARTUP Q2

Q1/Q4 DONE IN

* *
1 0 GSR ENABLE GSR INVERT STARTUP.GSR STARTUP.GTS GTS INVERT GTS ENABLE 0

IOBs OPERATIONAL PER CONFIGURATION

GLOBAL SET/RESET OF ALL CLB AND IOB FLIP-FLOP

CONTROLLED BY STARTUP SYMBOL IN THE USER SCHEMATIC (SEE LIBRARIES GUIDE)

GLOBAL 3-STATE OF ALL IOBs 1

*
1 0 1 0

DONE " FINISHED " ENABLES BOUNDARY SCAN, READBACK AND CONTROLS THE OSCILLATOR

FULL LENGTH COUNT

1 S Q D Q D Q 0 M K K K D Q D Q

CLEAR MEMORY CCLK STARTUP.CLK USER NET 0 1

*
Figure 49: Start-up Logic

CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"

X1528

Readback
The user can read back the content of conguration memory and the level of certain internal nodes without interfering with the normal operation of the device. Readback not only reports the downloaded conguration bits, but can also include the present state of the device, represented by the content of all ip-ops and latches in CLBs and IOBs, as well as the content of function generators used as RAMs. Note that in XC4000 Series devices, conguration data is not inverted with respect to conguration as it is in XC2000 and XC3000 families. XC4000 Series Readback does not use any dedicated pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA, RDBK.RIP and RDBK.CLK) that can be routed to any IOB. To access the internal Readback sig-

nals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 50. After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress) output goes High on the next rising edge of RDBK.CLK. Subsequent rising edges of this clock shift out Readback data on the RDBK.DATA net. Readback data does not include the preamble, but starts with ve dummy bits (all High) followed by the Start bit (Low) of the rst frame. The rst two data bits of the rst frame are always High. Each frame ends with four error check bits. They are read back as High. The last seven bits of the last frame are also read back as High. An additional Start bit (Low) and an 11-bit Cyclic Redundancy Check (CRC) signature follow, before RDBK.RIP returns Low.

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March 30, 1998 (Version 1.5)

IF UNCONNECTED, DEFAULT IS CCLK

CLK MD0 READ_TRIGGER IBUF TRIG READBACK

DATA RIP OBUF

READ_DATA

MD1

X1786

Figure 50: Readback Schematic Example

Readback Options
Readback options are: Read Capture, Read Abort, and Clock Select. They are set with the bitstream generation software.
I/O PROGRAMMABLE INTERCONNECT I/O

When the Read Capture option is selected, the readback data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the inverted values of the four CLB outputs, the IOB output ip-ops and the input signals I1 and I2. Note that while the bits describing conguration (interconnect, function generators, and RAM content) are not inverted, the CLB and IOB output signals are inverted. When the Read Capture option is not selected, the values of the capture bits reect the conguration data originally written to those memory locations. If the RAM capability of the CLBs is used, RAM data are available in readback, since they directly overwrite the F and G function-table conguration of the CLB. RDBK.TRIG is located in the lower-left corner of the device, as shown in Figure 51.

TRIG DATA RIP

Read Capture

rdbk

I/O

rdclk

X1787

Figure 51: READBACK Symbol in Graphical Editor

Violating the Maximum High and Low Time Specication for the Readback Clock
The readback clock has a maximum High and Low time specication. In some cases, this specication cannot be met. For example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. This necessitates stopping the clock, and thus violating the specication. The specication is mandatory only on clocking data at the end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the source of the maximum High and Low time requirements. Therefore, the specication only applies to the six clock cycles prior to and including any start bit, including the clocks before the rst start bit in the readback data stream. At other times, the frame data is already in the register and the register is not dynamic. Thus, it can be shifted out just like a regular shift register. The user must precisely calculate the location of the readback data relative to the frame. The system must keep track of the position within a data frame, and disable interrupts before frame boundaries. Frame lengths and data formats are listed in Table 20, Table 21 and Table 22.

Read Abort
When the Read Abort option is selected, a High-to-Low transition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger. After an aborted readback, additional clocks (up to one readback clock per conguration frame) may be required to re-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP is High whenever a readback is in progress.

Clock Select
CCLK is the default clock. However, the user can insert another clock on RDBK.CLK. Readback control and data are clocked on rising edges of RDBK.CLK. If readback must be inhibited for security reasons, the readback control nets are simply not connected. RDBK.CLK is located in the lower right chip corner, as shown in Figure 51.

Readback with the XChecker Cable

The XChecker Universal Download/Readback Cable and Logic Probe uses the readback feature for bitstream verication. It can also display selected internal signals on the PC or workstation screen, functioning as a low-cost in-circuit emulator.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E/EX/XL Program Readback Switching Characteristic Guidelines

Finished Internal Net

rdbk.TRIG 1 TRTRC rdclk.I 4 TRCL TRCH 5 TRCRT 2 1 TRTRC TRCRT 2

rdbk.RIP TRCRR 6

rdbk.DATA

DUMMY TRCRD 7

DUMMY

VALID

VALID X1790

E/EX rdbk.TRIG rdclk.1 Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time 1 2 7 6 5 4 Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL Min 200 50 250 250 Max 250 250 500 500 Units ns ns ns ns ns ns

Note 1: Note 2:

Timing parameters apply to all speed grades. If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.

XL rdbk.TRIG rdclk.1 Description rdbk.TRIG setup to initiate and abort Readback rdbk.TRIG hold to initiate and abort Readback rdbk.DATA delay rdbk.RIP delay High time Low time 1 2 7 6 5 4 Symbol TRTRC TRCRT TRCRD TRCRR TRCH TRCL Min 200 50 250 250 Max 250 250 500 500 Units ns ns ns ns ns ns

Note 1: Note 2:

Timing parameters apply to all speed grades. If rdbk.TRIG is High prior to Finished, Finished will trigger the rst Readback.

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March 30, 1998 (Version 1.5)

Table 23: Pin Functions During Conguration

SLAVE SERIAL <1:1:1> M2(HIGH) (I) M1(HIGH) (I) M0(HIGH) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (I) MASTER SERIAL <0:0:0> M2(LOW) (I) M1(LOW) (I) M0(LOW) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (O) CONFIGURATION MODE <M2:M1:M0> SYNCH. ASYNCH. MASTER PERIPHERAL PERIPHERAL PARALLEL DOWN <0:1:1> <1:0:1> <1:1:0> M2(LOW) (I) M2(HIGH) (I) M2(HIGH) (I) M1(HIGH) (I) M1(LOW) (I) M1(HIGH) (I) M0(HIGH) (I) M0(HIGH) (I) M0(LOW) (I) HDC (HIGH) HDC (HIGH) HDC (HIGH) LDC (LOW) LDC (LOW) LDC (LOW) INIT INIT INIT DONE DONE DONE PROGRAM (I) PROGRAM (I) PROGRAM (I) CCLK (I) CCLK (O) CCLK (O) RDY/BUSY (O) RDY/BUSY (O) RCLK (O) RS (I) CS0 (I) DATA 7 (I) DATA 7 (I) DATA 7 (I) DATA 6 (I) DATA 6 (I) DATA 6 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 2 (I) DATA 2 (I) DATA 2 (I) DATA 1 (I) DATA 1 (I) DATA 1 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) DOUT DOUT DOUT TDI TDI TDI TCK TCK TCK TMS TMS TMS TDO TDO TDO WS (I) A0 A1 CS1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21* MASTER PARALLEL UP <1:0:0> M2(HIGH) (I) M1(LOW) (I) M0(LOW) (I) HDC (HIGH) LDC (LOW) INIT DONE PROGRAM (I) CCLK (O) RCLK (O)

USER OPERATION (I) (O) (I) I/O I/O I/O DONE PROGRAM CCLK (I) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK4-GCK5-I/O TDI-I/O TCK-I/O TMS-I/O TDO-(O) I/O PGCK4-GCK6-I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SGCK1-GCK7-I/O PGCK1-GCK8-I/O I/O I/O I/O I/O I/O ALL OTHERS

DIN (I) DOUT TDI TCK TMS TDO

DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) DATA 0 (I) DOUT TDI TCK TMS TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21*

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 24: Pin Functions During Conguration

DIN (I) DOUT TDI TCK TMS TDO

DATA 7 (I) DATA 6 (I) DATA 5 (I) DATA 4 (I) DATA 3 (I) DATA 2 (I) DATA 1 (I) DATA 0 (I) DOUT TDI TCK TMS TDO A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18* A19* A20* A21*

* XC4000X only Notes 1. A shaded table cell represents a 50 k - 100 k pull-up before and during conguration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during conguration.

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March 30, 1998 (Version 1.5)

Conguration Timing
The seven conguration modes are discussed in detail in this section. Timing specications are included.

There is an internal delay of 0.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. Figure 52 shows a full master/slave system. An XC4000 Series device in Slave Serial mode should be connected as shown in the third device from the left. Slave Serial mode is selected by a <111> on the mode pins (M2, M1, M0). Slave Serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resistors during conguration.

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLK input of the FPGA. The serial conguration bitstream must be available at the DIN input of the lead FPGA a short setup time before each rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin.
NOTE: M2, M1, M0 can be shorted to Ground if not used as I/O

NOTE: M2, M1, M0 can be shorted to VCC if not used as I/O

VCC
N/C

4.7 K

4.7 K M0 M1 M2 DIN DOUT

4.7 K

M0 M1 M2 DOUT

N/C

M0 M1 M2 DIN CCLK

PWRDN

DOUT

XC4000E/X

VCC
4.7 K

CCLK

MASTER SERIAL
CCLK DIN PROGRAM DONE LDC INIT

XC1700D
CLK DATA CE RESET/OE CEO VPP

+5 V

XC4000E/X, XC5200

XC3100A

SLAVE

SLAVE
PROGRAM DONE INIT RESET D/P INIT

(Low Reset Option Used)

PROGRAM

X9025

Figure 52: Master/Slave Serial Mode Circuit Diagram

DIN 1 TDCC CCLK

Bit n 2 TCCD

Bit n + 1 5 TCCL

4 TCCH DOUT (Output) Bit n - 1

3 TCCO Bit n
X5379

CCLK

Description DIN setup DIN hold DIN to DOUT High time Low time Frequency

1 2 3 4 5

Symbol TDCC TCCD TCCO TCCH TCCL FCC

Min 20 0 45 45

Max

Units ns ns ns ns ns MHz

Note:

Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 53: Slave Serial Mode Programming Switching Characteristics

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Master Serial Mode

In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the FPGA DIN input. Each rising edge of the CCLK output increments the Serial PROM internal address counter. The next data bit is put on the SPROM data output, connected to the FPGA DIN pin. The lead FPGA accepts this data on the subsequent rising CCLK edge. The lead FPGA then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal pipeline delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In the bitstream generation software, the user can specify Fast CongRate, which, starting several bits into the rst

frame, increases the CCLK frequency by a factor of eight. For actual timing values please refer to Conguration Switching Characteristics on page 4-69. Be sure that the serial PROM and slaves are fast enough to support this data rate. XC2000, XC3000/A, and XC3100A devices do not support the Fast CongRate option. The SPROM CE input can be driven from either LDC or DONE. Using LDC avoids potential contention on the DIN pin, if this pin is congured as user-I/O, but LDC is then restricted to be a permanently High user output after conguration. Using DONE can also avoid contention on DIN, provided the early DONE option is invoked. Figure 52 on page 4-61 shows a full master/slave system. The leftmost device is in Master Serial mode. Master Serial mode is selected by a <000> on the mode pins (M2, M1, M0).

CCLK (Output) 2 TCKDS 1 Serial Data In TDSCK n n+1 n+2

Serial DOUT (Output)

n
X3223

CCLK

Description DIN setup DIN hold

1 2

Symbol TDSCK TCKDS

Min 20 0

Max

Units ns ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM Low until Vcc is valid. 2. Master Serial mode timing is based on testing in slave mode.

Figure 54: Master Serial Mode Programming Switching Characteristics

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March 30, 1998 (Version 1.5)

Master Parallel Modes

In the two Master Parallel modes, the lead FPGA directly addresses an industry-standard byte-wide EPROM, and accepts eight data bits just before incrementing or decrementing the address outputs. The eight data bits are serialized in the lead FPGA, which then presents the preamble dataand all data that overows the lead deviceon its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edge that accepts a byte of data (and also changes the EPROM address) until the falling CCLK edge that makes the LSB (D0) of this byte appear at DOUT. This means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. The PROM address pins can be incremented or decremented, depending on the mode pin settings. This option allows the FPGA to share the PROM with a wide variety of microprocessors and microcontrollers. Some processors must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is exible and can load its conguration bitstream from either end of the memory. Master Parallel Up mode is selected by a <100> on the mode pins (M2, M1, M0). The EPROM addresses start at 00000 and increment.

Master Parallel Down mode is selected by a <110> on the mode pins. The EPROM addresses start at 3FFFF and decrement.

Additional Address lines in XC4000 devices

4.7K

HIGH or LOW

TO DIN OF OPTIONAL DAISY-CHAINED FPGAS N/C N/C TO CCLK OF OPTIONAL DAISY-CHAINED FPGAS

M2 CCLK

NOTE:M0 can be shorted to Ground if not used as I/O. VCC 4.7K

DOUT A17 A16 A15 A14 INIT A13 A12 A11 A10 PROGRAM D7 D6 D5 D4 D3 D2 D1 D0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DONE ... ... ... ... ... A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OE CE D7 D6 D5 D4 D3 D2 D1 D0 DONE INIT EPROM (8K x 8) (OR LARGER) USER CONTROL OF HIGHER ORDER PROM ADDRESS BITS CAN BE USED TO SELECT BETWEEN ALTERNATIVE CONFIGURATIONS M0 DIN M1 M2 DOUT

CCLK XC4000E/X SLAVE

PROGRAM

DATA BUS PROGRAM

X9026

Figure 55: Master Parallel Mode Circuit Diagram

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XC4000E and XC4000X Series Field Programmable Gate Arrays

A0-A17 (output)

Address for Byte n

Address for Byte n + 1 1 TRAC

D0-D7

Byte 2 TDRC 3 TRCD

RCLK (output) 7 CCLKs CCLK

CCLK (output)

DOUT (output)

D6 Byte n - 1

D7
X6078

RCLK

Description Delay to Address valid Data setup time Data hold time

1 2 3

Symbol TRAC TDRC TRCD

Min 0 60 0

Max 200

Units ns ns ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay conguration by pulling PROGRAM Low until Vcc is valid. 2. The rst Data byte is loaded and CCLK starts at the end of the rst RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than 500 ns. EPROM data output has no hold-time requirements. Figure 56: Master Parallel Mode Programming Switching Characteristics

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Synchronous Peripheral Mode

Synchronous Peripheral mode can also be considered Slave Parallel mode. An external signal drives the CCLK input(s) of the FPGA(s). The rst byte of parallel conguration data must be available at the Data inputs of the lead FPGA a short setup time before the rising CCLK edge. Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge. The same CCLK edge that accepts data, also causes the RDY/BUSY output to go High for one CCLK period. The pin name is a misnomer. In Synchronous Peripheral mode it is really an ACKNOWLEDGE signal. Synchronous operation does not require this response, but it is a meaningful signal for test purposes. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High.

The lead FPGA serializes the data and presents the preamble data (and all data that overows the lead device) on its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK edge, and the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge. In order to complete the serial shift operation, 10 additional CCLK rising edges are required after the last data byte has been loaded, plus one more CCLK cycle for each daisychained device. Synchronous Peripheral mode is selected by a <011> on the mode pins (M2, M1, M0).

NOTE: M2 can be shorted to Ground if not used as I/O

N/C 4.7 k N/C

M0 M1 CLOCK 8 D0-7 CCLK

M2 OPTIONAL DAISY-CHAINED FPGAs DOUT

M0 M1 CCLK

DATA BUS

DIN

DOUT

VCC
4.7 k

XC4000E/X SYNCHRONOUS PERIPHERAL

XC4000E/X SLAVE

CONTROL SIGNALS 4.7 k PROGRAM

RDY/BUSY INIT DONE INIT DONE

PROGRAM

X9027

Figure 57: Synchronous Peripheral Mode Circuit Diagram

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XC4000E and XC4000X Series Field Programmable Gate Arrays

CCLK

INIT
BYTE 0 BYTE 1

BYTE 0 OUT DOUT 0 1 2 3 4 5 6 7

BYTE 1 OUT 0 1

RDY/BUSY
X6096

CCLK

Description INIT (High) setup time D0 - D7 setup time D0 - D7 hold time CCLK High time CCLK Low time CCLK Frequency

Symbol TIC TDC TCD TCCH TCCL FCC

Min 5 60 0 50 60

Max

Units s ns ns ns ns MHz

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the rst data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on every eighth consecutive rising edge of CCLK. 2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does not require such a response. 3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal. 4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore, additional CCLK pulses are clearly required after the last byte has been loaded.

Figure 58: Synchronous Peripheral Mode Programming Switching Characteristics

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Asynchronous Peripheral Mode

Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of the logic AND condition of WS and CS0 being Low and RS and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a double-buffered UART-like parallel-to-serial converter and is serially shifted into the internal logic. The lead FPGA presents the preamble data (and all data that overows the lead device) on its DOUT pin. The RDY/ BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. RDY/BUSY goes Low when a byte has been received, and goes High again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. A new write may be started immediately, as soon as the RDY/BUSY output has gone Low, acknowledging receipt of the previous data. Write may not be terminated until RDY/BUSY is High again for one CCLK period. Note that RDY/BUSY is pulled High with a high-impedance pullup prior to INIT going High. The length of the BUSY signal depends on the activity in the UART. If the shift register was empty when the new byte was received, the BUSY signal lasts for only two CCLK periods. If the shift register was still full when the new byte was received, the BUSY signal can be as long as nine CCLK periods. Note that after the last byte has been entered, only seven of its bits are shifted out. CCLK remains High with DOUT equal to bit 6 (the next-to-last bit) of the last byte entered.
N/C
4.7 k

The READY/BUSY handshake can be ignored if the delay from any one Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.

Status Read
The logic AND condition of the CS0, CS1and RS inputs puts the device status on the Data bus. D7 High indicates Ready D7 Low indicates Busy D0 through D6 go unconditionally High

It is mandatory that the whole start-up sequence be started and completed by one byte-wide input. Otherwise, the pins used as Write Strobe or Chip Enable might become active outputs and interfere with the nal byte transfer. If this transfer does not occur, the start-up sequence is not completed all the way to the nish (point F in Figure 48 on page 4-54). In this case, at worst, the internal reset is not released. At best, Readback and Boundary Scan are inhibited. The length-count value, as generated by the XACTstep software, ensures that these problems never occur. Although RDY/BUSY is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. For this purpose, D7 represents the RDY/BUSY status when RS is Low, WS is High, and the two chip select lines are both active. Asynchronous Peripheral mode is selected by a <101> on the mode pins (M2, M1, M0).

N/C N/C

DATA BUS

D07

CCLK OPTIONAL DAISY-CHAINED FPGAs DOUT

CCLK

DIN

DOUT

VCC
ADDRESS BUS

ADDRESS DECODE LOGIC

CS0

4.7 k

XC4000E/X ASYNCHRONOUS PERIPHERAL

...

XC4000E/X SLAVE

CS1 RS WS

CONTROL SIGNALS

RDY/BUSY INIT DONE REPROGRAM

4.7 k

INIT DONE PROGRAM

PROGRAM

X9028

Figure 59:

Asynchronous Peripheral Mode Circuit Diagram

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4-67

XC4000E and XC4000X Series Field Programmable Gate Arrays

Write to LCA WS/CS0

Read Status RS, CS0

RS, CS1

WS, CS1

TCA 2 3 TDC TCD 7

READY BUSY

4
D7

D0-D7

CCLK

TWTRB 4
RDY/BUSY

TBUSY

DOUT

Previous Byte D6

D2
X6097

Write

RDY

Description Effective Write time (CS0, WS=Low; RS, CS1=High) DIN setup time DIN hold time RDY/BUSY delay after end of Write or Read RDY/BUSY active after beginning of Read RDY/BUSY Low output (Note 4)

1 2 3 4 7 6

Symbol TCA TDC TCD TWTRB

Min 100 60 0

Max

Units ns ns ns ns ns CCLK periods

60 60

TBUSY

Notes: 1. Conguration must be delayed until the INIT pins of all daisy-chained FPGAs are High. 2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing and the phase of the internal timing generator for CCLK. 3. CCLK and DOUT timing is tested in slave mode. 4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data.

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write may not be terminated until RDY/BUSY has been High for one CCLK period. Figure 60: Asynchronous Peripheral Mode Programming Switching Characteristics

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Conguration Switching Characteristics

Vcc

T POR RE-PROGRAM >300 ns

PROGRAM T PI INIT T ICCK CCLK OUTPUT or INPUT <300 ns M0, M1, M2 (Required) X1532 I/O VALID DONE RESPONSE <300 ns TCCLK

Master Modes (XC4000E/EX)

Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast M0 = High M0 = Low Symbol TPOR TPOR TPI TICCK TCCLK TCCLK Min 10 40 1 40 640 80 Max 40 130 4 250 2000 250 Units ms ms s per CLB column s ns ns

Master Modes (XC4000XL)

Description Power-On Reset Program Latency CCLK (output) Delay CCLK (output) Period, slow CCLK (output) Period, fast M0 = High M0 = Low Symbol TPOR TPOR TPI TICCK TCCLK TCCLK Min 10 40 1 40 540 67 Max 40 130 4 250 1600 200 Units ms ms s per CLB column s ns ns

Slave and Peripheral Modes(All)

Description Power-On Reset Program Latency CCLK (input) Delay (required) CCLK (input) Period (required) Symbol TPOR TPI TICCK TCCLK Min 10 1 4 100 Max 33 4 Units ms s per CLB column s ns

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XC4000E and XC4000X Series Field Programmable Gate Arrays

March 30, 1998 (Version 1.5)

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL Switching Characteristics

Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered nal.

All specications subject to change without notice.

Additional Specications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specications included in this document are derived from measuring internal test patterns. All specications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. For design considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the Xilinx WEBLINX at http://www.xilinx.com.

Absolute Maximum Ratings

Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Longest Supply Voltage Rise Time from 1 V to 3V Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Description -0.5 to 4.0 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +260 +150 +125 Units V V V ms C C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions

Symbol Description Supply voltage relative to GND, TJ = 0 C to +85C Commercial VCC VIH VIL TIN Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Low-level input voltage Input signal transition time Industrial Min 3.0 3.0 50% of VCC 0 Max 3.6 3.6 5.5 30% of VCC 250 Unit s V V V V ns

Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Input and output measurement threshold is ~50% of VCC.

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DC Characteristics Over Recommended Operating Conditions

Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD IRLL
Note 1: Note 2:

Description High-level output voltage @ IOH = -4.0 mA, VCC min (LVTTL) High-level output voltage @ IOH = -500 A, (LVCMOS) Low-level output voltage @ IOL = 12.0 mA, VCC min (LVTTL) (Note 1) Low-level output voltage @ IOL = 1500 A, (LVCMOS) Data Retention Supply Voltage (below which conguration data may be lost) Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ packages PGA packages Pad pull-up (when selected) @ Vin = 0 V (sample tested) Pad pull-down (when selected) @ Vin = 3.6 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

Min 2.4 90% VCC

Max

Units V V

0.4 10% VCC 2.5 5 -10 +10 10 16 0.02 0.02 0.3 0.25 0.15 2.0

V V V mA A pF pF mA mA mA

With up to 64 pins simultaneously sinking 12 mA. With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and oating.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description Symbol Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL From pad through Global Low Skew buffer, TGLS to any clock K -3 Max 2.7 3.2 3.6 4.0 4.4 4.8 5.3 5.7 6.3 7.2 1.9 2.2 2.4 2.6 2.8 3.1 3.5 4.0 4.9 5.8 -2 Max 2.3 2.8 3.1 3.5 3.8 4.2 4.6 5.0 5.4 6.2 1.8 1.9 2.1 2.2 2.4 2.7 3.0 3.5 4.3 5.1 -1 Max 2.0 2.4 2.7 3.0 3.3 3.6 4.0 4.5 4.7 5.7 1.7 1.7 1.8 2.1 2.1 2.3 2.6 3.0 3.7 4.7 -09 Max 1.9 2.3 2.6 2.9 3.2 3.5 3.9 4.4 4.6 5.5 1.6 1.7 1.7 2.0 2.0 2.2 2.4 3.0 3.4 4.3 Note 1
Note 1: Preliminary specication only.

Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

From pad through Global Early buffer, TGE to any IOB clockK. Values are for BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.

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XC4000XL CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XL devices and expressed in nanoseconds unless otherwise noted.
Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs F/G inputs via transparent latch to Q outputs C inputs via SR/H0 via H to X/Y outputs C inputs via H1 via H to X/Y outputs C inputs via DIN/H2 via H to X/Y outputs C inputs via EC, DIN/H2 to YQ, XQ output (bypass) CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Symbol TILO TIHO TITO THH0O THH1O THH2O TCBYP TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW TMRQ FTOG 1.1 2.2 2.0 1.9 2.0 0.9 1.0 0.6 2.3 3.4 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.7 19.8 166 Min -3 Max 1.6 2.7 2.9 2.5 2.4 2.5 1.5 2.7 3.3 2.0 2.8 0.26 0.32 2.1 2.1 1.0 1.9 1.7 1.6 1.7 0.8 0.9 0.5 2.1 3.0 0 0 0 0 0 0 0 0 2.8 2.8 2.8 3.2 17.3 179 Min -2 Max 1.5 2.4 2.6 2.2 2.1 2.2 1.3 2.3 2.9 1.8 2.6 0.23 0.28 1.9 1.9 0.9 1.7 1.6 1.4 1.6 0.7 0.8 0.5 1.9 2.7 0 0 0 0 0 0 0 0 2.5 2.5 2.5 2.8 15.0 200 Min -1 Max 1.3 2.2 2.2 2.0 1.9 2.0 1.1 2.0 2.5 1.5 2.4 0.20 0.25 1.6 1.6 0.8 1.6 1.4 1.2 1.4 0.6 0.7 0.4 1.7 2.5 0 0 0 0 0 0 0 0 2.3 2.3 2.3 2.7 14.0 217 Min

-09
Max 1.2 2.0 2.0 1.8 1.6 1.8 1.0 1.6 1.8 1.0 1.7 0.14 0.24 1.5 1.5

Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

Minimum GSR Pulse Width Delay from GSR input to any Q

Toggle Frequency (MHz) (for export control) Note 1: Preliminary specication only.

See page13 for TRRI values per device.

Note 1

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Single Port RAM

Write Operation

Speed Grade Size

-3 Min

-2 Max Min

-1 Max

-09 Units Min Max

Symbol Min Max

Address write cycle time (clock K period) 16x2 TWCS 32x1 TWCTS Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K Read Operation Address read cycle time Data Valid after address change (no Write Enable) Address setup time before clock K 16x2 TRC 32x1 TRCT 16x2 TILO 32x1 TIHO 16x2 TICK 32x1 TIHCK 16x2 TWPS 32x1 TWPTS 16x2 TASS 32x1 TASTS 16x2 TAHS 32x1 TAHTS 16x2 TDSS 32x1 TDSTS 16x2 TDHS 32x1 TDHTS 16x2 TWSS 32x1 TWSTS 16x2 TWHS 32x1 TWHTS 16x2 TWOS 32x1 TWOTS

9.0 9.0 4.5 4.5 2.2 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 6.8 8.1

8.4 8.4 4.2 4.2 2.0 2.0 0 0 1.9 2.3 0 0 1.8 1.7 0 0 6.3 7.5

7.7 7.7 3.9 3.9 1.7 1.7 0 0 1.7 2.1 0 0 1.6 1.5 0 0 5.8 6.9

7.4 7.4 3.7 3.7 1.7 1.7 0 0 1.7 2.1 0 0 1.6 1.5 0 0 5.8 6.9

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

4.5 6.5 1.6 2.7 1.3 2.3

3.1 5.5 1.5 2.4 1.1 2.0

2.6 3.8 1.3 2.2 1.0 1.8

2.6 3.8 1.2 2.0 0.8 1.6 Note 1

ns ns ns ns ns ns

Note 1: Preliminary specication only.

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March 30, 1998 (Version 1.5)

XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Dual Port RAM Write Operation

Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-3 Max Min

-2 Max

--1 Min

-09 Units

Max Min Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

9.0 4.5 2.5 0 2.5 0 1.8 0 7.8

8.4 4.2 2.0 0 2.3 0 1.7 0 7.3

7.7 3.9 1.7 0 2.0 0 1.6 0 6.7

7.4 3.7 1.7 0 2.0 0 1.6 0 6.7 Note 2

ns ns ns ns ns ns ns ns ns

Note 1: Timing for16 x1 RAM option is identical to16 x 2 RAM. Note 2: Preliminary specication only.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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March 30, 1998 (Version 1.5)

XC4000XL Pin-to-Pin Output Parameter Guidelines

XC4000XL Output Flip-Flop, Clock to Out

Speed Grade Description Symbol Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL All Devices Global Low Skew Clock to Output using OFF TICKOF -3 Max 7.7 8.3 8.6 9.0 9.4 9.8 10.3 10.7 11.3 12.2 6.9 7.2 7.4 7.6 7.8 8.1 8.5 9.0 9.9 10.8 3.0 -2 Max 6.7 7.2 7.5 7.9 8.2 8.5 9.0 9.3 9.7 10.5 6.1 6.2 6.4 6.5 6.7 7.0 7.3 7.8 8.6 9.4 2.5 -1 Max 5.8 6.2 6.5 6.8 7.1 7.4 7.8 8.3 8.5 9.5 5.5 5.5 5.6 5.9 5.9 6.1 6.4 6.8 7.5 8.5 2.0 -09 Max 5.4 5.8 6.1 6.4 6.7 7.0 7.4 7.9 8.1 9.0 5.1 5.2 5.2 5.5 5.5 5.7 5.9 6.5 6.9 7.8 1.7 Note 3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Global Early Clock to Output using OFF TICKEOF Values are for BUFGE #s 3, 4, 7, and 8. Add 1.4 ns for BUFGE #s 1, 2, 5, and 6.

For output SLOW option add

OFF = Output Flip Flop

TSLOW

Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads, see graph below. Note 3: Preliminary specication only.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Capacitive Load Factor

Delta Delay (ns)
Figure 1 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the specied output delay if the load capacitance is different than 50 pF. For example, if the actual load capacitance is 120 pF, add 2.5 ns to the specied delay. If the load capacitance is 20 pF, subtract 0.8 ns from the specied output delay. Figure 1 is usable over the specied operating conditions of voltage and temperature and is independent of the output slew rate control.

3 2 1 0 -1 -2 0 20 40 60 80 100 120 140 Capacitance (pF)

X8257

Figure 1: Delay Factor at Various Capacitive Loads

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XC4000XL Pin-to-Pin Input Parameter Guidelines

XC4000XL Global Low Skew Clock, Set-Up and Hold

Description Input Setup and Hold Times Using Global Low Skew Clock and IFF No Delay Symbol Speed Grade Device -3 Min -2 Min -1 Min -09 Min Units

TPSN/TPHN

Partial Delay

TPSP/TPHP

Full Delay

TPSD/TPHD

XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL

1.2 / 2.6 1.2 / 3.0 1.2 / 3.2 1.2 / 3.7 1.2 / 4.4 1.2 / 5.5 1.2 / 5.8 1.2 / 7.1 1.2 / 7.0 1.2 / 9.4 10. 5 / 0.0 11.1 / 0.0 6.1 / 0.0 11.9 / 0.0 12.3 / 0.0 6.4 / 1.0 13.1 / 0.0 11.9 / 0.0 6.7 / 1.2 12.9 / 0.0

1.1 / 2.2 1.1 / 2.6 1.1 / 2.8 1.1 / 3.2 1.1 / 3.8 1.1 / 4.8 1.1 / 5.0 1.1 / 6.2 1.1 / 6.1 1.1 / 8.2 9.1 / 0.0 9.7 / 0.0 5.3 / 0.0 10.3 / 0.0 10.7 / 0.0 5.6 / 1.0 11.4 / 0.0 10.3 / 0.0 5.8 / 1.2 11.2 / 0.0

0.9 / 2.0 0.9 / 2.3 0.9 / 2.4 0.9 / 2.8 0.9 / 3.3 0.9 / 4.1 0.9 / 4.4 0.9 / 5.4 0.9 / 5.3 0.9 / 7.1 7.9 / 0.0 8.4 / 0.0 4.6 / 0.0 9.0 / 0.0 9.3 / 0.0 4.8 / 1.0 9.9 / 0.0 9.0 / 0.0 5.1 / 1.2 9.8 / 0.0 6.6 / 0.0 6.8 / 0.0 5.6 / 0.0 6.6 / 0.0 7.0 / 0.0 5.8 / 0.0 8.0 / 0.0 8.4 / 0.0 6.0 / 0.0 9.6 / 0.0

0.8 / 1.7 0.8 / 2.0 0.8 / 2.1 0.8 / 2.4 0.8 / 2.9 0.8 / 3.6 0.8 / 3.8 0.8 / 4.7 0.8 / 4.6 0.8 / 6.2 6.9 / 0.0 7.3 / 0.0 4.0 / 0.0 7.8 / 0.0 8.1 / 0.0 4.2 / 1.0 8.6 / 0.0 7.8 / 0.0 4.4 / 1.2 8.5 / 0.0 5.6 / 0.0 5.8 / 0.0 4.8 / 0.0 6.2 / 0.0 6.4 / 0.0 5.3 / 0.0 6.8 / 0.0 7.0 / 0.0 5.5 / 0.0 8.4 / 0.0 Note 3

8.8 / 0.0 7.6 / 0.0 9.0 / 0.0 7.8 / 0.0 6.4 / 0.0 6.0 / 0.0 8.8 / 0.0 7.6 / 0.0 9.3 / 0.0 8.1 / 0.0 6. 6 / 0.0 6.2 / 0.0 10.6 / 0.0 9.2 / 0.0 11.2 / 0.0 9.7 / 0.0 6.8 / 0.0 6.4 / 0.0 12.7 / 0.0 11.0 / 0.0

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

IFF = Input Flip-Flop or Latch

Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. Note 2: * The XC4013XL, XC4036XL, and 4062XL have signicantly faster partial and full delay setup times than other devices. Note 3: Preliminary specication only.

March 30, 1998 (Version 1.5)

4-79

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay Global Early Clock and IFF Global Early Clock and FCL Symbol Speed Grade Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL -3 Min -2 Min -1 Min -09 Min

TPSEN/TPHEN TPFSEN/TPFHEN

1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 8.4 / 0.0 10.3 / 0.0 5.4 / 0.0 9.8 / 0.0 12.7 / 0.0 6.4 / 0.8 13.8 / 0.0 14.5 / 0.0 8.4 / 1.5 14.5 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0

1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5

0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6

0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7

Partial Delay Global Early Clock and IFF Global Early Clock and FCL

TPSEP/TPHEP TPFSEP/TPFHEP

7.9 / 0.0 7.4 / 0.0 7.2 / 0.0 9.0 / 0.0 7.8 / 0.0 7.4 / 0.0 4.9 / 0.0 4.4 / 0.0 4.3 / 0.0 9.3 / 0.0 8.8 / 0.0 8.5 / 0.0 11.0 / 0.0 9.6 / 0.0 9.3 / 0.0 5.9 / 0.8 5.4 / 0.8 5.0 / 0.8 12.0 / 0.0 10.4 / 0.0 10.2 / 0.0 12.7 / 0.0 11.0 / 0.0 10.7 / 0.0 7.9 / 1.5 7.4 / 1.5 6.8 / 1.5 12.7 / 0.0 11.0 / 0.0 10.8 / 0.0 9.4 / 0.0 8.2 / 0.0 7.1 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 10.4 / 0.0 9.1/ 0.0 7.9 / 0.0 11.0/ 0.0 9.5 / 0.0 8.3 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 12.0 / 0.0 10.5/ 0.0 9.1 / 0.0 12.3 / 0.0 10.7/ 0.0 9.3 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0 Note 3

Full Delay Global Early Clock and IFF

TPSED/TPHED

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch

Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. Note 2: * The XC4013XL, XC4036XL, and 4062XL have signicantly faster partial and full delay setup times than other devices. Note 3: Preliminary specication only.

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March 30, 1998 (Version 1.5)

XC4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Description Input Setup and Hold Times No Delay Global Early Clock and IFF Global Early Clock and FCL Symbol Speed Grade Device XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL XC4002XL XC4005XL XC4010XL XC4013XL* XC4020XL XC4028XL XC4036XL* XC4044XL XC4052XL XC4062XL* XC4085XL -3 Min -2 Min -1 Min -09 Min

TPSEN/TPHEN TPFSEN/TPFHEN

1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 9.0 / 0.0 11.9 / 0.0 6.4 / 0.0 10.8 / 0.0 14.0 / 0.0 7.0 / 0.0 14.6 / 0.0 16.4 / 0.0 9.0 / 0.8 16.7 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0

1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5 8.5 / 0.0 10.4 / 0.0 5.9 / 0.0 10.3 / 0.0 12.2 / 0.0 6.6 / 0.0 12.7 / 0.0 14.3 / 0.0 8.6 / 0.8 14.5 / 0.0

0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6

0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7

Partial Delay Global Early Clock and IFF Global Early Clock and FCL

TPSEP/TPHEP TPFSEP/TPFHEP

8.0 / 0.0 7.5 / 0.0 9.0 / 0.0 8.0 / 0.0 5.4 / 0.0 4.9 / 0.0 9.8 / 0.0 9.0 / 0.0 10.6 / 0.0 9.8 / 0.0 6.2 / 0.0 5.2 / 0.0 11.0 / 0.0 10.8 / 0.0 12.4 / 0.0 11.4 / 0.0 8.2 / 0.8 7.0 / 0.8 12.6 / 0.0 11.6 / 0.0

Full Delay Global Early Clock and IFF

TPSED/TPHED

IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch

9.4 / 0.0 8.2 / 0.0 7.1 / 0.0 9.0 / 0.0 7.8 / 0.0 6.8 / 0.0 8.7 / 0.0 7.6 / 0.0 6.6 / 0.0 10.4 / 0.0 9.1 / 0.0 7.9 / 0.0 11.0 / 0.0 9.5 / 0.0 8.3 / 0.0 10.6 / 0.0 9.2 / 0.0 8.0 / 0.0 12.0 / 0.0 10.5 / 0.0 9.1 / 0.0 12.3 / 0.0 10.7 / 0.0 9.3 / 0.0 11.4 / 0.0 9.9 / 0.0 8.6 / 0.0 15.6 / 0.0 13.6 / 0.0 11.8 / 0.0 Note 3

Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. Note 2: * The XC4013XL, XC4036XL, and 4062XL have signicantly faster partial and full delay setup times than other devices. Note 3: Preliminary specication only.

March 30, 1998 (Version 1.5)

4-81

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000XL IOB Input Switching Characteristic Guidelines

ns ns

TPICK TPICKF TPOCK

All devices All devices All devices All devices

1.7 2.3 0.7 0 19.8 11.3 13.9 15.9 18.6 20.5 22.5 25.1 27.2 29.1 34.4 Max 1.6 2.6 3.1 1.8 1.9 3.6

1.5 2.1 0.6 0 17.3 9.8 12.1 13.8 16.1 17.9 19.6 21.9 23.6 25.3 29.9 Max 1.4 2.2 2.7 1.5 1.7 3.1

1.3 1.8 0.5 0 15.0 8.5 10.5 12.0 14.0 15.5 17.0 19.0 20.5 22.0 26.0 Max 1.2 1.9 2.4 1.3 1.4 2.7

1.3 1.7 0.5 0 14.0 8.1 10.0 11.4 13.3 14.3 16.2 18.1 19.5 20.9 24.7 Max 1.1 1.8 2.2 1.2 1.3 2.6 Note 1

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

TMRW TRRI

All devices XC4002XL XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL All devices All devices All devices All devices All devices All devices

Propagation Delays Pad to I1, I2 Pad to I1, I2 via transparent input latch, no delay Pad to I1, I2 via transparent FCL and input latch, no delay Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low) FCL Enable (OK) active edge to I1, I2 (via transparent standard input latch)
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Note 1: Preliminary specication only.

TPID TPLI TPFLI TIKRI TIKLI TOKLI

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March 30, 1998 (Version 1.5)

XC4000XL IOB Output Switching Characteristic Guidelines

-2 Max Min Max Min

-1 Max

-09 Min Max

Symbol

Min

Units

TCH TCL TOKPOF TOPF TTSHZ TTSONF TOFPF TOKFPF TOOK TOKO TECOK TOKEC TMRW TRPO

3.0 3.0

2.8 2.8

2.5 2.5

2.3 2.3

ns ns

5.0 4.1 4.4 4.1 5.5 5.1

4.4 3.6 3.8 3.6 4.8 4.5

3.8 3.1 3.3 3.1 4.2 3.9

3.5 3.0 3.3 3.0 4.0 3.7

ns ns ns ns ns ns

0.5 0.0 0.0 0.3

0.4 0.0 0.0 0.2

0.3 0.0 0.0 0.1

0.3 0.0 0.0 0.0

ns ns ns ns

19.8

17.3

15.0

14.0

ns ns ns ns ns ns ns ns ns ns ns ns

15.9 18.5 20.5 23.2 25.1 27.1 29.7 31.7 33.7 39.0

13.8 16.1 17.8 20.1 21.9 23.6 25.9 27.6 29.3 33.9

12.0 14.0 15.5 17.5 19.0 20.5 22.5 24.0 25.5 29.5

11.4 13.3 14.7 16.6 17.6 19.4 21.4 22.8 24.2 28.0

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX Switching Characteristics

Denition of Terms
In the following tables, some specications may be designated as Advance or Preliminary. These terms are dened as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specications not identied as either Advance or Preliminary are to be considered Final. All specications subject to change without notice.

XC4000EX Absolute Maximum Ratings

Symbol VCC VIN VTS VCCt TSTG TSOL TJ Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Longest Supply Voltage Rise Time from 1 V to 4 V Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Description Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 50 -65 to +150 +260 +150 +125 Units V V V ms C C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC4000EX Recommended Operating Conditions

Symbol VCC VIH VIL TIN Description Supply voltage relative to GND, TJ = 0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C High-level input voltage Commercial Industrial TTL inputs CMOS inputs Low-level input voltage TTL inputs CMOS inputs Input signal transition time Min 4.75 4.5 2.0 70% 0 0 Max 5.25 5.5 VCC 100% 0.8 20% 250 Units V V V VCC V VCC ns

Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V. Note 3: All timing parameters are specied for Commercial temperature range only.

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March 30, 1998 (Version 1.5)

XC4000EX DC Characteristics Over Recommended Operating Conditions

Symbol VOH VOL VDR ICCO IL CIN IRPU IRPD IRLL Pad pull-up (when selected) @ Vin = 0 V (sample tested) Pad pull-down (when selected) @ Vin = 5.5 V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low Description High-level output voltage @ IOH = -4.0 mA, VCC min High-level output voltage @ IOH = -1.0 mA Low-level output voltage @ IOL = 12.0 mA, VCC min (Note 1) TTL outputs CMOS outputs TTL outputs CMOS outputs 3.0 25 -10 BGA, SBGA, PQ, HQ, MQ packages PGA packages 0.02 0.02 0.3 +10 10 16 0.25 0.25 2.0 Min 2.4 VCC-0.5 0.4 0.4 Max Units V V V V V mA A pF pF mA mA mA

Data Retention Supply Voltage (below which conguration data may be lost) Quiescent FPGA supply current (Note 2) Input or output leakage current Input capacitance (sample tested)

Note 1: With up to 64 pins simultaneously sinking 12 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND.

XC4000EX Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade Description Symbol Device XC4028EX XC4036EX XC4028EX XC4036EX From pad through Global Low Skew buffer, TGLS to any clock K From pad through Global Early buffer, to any clock K in same quadrant TGE -4 Max 9.2 9.8 5.7 5.9 -3 Max 7.5 7.9 4.4 4.6 -2 Max 6.4 7.1 4.2 4.4 Units ns ns ns ns

March 30, 1998 (Version 1.5)

4-85

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX Longline and Wide Decoder Timing Guidelines

XC4000EX Horizontal Longline Switching Characteristic Guidelines

Speed Grade Description TBUF driving a Horizontal Longline I going High or Low to Horizontal Longline going High TIO1 or Low, while T is Low. Buffer is constantly active. T going Low to Horizontal Longline going from resis- TON tive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. T going High to Horizontal Longline going from Low to TPU2 High, pulled up by two resistors. (Note 1) TBUF driving Half a Horizontal Longline I going High or Low to half of a Horizontal Longline go- THIO1 ing High or Low, while T is Low. Buffer is constantly active. T going Low to half of a Horizontal Longline going from THON resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. T going High to half of a Horizontal Longline going THPU4 from Low to High, pulled up by four resistors. (Note 1) XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX 6.3 7.3 7.2 8.2 5.6 6.0 6.4 6.8 4.6 5.7 5.4 6.5 ns ns ns ns ns ns XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX 13.7 16.5 14.7 17.4 11.3 13.6 12.1 14.4 10.9 13.2 11.7 14.0 ns ns ns ns ns ns Symbol Device -4 Max -3 Max -2 Max Units

Note 1: These values include a minimum load of one output, spaced as far as possible from the activated pullup(s). Use the statictiming analyzer to determine the delay for each destination.

XC4000EX Wide Decoder Switching Characteristic Guidelines

Speed Grade Description Full length, two pull-ups, inputs from IOB I-pins Full length, two pull-ups, inputs from internal logic Half length, two pull-ups, inputs from IOB I-pins Half length, two pull-ups, inputs from internal logic Symbol TWAF2 TWAF2L TWAO2 TWAO2L Device XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX XC4028EX XC4036EX -4 Max -3 Max -2 Max Units ns ns ns ns ns ns ns ns

Note 1: These delays are specied from the decoder input to the decoder output.

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March 30, 1998 (Version 1.5)

XC4000EX CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devicees unless otherwise noted.
Speed Grade Description Symbol Combinatorial Delays TILO F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs TIHO F/G inputs via transparent latch to Q outputs TITO C inputs via SR/H0 via H to X/Y outputs THH0O C inputs via H1 via H to X/Y outputs THH1O C inputs via DIN/H2 via H to X/Y outputs THH2O C inputs via EC, DIN/H2 to YQ, XQ output (bypass) TCBYP CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Carry Net Delay, COUT to CIN Sequential Delays Clock K to Flip-Flop outputs Q Clock K to Latch outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H Hold Time after Clock K F/G inputs F/G inputs via H C inputs via SR/H0 through H C inputs via H1 through H C inputs via DIN/H2 through H C inputs via DIN/H2 C inputs via EC C inputs via SR, going Low (inactive) Clock Clock High time Clock Low time Set/Reset Direct Width (High) Delay from C inputs via S/R, going High to Q Global Set/Reset Minimum GSR Pulse Width Delay from GSR input to any Q (XC4028EX) Delay from GSR input to any Q (XC4036EX) Toggle Frequency ) (for export control purposes) TOPCY TASCY TINCY TSUM TBYP TNET TCKO TCKLO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK TCKI TCKIH TCKHH0 TCKHH1 TCKHH2 TCKDI TCKEC TCKR TCH TCL TRPW TRIO TMRW TMRQ TMRQ FTOG 1.3 3.0 2.8 2.2 2.8 1.2 1.2 0.8 2.2 3.9 0 0 0 0 0 0 0 0 3.5 3.5 3.5 4.5 13.0 22.8 24.0 143 -4 Min Max 2.2 3.8 3.2 3.6 3.0 3.6 2.0 2.5 4.1 1.9 3.0 0.60 0.18 2.2 2.2 1.1 2.5 2.3 1.8 2.3 0.9 1.0 0.7 1.8 3.2 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.8 11.5 19.0 21.0 166 Min -3 Max 1.8 3.2 2.7 3.0 2.5 3.0 1.6 2.2 3.6 1.6 2.6 0.50 0.15 1.9 1.9 1.1 2.2 2.0 1.8 2.0 0.9 0.9 0.6 2.1 3.2 0 0 0 0 0 0 0 0 3.0 3.0 3.0 3.6 11.5 19.0 21.0 166 Min -2 Max 1.5 2.7 2.5 2.5 2.3 2.5 1.4 1.9 3.1 1.4 2.2 0.40 0.15 1.7 1.7 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz

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4-87

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines

Single Port RAM

Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-4 Max Min

-3 Max Min

-2 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

11.0 11.0 5.5 5.5 2.7 2.6 0 0 2.4 2.9 0 0 2.3 2.1 0 0 8.2 10.1

9.0 9.0 4.5 4.5 2.3 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 6.8 8.4

9.0 9.0 4.5 4.5 2.2 2.2 0 0 2.0 2.5 0 0 2.0 1.8 0 0 6.8 8.2

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Note 2: Applicable Read timing specications are identical to Level-Sensitive Read timing.

Dual-Port RAM
Write Operation Address write cycle time (clock K period) Clock K pulse width (active edge) Address setup time before clock K Address hold time after clock K DIN setup time before clock K DIN hold time after clock K WE setup time before clock K WE hold time after clock K Data valid after clock K

Speed Grade Size Symbol Min

-4 Max Min

-3 Max

-2 Units Min Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

11.0 5.5 3.1 0 2.9 0 2.1 0 9.4

9.0 4.5 2.6 0 2.5 0 1.8 0 7.8

9.0 4.5 2.5 0 2.5 0 1.8 0 7.8

ns ns ns ns ns ns ns ns ns

Note 1: Applicable Read timing specications are identical to Level-Sensitive Read timing.

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XC4000EX CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000EX CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX CLB RAM Asynchronous (Level-Sensitive) Write and Read Operation Guidelines
Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000EX devices unless otherwise noted. Speed Grade Description Write Operation Address write cycle time Write Enable pulse width (High) Address setup time before WE Address hold time after end of WE DIN setup time before end of WE DIN hold time after end of WE Read Operation Address read cycle time Data valid after address change (no Write Enable) 16x2 32x1 16x2 32x1 TRC TRCT TILO TIHO 4.5 6.5 2.2 3.8 3.1 5.5 1.8 3.2 3.1 5.5 1.5 2.7 ns ns ns ns 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 TWC TWCT TWP TWPT TAS TAST TAH TAHT TDS TDST TDH TDHT 10.6 10.6 5.3 5.3 2.8 2.9 1.7 1.7 1.1 1.1 6.6 6.6 9.2 9.2 4.6 4.6 2.4 2.5 1.4 1.4 0.9 0.9 5.7 5.7 8.0 8.0 4.0 4.0 2.0 2.0 1.4 1.4 0.8 0.8 5.0 5.0 ns ns ns ns ns ns ns ns ns ns ns ns Size Symbol Min -4 Max Min -3 Max Min -2 Units Max

Read Operation, Clocking Data into Flip-Flop Address setup time before clock K Read During Write Data valid after WE goes active (DIN stable before WE) Data valid after DIN (DIN changes during WE) 16x2 32x1 16x2 32x1 TWO TWOT TDO TDOT 6.5 7.4 7.7 8.2 5.7 6.5 6.7 7.2 4.9 5.6 5.8 6.2 ns ns ns ns 16x2 32x1 TICK TIHCK 1.5 3.2 1.2 2.6 1.2 2.6 ns ns

Read During Write, Clocking Data into Flip-Flop WE setup time before clock K Data setup time before clock K 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK TDCKT 7.1 9.2 5.9 8.4 6.2 8.1 5.2 7.4 5.5 7.0 4.6 6.4 ns ns ns ns

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

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XC4000EX CLB RAM Asynchronous (Level-Sensitive) Timing Characteristics

T WC ADDRESS

WRITE
TAS WRITE ENABLE T DS T DH T WP T AH

DATA IN

REQUIRED

READ WITHOUT WRITE

T ILO

X,Y OUTPUTS

VALID

READ, CLOCKING DATA INTO FLIP-FLOP

T ICK CLOCK T CH

T CKO XQ, YQ OUTPUTS VALID (OLD) VALID (NEW)

READ DURING WRITE

WRITE ENABLE

T WP

T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID VALID

DATA IN (changing during WE)

OLD T WO T DO VALID (OLD)

NEW

X, Y OUTPUTS

VALID (PREVIOUS)

VALID (NEW)

READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP

T WP WRITE ENABLE T WCK T DCK DATA IN

CLOCK T CKO

XQ, YQ OUTPUTS
X2640

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX Pin-to-Pin Output Parameter Guidelines

XC4000EX Output Flip-Flop, Clock to Out

Speed Grade Description Global Low Skew Clock to TTL Output (fast) using OFF Symbol TICKOF Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Max 16.6 17.2 13.1 13.3 -3 Max 13.7 14.1 10.6 10.8 -2 Max 12.4 13.1 10.2 10.4 Units ns ns ns ns

Global Early Clock to TTL Output (fast) using TICKEOF OFF OFF = Output Flip Flop

XC4000EX Output MUX, Clock to Out

Speed Grade Description Global Low Skew Clock to TTL Output (fast) using OMUX Global Early Clock to TTL Output (fast) using OMUX OMUX = Output MUX
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. Note 2: Output timing is measured at TTL threshold with 50 pF external capacitive load. Note 3: Set-up time is measured with the fastest route and the lightest load. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions.

-4 Max 15.9 16.5 12.4 12.6

-3 Max 13.1 13.5 10.0 10.2

-2 Max 11.8 12.5 9.6 9.8

Symbol TPFPF TPEFPF

Device XC4028EX XC4036EX XC4028EX XC4036EX

Units ns ns ns ns

XC4000EX Output Level and Slew Rate Adjustments

The following table must be used to adjust output parameters and output switching characteristics. Speed Grade Symbol Device TTTLOF All Devices TTTLO TCMOSOF TCMOSO All Devices All Devices All Devices -4 Max 0 2.9 1.0 3.6 -3 Max 0 2.4 0.8 3.0 -2 Max 0 2.4 0.8 3.0 Units ns ns ns ns

Description For TTL output FAST add For TTL output SLOW add For CMOS FAST output add For CMOS SLOW output add

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XC4000EX Pin-to-Pin Input Parameter Guidelines

XC4000EX Global Low Skew Clock, Set-Up and Hold

Description Input Setup Time, using Global Low Skew clock and IFF (full delay) Input Hold Time, using Global Low Skew clock and IFF (full delay) IFF = Flip-Flop or Latch Symbol TPSD TPHD Speed Grade Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Min 8.0 8.0 0 0 -3 Min 6.8 6.8 0 0 -2 Min 6.8 6.8 0 0 Units ns ns ns ns

XC4000EX Global Early Clock, Set-Up and Hold for IFF

Description Input Setup Time, using Global Early clock and IFF (partial delay) Input Hold Time, using Global Early clock and IFF (partial delay) IFF = Flip-Flop or Latch Symbol TPSEP TPHEP Speed Grade Device XC4028EX XC4036EX XC4028EX XC4036EX -4 Min 6.5 6.5 0 0 -3 Min 5.4 5.4 0 0 -2 Min 5.4 5.4 0 0 Units ns ns ns ns

Note 1: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.6 ns for BUFGE #s 1, 2, 5 and 6.

XC4000EX Global Early Clock, Set-Up and Hold for FCL

Description Input Setup Time, using Global Early clock and FCL (partial delay) Input Hold Time, using Global Early clock and FCL (partial delay) FCL = Fast Capture Latch Speed Grade Device XC4028EX XC4036EX TPFHEP XC4028EX XC4036EX Symbol TPFSEP -4 Min 3.4 4.4 0 0 -3 Min 3.4 4.2 0 0 -2 Min 3.4 4.2 0 0 Units ns ns ns ns

Note 1: For CMOS input levels, see the XC4000EX Input Threshold Adjustments on page -93. Setup time is measured with the fastest route and the lightest load. Use the static timing analyzer to determine the setup time Note 2: under given design conditions. Hold time is measured using the farthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer to determine the setup and hold times under given design conditions. Note 3: Set-up parameters are for BUFGE #s 3, 4, 7 and 8. Add 1.2 ns for BUFGE #s 1, 2, 5 and 6.

XC4000EX Input Threshold Adjustments

The following table must be used to adjust input parameters and input switching characteristics. Speed Grade Symbol Device TTTLI All Devices TCMOSI All Devices -4 Max 0 0.3 -3 Max 0 0.2 -2 Max 0 0.2 Units ns ns

Description For TTL input add For CMOS input add

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4-93

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX IOB Input Switching Characteristic Guidelines

TPID TPLI TPPLI TPDLI

Pad to I1, I2 via transparent FCL and input latch, TPFLI no delay Pad to I1, I2 via transparent FCL and input latch, TPPFLI partial delay Propagation Delays Clock (IK) to I1, I2 (flip-flop) TIKRI Clock (IK) to I1, I2 (latch enable, active Low) TIKLI FCL Enable (OK) active edge to I1, I2 TOKLI (via transparent standard input latch) Global Set/Reset Minimum GSR Pulse Width TMRW Delay from GSR input to any Q TRRI Delay from GSR input to any Q TRRI FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch

All devices All devices XC4028EX XC4036EX XC4028EX XC4036EX All devices XC4028EX XC4036EX All devices All devices All devices

ns ns ns ns ns ns ns ns ns ns ns ns

All devices XC4028EX XC4036EX

13.0 22.8 24.0

11.5 19.0 21.0

ns ns ns

Note 1: For CMOS input levels, see the XC4000EX Input Threshold Adjustments on page -93. Note 2: For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Set-up and Hold tables on page -93. .

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XC4000EX IOB Input Switching Characteristic Guidelines (Continued)

ns ns ns ns ns ns ns ns ns ns ns ns

TECIK

TIKPI TIKPIP TIKPID

All devices All devices All devices

0 0 0

ns ns ns

TIKFPI TIKFPIP TIKFPID TIKEC TIKECP TIKECD TOKPI TOKPIP

All devices All devices All devices All devices All devices All devices All devices All devices

0 0 0 0 0 0 0 0

ns ns ns ns ns ns ns ns

March 30, 1998 (Version 1.5)

4-95

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000EX IOB Output Switching Characteristic Guidelines

Note 1: Output timing is measured at TTL threshold, with 35pF external capacitive loads. Note 2: For CMOS output levels, see the XC4000EX Output Level and Slew Rate Adjustments on page -92.

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March 30, 1998 (Version 1.5)

XC4000E Switching Characteristics

Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked:

XC4000E Absolute Maximum Ratings

Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage relative to GND (Note 1) Voltage applied to 3-state output (Note 1) Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) Junction temperature Ceramic packages Plastic packages Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +150 +125 Units V V V C C C C

Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this over- or undershoot lasts less than 20 ns. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

XC4000E Recommended Operating Conditions

Symbol VCC Description Supply voltage relative to GND, TJ = -0 C to +85C Supply voltage relative to GND, TJ = -40C to +100C Supply voltage relative to GND, TC = -55C to +125C High-level input voltage Low-level input voltage Input signal transition time Commercial Industrial Military TTL inputs CMOS inputs TTL inputs CMOS inputs Min 4.75 4.5 4.5 2.0 70% 0 0 Max 5.25 5.5 5.5 VCC 100% 0.8 20% 250 Units V V V V VCC V VCC ns

VIH VIL TIN

Note 1: At junction temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35% per C. Note 2: Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.

1. Notwithstanding the denition of the above terms, all specications are subject to change without notice.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E DC Characteristics Over Operating Conditions

Symbol VOH VOL ICCO Description High-level output voltage @ IOH = -4.0mA, VCC min High-level output voltage @ IOH = -1.0mA, VCC min Low-level output voltage @ IOL = 12.0mA, VCC min (Note 1) Quiescent FPGA supply current (Note 2) TTL outputs CMOS outputs TTL outputs CMOS outputs Commercial Industrial Military PQFP and MQFP packages Other packages -0.02 0.2 Min 2.4 VCC-0.5 Max Units V V V V mA mA mA A pF pF mA mA

IL CIN

Input or output leakage current Input capacitance (sample tested)

-10

0.4 0.4 3.0 6.0 6.0 +10 10 16 -0.25 2.5

IRIN* IRLL*

Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal Longline pull-up (when selected) @ logic Low

Note 1: With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. Note 2: With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA congured with a Development system Tie option. Note 3: *Characterized Only.

XC4000E Global Buffer Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB ip-ops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature) Speed Grade Device XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E -4 Max 7.0 7.0 7.5 8.0 11.0 11.5 12.0 12.5 7.5 7.5 8.0 8.5 11.5 12.0 12.5 13.0 -3 Max 4.7 4.7 5.3 6.1 6.3 6.8 7.0 7.2 5.2 5.2 5.8 6.6 6.8 7.3 7.5 7.7 -2 Max 4.0 4.3 5.2 5.2 5.4 5.8 6.4 6.9 4.4 4.7 5.6 5.6 5.8 6.2 6.7 7.2 -1 Max 3.5 3.8 4.6 4.6 4.8 5.2 6.0 4.0 4.3 5.1 5.1 5.3 5.7 6.5 Preliminary Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Description From pad through Primary buffer, to any clock K

Symbol TPG

From pad through Secondary buffer, to any clock K

TSG

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March 30, 1998 (Version 1.5)

XC4000E Horizontal Longline Switching Characteristic Guidelines

Description
TBUF driving a Horizontal Longline (LL):

-4 Max
5.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 5.0 6.0 7.8 8.1 10.5 11.0 12.0 12.0 5.5 7.0 7.5 8.0 8.5 8.7 11.0 11.0 1.8 20.0 23.0 25.0 27.0 29.0 32.0 35.0 42.0 9.0 10.0 11.5 12.5 13.5 15.0 16.0 18.0

-3 Max
4.2 5.0 5.9 6.3 6.4 7.2 8.2 9.1 4.2 5.3 6.4 6.8 6.9 7.7 8.7 9.6 4.6 6.0 6.7 7.1 7.3 7.5 8.4 8.4 1.5 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 7.0 8.0 9.0 10.0 11.0 13.0 14.8 16.5

-2 Max
3.4 4.0 4.7 5.0 5.1 5.7 7.3 7.3 3.6 4.5 5.4 5.8 5.9 6.5 8.7 9.6 3.9 5.7 5.7 6.0 6.2 7.0 7.1 7.1 1.3 14.0 16.0 18.0 20.0 22.0 26.0 32.5 39.1 6.0 6.8 7.7 8.5 9.4 11.7 14.8 16.5

-1 Max
2.9 3.4 4.0 4.3 4.4 4.9 5.6 3.1 3.8 4.6 4.9 5.0 5.5 7.4 3.5 4.7 4.9 5.2 5.4 6.2 6.3 1.1 12.0 14.0 16.0 16.0 18.0 21.0 26.0 5.4 5.8 6.5 7.5 8.0 9.4 10.5 Preliminary

Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

I going High or Low to LL going High or Low, while T is Low. Buffer is constantly active. (Note1)

I going Low to LL going from resistive pull-up High to active Low. TBUF configured as open-drain. (Note1) T going Low to LL going from resistive pull-up or floating High to active Low. TBUF configured as open-drain or active buffer with I = Low. (Note1) T going High to TBUF going inactive, not driving LL T going High to LL going from Low to High, pulled up by a single resistor. (Note 1)

TIO2

TON

TOFF TPUS

T going High to LL going from Low to High, pulled up by two resistors. (Note1)

TPUF

Note 1: These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E Wide Decoder Switching Characteristic Guidelines

Description Full length, both pull-ups, inputs from IOB I-pins

Symbol TWAF

Full length, both pull-ups, inputs from internal logic

Half length, one pull-up, inputs from IOB I-pins

Half length, one pull-up, inputs from internal logic

Note 1: These delays are specied from the decoder input to the decoder output. Note 2: Fewer than the specied number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.

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March 30, 1998 (Version 1.5)

XC4000E CLB Switching Characteristic Guidelines

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specic, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless otherwise noted. Speed Grade Description Combinatorial Delays F/G inputs to X/Y outputs F/G inputs via H to X/Y outputs C inputs via SR through H to X/Y outputs C inputs via H to X/Y outputs C inputs via DIN through H to X/Y outputs CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to COUT Add/Subtract input (F3) to COUT Initialization inputs (F1, F3) to COUT CIN through function generators to X/Y outputs CIN to COUT, bypass function generators Sequential Delays Clock K to outputs Q Setup Time before Clock K F/G inputs F/G inputs via H C inputs via H0 through H C inputs via H1 through H C inputs via H2 through H C inputs via DIN C inputs via EC C inputs via S/R, going Low (inactive) CIN input via F/G CIN input via F/G and H -4 Symbol TILO TIHO THH0O THH1O THH2O TOPCY TASCY TINCY TSUM TBYP TCKO TICK TIHCK THH0CK THH1CK THH2CK TDICK TECCK TRCK TCCK TCHCK 4.0 6.1 4.5 5.0 4.8 3.0 4.0 4.2 2.5 4.2 Min Max 2.7 4.7 4.1 3.7 4.5 3.2 5.5 1.7 3.8 1.0 3.7 3.0 4.6 3.6 4.1 3.8 2.4 3.0 4.0 2.1 3.5 Min -3 Max 2.0 4.3 3.3 3.6 3.6 2.6 4.4 1.7 3.3 0.7 2.8 2.4 3.9 3.5 3.3 3.7 2.0 2.6 4.0 Min -2 Max 1.6 2.7 2.4 2.2 2.6 2.1 3.7 1.4 2.6 0.6 2.8 1.8 2.8 2.4 2.1 2.5 1.0 2.0 1.5 Min -1 Max 1.3 2.2 1.9 1.6 1.9 1.7 2.5 1.2 1.8 0.5 1.9 Units

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Preliminary

March 30, 1998 (Version 1.5)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E CLB Switching Characteristic Guidelines (continued)

ns ns ns ns ns ns ns ns ns ns ns ns

13.0 23.0

11.5 18.7

11.5 17.4

10.0 15.0

ns ns

111

125

166 Preliminary

MHz

Note 1: Timing is based on the XC4005E. For other devices see the static timing analyzer. Note 2: Export Control Max. ip-op toggle rate.

4-102

March 30, 1998 (Version 1.5)

XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines

Single Port RAM

Speed Grade Size Symbol Min

-4 Max Min

-3 Max Min

-2 Max Min

-1 Units Max

16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1 16x2 32x1

TWCS TWCTS TWPS TWPTS TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS TWOS TWOTS

15.0 15.0 7.5 7.5 2.8 2.8 0 0 3.5 2.5 0 0 2.2 2.2 0 0 10.3 11.6 1 ms 1 ms

14.4 14.4 7.2 7.2 2.4 2.4 0 0 3.2 1.9 0 0 2.0 2.0 0 0 8.8 10.3 1 ms 1 ms

11.6 11.6 5.8 5.8 2.0 2.0 0 0 2.7 1.7 0 0 1.6 1.6 0 0 7.9 9.3 1 ms 1 ms

8.0 8.0 4.0 4.0 1.5 1.5 0 0 1.5 1.5 0 0 1.5 1.5 0 0 6.5 7.0 Preliminary

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing. Note 2: Applicable Read timing specications are identical to Level-Sensitive Read timing.

Speed Grade Size Symbol Min

-4 Max Min

-3 Max Min

-2 Max Min

-1 Units Max

16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1

TWCDS TWPDS TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS

15.0 7.5 7.5 2.8 0 2.2 0 2.2 0.3

1 ms

14.4 7.2 2.5 0 2.5 0 1.8 0

1 ms

10.0

7.8

11.6 5.8 1 ms 2.1 0 1.6 0 1.6 0 7.0

8.0 4.0 1.5 0 1.5 0 1.5 0 6.5 Preliminary

ns ns ns ns ns ns ns ns ns

Note 1: Applicable Read timing specications are identical to Level-Sensitive Read timing.

March 30, 1998 (Version 1.5)

4-103

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E CLB RAM Synchronous (Edge-Triggered) Write Timing

TWPS WCLK (K) TWSS WE TDSS DATA IN TASS ADDRESS TILO TAHS TDHS TWHS

TILO

TWOS OLD

DATA OUT

NEW
X6461

XC4000E CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing

TWPDS WCLK (K) TWSDS WE TDSDS DATA IN TASDS ADDRESS TILO TWODS DATA OUT OLD NEW
X6474

TWHDS

TDHDS

TAHDS

TILO

4-104

March 30, 1998 (Version 1.5)

XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines

Read Operation, Clocking Data into Flip-Flop Address setup time before clock K Read During Write Data valid after WE goes active (DIN stable before WE) Data valid after DIN (DIN changes during WE) 16x2 32x1 16x2 32x1 TWO TWOT TDO TDOT 10.0 12.0 9.0 11.0 6.0 7.3 6.6 7.6 4.9 5.6 5.8 6.2 4.9 5.6 5.8 6.2 ns ns ns ns 16x2 32x1 TICK TIHCK 4.0 6.1 3.0 4.6 2.4 3.9 2.4 3.9 ns ns

Read During Write, Clocking Data into Flip-Flop WE setup time before clock K Data setup time before clock K 16x2 32x1 16x2 32x1 TWCK TWCKT TDCK TDCKT 8.0 9.6 7.0 8.0 6.0 6.8 5.2 6.2 5.1 5.8 4.4 5.3 5.1 5.8 4.4 5.3 Preliminary
Note 1: Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

ns ns ns ns

March 30, 1998 (Version 1.5)

4-105

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E CLB Level-Sensitive RAM Timing Characteristics

T WC ADDRESS

WRITE
TAS WRITE ENABLE T DS T DH T WP T AH

DATA IN

REQUIRED

READ WITHOUT WRITE

T ILO

X,Y OUTPUTS

VALID

READ, CLOCKING DATA INTO FLIP-FLOP

T ICK CLOCK T CH

T CKO XQ, YQ OUTPUTS VALID (OLD) VALID (NEW)

READ DURING WRITE

WRITE ENABLE

T WP

T DH DATA IN (stable during WE) T WO X, Y OUTPUTS VALID VALID

DATA IN (changing during WE)

OLD T WO T DO VALID (OLD)

NEW

X, Y OUTPUTS

VALID (PREVIOUS)

VALID (NEW)

READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP

T WP WRITE ENABLE T WCK T DCK DATA IN

CLOCK T CKO

XQ, YQ OUTPUTS
X2640

4-106

March 30, 1998 (Version 1.5)

XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)

Testing of switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specic, more precise, and worst-case guaranteed data, reecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values apply to all XC4000E devices unless otherwise noted. Speed Grade Symbol Device XC4003E TICKOF
XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E

-4
12.5 14.0 14.5 15.0 16.0 16.5 17.0 17.0 16.5 18.0 18.5 19.0 20.0 20.5 21.0 21.0 2.5 2.0 1.9 1.4 1.0 0.5 0 0 4.0 4.6 5.0 6.0 6.0 7.0 7.5 8.0 8.5 8.5 8.5 8.5 8.5 8.5 9.5 9.5 0 0 0 0 0 0 0 0

-3
10.2 10.7 10.7 10.8 10.9 11.0 11.0 12.6 14.0 14.7 14.7 14.8 14.9 15.0 15.1 15.3 2.3 1.2 1.0 0.6 0.2 0 0 0 4.0 4.5 4.7 5.1 5.5 6.5 6.7 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.6 0 0 0 0 0 0 0 0

-2
8.7 9.1 9.1 9.2 9.3 9.4 10.2 10.8 11.5 12.0 12.0 12.1 12.2 12.8 12.8 13.0 2.3 1.2 1.0 0.6 0.2 0 0 0 4.0 4.5 4.7 5.1 5.5 5.5 5.7 5.9 6.0 6.0 6.0 6.0 6.0 6.0 6.8 6.8 0 0 0 0 0 0 0 0

-1
5.8 6.2 6.4 6.6 6.8 7.2 7.4 7.8 8.2 8.4 8.6 8.8 9.2 9.4 1.5 0.8 0.6 0.2 0 0 0 1.5 2.0 2.0 2.5 2.5 3.0 3.5 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 0 0 0 0 0 0

Description Global Clock to Output (fast) using OFF

TPG Global Clock-to-Output Delay OFF

Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

. . . . .
X3202

(Max)

Global Clock to Output (slew-limited) using OFF

TPG Global Clock-to-Output Delay OFF

TICKO

. . . . .
X3202

(Max)

Input Setup Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPSUF

(Min)

X3201

Input Hold Time, using IFF (no delay)

D Input Set - Up & Hold Time IFF TPG

TPHF

(Min)

X3201

Input Setup Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPSU

(Min)

X3201

Input Hold Time, using IFF (with delay)

D Input Set - Up & Hold Time IFF TPG

TPH

(Min)

X3201

OFF = Output Flip-Flop

IFF = Input Flip-Flop or Latch

Preliminary

March 30, 1998 (Version 1.5)

4-107

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E IOB Input Switching Characteristic Guidelines

Description
Propagation Delays (TTL Inputs)

Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay

TPID TPLI TPDLI

All devices All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices All devices XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E All devices All devices All devices All devices 0 0 1.5 0

3.0 4.8 10.4 10.8 10.8 10.8 11.0 11.4 13.8 13.8 5.5 8.8 16.5 16.5 16.8 17.3 17.5 18.0 20.8 20.8 5.6 6.2 0 0 1.5 0

2.5 3.6 9.3 9.6 10.2 10.6 10.8 11.2 12.4 13.7 4.1 6.8 12.4 13.2 13.4 13.8 14.0 14.4 15.6 15.6 2.8 4.0 0 0 0.9 0

2.0 3.6 6.9 7.4 8.1 8.2 8.3 9.8 11.5 12.4 3.7 6.2 11.0 11.9 12.1 12.4 12.6 13.0 14.0 14.0 2.8 3.9 0 0

1.4 2.8 6.4 6.5 6.9 7.0 7.3 8.4 9.0 1.9 3.3 6.9 7.0 7.4 7.4 7.8 9.0 9.5 2.7 3.2

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Propagation Delays (CMOS Inputs)

Pad to I1, I2 Pad to I1, I2 via transparent latch, no delay with delay

TPIDC TPLIC TPDLIC

Propagation Delays

Clock (IK) to I1, I2 (flip-flop) Clock (IK) to I1, I2 (latch enable, active Low)
Hold Times (Note 1)

TIKRI TIKLI TIKPI TIKPID

Pad to Clock (IK), no delay with delay Clock Enable (EC) to Clock (IK), no delay with delay

TIKEC All devices TIKECD All devices

0 0 Preliminary

Note 1: Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

4-108

March 30, 1998 (Version 1.5)

XC4000E IOB Input Switching Characteristic Guidelines (continued)

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

3.5 10.4 10.4 10.4 10.4 10.7 11.1 14.0 14.0 12.0 13.0

2.5 8.1 8.5 9.1 9.5 9.7 10.1 11.3 11.3 7.8 11.5

2.1 4.3 5.6 6.7 6.9 7.1 9.0 10.6 11.0 6.8 11.5

1.5 4.3 5.0 6.0 6.0 6.5 8.0 9.0 6.8 10.0

ns ns ns ns ns ns ns ns ns ns ns

Preliminary
Note 1: Note 2: Note 3: Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator.

March 30, 1998 (Version 1.5)

4-109

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E IOB Output Switching Characteristic Guidelines

-4 Min Max Min

-3 Max Min

-2 Max Min

-1 Max

Units

7.5 11.5 8.0 12.0 5.0

6.5 9.5 5.5 8.5 4.2

4.5 7.0 4.8 7.3 3.8

3.0 5.0 3.2 5.2 3.0

ns ns ns ns ns

9.7 13.7

8.1 11.1

7.3 9.8

6.8 8.8

ns ns

9.5 13.5 10.0 14.0 5.2

7.8 11.6 9.7 13.4 4.3

7.0 10.4 8.7 12.1 3.9

4.0 7.0 4.0 6.0 3.9

ns ns ns ns ns

9.1 13.1

7.6 11.4

6.8 10.2

6.8 8.8 Preliminary

ns ns

Note 2:

Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

4-110

March 30, 1998 (Version 1.5)

XC4000E IOB Output Switching Characteristic Guidelines (continued)

ns ns ns ns

4.5 4.5 15.0 13.0

4.0 4.0 11.8 11.5

4.0 4.0 8.7 11.5

3.0 3.0 7.0

ns ns ns ns

Preliminary
Note 1: Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source. Timing is based on the XC4005E. For other devices see the XACT timing calculator.

Note 2: Note 3:

March 30, 1998 (Version 1.5)

4-111

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines

Testing of the switching parameters is modeled after testing methods specied by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be printed in tabular format by running LCA2XNF -S. The following guidelines reect worst-case values over the recommended operating conditions. They are expressed in units of nanoseconds and apply to all XC4000E devices unless otherwise noted. Speed Grade Description Symbol Setup and Hold Input (TDI) to clock (TCK) TTDITCK setup time Input (TDI) to clock (TCK) TTCKTDI hold time Input (TMS) to clock (TCK) TTMSTCK setup time Input (TMS) to clock (TCK) TTCKTMS hold time Propagation Delay Clock (TCK) to Pad (TDO) TTCKPO Clock Clock (TCK) High TTCKH Clock (TCK) Low TTCKL FMAX (MHz) FMAX
Note 1: Note 2:

-4 Min 30.0 0 15.0 0 Max Min 30.0 0 15.0 0

-3 Max Min 30.0 0 15.0 0

-2 Max Min 20.0 0 10.0 0

-1 Max

Units

ns ns ns ns

30.0 5.0 5.0 15.0 5.0 5.0

30.0 5.0 5.0 15.0

30.0 4.0 4.0 15.0

20.0

ns ns ns ns

25.0 Preliminary

Note 3:

Input pad setup and hold times are specied with respect to the internal clock (IK). For setup and hold times with respect to the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table. Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test xture). Slew-rate limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see the Additional XC4000 Data section of the Programmable Logic Data Book. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be congured with the internal pull-up (default) or pull-down resistor, or congured as a driven output, or can be driven from an external source.

4-112

March 30, 1998 (Version 1.5)

XC4000E and XC4000X Series Field Programmable Gate Arrays

March 30, 1998 (Version 1.5)

Device-Specic Pinout Tables

Device-specic tables include all packages for each XC4000 and XC4000X Series device. They follow the pad locations around the die, and include boundary scan register locations..

Pin Locations for XC4003E Devices

XC4003E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O (A12) I/O (A13) I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O, TDI I/O, TCK I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O (LDC) I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O PC84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 PQ100 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 VQ100 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 PG120 G3 G1 F1 E1 F2 F3 D1 C1 D2 C2 D3 C3 C4 B2 B3 C5 B4 B5 A4 C6 A5 B6 A6 B7 C7 A7 A8 A9 B8 C8 A10 B9 A11 C9 A12 B11 C10 C11 D11 B12 C12 A13 D12 C13 E12 D13 F11 E13 F12 F13 G12 G11 G13 H13 J13 H12 H11 Bndry Scan 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 126 127 130 133 136 139 142 145 148 151 154 157 160 163 166 169 XC4003E Pad Name I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O (D6) I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O (CS1, A2) I/O (A3) I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 5/5/97 PC84 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 PQ100 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 VQ100 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 PG120 K13 J12 L13 M13 L12 K11 L11 L10 M12 M11 N13 M10 N11 M9 N10 L8 N9 M8 N8 M7 L7 N7 N6 N5 M6 L6 N4 M5 N3 N2 M3 L4 L3 M2 K3 L2 N1 K2 L1 J2 K1 H3 J1 H2 H1 G2 Bndry Scan 172 175 178 181 184 187 190 193 196 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 0 2 5 8 11 14 17 20 23 26 29 -

Additional XC4003E Package Pins

PG120 A1 E2 L5 5/5/97 A2 E3 L9 Not Connected Pins A3 B1 E11 J3 M1 M4 B10 J11 N12 B13 K12 -

March 30, 1998 (Version 1.5)

4-113

XC4000E and XC4000X Series Field Programmable Gate Arrays

Pin Locations for XC4005E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4005E/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O (A10) I/O (A11) I/O I/O GND I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK2 , GCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 , GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) PC PQ VQ TQ 84 100 100 144 P2 P92 P89 P128 P3 P93 P90 P129 P4 P94 P91 P130 P95 P92 P131 P96 P93 P132 P5 P97 P94 P133 P6 P98 P95 P134 P135 P136 P137 P7 P99 P96 P138 P8 P100 P97 P139 P140 P141 P9 P1 P98 P142 P10 P2 P99 P143 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P100 P144 P1 P1 P2 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 PG 156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 C6 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 B12 A13 A14 C12 B13 B14 A15 C13 A16 C14 B15 B16 D14 C15 D15 E14 C16 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P154 P155 P156 P157 P158 P159 PQ Bndry 208 Scan P183 P184 44 P185 47 P186 50 P187 53 P190 56 P191 59 P192 62 P193 65 P194 P199 68 P200 71 P201 74 P202 77 P203 80 P204 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 174 175 178 181 184 187 190 XC4005E/XL Pad Name GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3, GCK5 I/O I/O I/O (D6) I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O (D2) I/O I/O I/O GND I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) PC 84 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 PQ VQ 100 100 P34 P31 P35 P32 P36 P33 P37 P34 P38 P35 P39 P36 P40 P37 P41 P38 P42 P39 P43 P40 P44 P41 P45 P42 P46 P43 P47 P44 P48 P45 P49 P46 P50 P47 P51 P48 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 TQ 144 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 PG 156 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 T6 R7 P7 T5 R6 T4 P6 T3 P5 R4 R3 P4 PQ 160 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P113 P114 PQ Bndry 208 Scan P67 P68 193 P69 196 P70 199 P71 202 P74 205 P75 208 P76 211 P77 214 P78 P79 P80 217 P81 220 P82 223 P83 226 P86 229 P87 232 P88 235 P89 238 P90 P95 241 P96 244 P97 247 P98 250 P99 253 P100 256 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P119 P120 P121 P122 P123 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P138 P139 P140 P141 P142 P147 P148 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337

P160 P205 P1 P2 P2 P4 P3 P4 P5 P6 P7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P5 P6 P7 P8 P9 P14 P15 P16 P17 P18 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P33 P34 P35 P36 P37 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62

P115 P149 P116 P150 P117 P151

4-114

March 30, 1998 (Version 1.5)

XC4005E/XL Pad Name I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) GND I/O I/O I/O (A4) I/O (A5) I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND 6/10/97

PC 84 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1

PQ VQ TQ 100 100 144 P76 P73 P106 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127

PG 156 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2

PQ PQ Bndry 160 208 Scan P118 P152 340 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P131 P132 P133 P134 P135 P137 P138 P139 P140 P141 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P171 P172 P173 P174 P175 P178 P179 P180 P181 P182 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 -

PG156 A4 M1 T12 5/5/97 A12 M2 Not Connected Pins D1 D2 M15 N16 D16 R5 E15 R12 -

PQ160 P8 P71 P129 6/16/97 P9 P72 P130 Not Connected Pins P30 P31 P89 P90 P136 P152 P49 P111 P153 P50 P112 -

PQ208 P1 P19 P40 P63 P84 P102 P117 P143 P157 P176 P197 6/5/97 P3 P20 P41 P64 P85 P104 P118 P144 P158 P177 P198 Not Connected Pins P10 P11 P31 P32 P51 P52 P65 P66 P91 P92 P105 P107 P124 P125 P145 P146 P167 P168 P188 P189 P206 P207 P12 P38 P53 P72 P93 P115 P136 P155 P169 P195 P208 P13 P39 P54 P73 P94 P116 P137 P156 P170 P196 -

= E only = XL only

Additional XC4005E/XL Package Pins

TQ144 P117 5/5/97 Not Connected Pins -

Pin Locations for XC4006E Devices

XC4006E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND PC 84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 TQ 144 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 P5 P6 P7 P8 PG 156 H3 H1 G1 G2 G3 F1 F2 E1 E2 F3 D1 D2 E3 C1 C2 D3 B1 B2 C3 C4 B3 A1 A2 C5 B4 A3 A4 C6 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 PQ 208 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P14 Bndry Scan 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 XC4006E Pad Name I/O I/O I/O, TMS I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND PC 84 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 TQ 144 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 PG 156 B5 B6 A5 C7 B7 A6 A7 A8 C8 B8 C9 B9 A9 B10 C10 A10 A11 B11 C11 A12 B12 A13 A14 C12 B13 B14 A15 C13 PQ 160 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 PQ 208 P15 P16 P17 P18 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 Bndry Scan 122 125 128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 -

March 30, 1998 (Version 1.5)

4-115

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4006E Pad Name I (M0) VCC I (M2) I/O, PGCK2 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) PC 84 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 TQ 144 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 PG 156 A16 C14 B15 B16 D14 C15 D15 E14 C16 E15 D16 F14 F15 E16 F16 G14 G15 G16 H16 H15 H14 J14 J15 J16 K16 K15 K14 L16 M16 L15 L14 N16 M15 P16 M14 N15 P15 N14 R16 P14 R15 P13 R14 T16 T15 R13 P12 T14 T13 R12 T12 P11 R11 T11 T10 P10 R10 T9 R9 P9 R8 P8 T8 T7 PQ 160 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 PQ 208 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P67 P68 P69 P70 P71 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P86 P87 P88 P89 P90 P93 P94 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P119 P120 P121 P122 P123 P126 P127 P128 P129 P130 P131 P132 P133 Bndry Scan 197 198 199 202 205 208 211 214 217 220 223 226 229 232 235 238 241 244 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 XC4006E Pad Name I/O I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A6) I/O (A7) GND 5/5/97 PC 84 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P1 TQ 144 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 PG 156 T6 R7 P7 T5 R6 T4 P6 R5 T3 P5 R4 R3 P4 T2 R2 P3 T1 N3 R1 P2 N2 M3 P1 N1 M2 M1 L3 L2 L1 K3 K2 K1 J1 J2 J3 H2 PQ 160 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P137 P138 P139 P140 P141 PQ 208 P134 P135 P138 P139 P140 P141 P142 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P171 P172 P173 P174 P175 P178 P179 P180 P181 P182 Bndry Scan 349 352 355 358 361 364 367 370 373 376 379 382 385 388 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 -

Additional XC4006E Package Pins

PQ160 P136 5/5/97 PQ208 P1 P20 P51 P66 P91 P107 P136 P156 P176 P196 6/5/97 P3 P31 P52 P72 P92 P117 P137 P157 P177 P206 Not Connected Pins P12 P32 P53 P73 P102 P118 P143 P158 P188 P207 P13 P38 P54 P84 P104 P124 P144 P169 P189 P208 P19 P39 P65 P85 P105 P125 P155 P170 P195 Not Connected Pins -

4-116

March 30, 1998 (Version 1.5)

Pin Locations for XC4008E Devices

XC4008E Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O I/O (A10) I/O (A11) I/O I/O GND I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 (A15) VCC GND I/O, PGCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O GND I/O I/O I/O, TMS I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 PC84 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 PQ160 PG191 PQ208 Bndry Scan P142 J4 P183 P143 J3 P184 56 P144 J2 P185 59 P145 J1 P186 62 P146 H1 P187 65 H2 P188 68 H3 P189 71 P147 G1 P190 74 P148 G2 P191 77 P149 F1 P192 80 P150 E1 P193 83 P151 G3 P194 P152 C1 P197 86 P153 E2 P198 89 P154 F3 P199 92 P155 D2 P200 95 P156 B1 P201 98 P157 E3 P202 101 P158 C2 P203 104 P159 B2 P204 107 P160 D3 P205 P1 D4 P2 P2 C3 P4 110 P3 C4 P5 113 P4 B3 P6 116 P5 C5 P7 119 P6 A2 P8 122 P7 B4 P9 125 P8 C6 P10 128 P9 A3 P11 131 P10 C7 P14 P11 A4 P15 134 P12 A5 P16 137 P13 B7 P17 140 P14 A6 P18 143 C8 P19 146 A7 P20 149 P15 B8 P21 152 P16 A8 P22 155 P17 B9 P23 158 P18 C9 P24 161 P19 D9 P25 P20 D10 P26 P21 C10 P27 164 P22 B10 P28 167 P23 A9 P29 170 P24 A10 P30 173 A11 P31 176 C11 P32 179 P25 B11 P33 182 P26 A12 P34 185 P27 B12 P35 188 P28 A13 P36 191 P29 C12 P37 P30 A15 P40 194 P31 C13 P41 197 P32 B14 P42 200 P33 A16 P43 203 P34 B15 P44 206 P35 C14 P45 209 P36 A17 P46 212 P37 B16 P47 215 P38 C15 P48 218 P39 D15 P49 P40 A18 P50 221 P41 D16 P55 P42 C16 P56 222 P43 B17 P57 223 XC4008E Pad Name I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 I/O I/O I/O (D6) I/O I/O I/O GND I/O I/O I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O PC84 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 PQ160 PG191 PQ208 Bndry Scan P44 E16 P58 226 P45 C17 P59 229 P46 D17 P60 232 P47 B18 P61 235 P48 E17 P62 238 P49 F16 P63 241 P50 C18 P64 244 P51 G16 P67 P52 E18 P68 247 P53 F18 P69 250 P54 G17 P70 253 P55 G18 P71 256 H16 P72 259 H17 P73 262 P56 H18 P74 265 P57 J18 P75 268 P58 J17 P76 271 P59 J16 P77 274 P60 J15 P78 P61 K15 P79 P62 K16 P80 277 P63 K17 P81 280 P64 K18 P82 283 P65 L18 P83 286 L17 P84 289 L16 P85 292 P66 M18 P86 295 P67 M17 P87 298 P68 N18 P88 301 P69 P18 P89 304 P70 M16 P90 P71 T18 P93 307 P72 P17 P94 310 P73 N16 P95 313 P74 T17 P96 316 P75 R17 P97 319 P76 P16 P98 322 P77 U18 P99 325 P78 T16 P100 328 P79 R16 P101 P80 U17 P103 P81 R15 P106 P82 V18 P108 P83 T15 P109 331 P84 U16 P110 334 P85 T14 P111 337 P86 U15 P112 340 P87 V17 P113 343 P88 V16 P114 346 P89 T13 P115 349 P90 U14 P116 352 P91 T12 P119 P92 U13 P120 355 P93 V13 P121 358 P94 U12 P122 361 P95 V12 P123 364 T11 P124 367 U11 P125 370 P96 V11 P126 373 P97 V10 P127 376 P98 U10 P128 379 P99 T10 P129 382 P100 R10 P130 P101 R9 P131 P102 T9 P132 385 P103 U9 P133 388 P104 V9 P134 391 P105 V8 P135 394 U8 P136 397

March 30, 1998 (Version 1.5)

4-117

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4008E Pad Name I/O I/O (D2) I/O I/O I/O GND I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O GND I/O I/O I/O (A4) I/O (A5) PC84 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 PQ160 PG191 PQ208 Bndry Scan T8 P137 400 P106 V7 P138 403 P107 U7 P139 406 P108 V6 P140 409 P109 U6 P141 412 P110 T7 P142 P111 U5 P145 415 P112 T6 P146 418 P113 V3 P147 421 P114 V2 P148 424 P115 U4 P149 427 P116 T5 P150 430 P117 U3 P151 433 P118 T4 P152 436 P119 V1 P153 P120 R4 P154 P121 U2 P159 0 P122 R3 P160 P123 T3 P161 2 P124 U1 P162 5 P125 P3 P163 8 P126 R2 P164 11 P127 T2 P165 14 P128 N3 P166 17 P129 P2 P167 20 P130 T1 P168 23 P131 M3 P171 P132 P1 P172 26 P133 N1 P173 29 P134 M2 P174 32 P135 M1 P175 35 XC4008E Pad Name I/O I/O I/O I/O I/O (A6) I/O (A7) GND 5/5/97 PC84 P83 P84 P1 PQ160 PG191 PQ208 Bndry Scan L3 P176 38 P136 L2 P177 41 P137 L1 P178 44 P138 K1 P179 47 P139 K2 P180 50 P140 K3 P181 53 P141 K4 P182 -

Additional XC4008E Package Pins

PG191 A14 F2 V4 6/3/97 B5 F17 V5 Not Connected Pins B6 B13 N2 N17 V14 V15 D1 R1 D18 R18 -

PQ208 P1 P51 P91 P117 P157 P206 6/3/97 P3 P52 P92 P118 P158 P207 Not Connected Pins P12 P13 P53 P54 P102 P104 P143 P144 P169 P170 P208 P38 P65 P105 P155 P195 P39 P66 P107 P156 P196 -

Pin Locations for XC4010E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4010E/XL Pad Name PC 84 PQ TQ 100 144 PQ 160 TQ 176 PG 191 PQ/ HQ 208 BG 225 BG 256 Bndry Scan XC4010E/XL Pad Name PC 84 PQ TQ 100 144 PQ 160 TQ 176 PG 191 PQ/ HQ 208 BG 225 BG 256 Bndry Scan

VCC I/O (A8) I/O (A9) I/O (19) I/O (18) I/O I/O I/O (A10) I/O (A11) VCC I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1, GCK1 (A16) I/O (A17)

P2 P92 P128 P142 P155 VCC* P183 VCC* VCC* P3 P93 P129 P143 P156 J3 P184 E8 C10 P4 P94 P130 P144 P157 J2 P185 B7 D10 P95 P131 P145 P158 J1 P186 A7 A9 P96 P132 P146 P159 H1 P187 C7 B9 P160 H2 P188 D7 C9 P161 H3 P189 E7 D9 P5 P97 P133 P147 P162 G1 P190 A6 A8 P6 P98 P134 P148 P163 G2 P191 B6 B8 VCC* VCC* VCC* P135 P149 P164 F1 P192 A5 B6 P136 P150 P165 E1 P193 B5 A5 P137 P151 P166 GND* P194 GND* GND* F2 P195 D6 C6 P167 D1 P196 C5 B5 P152 P168 C1 P197 A4 A4 P153 P169 E2 P198 E6 C5 P7 P99 P138 P154 P170 F3 P199 B4 B4 P8 P100 P139 P155 P171 D2 P200 D5 A3 P140 P156 P172 B1 P201 B3 B3 P141 P157 P173 E3 P202 F6 B2 P9 P1 P142 P158 P174 C2 P203 A2 A2 P10 P2 P143 P159 P175 B2 P204 C3 C3

62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119

P11 P12 P13

P3 P4 P5

P144 P160 P176 VCC* P205 VCC* VCC* P1 P1 P1 GND* P2 GND* GND* P2 P2 P2 C3 P4 D4 B1

122

P14

125

I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O VCC I/O I/O

P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26

P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20

P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24

P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26

P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30

B3 C5 A2 B4 C6 A3 B5 B6 GND* A4 A5 B7 A6 VCC* C8 A7 B8 A8 B9 C9 GND* VCC* C10 B10 A9 A10 A11 C11 VCC* B11 A12

P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34

C2 E5 D3 C1 D2 G6 E4 D1 GND* F5 E1 F4 F3 VCC* G4 G3 G2 G1 G5 H3 GND* VCC* H4 H5 J2 J1 J3 J4 VCC* K2 K3

D2 D3 E4 C1 D1 E3 E2 E1 GND* G3 G2 G1 H3 VCC* J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 VCC* P1 P2

128 131 134 137 140 143 146 149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 194 197 200 203

4-118

March 30, 1998 (Version 1.5)

XC4010E/XL Pad Name

PC 84

PQ TQ 100 144

PQ 160

TQ 176

PG 191

PQ/ HQ 208

BG 225

BG 256

Bndry Scan

XC4010E/XL Pad Name

PC 84

PQ TQ 100 144

PQ 160

TQ 176

PG 191

PQ/ HQ 208

BG 225

BG 256

Bndry Scan

I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 , GCK2 O (M1) GND I (M0) VCC I (M2) I/O, PGCK2 , GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 , GCK5

P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57

P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57

P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84

P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47

B12 A13 GND* B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 GND* A18 VCC* C16 B17

P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57

J6 R1 L1 P3 GND* GND* L3 T2 M1 U1 K5 T3 M2 U2 L4 V1 N1 T4 M3 U3 N2 V2 K6 W1 P1 V3 N3 W2 GND* GND* P2 Y1 VCC* VCC* M4 W3 R2 Y2 P3 L5 N4 R3 P4 K7 M5 R4 N5 GND* R5 M6 N6 P6 VCC* R6 M7 R7 L7 N8 P8 VCC* GND* L8 P9 R9 N9 M9 L9 VCC* N10 K9 R11 P11 GND* R12 L10 P12 M11 R13 N12 P13 K10 R14 N13 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 GND* W7 Y7 V8 W8 VCC* Y8 U9 V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 VCC* Y15 V14 W15 Y16 GND* Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19

206 209 212 215 218 221 224 227 230 233 236 239 242 245 246 247 250 253 256 259 262 265 268 271 274 277 280 283 286 289 292 295 298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367 370

P48 E16 P58 P49 C17 P59 P50 D17 P60 P51 B18 P61 P52 E17 P62 P53 F16 P63 P54 C18 P64 D18 P65 F17 P66 P55 GND* P67 P56 E18 P68 P57 F18 P69 P58 G17 P70 P59 G18 P71 VCC* P60 H16 P72 P61 H17 P73 P62 H18 P74 P63 J18 P75 P64 J17 P76 P65 J16 P77 P66 VCC* P78 P67 GND* P79 P68 K16 P80 P69 K17 P81 P70 K18 P82 P71 L18 P83 P72 L17 P84 P73 L16 P85 VCC* P74 M18 P86 P75 M17 P87 P76 N18 P88 P77 P18 P89 P78 GND* P90 N17 P91 R18 P92 P79 T18 P93 P80 P17 P94 P81 N16 P95 P82 T17 P96 P83 R17 P97 P84 P16 P98 P85 U18 P99 P86 T16 P100

P87 GND* P101 GND* GND* P88 U17 P103 P14 Y20 P89 VCC* P106 VCC* VCC* P90 V18 P108 M12 V19 P91 T15 P109 P15 U19 P92 U16 P110 N14 U18

I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O GND I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O I/O I/O GND I/O I/O VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7)

P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72

P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106

P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118

P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130

T14 U15 V17 V16 T13 U14 V15 V14 GND* U13 V13 VCC* U12 V12 T11 U11 V11 V10 U10 T10 VCC* GND* T9 U9 V9 V8 U8 T8 V7 U7 VCC* V6 U6 GND* V5 V4 U5 T6 V3 V2 U4 T5 U3 T4

P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152

L11 M13 J10 L12 M15 L13 L14 K11 GND* K13 K14 VCC* K15 J12 J13 J14 J15 J11 H13 H14 VCC* GND* H12 H11 G14 G15 G13 G12 G11 F15 VCC* F14 F13 GND* E13 D15 F11 D14 E12 C15 D13 C14 F10 B15

T17 V20 T19 T20 R18 R19 R20 P18 GND* N19 N20 VCC* M17 M18 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H19 H18 VCC* G19 F20 GND* D20 E18 D19 C20 E17 D18 C19 B20 C18 B19

373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484

P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84

P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90

P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126

P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140

P131 V1 P153 C13 A20 P132 VCC* P154 VCC* VCC* P133 U2 P159 A15 A19 P134 GND* P160 GND* GND* P135 T3 P161 A14 B18 P136 U1 P162 B13 B17 P137 P3 P163 E11 C17 P138 R2 P164 C12 D16 P139 T2 P165 A13 A18 P140 N3 P166 B12 A17 P141 P2 P167 A12 A16 P142 T1 P168 C11 C15 R1 P169 B11 B15 N2 P170 E10 A15 P143 GND* P171 GND* GND* P144 P1 P172 A11 B14 P145 N1 P173 D10 A14 VCC* VCC* VCC* P146 M2 P174 A10 C12 P147 M1 P175 D9 B12 P148 L3 P176 C9 A12 P149 L2 P177 B9 B11 P150 L1 P178 A9 C11 P151 K1 P179 E9 A11 P152 K2 P180 C8 A10 P153 K3 P181 B8 B10

0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59

March 30, 1998 (Version 1.5)

4-119

XC4000E and XC4000X Series Field Programmable Gate Arrays

PQ/ HQ 208

XC4010E/XL Pad Name

PC 84

PQ TQ 100 144

PQ 160

TQ 176

PG 191

BG 225

BG 256

Bndry Scan

BG225 B2 R15 A1 H2 J8 A3 E3 F12 L6 P5 6/16/97 B14 A8 H6 J9 B10 E14 G10 L15 P7 VCC Pins H1 H15 GND Pins D12 F8 G7 H7 H8 H9 K8 M8 Not Connected Pins C4 C6 C10 E15 F1 F2 J5 K1 K4 M10 M14 N7 P10 R10 D8 R1 G8 H10 D11 F7 K12 N11 R8 G9 J7 E2 F9 L2 N15 -

GND 6/19/97

P91

P127 P141 P154 GND* P182 GND* GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. = E only = XL only

Additional XC4010E/XL Package Pins

PQ/HQ208 P1 P104 P206 5/27/97 P3 P105 P207 Not Connected Pins P51 P52 P53 P107 P155 P156 P208 P54 P157 P102 P158 -

BG256 C14 F1 P4 U7 A1 H4 U13 A6 C8 F3 J3 P20 V15 Y9 5/27/97 D6 F4 P17 U10 B7 H17 U17 A7 C13 F18 J4 R3 W6 Y13 VCC Pins D11 D14 G4 G17 R2 R4 U15 V7 GND Pins D4 D8 D13 N3 N4 N17 W14 Not Connected Pins A13 B13 B16 C16 D5 D12 F19 G18 H1 M4 M19 N1 T1 T18 U20 W9 W10 W13 Y14 D7 F17 P19 U14 D15 K4 R17 W20 D17 U4 C4 E19 H2 N2 V9 W16 E20 L17 U6 G20 U8 C7 F2 H20 N18 V13 Y6 -

PG191 D3 R15 C7 K4 T7 5/27/97 D10 C12 K15 T12 D16 D4 M3 VCC Pins J4 GND Pins D9 M16 J15 D15 R3 R4 G3 R9 R10 G16 R16 -

Pin Locations for XC4013E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name VCC P128 P142 P155 P183 VCC* VCC* I/O (A8) P129 P143 P156 P184 J3 E8 I/O (A9) P130 P144 P157 P185 J2 B7 I/O P131 P145 P158 P186 J1 A7 (A19) I/O P132 P146 P159 P187 H1 C7 (A18) I/O P160 P188 H2 D7 I/O P161 P189 H3 E7 I/O (A10) P133 P147 P162 P190 G1 A6 I/O (A11) P134 P148 P163 P191 G2 B6 VCC VCC* VCC* I/O H4 C6 I/O G4 F7 I/O P135 P149 P164 P192 F1 A5 I/O P136 P150 P165 P193 E1 B5 GND P137 P151 P166 P194 GND* GND* I/O P195 F2 D6 I/O P167 P196 D1 C5 I/O P152 P168 P197 C1 A4 I/O P153 P169 P198 E2 E6 I/O (A12) P138 P154 P170 P199 F3 B4 I/O (A13) P139 P155 P171 P200 D2 D5 I/O F4 A3 I/O E4 C4 I/O P140 P156 P172 P201 B1 B3 I/O P141 P157 P173 P202 E3 F6 PQ/ HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 BG Bndry 256 Scan VCC* C10 D10 A9 B9 C9 D9 A8 B8 VCC* A6 C7 B6 A5 GND* C6 B5 A4 C5 B4 A3 D5 C4 B3 B2 74 77 80 83 86 89 92 95 98 101 104 107 110 113 116 119 122 125 128 131 134 137 XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name I/O (A14) P142 P158 P174 P203 C2 A2 P143 P159 P175 P204 B2 C3 I/O, SGCK1 , GCK8 (A15) VCC P144 P160 P176 P205 VCC* VCC* GND P1 P1 P1 P2 GND* GND* P2 P2 P2 P4 C3 D4 I/O, PGCK1 , GCK1 (A16) I/O (A17) P3 P3 P3 P5 C4 B1 I/O P4 P4 P4 P6 B3 C2 I/O P5 P5 P5 P7 C5 E5 I/O, TDI P6 P6 P6 P8 A2 D3 I/O, TCK P7 P7 P7 P9 B4 C1 I/O P8 P8 P10 C6 D2 I/O P9 P9 P11 A3 G6 I/O P12 B5 E4 I/O P13 B6 D1 I/O D5 E3 I/O D6 E2 GND P8 P10 P10 P14 GND* GND* I/O P9 P11 P11 P15 A4 F5 I/O P10 P12 P12 P16 A5 E1 I/O, TMS P11 P13 P13 P17 B7 F4 I/O P12 P14 P14 P18 A6 F3 VCC VCC* VCC* PQ/ HQ 240 P238 P239 BG Bndry 256 Scan A2 C3 140 143

P240 P1 P2

VCC* GND* B1

146

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19

C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND* G3 G2 G1 H3 VCC*

149 152 155 158 161 164 167 170 173 176 179 182 185 188 191 -

4-120

March 30, 1998 (Version 1.5)

XC4013E HT /XL 144 Pad Name I/O I/O I/O I/O I/O P13 I/O P14 I/O P15 I/O P16 GND P17 VCC P18 I/O P19 I/O P20 I/O P21 I/O P22 I/O I/O I/O I/O VCC I/O P23 I/O P24 I/O P25 I/O P26 GND P27 I/O I/O I/O I/O I/O I/O I/O P28 I/O P29 I/O P30 I/O P31 I/O P32 I/O, P33 SGCK2 , GCK2 O (M1) P34 GND P35 I (M0) P36 VCC P37 I (M2) P38 I/O, P39 PGCK2 , GCK3 I/O (HDC) P40 I/O P41 I/O P42 I/O P43 P44 I/O (LDC) I/O I/O I/O I/O I/O I/O GND P45 I/O P46 I/O P47 I/O P48 I/O P49 VCC I/O I/O I/O I/O I/O P50 I/O P51 I/O P52 I/O (INIT) P53 VCC P54 GND P55 I/O P56

PQ 160 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37

HT PQ/HQ PG 176 208 223 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 D7 D8 C8 A7 B8 A8 B9 C9 GND* VCC* C10 B10 A9 A10 A11 C11 D11 D12 VCC* B11 A12 B12 A13 GND* D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16

BG 225 F2 F1 G4 G3 G2 G1 G5 H3 GND* VCC* H4 H5 J2 J1 J3 J4 J5 K1 VCC* K2 K3 J6 L1 GND* L2 K4 L3 M1 K5 M2 L4 N1 M3 N2 K6 P1

PQ/ HQ 240 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57

BG Bndry 256 Scan H2 H1 J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 N1 N2 VCC* P1 P2 R1 P3 GND* T1 R3 T2 U1 T3 U2 V1 T4 U3 V2 W1 V3 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 275 278 281 284 287

P38 P39 P40 P41 P42 P43

P42 P43 P44 P45 P46 P47

P48 P49 P50 P55 P56 P57

C15 N3 GND* GND* A18 P2 VCC* VCC* C16 M4 B17 R2

P58 P59 P60 P61 P62 P63

W2 GND* Y1 VCC* W3 Y2

290 293 294 295

P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62

P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68

P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80

E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 GND* E18 F18 G17 G18 VCC* H16 H17 G15 H15 H18 J18 J17 J16 VCC* GND* K16

P3 L5 N4 R3 P4 K7 M5 R4 N5 P5 L6 GND* R5 M6 N6 P6 VCC* R6 M7 N7 P7 R7 L7 N8 P8 VCC* GND* L8

P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92

W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 Y9 W10 V10 Y10 Y11 W11 VCC* GND* V11

298 301 304 307 310 313 316 319 322 325 328 331 334 337 340 343 346 349 352 355 358 361 364 367

XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name I/O P57 P63 P69 P81 K17 P9 I/O P58 P64 P70 P82 K18 R9 I/O P59 P65 P71 P83 L18 N9 I/O P72 P84 L17 M9 I/O P73 P85 L16 L9 I/O L15 R10 I/O M15 P10 VCC VCC* VCC* I/O P60 P66 P74 P86 M18 N10 I/O P61 P67 P75 P87 M17 K9 I/O P62 P68 P76 P88 N18 R11 I/O P63 P69 P77 P89 P18 P11 GND P64 P70 P78 P90 GND* GND* I/O N15 M10 I/O P15 N11 I/O P91 N17 R12 I/O P92 R18 L10 I/O P71 P79 P93 T18 P12 I/O P72 P80 P94 P17 M11 I/O P65 P73 P81 P95 N16 R13 I/O P66 P74 P82 P96 T17 N12 I/O P67 P75 P83 P97 R17 P13 I/O P68 P76 P84 P98 P16 K10 I/O P69 P77 P85 P99 U18 R14 I/O, P70 P78 P86 P100 T16 N13 SGCK3 , GCK4 GND P71 P79 P87 P101 GND* GND* DONE P72 P80 P88 P103 U17 P14 VCC P73 P81 P89 P106 VCC* VCC* PROP74 P82 P90 P108 V18 M12 GRAM I/O (D7) P75 P83 P91 P109 T15 P15 I/O, P76 P84 P92 P110 U16 N14 PGCK3 , GCK5 I/O P77 P85 P93 P111 T14 L11 I/O P78 P86 P94 P112 U15 M13 I/O R14 N15 I/O R13 M14 I/O (D6) P79 P87 P95 P113 V17 J10 I/O P80 P88 P96 P114 V16 L12 I/O P89 P97 P115 T13 M15 I/O P90 P98 P116 U14 L13 I/O P117 V15 L14 I/O P118 V14 K11 GND P81 P91 P99 P119 GND* GND* I/O R12 L15 I/O R11 K12 I/O P82 P92 P100 P120 U13 K13 I/O P83 P93 P101 P121 V13 K14 VCC VCC* VCC* I/O (D5) P84 P94 P102 P122 U12 K15 P85 P95 P103 P123 V12 J12 I/O (CS0) I/O P104 P124 T11 J13 I/O P105 P125 U11 J14 I/O P86 P96 P106 P126 V11 J15 I/O P87 P97 P107 P127 V10 J11 I/O (D4) P88 P98 P108 P128 U10 H13 I/O P89 P99 P109 P129 T10 H14 VCC P90 P100 P110 P130 VCC* VCC* GND P91 P101 P111 P131 GND* GND* I/O (D3) P92 P102 P112 P132 T9 H12 P93 P103 P113 P133 U9 H11 I/O (RS) I/O P94 P104 P114 P134 V9 G14 I/O P95 P105 P115 P135 V8 G15 I/O P116 P136 U8 G13 I/O P117 P137 T8 G12 I/O (D2) P96 P106 P118 P138 V7 G11 I/O P97 P107 P119 P139 U7 F15 VCC VCC* VCC* I/O P98 P108 P120 P140 V6 F14 I/O P99 P109 P121 P141 U6 F13 I/O R8 G10

PQ/ HQ 240 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118

BG Bndry 256 Scan U11 Y12 W12 V12 U12 V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17 V16 W17 Y18 U16 V17 W18 Y19 V18 W19 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436

P119 P120 P121 P122 P123 P124

GND* Y20 VCC* V19 U19 U18

439 442

P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164

T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H19 H18 VCC* G19 F20 G18

445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541

March 30, 1998 (Version 1.5)

4-121

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4013E HT PQ HT PQ/HQ PG BG /XL 144 160 176 208 223 225 Pad Name I/O R7 E15 GND P100 P110 P122 P142 GND* GND* I/O R6 E14 I/O R5 F12 I/O P143 V5 E13 I/O P144 V4 D15 I/O P111 P123 P145 U5 F11 I/O P112 P124 P146 T6 D14 I/O (D1) P101 P113 P125 P147 V3 E12 P148 V2 C15 I/O (RCLK, P102 P114 P126 RDY/ BUSY) I/O P103 P115 P127 P149 U4 D13 I/O P104 P116 P128 P150 T5 C14 I/O (D0, P105 P117 P129 P151 U3 F10 DIN) P106 P118 P130 P152 T4 B15 I/O, SGCK4 , GCK6 (DOUT) CCLK P107 P119 P131 P153 V1 C13 VCC P108 P120 P132 P154 VCC* VCC* O, TDO P109 P121 P133 P159 U2 A15 GND P110 P122 P134 P160 GND* GND* P111 P123 P135 P161 T3 A14 I/O (A0, WS) P112 P124 P136 P162 U1 B13 I/O, PGCK4 , GCK7 (A1) I/O P113 P125 P137 P163 P3 E11 I/O P114 P126 P138 P164 R2 C12 I/O (CS1, P115 P127 P139 P165 T2 A13 A2) I/O (A3) P116 P128 P140 P166 N3 B12 I/O P4 F9 I/O N4 D11 I/O P117 P129 P141 P167 P2 A12 I/O P130 P142 P168 T1 C11 I/O P169 R1 B11 I/O P170 N2 E10 GND P118 P131 P143 P171 GND* GND* I/O P119 P132 P144 P172 P1 A11 I/O P120 P133 P145 P173 N1 D10 I/O M4 C10 I/O L4 B10 VCC VCC* VCC* I/O (A4) P121 P134 P146 P174 M2 A10 I/O (A5) P122 P135 P147 P175 M1 D9 I/O P148 P176 L3 C9 I/O P136 P149 P177 L2 B9 I/O P123 P137 P150 P178 L1 A9 (A21) I/O P124 P138 P151 P179 K1 E9 (A20) I/O (A6) P125 P139 P152 P180 K2 C8 I/O (A7) P126 P140 P153 P181 K3 B8 GND P127 P141 P154 P182 GND* GND* PQ/ HQ 240 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174

BG Bndry 256 Scan F19 GND* F18 E19 D20 E18 D19 C20 E17 D18 544 547 550 553 556 559 562 565 568

Additional XC4013E/XL Package Pins

PQ/HQ208 P1 P102 P157 5/5/97 P3 P104 P158 Not Connected Pins P51 P52 P105 P107 P206 P207 P53 P155 P208 P54 P156 -

PG223 D3 R10 C7 G16 R9 5/5/97 D10 R15 C12 K4 R16 VCC Pins D16 J4 GND Pins D4 D9 K15 M3 T7 T12 J15 D15 M16 R4 G3 R3 -

P175 P176 P177 P178

C19 B20 C18 B19

571 574 577 580

P179 P180 P181 P182 P183 P184

A20 VCC* A19 GND* B18 B17

0 2 5

BG225 B2 R1 A1 G8 H8 J9 5/5/97 B14 R8 A8 G9 H9 K8 VCC Pins D8 R15 GND Pins D12 H2 H10 M8 H1 F8 H6 J7 H15 G7 H7 J8 -

P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211

C17 D16 A18 A17 C16 B16 A16 C15 B15 A15 GND* B14 A14 C13 B13 VCC* C12 B12 A12 B11 C11 A11 A10 B10 GND*

8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 -

The BG225 package pins in this table are bonded to an internal Ground plane on the XC4013E die. They must all be externally connected to Ground.
PQ/HQ240 P22 P204 P195 6/9/97 P37 P219 GND Pins P83 P98 Not Connected Pins P143 P158 -

Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible.
BG256 C14 E20 K4 R4 U15 A1 G20 U4 A7 J4 Y13 6/4/97 D6 F1 L17 R17 V7 B7 H4 U8 A13 M4 VCC Pins D7 D11 F4 F17 P4 P17 U6 U7 W20 GND Pins D4 D8 H17 N3 U13 U17 Not Connected Pins C8 D12 M19 V9 D14 G4 P19 U10 D13 N4 W14 H20 W9 D15 G17 R2 U14 D17 N17 J3 W13 -

6/9/97

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin. = E only, = XL only

4-122

March 30, 1998 (Version 1.5)

Pin Locations for XC4020E/XL Devices

The following table may contain pinout information for unsupported device/package combinations. Please see the availability charts elsewhere in the XC4000 Series data sheet for availability information.
XC4020E/XL Pad Name VCC I/O (A8) I/O (A9) I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) I/O I/O I/O I/O I/O (A14) I/O, SGCK1 , GCK8 (A15) VCC GND I/O, PGCK1 , GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O HT 144 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 PQ 160 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 HT 176 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 HQ208 PQ208 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 PG 223 VCC* J3 J2 J1 H1 H2 H3 G1 G2 VCC* H4 G4 F1 E1 GND* F2 D1 C1 E2 F3 D2 F4 E4 B1 E3 C2 B2 VCC* GND* C3 C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 GND* A4 A5 B7 A6 VCC* D7 D8 C8 A7 B8 A8 B9 C9 GND* VCC* C10 B10 A9 A10 A11 C11 D11 D12 VCC* B11 HQ240 PQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P38 P39 P40 P41 BG Bndry 256 Scan VCC* C10 86 D10 89 A9 92 B9 95 C9 98 D9 101 A8 104 B8 107 C8 110 A7 113 VCC* A6 116 C7 119 B6 122 A5 125 GND* C6 128 B5 131 A4 134 C5 137 B4 140 A3 143 D5 152 C4 155 B3 158 B2 161 A2 164 C3 167 VCC* GND* B1 C2 D2 D3 E4 C1 D1 E3 E2 E1 F3 F2 GND* G3 G2 G1 H3 VCC* H2 H1 J4 J3 J2 J1 K2 K3 K1 L1 GND* VCC* L2 L3 L4 M1 M2 M3 M4 N1 N2 VCC* P1 170 173 176 179 182 185 194 197 200 203 206 209 212 215 218 221 224 227 230 233 236 239 242 245 248 251 254 257 260 263 266 269 272 278 281 284 XC4020E/XL Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, SGCK2 , GCK2 O (M1) GND I (M0) VCC I (M2) I/O PGCK2 , GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HT PQ HT 144 160 176 P24 P26 P30 P25 P27 P31 P26 P28 P32 P27 P29 P33 P30 P34 P31 P35 P28 P32 P36 P29 P33 P37 P30 P34 P38 P31 P35 P39 P32 P36 P40 P33 P37 P41 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 HQ208 PQ208 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 PG 223 A12 B12 A13 GND* D13 D14 B13 A14 A15 C13 B14 A16 B15 C14 A17 B16 C15 GND* A18 VCC* C16 B17 E16 C17 D17 B18 E17 F16 C18 D18 F17 E15 F15 GND* E18 F18 G17 G18 VCC* H16 H17 G15 H15 H18 J18 J17 J16 VCC* GND* K16 K17 K18 L18 L17 L16 L15 M15 VCC* M18 M17 N18 P18 GND* N15 P15 N17 R18 T18 P17 HQ240 PQ240 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 BG Bndry 256 Scan P2 287 R1 290 P3 293 GND* T1 296 R3 299 T2 302 U1 305 T3 308 U2 311 V1 320 T4 323 U3 326 V2 329 W1 332 V3 335 W2 GND* Y1 VCC* W3 Y2 W4 V4 U5 Y3 Y4 V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 V9 W9 Y9 W10 V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 Y13 W13 V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17 V16 W17 Y18 338 341 342 343 346 349 352 355 358 367 370 373 376 379 382 385 388 391 394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484

March 30, 1998 (Version 1.5)

4-123

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4020E/XL Pad Name I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 , GCK5 I/O I/O I/O I/O I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) HT PQ HT 144 160 176 P65 P73 P81 P66 P74 P82 P67 P75 P83 P68 P76 P84 P69 P77 P85 P70 P78 P86 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 HQ208 PQ208 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 PG 223 N16 T17 R17 P16 U18 T16 GND* U17 VCC* V18 T15 U16 T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 GND* R12 R11 U13 V13 VCC* U12 V12 T11 U11 V11 V10 U10 T10 VCC* GND* T9 U9 V9 V8 U8 T8 V7 U7 VCC* V6 U6 R8 R7 GND* R6 R5 V5 V4 U5 T6 V3 V2 U4 T5 U3 T4 V1 VCC* U2 GND* T3 U1 P3 R2 T2 N3 HQ240 PQ240 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 BG Bndry 256 Scan U16 493 V17 496 W18 499 Y19 502 V18 505 W19 508 GND* Y20 VCC* V19 U19 U18 T17 V20 U20 T18 T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 M19 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H20 H19 H18 VCC* G19 F20 G18 F19 GND* F18 E19 D20 E18 D19 C20 E17 D18 C19 B20 C18 B19 A20 VCC* A19 GND* B18 B17 C17 D16 A18 A17 511 514 517 520 523 526 535 538 541 544 547 550 553 556 559 562 565 568 574 577 580 583 586 589 592 595 598 601 604 607 610 613 619 622 625 628 631 634 637 640 643 646 649 652 655 658 667 670 673 676 0 2 5 8 11 14 17 XC4020E/XL Pad Name I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND HT 144 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 PQ 160 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 HT 176 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 HQ208 PQ208 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 PG 223 P4 N4 P2 T1 R1 N2 GND* P1 N1 M4 L4 VCC* M2 M1 L3 L2 L1 K1 K2 K3 GND* HQ240 PQ240 P189 P190 P191 P192 P193 P194 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 P211 BG Bndry 256 Scan C16 26 B16 29 A16 32 C15 35 B15 38 A15 41 GND* B14 44 A14 47 C13 50 B13 53 VCC* A13 56 D12 59 C12 62 B12 65 A12 68 B11 71 C11 74 A11 77 A10 80 B10 83 GND* -

6/24/97

= E only = XL only

Additional XC4020E/XL Package Pins

PQ/HQ208 P1 P102 P157 5/5/97 P3 P104 P158 Not Connected Pins P51 P52 P105 P107 P206 P207 P53 P155 P208 P54 P156 -

PG223 D3 R10 C7 G16 R9 5/5/97 D10 R15 C12 K4 R16 VCC Pins D16 J4 GND Pins D4 D9 K15 M3 T7 T12 J15 D15 M16 R4 G3 R3 -

PQ/HQ240 P22 P204 P195 6/9/97 P37 P219 GND Pins P83 P98 Not Connected Pins P143 P158 -

Pins marked with this symbol are used for Ground connections on some revisions of the device. These pins may not physically connect to anything on the current device revision. However, they should be externally connected to Ground, if possible.
BG256 C14 E20 K4 R4 U15 A1 G20 U4 6/17/97 D6 F1 L17 R17 V7 B7 H4 U8 VCC Pins D7 D11 F4 F17 P4 P17 U6 U7 W20 GND Pins D4 D8 H17 N3 U13 U17 D14 G4 P19 U10 D13 N4 W14 D15 G17 R2 U14 D17 N17 -

4-124

March 30, 1998 (Version 1.5)

Pin Locations for XC4025E, XC4028EX/XL Devices

P183 VCC* P212 VCC* VCC* P184 J3 P213 C10 K2 P185 J2 P214 D10 K3 P186 J1 P215 A9 K5 P187 H1 P216 B9 K4 P188 H2 P217 C9 J1 P189 H3 P218 D9 J2 P190 G1 P220 A8 H1 P191 G2 P221 B8 J3 GND* GND* J4 J5 C8 H2 A7 G1 VCC* P222 VCC* VCC* H4 P223 A6 H3 G4 P224 C7 G2 P192 F1 P225 B6 H4 P193 E1 P226 A5 F2 P194 GND* P227 GND* GND* H5 G3 P195 F2 P228 C6 D1 P196 D1 P229 B5 G4 P197 C1 P230 A4 E2 P198 E2 P231 C5 F3 P199 F3 P232 B4 G5 P200 D2 P233 A3 C1 GND* GND* VCC* VCC* F4 E3 F4 P234 D5 D2 E4 P235 C4 C2 P201 B1 P236 B3 F5 P202 E3 P237 B2 E4 P203 C2 P238 A2 D3 P204 B2 P239 C3 C3

P160 P205 VCC* P240 VCC* VCC* P1 VCC* P1 P2 GND* P1 GND* GND* P304 GND* P2 P4 C3 P2 B1 D4 P303 D23

194

P3 P4 P5 P6 P7 P8 P9 -

P5 P6 P7 P8 P9 P10 P11 P12 P13 -

C4 B3 C5 A2 B4 C6 A3 B5 B6 D5 D6 -

P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 -

C2 B2 P302 C25 D2 B3 P301 D24 D3 E6 P300 E23 E4 D5 P299 C26 C1 C4 P298 E24 A3 P297 F24 D6 P296 E25 VCC* VCC* VCC* GND* GND* GND* D1 E7 P295 D26 E3 B4 P294 G24 E2 C5 P293 F25 E1 A4 P292 F26 F3 D7 P291 H23 F2 C6 P290 H24 E8 P289 G25

197 200 203 206 209 212 215 218 221 224 227 230 233 236

W2 A20 P231 AB23 GND* GND* P230 GND*

386 -

March 30, 1998 (Version 1.5)

4-125

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4025E, XC4028 HQ HQ PG HQ EX/XL 160 208 223 240 Pad Name I (M0) P40 P50 A18 P60 VCC P41 P55 VCC* P61 I (M2) P42 P56 C16 P62 I/O, P43 P57 B17 P63 PGCK2 , GCK3 I/O (HDC) P44 P58 E16 P64 I/O P45 P59 C17 P65 I/O P46 P60 D17 P66 I/O P47 P61 B18 P67 I/O (LDC) P48 P62 E17 P68 I/O I/O VCC GND I/O P49 P63 F16 P69 I/O P50 P64 C18 P70 I/O P65 D18 P71 I/O P66 F17 P72 I/O E15 P73 I/O F15 P74 I/O I/O GND P51 P67 GND* P75 I/O P52 P68 E18 P76 I/O P53 P69 F18 P77 I/O P54 P70 G17 P78 I/O P55 P71 G18 P79 VCC VCC* P80 I/O P72 H16 P81 I/O P73 H17 P82 I/O I/O GND P83 I/O I/O I/O G15 P84 I/O H15 P85 I/O P56 P74 H18 P86 I/O P57 P75 J18 P87 I/O P58 P76 J17 P88 I/O (INIT) P59 P77 J16 P89 VCC P60 P78 VCC* P90 GND P61 P79 GND* P91 I/O P62 P80 K16 P92 I/O P63 P81 K17 P93 I/O P64 P82 K18 P94 I/O P65 P83 L18 P95 I/O P84 L17 P96 I/O P85 L16 P97 I/O I/O GND P98 I/O I/O I/O L15 P99 I/O M15 P100 VCC VCC* P101 I/O P66 P86 M18 P102 I/O P67 P87 M17 P103 I/O P68 P88 N18 P104 I/O P69 P89 P18 P105 GND P70 P90 GND* P106 I/O I/O I/O N15 P107 I/O P15 P108 I/O P91 N17 P109 XC4025E, XC4028 EX/XL Pad Name I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O, SGCK3 , GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, PGCK3 , GCK5 I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O GND I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O

BG 256

PG 299

HQ 304

BG Bndry 352 Scan 389 390 391

HQ HQ PG 160 208 223 P71 P72 P73 P74 P75 P76 P77 P78 P92 P93 P94 P95 P96 P97 P98 P99 P100 R18 T18 P17 N16 T17 R17 P16 U18 T16

HQ 240

BG 256

PG 299

HQ 304

BG Bndry 352 Scan 550 553 556 559 562 565 568 571 574 577 580

Y1 C18 P229 AD24 VCC* VCC* P228 VCC* W3 D17 P227 AC23 Y2 B19 P226 AE24

W4 V4 U5 Y3 Y4 VCC* GND* V5 W5 Y5 V6 W6 Y6 GND* W7 Y7 V8 W8 VCC* Y8 U9 GND* V9 W9 Y9 W10 V10 Y10 Y11 W11 VCC* GND* V11 U11 Y12 W12 V12 U12 Y13 W13 GND* V13 Y14 VCC* Y15 V14 W15 Y16 GND* V15 W16 Y17

C19 F16 E17 D18 C20 F17 G16 VCC* GND* D19 E18 D20 G17 F18 H16 E19 F19 GND* H17 G18 G19 H18 VCC* J16 G20 J17 H19 GND* H20 J18 J19 K16 J20 K17 K18 K19 VCC* GND* L19 L18 L16 L17 M20 M19 N20 M18 GND* M17 M16 N19 P20 VCC* N18 P19 N17 R19 GND* N16 P18 U20 P17 T19

P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211 P210 P209 P208 P207 P206 P204 P203 P202 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 P186 P185 P184 P183 P182 P181 P180 P179 P178 P177 P175 P174 P173 P172 P171 P170 P169 P168 P167 P166

AD23 AC22 AF24 AD22 AE23 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 AE17 AE16 GND* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 GND* AE11 AD11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7

394 397 400 403 406 409 412 415 418 421 424 427 430 433 436 439 442 445 448 451 454 457 460 463 466 469 472 475 478 481 484 487 490 493 496 499 502 505 508 511 514 517 520 523 526 529 532 535 538 541 544 547

P110 V16 R18 P165 AD7 P111 W17 P16 P164 AE6 P112 Y18 V20 P163 AE5 GND* GND* GND* VCC* VCC* VCC* R17 P162 AD6 T18 P161 AC7 P113 U16 U19 P160 AF4 P114 V17 V19 P159 AF3 P115 W18 R16 P158 AD5 P116 Y19 T17 P157 AE3 P117 V18 U18 P156 AD4 P118 W19 X20 P155 AC5

P79 P80 P81 P82 P83 P84

P101 GND* P119 GND* GND* P154 GND* P103 U17 P120 Y20 V18 P153 AD3 P106 VCC* P121 VCC* VCC* P152 VCC* P108 V18 P122 V19 U17 P151 AC4 P109 P110 T15 U16 P123 P124 U19 U18 W19 W18 P150 P149 AD2 AC3

583 586

P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 -

P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 -

T14 U15 R14 R13 V17 V16 T13 U14 V15 V14 GND* R12 R11 U13 V13 VCC* U12 V12 T11 U11 V11 V10 U10 T10 VCC* GND* T9 U9 V9 V8 U8 T8 -

P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 -

T17 V20 U20 T18 VCC* GND* T19 T20 R18 R19 R20 P18 GND* P20 N18 N19 N20 VCC* M17 M18 GND* M19 M20 L19 L18 L20 K20 K19 VCC* GND* K18 K17 J20 J19 J18 J17 H20

T15 U16 V17 X18 U15 T14 VCC* GND* W17 V16 X17 U14 V15 T13 W16 W15 GND* U13 V14 W14 V13 VCC* T12 X14 U12 W13 GND* X13 V12 W12 T11 X12 U11 V11 W11 VCC* GND* W10 V10 T10 U10 X9 W9 X8

P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109 P108 P107

AB4 AD1 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 U2 T2 GND* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 M4

589 592 595 598 601 604 607 610 613 616 619 622 625 628 631 634 637 640 643 646 649 652 655 658 661 664 667 670 673 676 679 682 685 688 691 694 697

4-126

March 30, 1998 (Version 1.5)

XC4025E, XC4028 EX/XL Pad Name I/O GND I/O I/O I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O I/O I/O (D0, DIN) I/O, SGCK4 , GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, PGCK4 , GCK7 (A1) I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC

HQ HQ PG 160 208 223 P106 P107 P108 P109 P110 P111 P112 P113 P114

HQ 240

BG 256

PG 299

HQ 304 P106 P105 P104 P103 P102 P101 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85

BG Bndry 352 Scan L1 GND* L2 L3 J1 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 700 703 706 709 712 715 718 721 724 727 730 733 736 739 742 745 748 751 754

V9 P158 GND* GND* U9 T9 P138 V7 P159 H19 W8 P139 U7 P160 H18 X7 VCC* P161 VCC* VCC* P140 V6 P162 G19 V8 P141 U6 P163 F20 W7 R8 P164 G18 U8 R7 P165 F19 W6 P142 GND* P166 GND* GND* T8 V7 R6 P167 F18 X4 R5 P168 E19 U7 P143 V5 P169 D20 W5 P144 V4 P170 E18 V6 P145 U5 P171 D19 T7 P146 T6 P172 C20 X3 GND* GND* VCC* VCC* P147 V3 P173 E17 U6 P148 V2 P174 D18 V5

XC4025E, XC4028 EX/XL Pad Name I/O I/O I/O I/O GND I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) GND 6/19/97

HQ HQ PG 160 208 223 P134 P135 P136 P137 P138 P139 P140 P141 P174 M2 P175 M1 P176 L3 P177 L2 P178 L1 P179 K1 P180 K2 P181 K3 P182 GND*

HQ 240

BG 256

PG 299

HQ 304

BG Bndry 352 Scan 62 65 68 71 74 77 80 83 86 89 92 95 -

A13 M5 D12 P1 M4 N2 GND* GND* P202 C12 N1 P203 B12 M3 P205 A12 M2 P206 B11 L5 P207 C11 M1 P208 A11 L4 P209 A10 L3 P210 B10 L2 P211 GND* GND*

P51 A9 P50 D11 P49 B11 P48 A11 GND* P47 D12 P46 C12 P45 B12 P44 A12 P43 C13 P42 B13 P41 A13 P40 B14 P39 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin. = E only = XL only = EX, XL only

Additional XC4025E, XC4028EX/XL Package Pins

HQ208
Not Connected Pins

P115 P149 P116 P150 P117 P151 P118 P152

U4 T5 U3 T4

P175 P176 P177 P178

C19 B20 C18 B19

W4 W3 T6 U5 V4 X1

P84 P83 P82 P81 P80 P79

D2 F4 E3 C2 D3 E4

757 760 763 766 769 772

P1 P3 P51 5/9/97

P52 P53 P54

P102 P104 P105

P107 P155 P156

P157 P158 P206

P207 P208

PG223 P119 P120 P121 P122 P123 P153 V1 P179 A20 V3 P154 VCC* P180 VCC* VCC* P159 U2 P181 A19 U4 P160 GND* P182 GND* GND* P161 T3 P183 B18 W2 U1 P184 B17 V2 P78 C3 P77 VCC* P76 D4 P75 GND* P74 B3 P73 C4 0 2 5 5/9/97 P125 P163 P126 P164 P127 P165 P128 P129 P130 P131 P132 P133 P3 R2 T2 P185 P186 P187 C17 D16 A18 R5 T4 U3 V1 R4 P5 VCC* GND* U2 T3 U1 P4 R3 N5 T2 R2 GND* N4 P3 P2 N3 VCC* P72 P71 P70 P69 P68 P67 P66 P65 P64 P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P52 D5 A3 D6 C6 B5 A4 VCC* GND* C7 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 VCC Pins

D3 J15 C7 D15 K15 R9

D10 R4 GND Pins C12 G3 M3 R16

D16 R10 D4 G16 M16 T7

J4 R15 D9 K4 R3 T12

P124 P162

HQ240
GND Pins

P166 N3 P188 A17 VCC* GND* P4 P189 C16 N4 P190 B16 P167 P2 P191 A16 P168 T1 P192 C15 P169 R1 P193 B15 P170 N2 P194 A15 P195 P171 GND* P196 GND* P172 P1 P197 B14 P173 N1 P198 A14 M4 P199 C13 L4 P200 B13 VCC* P201 VCC*

P204 5/9/97

P219

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.

March 30, 1998 (Version 1.5)

4-127

XC4000E and XC4000X Series Field Programmable Gate Arrays

BG256
VCC Pins

HQ304
Not Connected Pins

C14 D14 F4 K4 P19 U6 U15 A1 D13 H17 U4 W14 5/9/97

D6 D15 F17 L17 R2 U7 V7

GND Pins

D7 E20 G4 P4 R4 U10 W20 D4 G20 N4 U13 -

D11 F1 G17 P17 R17 U14 D8 H4 N17 U17 -

P11 P24 5/15/97

P53 P100

P128 P176

P205 P254

P281 -

Note: In XC4025 (no extension) devices in the HQ304 package, P101 is a No Connect (N.C.) pin. P101 is Vcc in XC4025E and XC4028EX/XL devices. Where necessary for compatibility, this pin can be left unconnected.

B7 D17 N3 U8 -

BG352
VCC Pins

A10 D19 P4 AC14 A1 A22 E26 W26 AF2 AF25 A18 C5 F23 T4 AC11 AD26 5/9/97

A17 G23 U1 AC20 A2 A25 H1 AB1 AF5 AF26 A24 C8 J26 T24 AC16 AE4

PG299
VCC Pins

A2 B20 K1 T20 X15 A5 B1 K20 T5 X11 6/18/97

A6 E1 L20 W1 X19 GND Pins A10 E16 L1 W20 X16

A11 E5 R1 X5 A15 E20 R20 X2 -

A16 F20 T16 X10 A19 F1 T1 X6 -

B2 B25 H4 K1 U26 W23 AE2 AE25 GND Pins A5 A8 A26 B1 H26 N1 AB26 AE1 AF8 AF13 Not Connected Pins B4 B10 C11 D1 K2 L4 U25 AB3 AC21 AC25 AE10 -

D7 K26 Y4 AF10 A14 B26 P26 AE26 AF19 B23 D16 L23 AC2 AD16 -

D13 N23 AC8 AF17 A19 E1 W1 AF1 AF22 C1 D25 T3 AC6 AD21 -

Pin Locations for XC4036EX/XL

4-128

March 30, 1998 (Version 1.5)

XC4036EX/XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC

PQ HQ 160 208 P13 P10 P14 P11 P15 P12 P16 P13 P17 P14 P18 P19 P20 P15 P21 P16 P22 P17 P23 P18 P24 P19 P25 P20 P26 P21 P27 P22 P28 P23 P29 P24 P30 P31 P32 P25 P33 P26 P34 P27 P35 P28 P36 P29 P37 P38 P39 P30 P40 P31 P41 P32 P42 P33 P43 P34 P44 P35 P45 P36 P46 P37 P47 P38 P48 P39 P49 P40 P50 P41 P55

HQ 240 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61

HQ 304 P292 P291 P290 P289 P288 P287 P286 P285 P284 P283 P282 P280 P279 P278 P277 P276 P275 P274 P273 P272 P271 P270 P269 P268 P267 P266 P265 P264 P263 P262 P261 P260 P259 P258 P257 P256 P255 P253 P252 P251 P250 P249 P248 P247 P246 P245 P244 P243 P242 P241 P240 P239 P238 P237 P236 P235 P234 P233 P232 P231 P230 P229 P228

BG 352 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* K24 J25 J26 L23 L24 K25 GND* VCC* L25 L26 M23 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 VCC* GND* T26 T25 T24 U25 T23 V26 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 GND* VCC* AB25 AA24 Y23 AC26 AD26 AC25 AA23 AB24 AD25 AC24 AB23 GND* AD24 VCC*

PG 411 F12 D10 B10 F10 F14 GND* C11 B12 E11 E15 VCC* F16 C13 B14 E17 E13 A15 GND* VCC* B16 D16 D18 A17 E19 B18 C17 C19 GND* VCC* F20 B20 C21 B22 E21 D22 A23 B24 VCC* GND* A25 D24 B26 A27 C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 F28 F30 C31 E31 GND* VCC* B32 A33 A35 F32 C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC*

BG Bndry 432 Scan H30 257 J28 260 J29 263 H31 266 J30 269 GND* K28 272 K29 275 K30 278 K31 281 VCC* L29 284 L30 287 M29 290 M31 293 N31 296 N28 299 GND* VCC* P30 302 P28 305 P29 308 R31 311 R30 314 R28 317 R29 320 T31 323 GND* VCC* T30 326 T29 329 U31 332 U30 335 U28 338 U29 341 V30 344 V29 347 VCC* GND* W30 350 W29 353 Y30 356 Y29 359 Y28 362 AA30 365 VCC* AA29 368 AB31 371 AB30 374 AB29 377 GND* AB28 380 AC30 383 AC29 386 AC28 389 AD29 392 AD28 395 AE30 398 AE29 401 GND* VCC* AF31 404 AE28 407 AG31 410 AF28 413 AG30 416 AG29 419 AH31 422 AG28 425 AH30 428 AJ30 431 AH29 434 GND* AH28 437 VCC* -

XC4036EX/XL Pad Name I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O

PQ HQ 160 208 P42 P56 P43 P57 P44 P58 P45 P59 P46 P60 P47 P61 P48 P62 P49 P63 P50 P64 P65 P66 P51 P67 P52 P68 P53 P69 P54 P70 P55 P71 P72 P73 P56 P74 P57 P75 P58 P76 P59 P77 P60 P78 P61 P79 P62 P80 P63 P81 P64 P82 P65 P83 P84 P85 P66 P86 P67 P87 P68 P88 P69 P89 P70 P90 P91 P92 P71 P93 P72 P94

HQ 240 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112

HQ 304 P227 P226 P225 P224 P223 P222 P221 P220 P219 P218 P217 P216 P215 P214 P213 P212 P211 P210 P209 P208 P207 P206 P204 P203 P202 P201 P200 P199 P198 P197 P196 P195 P194 P193 P192 P191 P190 P189 P188 P187 P186 P185 P184 P183 P182 P181 P180 P179 P178 P177 P175 P174 P173 P172 P171 P170 P169 P168 P167 P166 P165 P164 P163

BG 352 AC23 AE24 AD23 AC22 AF24 AD22 AE23 AC21 AD21 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 AC16 AD16 AE17 AE16 GND* VCC* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 VCC* GND* AE11 AD11 AE10 AC11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5

PG 411 G33 D36 C37 F34 J33 D38 G35 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 V38 W37 VCC* GND* Y34 AC37 AB38 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 AK36 AM34 AH34 AJ35

BG Bndry 432 Scan AJ28 438 AK29 439 AH27 442 AK28 445 AJ27 448 AL28 451 AH26 454 AL27 457 AH25 460 AK26 463 AL26 466 VCC* GND* AH24 469 AJ25 472 AK25 475 AJ24 478 AL24 481 AH22 484 AJ23 487 AK23 490 GND* AJ22 493 AK22 496 AL22 499 AJ21 502 VCC* AH20 505 AK21 508 AK20 511 AJ19 514 AL20 517 AH18 520 GND* VCC* AK19 523 AJ18 526 AL19 529 AK18 532 AH17 535 AJ17 538 AJ16 541 AK16 544 VCC* GND* AL16 547 AH15 550 AK15 553 AJ14 556 AH14 559 AK14 562 AL13 565 AK13 568 VCC* GND* AJ13 571 AH13 574 AL12 577 AK12 580 AH12 583 AJ11 586 VCC* AL10 589 AK10 592 AJ10 595 AK9 598 GND* AL8 601 AH10 604 AJ9 607 AK8 610 AK7 613 AL6 616 AJ7 619 AH8 622

March 30, 1998 (Version 1.5)

4-129

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4036EX/XL Pad Name GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O (D2) PQ 160 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 HQ 208 P95 P96 P97 P98 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 HQ 240 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 HQ 304 P162 P161 P160 P159 P158 P157 P156 P155 P154 P153 P152 P151 P150 P149 P148 P147 P146 P145 P144 P143 P142 P141 P140 P139 P138 P137 P136 P135 P134 P133 P132 P131 P130 P129 P127 P126 P125 P124 P123 P122 P121 P120 P119 P118 P117 P116 P115 P114 P113 P112 P111 P110 P109 P108 P107 P106 P105 P104 P103 BG 352 GND* VCC* AD6 AC7 AF4 AF3 AE4 AC6 AD5 AE3 AD4 AC5 GND* AD3 VCC* AC4 AD2 AC3 AB4 AD1 AB3 AC2 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 T4 T3 U2 T2 GND* VCC* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 M4 L1 VCC* GND* L2 L3 K2 L4 J1 PG 411 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 AN35 AL33 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 AP32 AU35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 AR27 AW27 AT24 AR23 GND* VCC* AP22 AV24 AU23 AT22 AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 AT18 AW17 AV16 AP18 VCC* GND* AR17 AT16 AV14 AW13 AR15 BG Bndry 432 Scan GND* VCC* AK6 625 AL5 628 AH7 631 AJ6 634 AK5 637 AL4 640 AK4 643 AH5 646 AK3 649 AJ4 652 GND* AH4 VCC* AH3 AJ2 655 AG4 658 AG3 661 AH2 664 AH1 667 AF4 670 AF3 673 AG2 676 AE3 679 AF2 682 VCC* GND* AF1 685 AD4 688 AD3 691 AE2 694 AC3 697 AD1 700 AC2 703 AB4 706 GND* AB3 709 AB2 712 AB1 715 AA3 718 VCC* AA2 721 Y2 724 Y4 727 Y3 730 W4 733 W3 736 GND* VCC* V4 739 V3 742 U1 745 U2 748 U4 751 U3 754 T1 757 T2 760 VCC* GND* T3 763 R1 766 R2 769 R4 772 R3 775 P2 778 P3 781 P4 784 VCC* GND* N3 787 N4 790 M1 793 M2 796 L2 799 XC4036EX/XL Pad Name I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/ BUSY) I/O I/O I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O (A6) I/O (A7) PQ 160 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 HQ 208 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 HQ 240 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 HQ 304 P102 P101 P99 P98 P97 P96 P95 P94 P93 P92 P91 P90 P89 P88 P87 P86 P85 P84 P83 P82 P81 P80 P79 P78 P77 P76 P75 P74 P73 P72 P71 P70 P69 P68 P67 P66 P65 P64 P63 P62 P61 P60 P59 P58 P57 P56 P55 P54 P52 P51 P50 P49 P48 P47 P46 P45 P44 P43 P42 P41 P40 BG 352 K3 VCC* J2 J3 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 D1 C1 D2 F4 E3 C2 D3 E4 C3 VCC* D4 GND* B3 C4 D5 A3 C5 B4 D6 C6 B5 A4 VCC* GND* C7 B6 A6 D8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* A9 D11 C11 B10 B11 A11 GND* VCC* D12 C12 B12 A12 C13 B13 A13 B14 PG BG Bndry 411 432 Scan AP16 L3 802 VCC* VCC* AV12 K1 805 AR13 K2 808 AU11 K3 811 AT12 K4 814 GND* GND* AP14 J2 817 AR11 J3 820 AV10 J4 823 AT8 H1 826 AT10 H2 829 AP10 H3 832 AP12 H4 835 AR9 G2 838 GND* GND* VCC* VCC* AU7 G4 841 AW7 F2 844 AW5 AV6 AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 AA3 Y6 F3 E1 E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 B16 A16 847 850 853 856 859 862 865 868 0 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 86 89 92 95 98 101 104 107

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March 30, 1998 (Version 1.5)

XC4036EX/XL Pad Name GND 6/17/97

PQ HQ 160 208 P141 P182

HQ 240 P211

HQ 304 P39

BG 352 GND*

PG BG Bndry 411 432 Scan GND* GND* -

PG411
A3 F36 AL39 AW29 A9 D20 P4 AF4 AT14 AW21 A13 C25 E7 G5 L35 W35 AF2 AN1 AT2 AU17 AW15 A11 J1 AP4 AW37 A19 D26 P36 AF36 AT20 AW31 B6 C33 E23 H34 N3 Y38 AF38 AN5 AT30 AU25 AW23 VCC Pins A21 A31 L39 W1 AT34 AU1 GND Pins A29 A37 D34 F4 W39 Y4 AJ39 AL1 AT26 AU39 Not Connected Pins B34 C7 D8 D12 E37 F2 J5 K36 P38 R3 AA37 AB2 AJ5 AK2 AP8 AP30 AU5 AU9 AU37 AV8 AW25 AW35 C39 AA39 AW9 C1 J39 Y36 AP36 AW3 C15 D30 F18 K38 V2 AC3 AK38 AP38 AU13 AV26 D6 AJ1 AW19 D14 L1 AA1 AT6 AW11 C23 D32 F22 L5 W5 AC39 AL35 AR37 AU15 AV34 -

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin.

= XL only

Additional XC4036EX/XL Package Pins

HQ208
P1 P54 P155 P207 P3 P102 P156 P208 Not Connected Pins P51 P104 P157 P52 P105 P158 P53 P107 P206 -

5/15/97

HQ240
P204 P219 GND Pins -

6/17/97

6/16/97

The Ground (GND) package pins in the above table should be externally connected to Ground if possible; however, they can be left unconnected if necessary for compatibility with other devices.

BG432
A1 D11 AA1 AJ3 A11 D21 AA4 AJ29 A3 A25 B31 J1 V1 AH16 AK31 AL18 A8 B21 D13 F4 M3 N29 W28 AD30 AH6 AJ12 AK24 VCC Pins A21 A31 L1 L4 AA28 AA31 AL1 AL11 GND Pins A7 A9 A29 A30 C1 C31 J31 P1 V31 AC1 AJ1 AJ31 AL2 AL3 AL23 AL25 Not Connected Pins A15 A28 B25 C8 D20 D23 F28 F29 M4 M28 N30 V2 W31 Y1 AD31 AE4 AH9 AH19 AJ15 AJ20 AK27 AL15 C3 L28 AH11 AL21 A14 B1 D16 P31 AC31 AK1 AL7 AL29 B8 C16 D26 F30 M30 V28 Y31 AF29 AH23 AJ26 AL17 C29 L31 AH21 AL31 A18 B2 G1 T4 AE1 AK2 AL9 AL30 B12 C17 E2 F31 N1 W1 AC4 AF30 AJ5 AK11 -

HQ304
P11 P176 P24 P205 Not Connected Pins P53 P254 P100 P281 P128 -

5/15/97

BG352
A10 D19 P4 AC14 A1 A22 E26 W26 AF2 AF25 C8 A17 G23 U1 AC20 A2 A25 H1 AB1 AF5 AF26 VCC Pins B2 B25 H4 K1 U26 W23 AE2 AE25 GND Pins A5 A8 A26 B1 H26 N1 AB26 AE1 AF8 AF13 Not Connected Pins D7 K26 Y4 AF10 A14 B26 P26 AE26 AF19 D13 N23 AC8 AF17 A19 E1 W1 AF1 AF22 -

A2 A23 B30 G31 T28 AE31 AK30 AL14 A4 B17 D6 F1 G3 N2 W2 AD2 AG1 AJ8 AK17

6/16/97

5/15/97

Pin Locations for XC4044XL Devices

(Note: XC4044XL is also available in the HQ304 package. The pinout is identical to the XC4036XL in the HQ304. )
XC4044XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O (A19) HQ 160 P142 P143 P144 P145 HQ 208 P183 P184 P185 P186 HQ 240 P212 P213 P214 P215 BG 352 VCC* D14 C14 A15 PG 411 VCC* W3 Y2 V2 W5 V4 BG 432 VCC* D17 A17 C17 B17 C18 XC4044XL Pad Name I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O HQ 160 P146 P147 P148 HQ 208 P187 P188 P189 P190 P191 HQ 240 P216 P217 P218 P220 P221 BG 352 B15 C15 D15 A16 B16 VCC* GND* C16 B17 PG 411 T2 U1 V6 U3 R1 VCC* GND* U5 T4 BG 432 D18 B18 A19 B19 C19 VCC* GND* D19 A20

March 30, 1998 (Version 1.5)

4-131

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4044XL Pad Name I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O HQ 160 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 HQ 208 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P204 P205 P2 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 HQ 240 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 BG 352 D16 A18 C17 B18 VCC* C18 D17 A20 B19 GND* C19 D18 A21 B20 C20 B21 B22 C21 GND* VCC* D20 A23 A24 B23 D21 C22 B24 C23 D22 C24 VCC* GND* D23 C25 D24 E23 C26 E24 D25 F23 F24 E25 VCC* GND* D26 G24 F25 F26 H23 H24 G25 G26 GND* J23 J24 H25 K23 VCC* K24 J25 J26 L23 L24 K25 GND* VCC* L25 L26 M23 PG 411 P2 N1 R5 M2 VCC* L3 T6 N5 M4 GND* K2 K4 P6 M6 L5 J5 J3 H2 H4 G3 GND* VCC* K6 G1 E1 E3 J7 H6 C3 D2 E5 G7 VCC* GND* H8 F6 B4 D4 B2 G9 F8 C5 A7 A5 VCC* GND* C7 D8 B8 C9 E9 F12 D10 B10 F10 F14 GND* C11 B12 E11 E15 VCC* F16 C13 B14 E17 E13 A15 GND* VCC* F18 C15 B16 D16 D18 BG 432 B20 C20 C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 XC4044XL Pad Name I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O HQ 160 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 HQ 208 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 HQ 240 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 BG 352 M24 M25 M26 N24 N25 GND* VCC* N26 P25 P23 P24 R26 R25 R24 R23 VCC* GND* T26 T25 T24 U25 T23 V26 VCC* U24 V25 V24 U23 GND* Y26 W25 W24 V23 AA26 Y25 Y24 AA25 GND* VCC* AB25 AA24 Y23 AC26 AD26 AC25 AA23 AB24 AD25 AC24 AB23 GND* AD24 VCC* AC23 AE24 AD23 AC22 AF24 AD22 AE23 AC21 AD21 AE22 AF23 VCC* GND* AD20 AE21 AF21 AC19 PG 411 A17 E19 B18 C17 C19 GND* VCC* F20 B20 C21 B22 E21 D22 A23 B24 C23 F22 VCC* GND* A25 D24 B26 A27 C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 D30 D32 F28 F30 C31 E31 GND* VCC* B32 A33 A35 F32 C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC* G33 D36 C37 F34 J33 D38 G35 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 K36 BG 432 R31 R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30 U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 Y30 Y29 Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AG31 AF28 AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23

4-132

March 30, 1998 (Version 1.5)

XC4044XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O

HQ 160 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76

HQ 208 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98

HQ 240 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116

BG 352 AD19 AE20 AF20 AC18 GND* AD18 AE19 AC17 AD17 VCC* AE18 AF18 AC16 AD16 AE17 AE16 GND* VCC* AF16 AC15 AD15 AE15 AF15 AD14 AE14 AF14 VCC* GND* AE13 AC13 AD13 AF12 AE12 AD12 AC12 AF11 VCC* GND* AE11 AD11 AE10 AC11 AF9 AD10 VCC* AE9 AD9 AC10 AF7 GND* AE8 AD8 AC9 AF6 AE7 AD7 AE6 AE5 GND* VCC* AD6 AC7 AF4 AF3 AE4 AC6 AD5 AE3

PG 411 K38 N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 W35 AC39 V38 W37 VCC* GND* Y34 AC37 Y38 AA37 AB38 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 AK38 AP38 AK36 AM34 AH34 AJ35 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 AN35 AL33

BG 432 AK24 AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 AK4 AH5

XC4044XL Pad Name I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O (D2) I/O VCC I/O I/O

HQ 160 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109

HQ 208 P99 P100 P101 P103 P106 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141

HQ 240 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163

BG 352 AD4 AC5 GND* AD3 VCC* AC4 AD2 AC3 AB4 AD1 AB3 AC2 AA4 AA3 AB2 AC1 VCC* GND* Y3 AA2 AA1 W4 W3 Y2 Y1 V4 GND* V3 W2 U4 U3 VCC* V2 V1 T4 T3 U2 T2 GND* VCC* T1 R4 R3 R2 R1 P3 P2 P1 VCC* GND* N2 N4 N3 M1 M2 M3 M4 L1 VCC* GND* L2 L3 K2 L4 J1 K3 VCC* J2 J3

PG 411 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 AP32 AU35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AP30 AT30 AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 AR27 AW27 AT24 AR23 GND* VCC* AW25 AW23 AP22 AV24 AU23 AT22 AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 AT18 AW17 AV16 AP18 AU17 AW15 VCC* GND* AR17 AT16 AV14 AW13 AR15 AP16 VCC* AV12 AR13

BG 432 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 AF3 AG2 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2 Y4 Y3 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 L2 L3 VCC* K1 K2

March 30, 1998 (Version 1.5)

4-133

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4044XL Pad Name I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O I/O (CS1,A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) I/O I/O I/O (A6) I/O (A7) HQ 160 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 HQ 208 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 HQ 240 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206 P207 P208 P209 P210 BG 352 K4 G1 GND* H2 H3 J4 F1 G2 G3 F2 E2 GND* VCC* F3 G4 D1 C1 D2 F4 E3 C2 D3 E4 C3 VCC* D4 GND* B3 C4 D5 A3 C5 B4 D6 C6 B5 A4 VCC* GND* C7 B6 A6 D8 C8 B7 A7 D9 C9 GND* B8 D10 C10 B9 VCC* A9 D11 C11 B10 B11 A11 GND* VCC* D12 C12 B12 A12 C13 B13 A13 B14 PG 411 AU11 AT12 GND* AP14 AR11 AV10 AT8 AT10 AP10 AP12 AR9 AU9 AV8 GND* VCC* AU7 AW7 AW5 AV6 AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AN1 AK2 AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 AB2 AC3 AA3 Y6 BG 432 K3 K4 GND* J2 J3 J4 H1 H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 A15 C16 B16 A16 XC4044XL Pad Name GND 6/18//97 HQ 160 P141 HQ 208 P182 HQ 240 P211 BG 352 GND* PG 411 GND* BG 432 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin.

Additional XC4044XL Package Pins

HQ208
P1 P104 P206 P3 P105 P207 Not Connected Pins P51 P52 P53 P107 P155 P156 P208 P54 P157 P102 P158 -

5/29/97

HQ240
P204 P219 GND Pins -

5/29/97

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.

BG352
A10 G23 U26 AE25 A1 A25 H26 AE1 AF19 A17 H4 W23 AF10 A2 A26 N1 AE26 AF22 B2 K1 Y4 AF17 A5 B1 P26 AF1 AF25 VCC Pins B25 K26 AC8 GND Pins A8 B26 W1 AF2 AF26 D7 N23 AC14 A14 E1 W26 AF5 D13 P4 AC20 A19 E26 AB1 AF8 D19 U1 AE2 A22 H1 AB26 AF13 -

6/13/97

PG411
A3 J1 AT34 A9 D26 W39 AL1 AW3 A13 E23 P38 AP8 AU37 A11 L39 AU1 A19 D34 Y4 AP36 AW11 B6 E37 R3 AR37 AV26 VCC Pins A31 C39 AA39 AJ1 AW19 AW29 GND Pins A29 A37 C1 F4 J39 L1 Y36 AA1 AF4 AT6 AT14 AT20 AW21 AW31 Not Connected Pins B34 C25 C33 F2 G5 H34 AF2 AF38 AJ5 AT2 AU5 AU13 AV34 AW35 A21 W1 AW9 D6 AL39 AW37 D14 P4 AF36 AT26 D12 L35 AL35 AU15 F36 AP4 D20 P36 AJ39 AU39 E7 N3 AN5 AU25 -

6/2/97

4-134

March 30, 1998 (Version 1.5)

BG432
A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 A4 D20 M4 AE4 AJ12 A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 A28 D26 M28 AF29 AJ20 A21 L4 AH11 AL31 VCC Pins A31 C3 L28 L31 AH21 AJ3 GND Pins A7 A9 A14 A30 B1 B2 D16 G1 G31 T4 T28 V1 AE31 AH16 AJ1 AK31 AL2 AL3 AL23 AL25 AL29 Not Connected Pins B12 B21 C8 E2 F4 F28 M30 W1 W28 AF30 AG1 AH6 AJ26 AK11 AK27 C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 D6 F29 Y1 AH19 D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 D13 M3 Y31 AJ5 -

5/29/97

Pin Locations for XC4052XL Devices

(Note: XC4052XL is also available in the HQ304 package. The pinout is identical to the XC4036XL in HQ304.)
XC4052XL Pad Name GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O HQ 240 P234 P235 P236 P237 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 PG 411 GND* VCC* K6 G1 E1 E3 F2 G5 GND* J7 H6 C3 D2 E5 G7 VCC* GND* H8 F6 B4 D4 B2 G9 GND* E7 B6 F8 C5 A7 A5 VCC* GND* C7 D8 B8 C9 E9 F12 GND* D10 B10 F10 F14 GND* C11 BG 432 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 GND* J28 J29 H31 J30 GND* K28 BG 560 GND* VCC* C28 D27 B30 C29 E27 A31 GND* D28 C30 D29 E28 D30 E29 VCC* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29 VCC* GND* H30 G31 J29 F33 G32 J30 GND* K30 H33 L29 K31 GND* L30

XC4052XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13)

HQ 240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233

PG 411 VCC* W3 Y2 V2 W5 GND* V4 T2 U1 V6 U3 R1 VCC* GND* U5 T4 P2 N1 R3 N3 GND* R5 M2 VCC* L3 T6 N5 M4 GND* K2 K4 P6 M6 GND* L5 J5 J3 H2 H4 G3

BG 432 VCC* D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 GND* C21 A22 VCC* B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* D23 B25 A26 C25 D24 B26

BG 560 VCC* A17 B18 C18 E18 GND* C19 D19 E19 B20 C20 D20 VCC* GND* A21 E20 B21 C21 D21 B22 GND* C23 E22 VCC* B24 D23 C24 A25 GND* E23 B25 D24 C25 GND* E25 C27 D26 B28 B29 E26

March 30, 1998 (Version 1.5)

4-135

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4052XL Pad Name I/O I/O, TMS I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O HQ 240 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 PG 411 B12 E11 E15 VCC* F16 C13 GND* A13 D12 B14 E17 E13 A15 GND* VCC* F18 C15 B16 D16 D18 A17 GND* E19 B18 C17 C19 GND* VCC* F20 B20 C21 B22 GND* E21 D22 A23 B24 C23 F22 VCC* GND* A25 D24 E23 C25 B26 A27 GND* C27 F24 VCC* E25 E27 B28 C29 GND* F26 D28 B30 E29 GND* D30 D32 F28 F30 C31 E31 GND* VCC* B32 BG 432 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 BG 560 K32 J33 M29 VCC* L32 M31 GND* N29 L33 M32 P29 P30 N33 GND* VCC* P31 P32 R29 R30 R31 R33 GND* T31 T29 U32 U31 GND* VCC* U29 U30 V31 V29 GND* V30 W33 W31 W30 W29 Y32 VCC* GND* Y31 Y30 AA32 AA31 AA30 AB32 GND* AA29 AB31 VCC* AC31 AB29 AD32 AC30 GND* AD31 AE33 AC29 AE32 GND* AG33 AH33 AE29 AG31 AF30 AH32 GND* VCC* AJ32 XC4052XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O HQ 240 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 PG 411 A33 C33 B34 A35 F32 GND* C35 B38 E33 G31 H32 B36 A39 GND* E35 VCC* G33 D36 C37 F34 J33 D38 G35 GND* E37 H34 E39 K34 F38 G37 VCC* GND* H38 J37 G39 M34 K36 K38 GND* N35 P34 J35 L37 GND* M38 R35 H36 T34 VCC* N37 N39 GND* P38 L35 U35 R39 M36 V34 GND* VCC* R37 T38 T36 V36 U37 U39 GND* W35 AC39 V38 BG 432 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 BG 560 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30 AH29 AK30 GND* AJ29 VCC* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30 VCC* GND* AM29 AK26 AL27 AJ25 AN29 AN28 GND* AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCC* AM24 AK22 GND* AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCC* AL20 AJ19 AM20 AK19 AL19 AN19 GND* AL18 AM18 AK17

4-136

March 30, 1998 (Version 1.5)

XC4052XL Pad Name I/O (INIT) VCC GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O

HQ 240 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128

PG 411 W37 VCC* GND* Y34 AC37 Y38 AA37 GND* AB38 AD36 AA35 AE37 AB36 AD38 VCC* GND* AB34 AE39 AM36 AC35 AL35 AF38 GND* AG39 AG37 VCC* AD34 AN39 AE35 AH38 GND* AJ37 AG35 AF34 AH36 GND* AK38 AP38 AK36 AM34 AH34 AJ35 GND* VCC* AL37 AT38 AM38 AN37 AK34 AR39 GND* AR37 AU37 AN35 AL33 AV38 AT36 GND* AR35 VCC* AN33 AM32 AP34 AW39 AN31 AV36 AR33 GND* AP32 AU35

BG 432 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2

BG 560 AJ17 VCC* GND* AL17 AM17 AN17 AK16 GND* AM16 AL15 AK15 AJ15 AN15 AM14 VCC* GND* AL14 AK14 AJ14 AN13 AM13 AL13 GND* AK12 AN11 VCC* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 GND* AN7 AJ9 AL7 AK8 AN6 AM6 GND* VCC* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCC* AM1 AH5 AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2

XC4052XL Pad Name I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O VCC

HQ 240 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161

PG 411 AV34 AW35 AW33 AU33 VCC* GND* AV32 AU31 AR31 AP28 AP30 AT30 GND* AT32 AV30 AR29 AP26 GND* AU29 AV28 AT28 AR25 VCC* AP24 AU27 GND* AR27 AW27 AU25 AV26 AT24 AR23 GND* VCC* AW25 AW23 AP22 AV24 AU23 AT22 GND* AR21 AV22 AP20 AU21 VCC* GND* AU19 AV20 AV18 AR19 GND* AT18 AW17 AV16 AP18 AU17 AW15 VCC* GND* AR17 AT16 AV14 AW13 AU15 AU13 GND* AR15 AP16 VCC*

BG 432 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC*

BG 560 AG4 AH3 AF5 AJ2 VCC* GND* AJ1 AF4 AG3 AE5 AH1 AF3 GND* AE3 AC5 AE1 AD3 GND* AC4 AD2 AB5 AC3 VCC* AA5 AB3 GND* AB2 AA4 AA3 Y5 Y3 Y2 GND* VCC* W5 W4 W3 W1 V3 V5 GND* V4 V2 U5 U4 VCC* GND* U3 T2 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCC* GND* N1 P5 N2 N3 N5 M3 GND* M4 L1 VCC*

March 30, 1998 (Version 1.5)

4-137

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4052XL Pad Name I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND HQ 240 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 PG 411 AV12 AR13 AU11 AT12 GND* AP14 AR11 AV10 AT8 GND* AT10 AP10 AP12 AR9 AU9 AV8 GND* VCC* AU7 AW7 AW5 AV6 AU5 AP8 GND* AR7 AV4 AN9 AW1 AP6 AU3 AR5 VCC* AN7 GND* AT4 AV2 AM8 AL7 AT2 AN5 GND* AR3 AR1 AK6 AN3 AM6 AM2 VCC* GND* AL3 AH6 AP2 AK4 AN1 AK2 GND* AG5 AF6 AL5 AJ3 GND* AH2 AE5 AM4 AD6 VCC* AG3 AG1 GND* BG 432 K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* BG 560 K2 L4 J1 K3 GND* L5 J2 K4 J3 GND* G1 F1 J5 G3 H4 F2 GND* VCC* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCC* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCC* GND* D8 C7 E9 A6 B7 D9 GND* E11 A9 C10 D11 GND* B10 E12 C11 B11 VCC* D12 A11 GND* XC4052XL Pad Name I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O (A6) I/O (A7) GND 6/20/97 HQ 240 P202 P203 P205 P206 P207 P208 P209 P210 P211 PG 411 AF2 AJ5 AC5 AE1 AH4 AB6 GND* VCC* AD2 AB4 AE3 AC1 AD4 AA5 GND* AB2 AC3 AA3 Y6 GND* BG 432 D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND* BG 560 C13 E14 A13 D14 C14 B14 GND* VCC* E15 D15 C15 A15 C16 E16 GND* B17 C17 E17 D17 GND*

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin.

Additional XC4052XL Package Pins

HQ240 GND Pins

P204 6/3/97

P219

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.
PG411 VCC Pins

A3 J1 AT34 A9 D26 W39 AL1 AW3 6/3/97

BG432

A11 L39 AU1 A19 D34 Y4 AP36 AW11

A21 W1 AW9 A29 F4 Y36 AT6 AW21

A31 AA39 AW19

GND Pins

C39 AJ1 AW29 C1 LI AF4 AT20 -

D6 AL39 AW37 D14 P4 AF36 AT26 -

F36 AP4 D20 P36 AJ39 AU39 -

A37 J39 AA1 AT14 AW31

VCC Pins

A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 C8 6/3/97

A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 -

A21 L4 AH11 AL31 A7 A30 D16 T4 AE31 AK31 AL23 -

A31 L28 AH21 GND Pins

C3 L31 AJ3 A14 B2 G31 V1 AJ1 AL3 AL29 -

C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 -

D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 -

A9 B1 G1 T28 AH16 AL2 AL25 -

Not Connected Pins

4-138

March 30, 1998 (Version 1.5)

PG560 VCC Pins

A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 K1 V33 AE2 AM7 AN5 A1 B8 C22 D25 E33 J31 M30 T32 AA1 AD4 AF1 AJ16 AK24 AL26 AN1 6/20/97

A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 L2 W2 AG1 AM11 AN10 A8 B12 C26 E2 H2 K5 N4 U1 AA33 AD5 AF2 AJ18 AK25 AM8 AN23

A16 B32 H1 W32 AK33 AM32 A14 B6 E1 M33 Y1 AG32 AM19 AN14 A19 B16 D10 E10 H3 K29 N30 U2 AB4 AD29 AF31 AJ21 AL8 AM9 AN33

A22 C3 K33 AA2 AL2 AN4 GND Pins

A26 C31 M1 AB33 AL3 AN8 A20 B15 G2 P33 AB1 AJ33 AM28 AN20 A27 C8 D16 E21 H31 L31 T3 V32 AC1 AE4 AG2 AK9 AL12 AM23 -

A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 R32 AC32 AL32 AM33 AN22 A28 C9 D18 E24 H32 M2 T5 Y4 AC2 AE30 AJ10 AK13 AL16 AM26 -

B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 T1 AD33 AM3 AN2 AN27 A33 C12 D22 E32 J4 M5 T30 Y29 AC33 AE31 AJ13 AK18 AL22 AM27 -

A18 B9 F32 P1 Y33 AH2 AM25 AN16 A23 B26 D13 E13 H5 L3 N31 U33 AB30 AD30 AF32 AJ24 AL9 AM12 -

Not Connected Pins

Pin Locations for XC4062XL Devices

(Note: XC4062XL is also available in the HQ304 package. The pinout is identical to the XC4036XL in HQ304.)
XC4062XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O GND I/O (A19) I/O (A18) I/O I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O HQ240 P212 P213 P214 P215 P216 P217 P218 P220 P221 P222 P223 BG432 VCC* D17 A17 C17 B17 GND* C18 D18 B18 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 GND* C21 A22 VCC* B22 PG475 VCC* Y2 Y4 W5 Y6 U3 W3 GND* W1 U5 W7 U7 V2 V4 VCC* GND* V6 R1 T6 R3 R5 T4 GND* P2 N1 VCC* N3 BG560 VCC* A17 B18 C18 E18 D18 A19 GND* C19 D19 E19 B20 C20 D20 VCC* GND* A21 E20 B21 C21 D21 B22 GND* C23 E22 VCC* B24 XC4062XL Pad Name I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O HQ240 P224 P225 P226 P227 P228 P229 P230 P231 P232 P233 P234 P235 P236 P237 BG432 C22 B23 A24 GND* D22 C23 B24 C24 GND* D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 PG475 P4 R7 M2 GND* M4 L3 N5 K2 L5 J1 GND* M6 K4 J3 J5 H2 G1 GND* VCC* L7 K6 E1 H4 G5 F2 GND* H6 C3 F4 C5 BG560 D23 C24 A25 GND* E23 B25 D24 C25 B26 E24 GND* E25 C27 D26 B28 B29 E26 GND* VCC* C28 D27 B30 C29 E27 A31 GND* D28 C30 D29 E28

March 30, 1998 (Version 1.5)

4-139

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4062XL Pad Name I/O (A14) I/O GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O, TDI I/O, TCK GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O, TMS I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O XC4062XL Pad Name GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O

HQ240 P238 P239 P240 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34

BG432 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29 VCC* GND* F30 F31 H28 H29 G30 H30 GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31 U30

PG475 E3 E5 VCC* GND* G7 D4 A5 B4 D6 F8 GND* B6 E7 D8 G9 E9 A7 VCC* GND* B8 C9 G11 D10 E11 A9 GND* B10 C11 F12 D12 A11 G15 GND* B12 E13 C13 A13 VCC* B14 C15 GND* G17 F14 D16 D14 A15 C17 GND* VCC* D18 B18 F16 G19 E17 E19 GND* A19 F18 C19 D20 F20 B20 GND* VCC* C21 A21 D22 B22 E23 F22

BG560 D30 E29 VCC* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29 VCC* GND* H30 G31 J29 F33 G32 J30 GND* H32 J31 K30 H33 L29 K31 GND* L30 K32 J33 M29 VCC* L32 M31 GND* N29 L33 M32 P29 P30 N33 GND* VCC* P31 P32 R29 R30 R31 R33 GND* T31 T29 T30 T32 U32 U31 GND* VCC* U29 U30 U33 V32 V31 V29

HQ240 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 P49 P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P60 P61 P62 P63 P64 P65 P66 P67 P68 -

BG432 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26

PG475 GND* C23 F24 A23 E25 G23 B24 VCC* GND* D24 C25 D28 A27 E29 C27 GND* G25 D26 VCC* F26 B28 D30 A29 GND* C29 G27 F30 B30 E31 C31 GND* F28 D32 B32 G31 A33 C33 GND* VCC* B34 A35 E33 D34 D36 B36 GND* F34 D38 C37 G37 B38 F38 A39 GND* E35 VCC* G33 J37 G35 K36 C39 K38 C41 GND* D40 L37 H36 M36 J35 E41

BG560 GND* V30 W33 W31 W30 W29 Y32 VCC* GND* Y31 Y30 AA32 AA31 AA30 AB32 GND* AA29 AB31 VCC* AC31 AB29 AD32 AC30 GND* AD31 AE33 AC29 AE32 AD30 AE31 GND* AG33 AH33 AE29 AG31 AF30 AH32 GND* VCC* AJ32 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30 AH29 AK30 GND* AJ29 VCC* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30

4-140

March 30, 1998 (Version 1.5)

XC4062XL Pad Name VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I//O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O

HQ240 P69 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P80 P81 P82 P83 P84 P85 P86 P87 P88 P89 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99

BG432 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12

PG475 VCC* GND* F40 H38 N37 L35 R35 G41 GND* H40 P38 J39 R37 J41 K40 GND* L39 M38 T36 M40 VCC* N39 N41 GND* P40 T38 U35 U37 R39 R41 GND* VCC* V36 U39 V38 V40 W37 W35 GND* W41 Y36 W39 AB36 Y40 Y38 VCC* GND* AA39 AB38 AB40 AC37 AC39 AC41 GND* AD36 AC35 AE37 AD40 AD38 AE39 VCC* GND* AG41 AG39 AG37 AE35 AH38 AF38 GND* AF36

BG560 VCC* GND* AM29 AK26 AL27 AJ25 AN29 AN28 GND* AM26 AK24 AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCC* AM24 AK22 GND* AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCC* AL20 AJ19 AM20 AK19 AL19 AN19 GND* AJ18 AK18 AL18 AM18 AK17 AJ17 VCC* GND* AL17 AM17 AN17 AK16 AJ16 AL16 GND* AM16 AL15 AK15 AJ15 AN15 AM14 VCC* GND* AL14 AK14 AJ14 AN13 AM13 AL13 GND* AK12

XC4062XL Pad Name I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O

HQ240 P100 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 P111 P112 P113 P114 P115 P116 P117 P118 P119 P120 P121 P122 P123 P124 P125 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137

BG432 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* AJ8 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 GND* AC3 AD1 AC2 AB4 GND* AB3 AB2

PG475 AH40 VCC* AJ41 AJ39 AJ37 AG35 GND* AK40 AK38 AL37 AL39 AM38 AM40 GND* AN41 AM36 AK36 AU41 AN39 AP40 GND* VCC* AR41 AL35 AV40 AN37 AT38 AP38 GND* AT40 AW39 AP36 AU37 AR37 AU39 GND* AR35 VCC* AN35 AU35 AV38 AT34 BA39 AU33 AY38 GND* AV36 AR31 AR33 AV32 BA37 AY36 VCC* GND* AV34 BA35 AU31 AY34 AT30 AW33 GND* BA33 AV30 AY32 AU29 AW31 BA31 GND* AR27 AT28

BG560 AN11 VCC* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 AM9 AL9 GND* AN7 AJ9 AL7 AK8 AN6 AM6 GND* VCC* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCC* AM1 AH5 AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2 AG4 AH3 AF5 AJ2 VCC* GND* AJ1 AF4 AG3 AE5 AH1 AF3 GND* AF1 AD4 AE3 AC5 AE1 AD3 GND* AC4 AD2

March 30, 1998 (Version 1.5)

4-141

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4062XL Pad Name I/O I/O VCC I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O XC4062XL Pad Name I/O I/O GND VCC I/O (D1) I/O (RCLK, RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O

HQ240 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 P150 P151 P152 P153 P154 P155 P156 P157 P158 P159 P160 P161 P162 P163 P164 P165 P166 P167 P168 P169 P170 P171 P172

BG432 AB1 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC* K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* H2 H3 H4 G2

PG475 AY30 AW29 VCC* BA29 AY28 GND* AR25 AV28 AW27 AT26 AV26 BA27 GND* VCC* AW25 AV24 AU25 AR23 AT24 AY24 GND* BA23 AU23 AW23 AV20 AY22 AV22 VCC* GND* AW21 BA21 AU19 AY20 AU17 AW19 GND* BA19 AT16 AR19 AV14 AY18 AV18 VCC* GND* AT18 AW17 AR15 BA15 AT14 AR17 GND* AW15 AV16 VCC* AY14 BA13 AU13 AW13 GND* AY12 BA11 AV12 AT12 AW11 AY10 GND* BA9 AU11 AW9 AV10

BG560 AB5 AC3 VCC* AA5 AB3 GND* AB2 AA4 AA3 Y5 Y3 Y2 GND* VCC* W5 W4 W3 W1 V3 V5 GND* V4 V2 U2 U1 U5 U4 VCC* GND* U3 T2 T3 T5 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCC* GND* N1 P5 N2 N3 N5 M3 GND* M4 L1 VCC* K2 L4 J1 K3 GND* L5 J2 K4 J3 H2 K5 GND* G1 F1 J5 G3

HQ240 P173 P174 P175 P176 P177 P178 P179 P180 P181 P182 P183 P184 P185 P186 P187 P188 P189 P190 P191 P192 P193 P194 P195 P196 P197 P198 P199 P200 P201 P202 P203 P205 P206

BG432 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7 B7 D9 B8 A8 GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15

PG475 AY8 BA7 GND* VCC* AV8 AY6 AR11 AT8 AU9 AW5 GND* AY4 BA5 AV4 AR9 AU5 AV6 AR5 VCC* AN7 GND* AR7 AW3 AU3 AW1 AP6 AV2 GND* AT4 AN5 AU1 AM6 AT2 AL7 VCC* GND* AR1 AP2 AM4 AN3 AL5 AK6 GND* AN1 AJ5 AM2 AH4 AL3 AK4 GND* AG7 AG5 AK2 AJ3 VCC* AJ1 AF6 GND* AH2 AF4 AE7 AE5 AG3 AG1 GND* VCC* AD6 AD4 AE3 AC5

BG560 H4 F2 GND* VCC* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCC* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCC* GND* D8 C7 E9 A6 B7 D9 GND* D10 C9 E11 A9 C10 D11 GND* B10 E12 C11 B11 VCC* D12 A11 GND* C13 E14 A13 D14 C14 B14 GND* VCC* E15 D15 C15 A15

4-142

March 30, 1998 (Version 1.5)

XC4062XL Pad Name I/O (A21) I/O (A20) GND I/O I/O I/O I/O I/O (A6) I/O (A7) GND 6/16/97

HQ240 P207 P208 P209 P210 P211

BG432 C15 B15 GND* A15 C16 B16 A16 GND*

PG475 AD2 AC7 GND* AC1 AC3 AB6 AB2 AB4 AA3 GND*

BG560 C16 E16 GND* D16 B16 B17 C17 E17 D17 GND*

PG475
VCC Pins

A37 E21 N35 AA41 AR29 AW41 A3 U1 AH6 E15 L41 AL41 AU15 E37 5/5/97

B2 F6 T2 AF2 AT6 AY2 C1 A17 AL1 E27 P36 AR21 AU27 E39

* Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin.

B16 B26 F36 G13 T40 AA1 AF40 AJ7 AT22 AT36 AY16 AY26 GND Pins C7 G3 A25 A41 AR3 AW7 F10 F32 U41 AA35 AR39 AT10 AW35 BA17 A31 J7

B40 G29 AA5 AJ35 AU21 AY40 L1 AA7 BA1 G21 AE41 AT20 BA25 AP4

D2 N7 AA37 AR13 AW37 BA3 P6 AE1 C35 G39 AH36 AT32 BA41 AU7

Additional XC4062XL Package Pins

HQ240 GND Pins P204 5/5/97 P219 -

BG560
VCC Pins

Note: These pins may be Not Connected for this device revision, however for compatability with other devices in this package, these pins should be tied to GND.

BG432
VCC Pins

A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 K1 V33 AE2 AM11 AN5 A1 B12 D25 H3 M2 Y29 AC33 AF32 AK13 AM12 5/5/97

A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 L2 W2 AG1 AM19 AN10 A8 C8 E2 H5 M5 AA1 AD5 AG2 AK25 AM23

A16 B32 H1 W32 AK33 AM32 -

A1 D21 AA28 AL11 A2 A25 C1 P1 AC31 AK2 AL14 C8 5/5/97

A11 L1 AA31 AL21 A3 A29 C31 P31 AE1 AK30 AL18 -

A21 L4 AH11 AL31

A31 C3 L28 L31 AH21 AJ3 GND Pins A7 A9 A14 A30 B1 B2 D16 G1 G31 T4 T28 V1 AE31 AH16 AJ1 AK31 AL2 AL3 AL23 AL25 AL29 Not Connected Pins -

C29 AA1 AJ29 A18 B30 J1 V31 AJ31 AL7 AL30 -

D11 AA4 AL1 A23 B31 J31 AC1 AK1 AL9 -

A22 A26 C3 C31 K33 M1 AA2 AB33 AL2 AL3 AN4 AN8 GND Pins A14 A18 A20 B6 B9 B15 E1 F32 G2 M33 P1 P33 Y1 Y33 AB1 AG32 AH2 AJ33 AM25 AM28 AM33 AN14 AN16 AN20 Not Connected Pins A23 A27 A28 C12 C22 C26 E10 E13 E21 H31 J4 K29 M30 N4 N30 AA33 AB4 AB30 AD29 AE4 AE30 AJ10 AJ13 AJ21 AL8 AL12 AL22 AM27 AN1 AN23

A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 R32 AC32 AL32 AM7 AN22 A33 D13 E32 L3 N31 AC1 AF2 AJ24 AL26 AN33

B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 T1 AD33 AM3 AN2 AN27 B8 D22 E33 L31 Y4 AC2 AF31 AK9 AM8 -

Pin Locations for XC4085XL Devices

XC4085XL Pad Name VCC I/O (A8) I/O (A9) I/O I/O I/O I/O GND I/O (A19) I/O (A18) I/O BG432 VCC D17 A17 C17 B17 GND* C18 D18 B18 BG560 VCC* A17 B18 C18 E18 D18 A19 GND* C19 D19 E19 PG559 VCC* AB6 AB4 AA7 AC1 AA5 AA3 GND* Y8 AB2 Y6 XC4085XL Pad Name I/O I/O (A10) I/O (A11) VCC GND I/O I/O I/O I/O I/O I/O I/O BG432 A19 B19 C19 VCC* GND* D19 A20 B20 C20 B21 D20 BG560 B20 C20 D20 VCC* GND* A21 E20 B21 C21 D21 B22 E21 PG559 AA1 Y4 W7 VCC* GND* W5 V6 V4 Y2 U3 U7 V2

March 30, 1998 (Version 1.5)

4-143

XC4000E and XC4000X Series Field Programmable Gate Arrays XC4085XL Pad Name I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O (A12) I/O (A13) GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (A14) I/O, GCK8 (A15) VCC GND I/O, GCK1 (A16) I/O (A17) I/O I/O I/O (TDI) I/O (TCK) GND I/O I/O I/O I/O I/O I/O XC4085XL Pad Name VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O (TMS) I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

BG432 GND* C21 A22 VCC B22 C22 B23 A24 GND* D22 C23 B24 C24 GND* VCC* D23 B25 A26 C25 D24 B26 GND* VCC* A27 D25 C26 B27 A28 D26 GND* C27 B28 D27 B29 C28 D28 VCC* GND* D29 C30 E28 E29 D30 D31 GND* F28 F29 E30 E31 G28 G29

BG560 C22 GND* D22 A23 C23 E22 VCC* B24 D23 C24 A25 GND* E23 B25 D24 C25 B26 E24 C26 D25 GND* VCC* A27 A28 E25 C27 D26 B28 B29 E26 GND* VCC* C28 D27 B30 C29 E27 A31 GND* D28 C30 D29 E28 D30 E29 VCC* GND* B33 F29 E30 D31 F30 C33 GND* G29 E31 D32 G30 F31 H29

PG559 U5 GND* T4 U1 R3 R5 VCC* T8 T2 P4 R7 GND* N3 R1 N5 P2 M4 L1 L3 P8 GND* VCC* N7 K2 M6 J1 L5 H2 K4 J3 GND* VCC* L7 J5 G1 H4 F2 G5 GND* H6 K8 D2 J7 F4 E3 VCC* GND* C1 C3 F6 A3 H8 D4 GND* D6 C5 E7 B4 H10 G9

BG432 VCC* GND* F30 F31 H28 H29 G30 H30 VCC* GND* J28 J29 H31 J30 GND* K28 K29 K30 K31 VCC* L29 L30 GND* M30 M28 M29 M31 N31 N28 GND* VCC* N29 N30 P30 P28 P29 R31 GND* R30 R28 R29 T31 GND* VCC* T30 T29 U31

BG560 VCC* GND* E32 E33 H30 G31 J29 F33 G32 J30 VCC* GND* H31 K29 H32 J31 K30 H33 L29 K31 GND* L30 K32 J33 M29 VCC* L31 M30 L32 M31 GND* N29 L33 N30 N31 M32 P29 P30 N33 GND* VCC* P31 P32 R29 R30 R31 R33 GND* T31 T29 T30 T32 U32 U31 GND* VCC* U29 U30 U33 V32 V31

PG559 VCC* GND* F8 D8 B6 E9 A7 G11 H14 F12 VCC* GND* G13 E11 B8 D10 A9 G15 B10 H16 GND* C9 E13 A11 D12 VCC* C11 B14 G17 E15 GND* D14 A15 C13 B16 E17 F18 A17 G19 GND* VCC* D16 C15 B18 H20 B20 E19 GND* D18 F20 G21 C17 D20 E21 GND* VCC* C21 F22 A21 D22 B22

4-144

March 30, 1998 (Version 1.5)

XC4085XL Pad Name I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O

BG432 U30 GND* U28 U29 V30 V29 V28 W31 VCC* GND* W30 W29 W28 Y31 Y30 Y29 GND* Y28 AA30 VCC* AA29 AB31 AB30 AB29 GND* AB28 AC30 AC29 AC28 GND* VCC* AD31 AD30 AD29 AD28 AE30 AE29 GND* VCC* AF31 AE28 AF30 AF29 AG31 AF28 GND* AG30 AG29 AH31 AG28 AH30

BG560 V29 GND* V30 W33 W31 W30 W29 Y32 VCC* GND* Y31 Y30 AA33 Y29 AA32 AA31 AA30 AB32 GND* AA29 AB31 AB30 AC33 VCC* AC31 AB29 AD32 AC30 GND* AD31 AE33 AC29 AE32 AD30 AE31 AF32 AD29 GND* VCC* AF31 AE30 AG33 AH33 AE29 AG31 AF30 AH32 GND* VCC* AJ32 AF29 AH31 AG30 AK32 AJ31 GND* AG29 AL33 AH30 AK31 AJ30

PG559 G23 GND* E23 C23 A23 D24 B24 H24 VCC* GND* F24 E25 B26 D26 A27 G25 B28 C27 GND* F26 E27 A29 D28 VCC* G27 B30 C29 E29 GND* D30 A33 C31 B34 H28 A35 G29 E31 GND* VCC* D32 C35 C33 B36 H30 A37 G31 F32 GND* VCC* E33 D34 B38 G33 A41 E35 GND* D36 F36 G35 H34 B40

XC4085XL Pad Name I/O, GCK2 O (M1) GND I (M0) VCC I (M2) I/O, GCK3 I/O (HDC) I/O I/O I/O I/O (LDC) GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O

BG432 AJ30 AH29 GND* AH28 VCC* AJ28 AK29 AH27 AK28 AJ27 AL28 AH26 GND* AK27 AJ26 AL27 AH25 AK26 AL26 VCC* GND* AH24 AJ25 AK25 AJ24 AH23 AK24 VCC* GND* AL24 AH22 AJ23 AK23 GND* AJ22 AK22 AL22 AJ21 VCC* AH20 AK21 GND* AJ20 AH19 AK20 AJ19 AL20 AH18 GND* VCC* AK19

BG560 AH29 AK30 GND* AJ29 VCC* AN32 AJ28 AK29 AL30 AK28 AM31 AJ27 GND* AN31 AL29 AK27 AL28 AJ26 AM30 VCC* GND* AM29 AK26 AL27 AJ25 AN29 AN28 AK25 AL26 VCC* GND* AJ24 AM27 AM26 AK24 AL25 AJ23 AN26 AL24 GND* AK23 AN25 AJ22 AL23 VCC* AM24 AK22 AM23 AJ21 GND* AL22 AN23 AK21 AM22 AJ20 AL21 AN21 AK20 GND* VCC* AL20

PG559 E37 D38 GND* C39 VCC* H36 F38 C41 D40 B42 J37 K36 GND* H38 D42 G39 C43 F40 E41 VCC* GND* L37 J39 F42 H40 G43 J41 H42 N37 VCC* GND* P36 M38 J43 L39 K42 K40 L43 L41 GND* R37 P42 T36 N39 VCC* M40 R43 N41 R39 GND* U37 T42 P40 U43 R41 V42 U39 V38 GND* VCC* W37

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XC4000E and XC4000X Series Field Programmable Gate Arrays XC4085XL Pad Name I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O (INIT) VCC GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O XC4085XL Pad Name I/O I/O I/O I/O I/O GND VCC I/O I.O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O, GCK4 GND DONE VCC PROGRAM I/O (D7) I/O, GCK5 I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O (D6) I/O I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O

BG432 AJ18 AL19 AK18 AH17 AJ17 GND* AK17 AL17 AJ16 AK16 VCC* GND* AL16 AH15 AL15 AJ15 GND* AK15 AJ14 AH14 AK14 AL13 AK13 VCC* GND* AJ13 AH13 AL12 AK12 AJ12 AK11 GND* AH12 AJ11 VCC* AL10 AK10 AJ10 AK9 GND* AL8 AH10 AJ9 AK8 GND* VCC* AJ8

BG560 AJ19 AM20 AK19 AL19 AN19 GND* AJ18 AK18 AL18 AM18 AK17 AJ17 VCC* GND* AL17 AM17 AN17 AK16 AJ16 AL16 GND* AM16 AL15 AK15 AJ15 AN15 AM14 VCC* GND* AL14 AK14 AJ14 AN13 AM13 AL13 AK13 AJ13 GND* AM12 AL12 AK12 AN11 VCC* AJ12 AL11 AK11 AM10 GND* AL10 AJ11 AN9 AK10 AM9 AL9 AJ10 AM8 GND* VCC* AK9 AL8 AN7

PG559 T40 Y42 U41 Y36 V40 GND* W39 AA43 Y38 Y40 AA37 AA39 VCC* GND* AA41 AB38 AB42 AB40 AC37 AC39 GND* AD36 AC41 AD38 AC43 AD40 AE39 VCC* GND* AE37 AF40 AD42 AF42 AF38 AG39 AG43 AG37 GND* AH40 AJ41 AG41 AK40 VCC* AJ39 AH42 AH36 AL39 GND* AJ37 AJ43 AM40 AK42 AN41 AL41 AR41 AK36 GND* VCC* AL37 AN43 AM38

BG432 AH9 AK7 AL6 AJ7 AH8 GND* VCC* AK6 AL5 AH7 AJ6 AK5 AL4 GND* AH6 AJ5 AK4 AH5 AK3 AJ4 GND* AH4 VCC* AH3 AJ2 AG4 AG3 AH2 AH1 AF4 GND* AF3 AG2 AG1 AE4 AE3 AF2 VCC* GND* AF1 AD4 AD3 AE2 AD2 AC4 VCC* GND* AC3 AD1 AC2 AB4 GND* AB3 AB2 AB1

BG560 AJ9 AL7 AK8 AN6 AM6 GND* VCC* AJ8 AL6 AK7 AM5 AM4 AJ7 GND* AL5 AK6 AN3 AK5 AJ6 AL4 GND* AJ5 VCC* AM1 AH5 AJ4 AK3 AH4 AL1 AG5 GND* AJ3 AK2 AG4 AH3 AF5 AJ2 VCC* GND* AJ1 AF4 AG3 AE5 AH1 AF3 AE4 AG2 VCC* GND* AD5 AF2 AF1 AD4 AE3 AC5 AE1 AD3 GND* AC4 AD2 AB5

PG559 AP42 AN39 AR43 AP40 AT40 GND* VCC* AN37 AR39 AT42 BA43 AU43 AU39 GND* AT38 AP36 AR37 AV42 AV40 AW41 GND* AY42 VCC* BB42 BC41 AV38 BA39 AT36 BB40 AY40 GND* BA41 BB38 AY38 BC37 AW37 AT34 VCC* GND* AU35 AV36 BB36 AY36 BC35 AW35 AU33 AT30 VCC* GND* AV32 AU31 AW33 BB34 AY34 BC33 AU29 AT28 GND* BA35 BB30 AW31

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XC4085XL Pad Name I/O VCC I/O I/O I/O (D5) I/O (CS0) GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D4) I/O VCC GND I/O (D3) I/O (RS) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O (D2) I/O I/O I/O VCC

BG432 AA3 VCC* AA2 Y2 GND* Y4 Y3 Y1 W1 W4 W3 GND* VCC* W2 V2 V4 V3 U1 U2 GND* U4 U3 T1 T2 VCC* GND* T3 R1 R2 R4 GND* R3 P2 P3 P4 N1 N2 VCC* GND* N3 N4 M1 M2 M3 M4 GND* L2 L3 VCC*

BG560 AC3 VCC* AB4 AC1 AA5 AB3 GND* AB2 AA4 AA3 Y5 AA1 Y4 Y3 Y2 GND* VCC* W5 W4 W3 W1 V3 V5 GND* V4 V2 U2 U1 U5 U4 VCC* GND* U3 T2 T3 T5 T4 R1 GND* R3 R4 R5 P2 P3 P4 VCC* GND* N1 P5 N2 N3 N4 M2 N5 M3 GND* M4 L1 L3 M5 VCC*

PG559 AY32 VCC* BA33 AU27 BC29 AW29 GND* AY30 BA31 BB28 AW27 BC27 AV26 AU25 AY28 GND* VCC* BA29 AT24 BB26 AW25 BB24 AY26 GND* AV24 AU23 BA27 BC23 AY24 AW23 VCC* GND* BA23 AV22 AY22 BB22 AU21 AW21 GND* BA21 BC21 AY20 BB20 AT20 AV20 VCC* GND* AW19 AY18 BB18 AU19 BC17 BA17 AV18 AW17 GND* AY16 BB16 AU17 BA15 VCC*

XC4085XL Pad Name I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (D1) I/O (RCLK RDY/BUSY) I/O I/O I/O I/O GND I/O I/O I/O I/O I/O (D0, DIN) I/O, GCK6 (DOUT) CCLK VCC O, TDO GND I/O (A0, WS) I/O, GCK7 (A1) I/O I/O I/O I/O GND I/O I/O I/O (CS1, A2) I/O (A3) I/O I/O VCC GND I/O I/O

BG432 K1 K2 K3 K4 GND* J2 J3 J4 H1 GND* VCC* H2 H3 H4 G2 G3 F1 GND* VCC* G4 F2 F3 E1 F4 E2 GND* E3 D1 E4 D2 C2 D3 D4 VCC* C4 GND* B3 D5 B4 C5 A4 D6 GND* B5 C6 A5 D7 B6 A6 VCC* GND* D8 C7

BG560 K2 L4 J1 K3 GND* L5 J2 K4 J3 H2 K5 H3 J4 GND* VCC* G1 F1 J5 G3 H4 F2 E2 H5 GND* VCC* F3 G4 D2 E3 G5 C1 GND* F4 D3 B3 F5 E4 D4 C4 VCC* E6 GND* D5 A2 D6 A3 E7 C5 GND* B4 D7 C6 E8 B5 A5 VCC* GND* D8 C7

PG559 AW15 BC15 AY14 BA13 GND* AT16 BB14 AU15 BC11 AW13 BB10 AY12 BA11 GND* VCC* AT14 AU13 AV12 BC9 AW11 BB8 AY10 AU11 GND* VCC* BA9 AW9 BC7 AY8 AV8 AT10 GND* AU9 BB6 AW7 BC3 AY6 BB4 BA5 VCC* BA3 GND* AT8 AV6 BB2 AY4 AR7 AP8 GND* AT6 AY2 AU5 BA1 AV4 AW3 VCC* GND* AN7 AR5

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4-147

XC4000E and XC4000X Series Field Programmable Gate Arrays XC4085XL Pad Name I/O I/O I/O I/O I/O I/O VCC GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O GND VCC I/O (A4) I/O (A5) I/O I/O I/O (A21) I/O (A20) GND I/O I/O I/O I/O I/O (A6) I/O (A7) GND 6/13/97

BG432 B7 D9 B8 A8 VCC* GND* D10 C9 B9 C10 GND* B10 A10 C11 D12 VCC* B11 C12 GND* D13 B12 C13 A12 D14 B13 GND* VCC* C14 A13 B14 D15 C15 B15 GND* A15 C16 B16 A16 GND*

BG560 E9 A6 B7 D9 C8 E10 VCC* GND* B8 A8 D10 C9 E11 A9 C10 D11 GND* B10 E12 C11 B11 VCC* D12 A11 E13 C12 GND* B12 D13 C13 E14 A13 D14 C14 B14 GND* VCC* E15 D15 C15 A15 C16 E16 GND* D16 B16 B17 C17 E17 D17 GND*

PG559 AV2 AT4 AU1 AR3 AT2 AL7 VCC* GND* AK8 AM6 AN5 AR1 AP4 AN3 AP2 AJ7 GND* AH8 AL5 AN1 AM4 VCC* AL3 AJ5 AK2 AG7 GND* AK4 AJ3 AG5 AJ1 AF6 AH2 AE7 AH4 GND* VCC* AG3 AD8 AG1 AF4 AE5 AD6 GND* AD4 AF2 AC7 AD2 AC5 AC3 GND*

Additional XC4085XL Package Pins

BG560 A4 B13 D33 T33 AK1 AM15 AN24 A7 A32 B31 K1 V33 AE2 AM11 AN5 A1 6/4/97 A10 B19 E5 V1 AK4 AM21 AN30 A12 B1 C2 L2 W2 AG1 AM19 AN10 A33 VCC Pins A22 A26 C3 C31 K33 M1 AA2 AB33 AL2 AL3 AN4 AN8 GND Pins A14 A18 A20 B6 B9 B15 E1 F32 G2 M33 P1 P33 Y1 Y33 AB1 AG32 AH2 AJ33 AM25 AM28 AM33 AN14 AN16 AN20 Not Connected Pins AC2 AN1 AN33 A16 B32 H1 W32 AK33 AM32 A30 C32 N32 AD1 AL31 AN12 A24 B23 G33 R32 AC32 AL32 AM7 AN22 B2 D1 R2 AF33 AM2 AN18 A29 B27 J32 T1 AD33 AM3 AN2 AN27 -

*Pads labelled GND* or VCC* are internally bonded to Ground or VCC planes within the package. They have no direct connection to any specific package pin.

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March 30, 1998 (Version 1.5)

PG559 A13 C37 H12 N43 AE3 AL43 AU3 BA19 A5 E5 H22 W1 AH38 AV16 BB12 5/8/97 A31 F14 H18 P6 AE41 AM8 AU7 BA25 A19 E39 K6 W43 AM2 AV28 BB32 A43 F30 H26 P38 AF8 AM36 AU37 BA37 A25 E43 K38 AB8 AM42 AV34 BC5 VCC Pins B2 G3 H32 V8 AF36 AT12 AU41 BC1 GND Pins A39 F10 M2 AB36 AP6 AW1 BC19 C7 G7 M8 V36 AK6 AT18 AV14 BC13 B12 F16 M42 AE1 AP38 AW5 BC25 C19 G37 M36 W3 AK38 AT26 AV30 BC31 B32 F28 T6 AE43 AT22 AW39 BC39 C25 G41 N1 W41 AL1 AT32 BA7 BC43 E1 F34 T38 AH6 AV10 AW43 -

BG432 A1 L4 AH11 C29 A11 L28 AH21 AJ3 A21 L31 AL1 AJ29 VCC Pins A31 D11 AA1 AA4 AL11 AL21 D21 AA28 AL31 L1 AA31 C3

A2 A25 C1 P1 AC31 AK2 AL14 C8 3/3/98

A3 A29 C31 P31 AE1 AK30 AL18

GND Pins A7 A9 A14 A30 B1 B2 D16 G1 G31 T4 T28 V1 AE31 AH16 AJ1 AK31 AL2 AL3 AL23 AL25 AL29 Not Connected Pins

A18 B30 J1 V31 AJ31 AL7 AL30

A23 B31 J31 AC1 AK1 AL9

March 30, 1998 (Version 1.5)

4-149

XC4000E and XC4000X Series Field Programmable Gate Arrays

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March 30, 1998 (Version 1.5)

XC4000E and XC4000X Series Field Programmable Gate Arrays

March 30, 1998 (Version 1.5)

Product Availability
Table 25 - Table 27 show the planned packages and speed grades for XC4000-Series devices. Call your local sales ofce for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the specications. Table 25: Component Availability Chart for XC4000XL FPGAs
PINS 84 Plast. PLCC 100 Plast. PQFP 100 Plast. VQFP 144 Plast. TQFP 144 High-Perf. TQFP 160 High-Perf. QFP 160 Plast. PQFP 176 Plast. TQFP 176 High-Perf. TQFP 208 High-Perf. QFP 208 Plast. PQFP 240 High-Perf. QFP 240 Plast. PQFP 256 Plast. BGA 299 Ceram. PGA 304 High-Perf. QFP 352 Plast. BGA 411 Ceram. PGA 432 Plast. BGA 475 Ceram. PGA 559 Ceram. PGA 560 Plast. BGA

TYPE

HQ160

HQ208

HQ240

HQ304

PQ100

VQ100

PQ160

PQ208

PQ240

BG256

PG299

BG352

PG411

BG432

PG475

PG559
CI C C

CODE

-3

CI C C CI C C

CI C C

CI C C CI C C CI C C CI C C CI C C C CI C CI C C

CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C

CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C CI C C

XC4005XL XC4010XL XC4013XL XC4020XL XC4028XL XC4036XL XC4044XL XC4052XL XC4062XL XC4085XL
3/27/98

-2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1 -3 -2 -1

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

March 30, 1998 (Version 1.5)

4-151

BG560

TQ144

TQ176

HT144

HT176

PC84

XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 26: Component Availability Chart for XC4000E FPGAs

PINS 84 Plast. PLCC 100 Plast. PQFP 100 Plast. VQFP 120 Ceram. PGA 144 Plast. TQFP 156 Ceram. PGA 160 Plast. PQFP 191 Ceram. PGA 208 High-Perf. QFP 208 Plast. PQFP 223 Ceram. PGA 225 Plast. BGA 240 High-Perf. QFP 240 Plast. PQFP 299 Ceram. PGA 304 High-Perf. QF C C

TYPE

HQ208

HQ240

CODE

-4

CI C C C CI C C C CI C C C CI C C C CI C C C

CI C C C CI C C C

CI C C C

CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C C CI C C CI C C C CI C C C CI C C C CI C C C CI C C CI C C CI C C CI C C C

XC4003E

-3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4 -3 -2 -1 -4

XC4005E

XC4006E

XC4008E

XC4010E

XC4013E

XC4020E

XC4025E
8/4/97

-3 -2

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

Table 27: Component Availability Chart for XC4000EX FPGAs

PINS TYPE CODE -3 208 High-Perf. QFP 240 High-Perf. QFP 299 Ceram. PGA 304 High-Perf. QFP 352 Plast. BGA 411 Ceram. PGA 432 Plast. BGA

HQ208
CI C C

HQ240
CI C C

PG299
CI C C

HQ304
CI C C CI C C

BG352
CI C C

PG411

BG432

XC4028EX XC4036EX
8/4/97

-2 -1 -3 -2 -1

CI C C

C = Commercial TJ = 0 to +85C I= Industrial TJ = -40C to +100C

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March 30, 1998 (Version 1.5)

HQ304

PQ100

VQ100

PG120

PG156

PQ160

PG191

PQ208

PG223

BG225

PQ240

PG299

TQ144

PC84

User I/O Per Package

Table 28 - Table 30 show the number of user I/Os available in each package for XC4000-Series devices. Call your local sales ofce for the latest availability information, or see the Xilinx WEBLINX at http://www.xilinx.com for the latest revision of the specications. Table 28: User I/O Chart for XC4000XL FPGAs Package Type HQ160 HQ208 HQ240 HQ304 PQ100 VQ100 PQ160 PQ208 PQ240 BG256 PG299 BG352 PG411 BG432 PG475 PG559
4