Topic Video 06
Memory: Types and how to use them...
Wednesday, 8 July 2009
Memory
The Black Box
All memory devices are attached to the data, address and control buses of the microprocessor.
Control
uP
Data
Memory Device
Address
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The Black Box : The Control Bus
The control bus denes how the memory device should communicate with the uP. The Control Bus handles things like: The direction of the Data Bus; are we reading from the memory device or writing to it. The speed of communication; an external clock is part of the control bus. Interrupt handling; any interrupt sources from the device are part of this bus.
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : The Address Bus
The address bus provides the address of the memory location that the uP wants to access. The bus is unidirectional. The width of the address bus denes the total amount of addressable memory. If a uP has 16 address pins then it is capable of addressing 65536 unique memory locations. If a memory device has only 3 address pins then it must contain 8 addressable memory words.
Memory
Control
uP
Data
Memory Device
Address
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The Black Box : The Data Bus
The Data Bus is responsible for moving the data between the uP and the memory device. The Data Bus is bidirectional; when writing data to the memory device the data ows from the uP to the memory device. When reading data from the device it ows towards the uP. The width of the uPs data bus denes the word length of the uP. The MC9S12XDP512 has a 16 bit internal data bus, therefore it is a 16 bit processor.
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
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The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
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The Black Box : How it all works
Memory
Control
LDAA $2000
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
Wednesday, 8 July 2009
The Black Box : How it all works
Memory
Control
uP
Data
Memory Device
Address
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The Black Box : How it all works
Memory
Control
uP
Data
Address
Memory Device
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The Black Box : How it all works
Memory
Memory Elements
Control
uP
Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Memory Elements
Control
uP
Data
Address
$2000
Memory Decoder
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The Black Box : How it all works
Memory
Memory Elements
Control
uP
Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Memory Elements
Control
uP
Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Position Memory 8192 ($2000) Elements
Control
$45
uP
Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Memory Elements
Control
$45
uP
Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Control
Read
Memory Elements
$45
uP
Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Control
Read
Memory Elements
uP
$45 Data
Address
Memory Decoder
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The Black Box : How it all works
Memory
Read
uP
Control
Data
Memory Device
Address
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The Black Box : How it all works
Memory
Read
uP
Control
Data
Address
Memory $45 Device
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The Black Box : How it all works
Memory
Read
$45 uP
Control
Data
Address
Memory Device
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The Black Box : How it all works
Memory
Read
$45 uP
Control
Data
Memory Device
Address
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The Black Box : Summary
Memory
The address of the location is placed on the address bus, the control line then denes either a read or write cycle. During a write cycle the data is also made available on the data bus at this time. When the device receives the R/W signal it latches the address internally. This address is then used to drive an internal memory decoder which activates a particular row of memory elements. The row of memory elements is then connected to the data bus. During a read cycle, the data in the row of elements is driven on to the data bus and read by the uP. During a write cycle, the data bus is driven on to the memory elements. The memory transaction is then complete.
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Memory
Types
All memory is categorized into two main types:
ROM RAM
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Commonly referred to as Read-Only Memory, or Non-Volatile RAM (NVRAM). This type of memory can only be read. Generally programs and constants are stored in ROM, once they are written they very rarely change, and they never change while programs are running.
No R/W line just a RE line instead.
Read-Only Memory
ROM
Clock Read Enable
Data
ROM Memory Device
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Address
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Read-Only Memory
ROM
There exists two major reason why ROM memory is used instead of RAM:
Values stored in ROM always remain stored under all possible power conditions. The ROM chip can be removed from the system and stored elsewhere and the contents will remain intact. Like Hard Drives, ROM is considered to be non volatile memory. The second reason is security, since the ROM can only be read from, the contents of the ROM can not be altered through malicious or accidental use.
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Read-Only Memory: How it Works
ROM
Inside a basic 1k ROM.
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Memory Elements
Memory Elements are congured as a 2D structure. The number of columns equals the width of the data bus and the number of rows equals 2width of address bus.
A0 A1
Memory Decoder
D7
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D0
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ROM
Historically Originally ROM referred to memory that could only be written to once. It was constructed from hardwired logic, encoded into the silicon itself. Bit values were manually wired into the memory elements via a metallization layer. This type of memory was highly inexible and extremely expensive.
Memory Element of a ROM
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ROMS
The Pros
Nonvolatile: if power is lost the contents remain unchanged. When a device is powered ON it needs a program to run...
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ROMS
The Cons
Extremely inexible If a mistake is made then the 1000+ devices built are landll...
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The Good News
ROM
Not all ROMs are made equal. There are variants that provide some level of exibility. These variants include: PROM EPROM EEPROM Flash EPROM
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Programmable Read-Only Memory
PROM
This type of memory has the ability to be programmed only once. Programming of these devices is achieved using PROM Programmer.
The Pocket Programmer PROM/EPROM Programmer.
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Programmable Read-Only Memory
PROM
PROM is suitable for ROM applications where a small number of inexible ROM are required. In situations were programs are upgraded the PROM would simply be replaced with one containing a newer version of the code. Expensive and required a technician to do it.
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PROM
Memory Element
The PROM programmer applies enough current to blow the fuses for all memory elements that should contain a logical 1 value.
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Erasable Programmable Read Only Memory
EPROM
EPROM allows slightly more exibility than PROM. EPROM is a ROM device that can be programmed using a PROM programmer. It however can be erased using ultraviolet light.
A little quartz window is installed on the top of the ROM package, through which you can actually see the silicon chip that contains the data.
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Erasable Programmable Read Only Memory
EPROM
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Erasable Programmable Read Only Memory
The window on the top of the chip is made of quartz as ultraviolet light will not pass through glass. The ultraviolet light discharges all of the memory elements on the chip, allowing them to be reprogrammed. In a UV eraser it usually takes around 30 minutes to erase an EPROM. If the chip is left unprotected outside in the sun, it would take 3 weeks of sunshine to erase the chip, if left unprotected under orescent lights it would take a year to be erased.
EPROM
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EPROM
Memory Elements
The EPROM Transistor plays a signicant role in the EPROM memory element. When the oating gate is uncharged the transistor functions normally.
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EPROM
Memory Elements
The EPROM Memory Element
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EEPROM
Electrically Erasable Programmable Read Only Memory
2PROM) (E
The next level of exibility is EEPROM. EEPROM is considered to be the most exible type of ROM, the contents of the ROM can be erased and reprogrammed on the y, while situated inside the nal product. The EEPRROM can in fact be used as if it were RAM, however the access time for a write cycle is extremely slow. An EEPROM device has a limited number of times it can be written to, which is generally in the order of thousands.
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EEPROM
Memory Elements
The EEPROM Cell contains a EEPROM Transistor, this transistor also has a oating gate. Once charged this transistor will always show a logical 1 until discharged.
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FLASH
Flash memories have grown to be very popular and many microcontrollers contain Flash memory on-chip. The MC9S12XDP512 includes 512k of Flash memory. Flash has a number of built-in write protection mechanisms. Flash programming voltage Programming Algorithm
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FLASH
Memory Elements
The FLASH memory Element.
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Random Access Memory
RAM
RAM is primarily used for the storage of program data. RAM is extremely volatile. Any uctuation in power will result in all memory elements being corrupted or erased. Data can be easily written and read from RAM, quickly and efciently due to the nature in which it stores information.
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RAM
Like all other memory devices, the RAM chip connects to the data, address and control buses. Externally, the RAM chip differs from the ROM chip as it contains an additional control line to allow data to be written to the RAM chip. This additional line is the write line. However internally there are many differences between RAM and ROM.
Clock Read/Write
Data WE RE
RAM Memory Device
36
Address
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Random Access Memory
RAM
Wednesday, 8 July 2009
Inside a basic 1k RAM.
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Random Access Memory
RAM
There are currently two major types of RAM, these are: SRAM, And DRAM.
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SRAM
SRAM has extremely low latency. It is the fastest memory technology that is currently available. The Cache of CPUs consist of SRAM memory. The basic SRAM memory element is made up of 6 transistors. An SRAM memory element occupies a lot of space on the silicon wafer. SRAM is expensive and is generally only available in small quantities.
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SRAM
Memory Element
An SRAM Memory Element.
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Dynamic Random Access Memory
DRAM
DRAM is a type of RAM capable of holding data as long as each memory element is continually written to. A special logic circuit referred to as the refresh circuit, reads each column of the 2D memory structure and writes the values back. The refresh circuit performs this task over a hundred times a second. If the memory elements are not refreshed at regular intervals then the data contained inside the DRAM memory element will be lost.
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Dynamic Random Access Memory
DRAM
Due to the overhead of refreshing each element, DRAM is generally a lot slower than SRAM. However, DRAM has the advantage of occupying of the space on an IC than SRAM and is therefore cheaper. The overhead of the refresh circuit is tolerated in order to allow the use of larger capacity and yet less expensive memory.
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Dynamic Random Access Memory
DRAM
A DRAM memory element consists of only one transistor and a capacitor. When the capacitor is charged it holds the bit value is 1 and if it is discharged it holds the bit value is 0. The transistor is used to read the value held by the capacitor. The problem with capacitors is that they hold their charge for only a limited time and then fades. These capacitors are very small so their charges fade particularly quickly.
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DRAM
Memory Element
A DRAM Memory Element.
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DRAM Versus SRAM
The Pros and Cons
The use of SRAM has two major advantages over DRAM:
SRAM does not require an external refresh making it easier to implement than DRAM. Access times for SRAM are much lower than DRAM. SRAM can give access times as low as 10 nanoseconds, as opposed to the average 60 nanoseconds of DRAM. The cycle time of SRAM is much shorter as the memory does not need to be refreshed between memory reads and writes.
The use of SRAM has two major disadvantages over DRAM:
SRAM is much more expensive than DRAM SRAM occupies more area on a silicon wafer than DRAM.
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Interfacing to Memory
Interfacing a uP to memory can be either a difcult or a simple task, depending on whether you do your homework rst or not. In a uP based system, the uP is the master. The uP denes when the memory device is accessed and when data is made available to, or read from the data bus. So the memory device you choose must to meet the timing requirements of the uP.
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Interfacing to Memory
When connecting a memory device to a uP you need to do the following:
Connect the external clock from the uP to the memory devices clock pin. Connect the R/W pin of the uP to the memory device's R/W or RE pin.
uP
EClk R/W
Memory Device
CLK RE
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Interfacing to Memory
Connect the Data Bus of the uP to the Data Bus of the memory device ensuring the bits align properly. If the data buses differ in size then align the smaller bus to the least signicant bits of the larger bus.
uP
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Memory Device
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Interfacing to Memory
Connect the address bus of the memory device to the least signicant end of the uPs address bus.
uP
A5 A4 A3 A2 A1 A0
Memory Device
A2 A1 A0
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Interfacing to Memory
If this uP with a 6 bit address bus is connected to the memory device that only has a 3 bit address input. What does it do to the memory space?
uP
A5 A4 A3 A2 A1 A0
Memory Device
A2 A1 A0
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Interfacing to Memory
Since only the bottom 3 bits of the address bus are used and the top 3 are ignored, that means the eight memory location on the device are:
XXX000 - XXX111
Therefore the address 000001 refers to same location as 111001.
uP
A5 A4 A3 A2 A1 A0
A2 A1 A0
Memory Device
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Interfacing to Memory
So the memory space would look something like this. $3F
MD MD MD MD MD MD MD MD
The memory Device repeats every 8 bytes.
Memory Map
$00
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Interfacing to Memory
So how could we stop the device from repeating? How could we ensure it only occupied 8 bytes in our memory space? What role could the 3 most signicant bits of the address bus play?
uP
A5 A4 A3 A2 A1 A0
CE
A2 A1 A0
Memory Device
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Interfacing to Memory
So how could we stop the device from repeating? How could we ensure it only occupied 8 bytes in our memory space? What role could the 3 most signicant bits of the address bus play?
uP
A5 A4 A3 A2 A1 A0
&
CE
A2 A1 A0
Memory Device
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Interfacing to Memory
Now when the 3 most signicant bits of the address bus are all high the memory device is enabled. The CE pin of the memory device is a chip enable pin, its kind of like an ON/OFF switch.
uP
A5 A4 A3 A2 A1 A0
&
CE
A2 A1 A0
Memory Device
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Interfacing to Memory
The Memory Device is now only available in the range 111000 to 111111. $3F MD $38 Memory Map
$00
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Interfacing to Memory
Example of Cascaded Memory Chips.
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MC9S12XDP512
Memory Map
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Need Further Assistance?
Ask your Demonstrator, Post a question on the Forum, Email the Convener, or Make an appointment.
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