John Notor July 17, 2009 Rev 3
I N VE N TI V E
Analog Design Methodology in a Time to Market Environment
Overview
Cadence Services Overview Cadence AMS Project Flow and Management Cadence Projects vs Academic Research Example Designs
July 20, 2009
Cadence Holistic Solutions
Enabling customers to achieve breakthrough results
Extending Customer Capabilities
Partners: Verification IP, Silicon IP, Silicon & Board Mfg, Packaging, Test
Design Augmentation
AMS IP System Design Functional Verif IP Verification Digital IP Physical Implement
Timing Electrical Verify
DFT & DFM
Pkg
Board
Design Environment Enablement Training Cadence Leading-edge EDA Products
Design Centric Flows, Methodologies, CAD Support Design Ready Process Design Kits Custom, On Site, On Line, Public Course Offerings
ENCOUNTER VIRTUOSO ALLEGRO INCISIVE
Digital IC
Custom IC
Package and PCB
Verification
Maximizing Results from Cadence Technology Platforms
July 20, 2009
Worldwide Services Team
USA
Livingston Zelenograd Bracknell Paris Noida Bangalore Yokohama Shanghai Munich
San Jose
Columbia Cary Melbourne
Collaboration Hub Hosting Hub
July 20, 2009
Analog/RF/Mixed-signal Design and Methodology
Broad and Deep Design Expertise
83% SoC designs, 90% low power, hi-perf CMOS 111 analog specific tapeouts in the last 4 years Package/IO interactions, digital substrate coupling/isolation, multiple power, device matching, stress, well, NBTI/LOD feature implementation AFEs, Datacom, RF, Synthesizers, PLLs, A/D, D/A System-on-Chip Analog/Mixed Signal/RF Logic Design & Verification Silicon/Package/Board
Efficient and Effective Design Environment
Design and methodology project collaborations Experts in design environment enablement Design-ready PDK customization
Reliable Tape-out Success
98.1% First Pass Functionality 87.4% First Pass to Production 96.1% Full Parametric Operation with 1 metal spin 100+ products in volume production .35u to 40nm for CMOS, Bipolar, BICMOS, SiGe
July 20, 2009
Design Flow Focused on Achieving First Pass Success
System Design Architectural Simulation
Analog Design & Simulation
VSE-L Spectre (RF) Spectre Excel Matlab SystemVue Custom AMS Designer AMS Designer
Spec Review, Partitioning White board
Excel
NC SIM NC SIM
MS Design Simulation MS Design && Simulation
VSE-L Spectre/Verilog AMS UltraSim
Digital Synthesis
RTL Compiler NCSIM Conformal First Encounter - Floorplanning
ADE-XL (Corners)
ADE-XL (Corners)
DFII based design
Simulation Verification Floorplanning Physical Design Extraction Re-Simulation Chip Assembly Chip Verification
MMSim: NCSIM, Spectre, Ultrasim Verilog (D, A, AMS) VLS-GXL Encounter SOC Encounter
VLS-XL
VCAR - Custom routing
Digital Place & Route (VDIO)
Assura DRC/LVS/RCX/RF Spectre Verilog (D, A, AMS) PVS DRC UltraSim FE SE
VLS-XL Assura DRC/LVS/RCX/RF VAVO/VAEO EM/IR
VCAR power grid PVS DRC UltraSim
July 20, 2009
Emphasis on Top Down Mixed Signal Design Flow
Top-Down Design Methodology (INVITED Tutorial) E1-1 Proceedings of the IEEE 2007
Paper Spec
Functional Simulation
Spec Verification Top Level Simulation Development
Simulation strategy test bench(s), modes, startups, I/O considerations
Analog Circuits
Mixed Signal Blocks
Analog Circuits
Logic
Block Level: Design / Synthesis Corner Verification Spares Layout constrains Block Level: Abstract Creation
HDL Schematic HDL Schematic HDL Schematic HDL/Verilog RTL Verilog HDL Abstract Schematic HDL Abstract Schematic HDL Abstract Schematic HDL/Verilog Abstract RTL Verilog
Verilog/HDL
Verilog
Functional Sim (Pin for Pin)
Schematic Verilog/HDL
Top Level Device Verification
HDL Verilog
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Program Flow Emphasizes Review at Key Milestones
Deliverables
Customer Participation KOR Design Definition Specification Development Tech Definition Foundry Selection PDR
Partitioning, Interfaces, Prelim Floor Plan, Testability Design Kit
Functional Model: AMS Designer
Customer
Model Extraction Tech. Table Devel
Analog Layout Parasitic Extraction Digital Layout CDR
Customer Participation Floor Plan
Analog Simulations Composite Simulation Digital Simulations
Analog Design, Schematic Entry
Deliverables
Digital Design, Schematic Entry OR Synthesis
Customer Participation Comp Sim Physical Verification DRC, LVS, EM/IR etc. FDR RFD Fab Proto Test TR Customer
Deliverables
Deliverables
Deliverables
July 20, 2009
Project Management Focused on Clear Communication
Program Manager Primary point of contact Program execution ownership Project Communication Plan Weekly Meetings Weekly Status Report Deliverables Action Items Open Issues/Risks Agreements Project Tracking Schedule Formal Design Reviews Design Milestone Deliveries Steering Committee Meetings
<ProjectName> Project Status - Summary
Executive Summary
Status
Key Issues
Key Risks
Rating
Plans for next week
New Actions (see Actions tab for details)
No new actions.
Resp
Actions closed this week (see Actions tab for details)
Resp
New Agreements (see Agreements tab for details)
No new agreements
At a glance weekly status clearly reports on glance all aspects of the on-going project on-
July 20, 2009
Cadence Design-Ready PDKs Increase Productivity
Additional components to standard baseline foundry PDK
Metal resistors for each level of metal with a unique recognition shape Metal fingered interconnect capacitor PCells Symmetrical center-tapped inductors MOS varactor Native devices Guard ring structures
Enhanced simulation features
Device parameters minimum set to recommended Corner models for Parasitic resistors and capacitors MOS cells that allow the user to anticipate LOD (STI) effects at schematic level and control the effect in simulation Model and control well proximity effects MOS layout-XL multiplier separate from simulation multiplier to enable interdigitation while simulating as a single multi-fingered device
Analog layout capabilities
Recommended rules followed in all PDK device layouts Minimum area diodes for use as antenna diodes Guard rings that can create multiple contact rows Integrated dummy gates on each end of MOS device Ability to merge source drains of devices and reflect in callback
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July 20, 2009
Cadence Projects Differ from Academic Research
Project length fixed in the range ~18-26 weeks. Project team expands to complete the design effort in the allotted time. Dedicated layout personnel work with the circuit designers to create/complete layout. Server resources are sufficient to meet the needs of multiple projects, resources are scheduled appropriately for the project phase. The core team has worked together on multiple projects, cooperates well in the midst of complex and diverse competing projects. For the most part, technology objectives for the project, including performance requirements and process limitations, are well understood before the design effort begins. The technical approach taken most often involves evolution from an existing, proven approach.
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July 20, 2009
13.2 GHz Frequency Synthesizer Macro
Synthesizer Output from ~11.5 to 13.2 GHz 66 MHz Reference Differential Quadrature I & Q outputs Very low phase noise operation Jitter < 60 fs rms, integrated from 3.5 MHz to 1 GHz Internal Self-Calibrating LC VCO Internal regulator for power supply immunity Integrated Analog Test Bus No external loop filter required Power Down Mode TSMC 90 nm G Logic Process Area ~ 1.2 sq mm In Production
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July 20, 2009
AFE for Next Generation Wireless Multimedia
Dual 6-Bit 2.6 GHz ADC
Interpolating Flash Architecture
Dual 6-Bit 2.6 GHz DAC
Programmable current source output
Low Jitter 2.6 GHz PLL
LC VCO architecture
7 to 8 GHz Frequency Synthesizer
4th order, dual path Low jitter LC VCO
Low Phase Noise Crystal Oscillator 1:8 and 8:1 data serializer/deserializer TSMC 65 nm LP Process Multiple versions of this macro delivered In Pre-Production
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July 20, 2009
900 MHz Zigbee Transceiver RF Macro
Low IF RX Complex BPF Complex CT Delta Sigma ADC (IQ) Direct upconversion TX Integrated -10 to +14 dBm PA Fully integrated synthesizer TSMC 180 nm CMOS
Mixer Complex Bandpass Filter PGAs adcclk
I
LNA lna_rf_p
adc _ref _p
adc _ref _m adc_i 4 adc_q
Digital Modem
IQ-ADC
2
lna_rf_m
pga_gain<3:0>
4 adcclk
Demod AGC AFC Modulation Control
gain ctrl
Q
offseti<12:0> Cal
refclk_p Synthesizer refclk_m control Tx IQ_DAC_LPF Tx I_LPF lnagain<1:0> pgagain<3:0> anttune<3:0> Antenna Tuning Mixer Tx I_DAC offsetq<12:0>
daci<5:0>
PA io_rf_p
2
io_rf_m Tx Q_LPF Tx pwr ctrl Tx Q_DAC
dacclk
dacq<5:0>
ATB MUX Bias
atbaddr<7:0>
bias_rext atb_ p atb_ m
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July 20, 2009
12-bit Bandpass Complex Delta-Sigma ADC
Application: Zigbee Transceiver Topology: Fourth Order Hybrid Delta-Sigma Modulator with 4-bit Internal ADC/DAC Tunable loop filter Integrated ATB test bus Specifications:
1 Vpp differential inputs (I/Q) IF = 1 MHz Bandwidth = 1.2 MHz Sampling Rate = 30 MHz
SNDR = 72.4 dB 6.3 mW typical at 1.7 V Area of 0.7 sq mm TSMC 180 nm CMOS
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July 20, 2009
10-bit 500MHz ADC in 90nm
10-bit 12 channel SAR ADC architecture All 12 channels share a master sample and hold Differential analog input ENOB: 8.8 (typ) @500 Msps; 250 MHz input rate 500 MHz maximum sample rate Integrated reference Integrated offset trim DAC Power down modes Integrated analog test bus No off-chip components required Low power: 62 mW typical Area = 0.82 sq mm TSMC 90 nm G process 1.0 V/1.8 V First silicon success
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