CSE325 Principles of Operating Systems
Computer System Overview
David Duggan
[email protected]January 20, 2011
What is a Computer System?
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Computer System Functional Areas
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Major Computer Components
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Processor
Internal registers
Memory address register (MAR)
Specifies the address for the next read or write Contains data written into memory or receives data read from memory
Memory buffer register (MBR)
I/O address register I/O buffer register
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User-Visible Registers
May be read by user processes Available to all programs - application programs and system programs Types of registers
Data Address
Index Segment pointer Stack pointer
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Control and Status Registers
Program Counter (PC)
Contains the address of an instruction to be fetched Contains the instruction most recently fetched Condition codes Interrupt enable/disable Supervisor/user mode
Instruction Register (IR)
Program Status Word (PSW)
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Simple Instruction Cycle
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Interrupts
Suspends the normal sequence of execution Used to improve processor utilization
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Interrupt Cycle
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Interrupt Timeline
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Simple Interrupt Processing
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Multiple Interrupts
Disable interrupts while an interrupt is being processed
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Multiple Interrupts (Cont.)
Define priorities for interrupts
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Data Transfer on the Bus
CPU cache Memory memory bus I/O bus
disk
Net interface
cache-memory: cache misses, write-through/write-back memory-disk: swapping, paging, file accesses memory-network Interface : packet send/receive I/O devices to the processor: interrupts
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Two I/O Methods
Synchronous Asynchronous
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I/O Operation: Synchronous vs. Asynchronous
After I/O starts, control returns to user program only upon I/O completion
Wait instruction idles the CPU until operation completes Wait loop (contention for memory access?) At most one I/O request is outstanding at a time, no simultaneous I/O processing
After I/O starts, control returns to user program without waiting for I/O completion
to wait for I/O completion Device-status table contains entry for each I/O device indicating its type, address, and state Operating system indexes into I/O device table to determine device status and to modify table entry to include interrupt
System call request to the operating system to allow user
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Programmed I/O
I/O module performs the action, not the processor Sets appropriate bits in the I/O status register No interrupts occur Processor checks status until operation is complete
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Interrupt-Driven I/O
Processor is interrupted when I/O module ready to exchange data Processor is free to do other work No needless waiting Consumes a lot of processor time because every byte read or written passes through the processor
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Direct Memory Access (DMA)
Used for high-speed I/O devices able to transmit information at close to memory speeds. Device controller transfers blocks of data from buffer storage directly to main memory without CPU intervention. Only one interrupt is generated per block, rather than the one interrupt per byte. Programming a DMA transfer
address of the I/O buffer starting location in memory number of bytes direction of transfer (read/write from/to memory)
Bus arbitration between cache-memory and DMA transfers Memory cache must be consistent with DMA
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Storage-Device Hierarchy
Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access of the memory by the processor
Locality of reference
Increase size of the transfer unit
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Storage Hierarchy
Storage systems organized in hierarchy.
Speed Cost Volatility
Caching copying information into faster storage system; main memory can be viewed as a last cache for secondary storage.
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Performance of Various Levels of Storage
Movement between levels of storage hierarchy can be explicit or implicit
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Cache-Memory Transfers
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Cache Memory
The mismatch between processor and memory speed closer to the processor than the main memory; smaller and faster than the main memory contains the value of main memory locations that were recently accessed (temporal locality) transfer between caches and main memory is performed in units called cache blocks/lines contains also the value of memory locations that are close to locations which were recently accessed (spatial locality) Cache performance: miss ratio, miss penalty, average access time invisible to the OS, operated by the hardware/firmware
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Cache/Main Memory System
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Cache Read Operation
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Cache Design
Mapping function
Determines which cache location the block will occupy Direct-mapped vs. fully-associative vs. setassociative Conflict misses Determines which block to replace Least-Recently-Used (LRU) algorithm
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Replacement algorithm
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Cache Design (Cont.)
Write policy
When the memory write operation takes place Can occur every time block is updated: write through Can occur only when block is replaced: write back
Minimizes memory write operations Leaves main memory in an obsolete state
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Disk Cache/Buffer Cache
A portion of main memory used as a buffer to temporarily to hold data for the disk Disk writes are clustered Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk
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Multiprocessors
CPU cache CPU cache Memory memory bus I/O bus
disk
Net interface
more than one processor on the same bus memory is shared among processors-- cache coherency goal: performance speedup single-image operating systems Multi-core processors (chip-level multiprocessors/CMP)
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Clusters of Computers
CPU cache Memory memory bus I/O bus CPU cache Memory memory bus I/O bus
network
disk
Net interface
Net interface
disk
network of computers: share-nothing communication through message-passing fast interconnects: memory-to-memory communication goals: performance and availability each system runs its own operating system
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