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VLSI, Verilog, FPGA Training Guide

The document outlines the training contents which are divided into 6 modules. Module 1 provides an overview of VLSI design flow. Module 2 covers digital design topics like number representation, logic gates, combinational and sequential circuits. Module 3 introduces Verilog HDL for gate-level, dataflow and behavioral modeling. Module 4 involves a project design and implementation using Verilog. Module 5 discusses FPGA basics like resources and interfacing. Module 6 includes an FPGA mini project using Xilinx tools. Study materials like examples and assignments will be provided to candidates on a CD.

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Bharat Tanwar
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108 views2 pages

VLSI, Verilog, FPGA Training Guide

The document outlines the training contents which are divided into 6 modules. Module 1 provides an overview of VLSI design flow. Module 2 covers digital design topics like number representation, logic gates, combinational and sequential circuits. Module 3 introduces Verilog HDL for gate-level, dataflow and behavioral modeling. Module 4 involves a project design and implementation using Verilog. Module 5 discusses FPGA basics like resources and interfacing. Module 6 includes an FPGA mini project using Xilinx tools. Study materials like examples and assignments will be provided to candidates on a CD.

Uploaded by

Bharat Tanwar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

TRAINING CONTENTS

MODULE 1: VLSI DESIGN FLOW


1. VLSI design flow awareness

MODULE 2: DIGITAL DESIGN


1. 2. 3. 4. 5. 6. Introduction to digital design Number representation, complements and Boolean logic Basic logic gates and logic functions Optimization techniques for logic functions Designing combinational circuits Analysis of combinational circuits like, adders, comparator, multiplier etc. 7. Designing synchronous sequential circuits 8. Analysis of sequential circuits Flip-Flops, registers, counters, and simple processor 9. Designing Asynchronous Sequential Circuits 10. Designing Finite State Machines (FSM)

MODULE 3: VERILOG HDL


1. Introduction to Verilog HDL 2. Gate-Level modeling 3. Dataflow modeling 4. Operators 5. Data types 6. Modeling timing and delays 7. Behavioral modeling 8. Parameters, tasks and functions 9. Switch-level modeling 10. Design examples FSM, ALU, RAM, ROM

MODULE 4: PROJECT IN VERILOG


1. Project Study 2. Design & Implementation using Mentor Graphics Model Sim simulation tools 3. Presentation 4. Document submission 5. Evaluation of Project

MODULE 5: FPGA BASICS


1. FPGA Kit Introduction 2. Using special FPGA Resources: a) Block RAM. b) DCM. c) Dedicated Arithmetic Functions. 3. FPGA Kit interfacing and Configuration: a) General purpose Input Outputs. b) Seven Segment LED 4. Implementation of Design Examples

MODULE 6: FPGA MINI PROJECT


1. Project Study 2. Design & Implementation using Xilinx FPGA kit and Xilinx Synthesis tools 3. Presentation 4. Document submission 5. Evaluation of Project

We will provide the following to the candidates: 1. Study material, examples, assignments, questions, etc. in a CD

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