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CMOS Layer Design and Layout Techniques

The document discusses different CMOS layer processes used in integrated circuits, including n-well, p-well, and twin-tub processes. It describes the layers used such as p-substrate, n-well, field oxide, gate oxide, and metal interconnect layers. Examples of MOSFET layouts are provided, including the basic components of gates, contacts between layers, and different gate designs like NOT, NAND, and NOR gates. Stick diagrams are introduced as a simplified way to visualize circuit layout and connectivity between components.

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3K views27 pages

CMOS Layer Design and Layout Techniques

The document discusses different CMOS layer processes used in integrated circuits, including n-well, p-well, and twin-tub processes. It describes the layers used such as p-substrate, n-well, field oxide, gate oxide, and metal interconnect layers. Examples of MOSFET layouts are provided, including the basic components of gates, contacts between layers, and different gate designs like NOT, NAND, and NOR gates. Stick diagrams are introduced as a simplified way to visualize circuit layout and connectivity between components.

Uploaded by

MGR
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd

CMOS Layers

 n-well process
 p-well process
 Twin-tub process

Jhon P. U
n-well process
Gate NMOS NMOS PMOS PMOS

FOX

n+ n+ n+ n+ p+ p+ p+ p+

n-well
p-substrate

MOSFET Layers in an n-well process

Jhon P. U
Layer Types
 p-substrate
 n-well
 n+
 p+
 Gate oxide
 Gate (polycilicon)
 Field Oxide
 Insulated glass
 Provide electrical isolation

Jhon P. U
Top view of the FET pattern
NMOS NMOS PMOS PMOS

n+ n+ n+ n+ p+ p+ p+ p+

n-well

Jhon P. U
Metal Interconnect Layers

 Metal layers are electrically isolated from


each other
 Electrical contact between adjacent
conducting layers requires contact cuts and
vias

Jhon P. U
Metal Interconnect Layers
Ox3
Via
Metal2

Active Ox2
contact
Metal1

Ox1

n+ n+ n+ n+

p-substrate

Jhon P. U
Interconnect Layout Example
Gate contact

Metal1

Metal2

Metal1
MOS

Active contact

Jhon P. U
Designing MOS Arrays
A B C

x y

A B C

x
Jhon P. U
Parallel Connected MOS Patterning

x x
A B
A B

X X X

y
y

Jhon P. U
Alternate Layout Strategy

x
x

X X

A B
A B
X X

y y

Jhon P. U
Basic Gate Design

 Both the power supply and ground are routed


using the Metal layer
 n+ and p+ regions are denoted using the
same fill pattern. The only difference is the n-
well
 Contacts are needed from Metal to n+ or p+

Jhon P. U
The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well

X
x x
x x X

X
Gnd

Gnd

Jhon P. U
Alternate Layout of NOT Gate
Vp
Vp

X X

x x

X X

Gnd
x Gnd
x

Jhon P. U
NAND2 Layout

Vp Vp

X X X
a.b

Gnd
a.b
a b
X X

a b
Gnd

Jhon P. U
NOR2 Layout
Vp
Vp

X X

ab
ab

a b X
Gnd X X
a b
Gnd

Jhon P. U
NAND2-NOR2 Comparison
Vp
X X
X

X
X
Gnd

Vp

X
X

MOS Layout X
Wiring X X
Gnd

Jhon P. U
General Layout Geometry
Vp

Shared drain/
source

Individual Shared Gates


Transistors

Gnd

Jhon P. U
Graph Theory: Euler Path
Vp

x Vertex b c
x

Edge a

Out

y
y c
Vertex a

Gnd

Jhon P. U
Stick Diagram

Jhon P. U
Stick Diagrams
• Cartoon of a layout.
• Shows all components.
• Does not show exact placement, transistor sizes,
wire lengths, wire widths, boundaries, or any
other form of compliance with layout or design rules.
• Useful for interconnect visualization, preliminary layout
layout compaction, power/ground routing, etc.

Jhon P. U
Stick Diagrams

Metal

poly

ndiff

pdiff
Can also draw
in shades of
gray/line style.

Jhon P. U
Stick Diagrams

Buried Contact

Contact Cut

Jhon P. U
5V 5v

Dep

Vout

Vin
Enh in

0V

0V
Jhon P. U
Stick Diagram - Example I A
OUT
B

NOR Gate

Jhon P. U
Stick Diagram - Example II

Power

A Out

Ground

Jhon P. U
Points to Ponder
• be creative with layouts

• sketch designs first

• minimize junctions but avoid long poly runs

• have a floor plan plan for input, output, power


and ground locations

Jhon P. U
The End

Jhon P. U

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