SystemVerilog for VHDL Users

Tom Fitzpatrick
Principal Technical Specialist
Synopsys, Inc.
Agenda
• Introduction
• SystemVerilog Design Features
• SystemVerilog Assertions
• SystemVerilog Verification Features
• Using SystemVerilog and VHDL Together

2
 SystemVerilog Charter
• Charter: Extend Verilog IEEE 2001 to higher
abstraction levels for Architectural and
Algorithmic Design , and Advanced
Verification.
Advanced
Transaction-Level V
As er verification capability

be g
Full Testbench
st ilo se ilog

h
for semiformal and
nc
Language with rt
Te Ver
io formal methods.
Coverage n
IEEE The Assertion
Language Standard
Verilog For Verilog
2001 PI
A e
Ar
Ve itect

Design c
&
ch

a
ril ur

Abstraction:
P I rf Direct C interface,
D nte
og al

Interface Assertion API and

semantics, abstract I
Coverage API
data types,
abstract operators
and expressions 3
SystemVerilog: Verilog 1995

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Verilog-95:
Single language
Hardware concurrency Gate level modelling for design &
design entity modularization and timing
testbench
Switch level modeling and timing ASIC timing
4
SystemVerilog: VHDL

Operator VHDL adds

Packages Overloading
higher level
Architecture Simple assertions
Dynamic pointers data types and
memory
configuration
User-defined types allocation management
records/ functionality
Dynamic enums structs
multi-D arrays
hardware
generation Automatic variables Signed numbers Strings

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Hardware concurrency Gate level modelling

design entity modularization and timing

Switch level modeling and timing ASIC timing

5
Semantic Concepts: C

Operator
Packages Overloading
Associative
Dynamic & Sparse arrays
Architecture Simple assertions pointers
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings
++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..) prog C has

r e
but ammin xtra
lack g
Hardware concurrency Gate level modelling
s all featur
design entity modularization and timing con hardw es
cep are
ts
Switch level modeling and timing ASIC timing
6
 SystemVerilog: Verilog-2001
Verilog-2001 adds a lot of
VHDL functionality but still
lacks advanced data
structures
Operator
Packages Overloading
Associative
Dynamic & Sparse arrays
Architecture Simple assertions pointers
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings
++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Hardware concurrency Gate level modelling

design entity modularization and timing

Switch level modeling and timing ASIC timing

7
 SystemVerilog: Enhancements
Constrained Program Clocking Enhanced Scheduling for Cycle Sequence
Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware g
rilo Automatic variables
generation Signed numbers Strings
break, continue,
eV s ++, --, +=. etc)
e m v i de
t ro
sEvent handling d dBasic datatypes (bit, int, reg, wire…)
y
S . 1 an p c e n
a
34 state
d vlogicion Basic programming (for, if, while,..)
a cat ing Packed structs
el
ifi concurrency and unions
e r
Hardware
o d res Gate level modelling
v
design m u
entity tmodularization and timing Coverage & C interface
f ea Assertion
API
Switch level modeling and timing ASIC timing
8
SystemVerilog: Unified Language
Constrained Program Clocking Enhanced Scheduling for Cycle Sequence
Random Data Block Domain Testbench and Assertions Delays Events
Generation
Sequential Semaphores Persistent Functional
Queues
Classes, methods Regular events Coverage
Mailboxes
& inheritance Expressions Process Virtual
Interface Temporal Operator Control Interfaces
Specification Properties Packages Overloading
Associative
Dynamic safe pointers & Sparse arrays
Architecture Simple assertions
memory
configuration allocation
User-defined types Void type Further
records/ programming
Dynamic enums structs Unions
multi-D arrays (do while,
hardware
break, continue,
generation Automatic variables Signed numbers Strings
++, --, +=. etc)

Event handling Basic datatypes (bit, int, reg, wire…)

4 state logic Basic programming (for, if, while,..)

Packed structs
and unions
Hardware concurrency Gate level modelling
design entity modularization and timing Coverage & C interface
Assertion
API
Switch level modeling and timing ASIC timing
9
SystemC & SystemVerilog

Platform Software
Based
Design

Transaction
Level (TL) System
Testbench
RTL
Assertions RTL
Testbench RTL
RTL
Assertions
Coverage Gates
SystemC
Coverage Gates
Gates
SystemVerilog
….
Verilog/VHDL

10
Agenda
• Introduction
• SystemVerilog Design Features
• SystemVerilog Assertions
• SystemVerilog Verification Features
• Using SystemVerilog and VHDL Together

11
Basic SystemVerilog Data Types

reg r; // 4-state Verilog-2001 single-bit datatype

integer i; // 4-state Verilog-2001 >= 32-bit datatype
bit b; // single bit 0 or 1
logic w; // 4-valued logic, x 0 1 or z as in Verilog
byte b8; // 8 bit signed integer
int i; // 2-state, 32-bit signed integer

Explicit 2-state Variables Allow Compiler

Optimizations to Improve Performance

The unresolved type “logic” in SystemVerilog

is equivalent to “std_ulogic” in VHDL

12
 Familiar C Features In SystemVerilog
do continue starts
begin next loop iteration works with:
for
if ( (n%3) == 0 ) continue;
while
if (foo == 22) break; break exits
forever
end the loop repeat
while (foo != 0); (= “exit” in VHDL do while
…

Blocking Assignments Extra parentheses

if ((a=b)) …
as expressions required to distinguish
while ((a = b || c)) from if(a==b)

Auto increment/ x++;

decrement operators if (--c > 17) c=0;

13
SystemVerilog Struct = Record
type PKT_T is record typedef struct {
PARITY: std_ulogic; logic PARITY;
ADDR: std_ulogic_vector(3 downto 0); logic[3:0] ADDR;
DEST: std_ulogic_vector(3 downto 0); logic[3:0] DEST;
end record; } pkt_t;

signal MYPKT : PKT_T; pkt_t mypkt;

... ...
MYPKT.ADDR <= “1100”; mypkt.ADDR = 12;

31 3 0 The mypkt
PARITY structure/
ADDR record is
DEST “unpacked”

In SystemVerilog, struct variables can struct {

also be declared directly, without the typedef bit [7:0] opcode;
bit [23:0] addr;
Structure definitions are just like in C but } IR;
without the optional structure tag before the ‘{‘
no typedef
14
Packed Structures and Unions
typedef struct packed { typedef union packed {
logic [15:0] source_port; tcp_t tcp_h; All
logic [15:0] dest_port; udp_t udp_h; members
logic [31:0] sequence; bit [63:0] bits; of a union
} tcp_t; bit [7:0][7:0] bytes; must
typedef struct packed { } ip_t; be the
logic [15:0] source_port; same size
logic [15:0] dest_port;
logic [15:0] length;
logic [15:0] checksum ip_t ip_h;
} udp_t; logic parity;

ip_h.udp_h.length = 5;
ip_h.bits[31:16] = 5;
tcp_t source_port dest_port sequence ip_h.bytes[3:2] = 5;
udp_t source_port dest_port length checksum
parity = ^ip_h; Equivalent

Operate on entire
Create multiple layouts for accessing data structure as a whole
VHDL records not explicitly packed
15
Type Conversion
Unpacked Structure
typedef struct {
logic PARITY;
logic[3:0] ADDR; User-defined type:
logic[3:0] DEST; packed bit vector
} pkt_t;

typedef bit[8:0] vec_t;

pkt_t mypkt;
vec_t myvec;
Cast mypkt as type vec_t
myvec = vec_t’(mypkt);
mypkt = pkt_t’(myvec);
Cast myvec as type pkt_t

User-defined types and explicit casting

improve readability and modularity

Similar to Qualified Expressions

or conversion functions in VHDL
16
Data Organization - Enum
VHDL: SystemVerilog:
type FSM_ST is typedef enum logic [2:0]
{IDLE, {idle,
{idle = 0,
INIT, init,
init = 3,
DECODE, decode, // = 4
…}; …} fsmstate;
signal pstate, nstate : FSM_ST; fsmstate pstate, nstate;
case (pstate) is case (pstate)
when idle: idle: if (sync)
if (sync = ‘1’) then nstate = init;
nstate <= init; init: if (rdy)
end if;
nstate = decode;
when init:
if (rdy = ‘1’) then …
nstate = decode; endcase
end if;
…
end case;

VHDL enums not explicitly typed

17
Packed and Unpacked Arrays
unpacked bit a [3:0]; a0
array of
a1
bits
a2

Don’t
Don’tget
getthem
themmixed
mixedup
up unused
a3

packed
array of bit [3:0] p; p3 p2 p1 p0
bits
1k 16 bit
unpacked bit [15:0] memory [1023:0];
memory memory[i] = ~memory[i]; Packed
memory[i][15:8] = 0; indexes can be
1k 16 bit sliced
packed bit [15:0][1023:0] Frame;
Can operate on
memory always @inv Frame = ~Frame;
entire memory

SystemVerilog also includes the VHDL-like array attribute functions:

$left, $right, $low, $high, $increment, $length and $dimensions
18
Pre-Post Synthesis Mismatches

RTL Synthesis
Gates

=/

• Causes
• Sensitivity list mismatches
• Pragmas affect synthesis but not simulation
• SystemVerilog Solves these problems
• Specialized always blocks automate sensitivity
• Synthesis directives built into the language
19
Design Intent – always_{comb,latch,ff}
• always blocks do not //OOPS forgot Else but it’s
guarantee capture of intent //only a synthesis warning
always @(a or b)
• If not edge-sensitive then if (b) c = a;
only a warning if latch
inferred
//Compiler now asks
• always_comb, always_latch //“Where’s the else?”
and always_ff are explicit always_comb
• Compiler Now Knows User if (b) c = a;
Intent and can flag errors //Intent: Conditional
accordingly // Assignment
always_latch
if (clk)
if (en) Q <= d;
//Conversely unconditionally
//assigned –is it a latch?
always_latch
q <=d

20
always_comb Sensitivity
• always_comb eliminates sensitivity list issues
• Ensures synthesis-compatible sensitivity
• Helps reduce “spaghetti code”
• Consider that always_comb derives sensitivity from
• RHS/expr in process
• RHS/expr of statements in Function Calls
logic avar,a,b,c,d,e;
logic [1:0] sel;
always_comb begin
a = b; always @(sel,b,c,d,e) begin
StepA(); a = b;
end case (sel)
…
function StepA
endcase
case (sel)
end
2’b01: avar = a | c;
2’b10: avar = d & e;
Encapsulate blocks of
default: avar = c;
combinational logic into functions –
endcase
endfunction
Easier to read and debug
21
 Design Intent – Unique/Priority
• Parallel_case/full_case pragmas affect synthesis behavior
but not simulation behavior
• Unique keyword means that one and only one branch will be taken
(same as full_case parallel_case)
• Priority keyword means that the first branch will be taken (same
as full_case)
• Will cause simulation run-time error if illegal value is seen
sel must be unique case (sel) unique if (sel==3’b001)
“one-hot” sel[0] : muxo = a; muxo = a;
sel[1] : muxo = b; else if (sel == 3’b010)
sel[2] : muxo = c; muxo = b;
No default endcase else if (sel == 3’b100) No ending
clause needed muxo = c; else needed

priority case (1’b1) priority if (irq0)

irq0 has irq0: irq = 4’b1 << 0; irq = 4’b1;
highest irq1: irq = 4’b1 << 1; else if (irq1)
priority irq2: irq = 4’b1 << 2; irq = 4’b2;
irq3: irq = 4’b1 << 3; else if (irq2)
endcase irq = 4’b4;

22
Syntax – Implicit Named Port
Connections
• Creating netlists by hand is
tedious
• Generated netlists are module top();
unreadable logic rd,wr;
• Many signals in tri [31:0] dbus,abus;
instantiations tb(.*);
dut(.*);
• Instantiations cumbersome
to manage endmodule

• Implicit port connections module top();

dramatically improve logic rd,wr;
readability tri [31:0] dbus,abus;
• Use same signal names up tb tb(.*, .ireset(start),
and down hierarchy where .oreset(tbreset));
possible dut d1(.*,.reset(tbreset[0]));
dut d2(.rd, .wr, .dbus, .abus,
• Port Renaming Accentuated .reset(tbreset[1]));
• .name allows explicit endmodule
connections with less typing
(and less chance for error)

23
SystemVerilog Interfaces
Design On A White Board HDL Design

Complex signals
SystemVerilog Bus protocol repeated in blocks
Interface Bus Hard to add signal through hierarchy
Design Signal 1
Signal 2
Read()
Communication encapsulated in interface
Write()
- Reduces errors, easier to modify
Bus Bus Assert
- Significant code reduction saves time
- Enables efficient transaction modeling
Bus
- Allows automated block verification

24
 Example without Interface
entity memMod is architecture netlist of top is
port(reg,clk,start : in bit; signal req,gnt,start,rdy : bit;
mode : in std_logic_vector(1 downto 0); signal clk : bit := ‘0’;
addr : in std_logic_vector(7 downto 0); signal mode :
std_logic_vector(1 downto 0);
data : inout std_logic_vector(7 downto 0);
signal addr, data :
gnt, rdy : out bit); std_logic_vector(7 downto 0);
end memMod;
mem: memMod port map
architecture RTL of memMod is (req,clk,start,mode,
process (clk) begin addr,data,gnt,rdy);
wait until clk’event and clk=‘1’; cpu: cpuMod port map
gnt <= req AND avail; (clk,gnt,rdy,data,
end architecture RTL; req,start,mode,addr);
end architecture netlist;
entity cpuMod is
port(clk, gnt, rdy : in bit;
data : inout std_logic_vector(7 downto 0);
Top clk
req, start : out bit; req
mode : out std_logic_vector(1 downto 0); start
addr : out std_logic_vector(7 downto 0)); gnt
rdy

CPU Mem
end cpuMod; mode[1:0]

addr[7:0]
architecture RTL of cpuMod is
... data[7:0]
end architecture RTL;

25
 Example Using Interfaces
interface simple_bus; module top;
logic req,gnt; bit clk = 0;
Bundle
logic [7:0] addr,data; simple_bus sb_intf;
signals in
logic [1:0] mode; interface instance
interface
logic start,rdy; memMod mem(sb_intf, clk);
endinterface: simple_bus
cpuMod cpu(.b(sb_intf),
Use interface .clk(clk));
keyword in port list endmodule
Connect
module memMod(interface a, interface
input bit clk);
logic avail;
always @(posedge clk)
a.gnt <= a.req & avail; Top clk
endmodule
Refer to intf
signals
module cpuMod(interface b, sb_intf
input bit clk); CPU Mem
endmodule

26
 Using Different Interfaces
typedef logic [31:0] typedef logic [31:0]
data_type; data_type;

bit clk; bit clk;

always #100 clk = !clk; always #100 clk = !clk;

parallel channel(clk); serial channel(clk);

send s(clk, channel); send s(clk, channel);
receive r(clk, channel); receive r(clk, channel);

module send(input bit clk,

send receive interface ch);
data_type d;
parallel
serial
interface ...
Module inherits
communication
ch.write(d); method from
endmodule interface

Simplifies design exploration

Extends block-based design to the communication between blocks
27
 Conventional Verification
Strategy
• Pre- tbA tbB • Testbench reuse
Integration problems
• tbA and tbB separate
Test
Subblocks in A B
isolation

tbS • Complex
Only need to
interconnect
test S
interconnect • Hard to create tests
to check all signals
structure. A B
(missing wires, • Slow, runs whole
twisted busses) design even if only
structure is tested

• Post-
Integration
28
 SystemVerilog Verification
Strategy
• Pre-Integration
• Interfaces provide
tbI
tbA tbB reusable
I I components
• tbA and tbB are
Test
I
in ‘linked’
f ace s A B
inter ion
• Interface is
isolat executable spec
• Wiring up is simple
and not error prone
• Post-Integration • Interfaces can
tbS contain protocol
checkers and
S coverage counters
Protocol bugs • Start Chip-Level
already flushed A I
B Verification at the
out Block Level

29
Operator Overloading
• Enable use of simple operators with Complex SV Types
struct3 = struct1 + struct2
• Operator Overloading is allowed for type combinations
not already defined by SV Syntax
bind overload_operator function data_type
function_identifier (overload_proto_formals)
typedef struct {
bit sign;
bit [3:0] exponent;
bit [10:0] mantissa;
} float;
bind + function float faddfr(float, real);
bind + function float faddff(float, float);
float A, B, C, D;
assign A = B + C; //equivalent to A = faddff(B, C);
assign D = A + 1.0; //equivalent to A = faddfr(A, 1.0);

30
Packages and Separate
Compilation
• Allows sharing of: package ComplexPkg;

• nets, variables, types, typedef struct {

float i, r;
• tasks, functions } Complex;
• classes, extern function Complex add(Complex a, b)
constraints, extern add.r = a.r + b.r;
methods add.i = a.i + b.i;
endfunction
• parameters, localparams,
function Complex mul(Complex a, b)
spec params mul.r = (a.r * b.r) + (a.i * b.i);
• properties, sequences mul.i = (a.r * b.i) + (a.i * b.r);
endfunction
• Allows unambiguous
references to shared endpackage : ComplexPkg

declarations
• Built-in functions and types module foo (input bit clk);
import ComplexPkg::*
included in std package Complex a,b;
• Groups of files can now be always @(posedge clk)
compiled separately c = add(a,b);
endmodule
31
Agenda
• Introduction
• SystemVerilog Design Features
• SystemVerilog Assertions
• SystemVerilog Verification Features
• Using SystemVerilog and VHDL Together

32
What is an Assertion?
A concise description of [un]desired behavior

0 1 2 3 4 5
req

ack
Example intended behavior

“After the request signal is asserted, the

acknowledge signal must come 1 to 3 cycles later”

33
 Concise and Expressive SVA
property req_ack;
SVA Assertion @(posedge clk) req ##[1:3] $rose(ack);
endproperty
as_req_ack: assert property (req_ack);

sample_inputs : process (clk)

always
begin @(posedge req) Verilog
VHDL
if rising_edge(clk) then
begin
STROBE_REQ <= REQ;
repeat
STROBE_ACK (1) @(posedge clk);
<= ACK;
end if;
0 1 2 3 4 5 fork: pos_pos
end process;
begin
protocol: process

req variable CYCLE_CNT : Natural;

begin
@(posedge ack)
loop $display("Assertion Success",$time);
wait until rising_edge(CLK);
disable
exit when (STROBE_REQ pos_pos;
= '0') and (REQ = '1');
ack end loop; end
CYCLE_CNT := 0;
Example intended behavior loop begin
wait until rising_edge(CLK);
repeat (2) @(posedge clk);
CYCLE_CNT := CYCLE_CNT + 1;
$display("Assertion
exit when ((STROBE_ACK Failure",$time);
= '0') and (ACK = '1')) or (CYCLE_CNT = 3);
end loop;
disable pos_pos;
if ((STROBE_ACK = '0') and (ACK = '1')) then
report end
"Assertion success" severity Note;
else
join
report "Assertion failure" severity Error;
end
end if; // always
HDL Assertion end process protocol;

34
 Sequential Regular Expressions
• Describing a sequence of events
• Sequences of Boolean expressions can be described
with a specified time step in-between

@(posedge clk) a ##1 b ##4 c ##[1:5] z;

z
c
b
a
clk

35
 Property Definition
• Property Declaration: property
• Declares property by name
• Formal parameters to enable property reuse
• Top Level Operators
–not desired/undesired
–disable iff reset
–|->, |=> precondition
• Assertion Directives
• assert – checks that the property is never violated
• cover – tracks all occurrences of property
property prop1(a,b,c,d);
disable iff (reset)
(a) |-> [not](b ##[2:3]c ##1 d);
endproperty
assert1: assert prop1 (g1, h2, hxl, in3);
36
Manipulating Data:
Local Dynamic Variables
• Declared Locally within Sequence/Property
• New copy of variable for each sequence invocation
• Assigned anywhere in the sequence
• Value of assigned variable remains stable until
reassigned in a sequence
Local Dynamic Variable Example

valid
in EA BF
out EB C0

property e;
int x;
(valid,(x=in))|=> ##5(out==(x+1));
endproperty
37
Embedding Concurrent Assertions
property s1;
(req && !gnt)[*0:5] ##1 gnt && req ##1 !req ;
endproperty
• Automatically Updates
always @(posedge clk or negedge reset) Enabling Condition as
if(reset == 0) do_reset; Design Changes
else if (mode == 1) • Infers clock from
case(st) instantiation
REQ: if (!arb)
if (foo)
• Requires User to Update
st <= REQ2;
PA: assert property (s1); Manually as Design
Changes
property p1;
@(posedge clk) ((reset == 1) && (mode == 1)
&& (st == REQ) && (!arb) && (foo)) => s1;
endproperty

DA: assert property (p1);

38
 Bind statement
bind module_or_instance_name instantiation;

Top module/instance name

cpu1
module cpu(a,b); bind cpu cpu_props cpu_rules1(a,b,c);
reg c;
... instance name
endmodule
program name
cpu2
module cpu(a,b); program cpu_props(input d,e,f);
reg c; assert property (d ##1 e |=> f[*3]);
... endprogram
endmodule
Equivalent to:
assert property (top.cpu1.a ##1 top.cpu1.b |=> top.cpu1.c[*3]);
assert property (top.cpu2.a ##1 top.cpu2.b |=> top.cpu2.c[*3]);
or
cpu_props cpu_rules1(a,b,c); // in module cpu

Bind assertions to VHDL code

39
Flexible Assertions Use-Model
• Design Engineers
• Able to define assertions in-line with design code
• Assertions typically cover implementation-level
detail
• Capture assumptions while they’re fresh in the
designer’s mind
• Verification Engineers
• Able to define assertions external to RTL code and
“bind” them to the design
• Assertions typically cover interface/system
behavior
• Do not need to modify the golden RTL to add
assertions

40
Agenda
• Introduction
• SystemVerilog Design Features
• SystemVerilog Assertions
• SystemVerilog Verification Features
• Using SystemVerilog and VHDL Together

41
Dynamic Arrays
Declaration syntax
<type> <identifier> [ ];
bit[3:0] dyn[ ];
Initialization syntax
<array> = new[<size>];
dyn = new[4]; dyn
Equivalent to:
bit[3:0] dyn[0:3];

Size method
function int size();
int j = dyn.size;//j=4
Resize syntax
dyn = new[j * 2];
Equivalent to:
bit[3:0] dyn[0:7];

42
Associative Arrays
• Sparse Storage
• Elements Not Allocated Until Used
• Index Can Be of Any Packed Type, String or Class

Declaration syntax
<type> <identifier> [<index_type>];
<type> <identifier> [*]; // “arbitrary” type

Example
struct packed {int a; logic[7:0] b} mystruct;
int myArr [mystruct]; //Assoc array indexed by mystruct

Built-in Methods
num(), delete([index]), exists(index);
first/last/prev/next(ref index);
Ideal for Dealing with Sparse Data
43
Queues
• Variable-sized Array: data_type name [$]
• Uses array syntax and operators
int q[$] = { 2, 4, 8 }; int e, pos, p[$];
e = q[0]; // read the first (leftmost) item
e = q[$]; // read the last (rightmost) item
q = { q, 6 }; // append: insert ‘6’ at the end
q = { e, q }; // insert ‘e’ at the beginning
q = q[1:$]; // delete the first (leftmost) item
q = q[1:$-1]; // delete the first and last items

• Synthesizable if maximum size is known

• q[$:25] // maximum size is 25

44
Dynamic Processes and Threads
• SystemVerilog adds dynamic parallel processes
using fork/join_any and fork/join_none
fork fork fork

join join_any join_none

• Threads created via fork…join

• Threads execute until a blocking statement
• wait for: (event, mailbox, semaphore, variable, etc.)
• disable fork to terminate child processes
• wait_child to wait until child processes complete
• Built-in process object for fine-grain control
Multiple Independent Threads
Maximize Stimulus Interactions
45
Inter-Process Synchronization
• Events
• Events are variables – can be copied, passed to tasks,
etc.
• event.triggered; // persists throughout timeslice,
avoids races
• wait_order(), wait_any(), wait_all(<events>);
• Semaphore – Built-in Class
semaphore semID = new(1);
semID.get(1);
semID.put(1);
keys

• Mailbox – Built-in Class

• Arbitrary type

packetN
packet1
mailbox #(type) mbID = new(5);
mbID.get(msg);
mbID.put(msg);

Ensures meaningful, race-free

communication between processes

46
Class Definition
Definition syntax
class name;
<data_declarations>; class Packet;
<task/func_decls>; bit[3:0] cmd;
endclass int status;
myStruct header;
extern keyword function int get_status();
allows for out-of-body return(status);
method declaration endfunction
extern task set_cmd(input bit[3:0] a);
endclass

“::” operator links

method declaration to
task Packet::set_cmd(input bit[3:0] a);
Class definition
cmd = a;
endtask

Note: Class declaration does

not allocate any storage
47
Class Instantiation
Declare myPkt handle;
No storage allocated yet

Packet myPkt
myPkt;= new;
Call to “new” method
allocates storage for object

myPkt
cmd
status

header

• User may override default “new” method

• Assign values, call functions, etc.
• User-defined new method may take arguments
• Garbage Collection happens automatically
48
Class Inheritance
•Keyword extends
Denotes Hierarchy of class ErrPkt extends Packet;
Class Definitions bit[3:0] err;
• Subclass inherits function bit[3:0] show_err();
properties, constraints return(err);
and methods from endfunction
parent task set_cmd(input bit[3:0] a);
• Subclass can redefine cmd = a+1;
methods explicitly endtask // overrides Packet::set_cmd
endclass

Packet: ErrPkt:
cmd cmd
status get_status status get_status

show_err
header header
set_cmd set_cmd
cmd = a; err cmd = a+1;

Allows Customization Without Breaking or Rewriting

Known-Good Functionality in the Base Class
49
Constrained Random Simulation
Test Scenarios
• Valid Inputs Specified as Constraints
Constraints
• Declarative
Constraints

Input Space
Design

Constraint Solver
• Find solutions
Valid

Exercise Hard-to-Find Corner Cases

While Guaranteeing Valid Stimulus
50
Basic Constraints
• Constraints are Declarative
class Bus;
rand bit[15:0] addr;
rand bit[31:0] data;
randc bit[3:0] mode;
constraint word_align {addr[1:0] == 2’b0;}
endclass
• Calling randomize selects values for all
random variables in an object such that all
constraints are satisfied
• Generate 50 random data and word_aligned addr values
Bus bus = new;
repeat (50)
if ( bus.randomize() == 1 ) // 1=success,0=failure
$display ("addr = %16h data = %h\n", bus.addr,
bus.data);
else
$display ("Randomization failed.\n");
51
 In-Line Constraints
• Additional Constraints In-line Via
obj.randomize()with <constraint_blk>
task exerBus(MyBus m); Force type
int r; to be small
r = m.randomize() with {type==small};
endtask

• In-Line Constraints Pick Up Variables From

the Object

52
 Layered Constraints
• Constraints Inherited via Class Extension
• Just like data and methods, constraints can be
inherited or overridden
typedef enum { low, high, other } AddrType ;
type variable
class MyBus extends Bus; selects address
rand AddrType type;
constraint addr_rang { range
( type == low ) => addr in { [ 0 : 15] };
( type == high ) => addr in { [128 : 255] }; }
endclass

• Bus::word_align Constraint is also active

• Inheritance allows layered constraints
• Constraints can be enabled/disabled
via constraint_mode() method
Allows Reusable Objects to be Extended and/or
Constrained to Perform Specific Functions
53
Weighted Random Case
• Randomly select one statement
• Label expressions specify distribution weight
randcase
3 : x = 1; // branch 1
1 : x = 2; // branch 2
a : x = 3; // branch 3
endcase

• If a == 4:
–branch 1 taken with 3/8 probability (37.5%)
–branch 2 taken with 1/8 probability (12.5%)
–branch 3 taken with 4/8 probability (50.0%)

54
Scope Randomization &
Constraint Checking
• randomize method can be applied to any
variable
[std::] randomize ( [ variable_list ] ) [ with { constraint_block } ]
module stim;
bit[15:0] a;
bit[31:0] b;
Optional “::” namespace operator to
function bit gen_stim(); disambiguate method name
bit success, rd_wr;
success = randomize( a, b, rd_wr ) with { a > b };
return rd_wr ;
endfunction
...
endmodule

• Constraints can be checked in-line

status = class_obj.randomize(null);
Passing “null” argument to randomize
checks the constraints
0 = valid, 1 = invalid

55
Functional Coverage
• New covergroup container allows
declaration of
• coverage points
–variables
–expressions
–transitions
• cross coverage
• sampling expression : clocking event

enum { red, green, blue } color; Sample event

bit [3:0] pixel_adr;

covergroup g1 @(posedge clk); 3 bins for color

c: coverpoint color;
a: coverpoint pixel_adr; 16 bins for pixel
AxC: cross color, pixel_adr; 48 (=16 * 3)
endgroup; cross products
56
Synchronous Interfaces: Clocking
clk
enable
device bus full Synchronous
data[7:0] Interface
empty

clocking bus @(posedge clk); Clocking Event “clock”

default input #1ns output #2ns; Default I/O skew
input enable, full;
inout data;
output empty;
endclocking

initial begin
tb_en = bus.enable; // read sampled value of enable
bus.empty <= 1; // write “empty” after 2 ns
end
57
Program Block
• Purpose: Identifies verification code
• A program differs from a module
• Only initial blocks allowed
• Special semantics
– Executes in Reactive region
design → clocking/assertions → program
• Program block variables cannot be modified by
the design
program name (<port_list>);
<declarations>;// type, func, class, clocking…
<continuous_assign>
initial <statement_block>
endprogram

The Program block functions pretty much like a C program

Testbenches are more like software than hardware
58
 TB + Assertions Example
A new bus cycle may not start for 2 clock
cycles after an abort cycle has completed
sequence abort_cycle; as
ds
!rdy throughout (as ##1 ds[*1:$] ##1 abort); rdy
abort
endsequence

cover property (@(posedge clk) abort_cycle)

wait_cnt = 2;

property wait_after_abort;
@(posedge clk) abort_cycle |=> !as[*2];
endproperty
assert property (wait_after_abort);

program manual_stimulus_generator;
Simulation Monitors repeat(1000) begin
and Constraints generate_transaction(addr,data);
for Formal while(wait_cnt > 0)
@(posedge clk) wait_cnt--;
Analysis end
endprogram
59
 SystemVerilog Enhanced Scheduling
Previous
Time Slot
Active

Inactive

NBA

Next
Read-Only Time Slot

60
 SystemVerilog Enhanced Scheduling
Previous
Time Slot
Preponed Active

Inactive Verilog
Sample 2001
Stable
Values NBA
Evaluate
Assertions
Observe
SystemVerilog
Execute
3.1 TestBench
Reactive
Next
Postponed Time Slot

61
Agenda
• Introduction
• SystemVerilog Design Features
• SystemVerilog Assertions
• SystemVerilog Verification Features
• Using SystemVerilog and VHDL Together

62
SystemVerilog With VHDL
• Verilog-VHDL Interface limited to net/vector
types
• VHDL records and arrays packed into bit
vectors
• SystemVerilog supports higher-level data
types
• Synthesizable types are synthesizable across
the interface

VHDL SystemVerilog
Record Struct
Array Array
Multi-D Array Multi-D Array
Enum Enum
63
Pure VHDL Simulation Flow
+ Single language (VHDL) for
Design Testbench
design and testbench

- No constrained
VHDL RTL VHDL
random TB
Performance
- No temporal
assertions
Effectiveness
- No functional
coverage

• Coherent environment for design and verification

• Limited testbench capabilities in VHDL “promote” a
directed test based verification methodology
• Lack of constrained random / assertion / coverage
low “bug-finding effectiveness”

64
 SystemVerilog is Evolutionary for
VHDL and Verilog Users
Design Testbench Design
SystemVerilog
HVL VHDL/ Verilog
VHDL / Verilog
(Behavioral Testbench
RTL)
C/C++  Assertions
VHPI / FLI

• Increases productivity for

Design and Verification SystemVerilog
• Concise coding constructs Design

• Rich assertions Testbench

• Complete testbench  Assertions

– Constrained Random Performance

Data
– Functional Coverage Effectiveness

65
 The Importance of a Single
Language
Unified Scheduling Knowledge of
• Basic Verilog Other Language
won’t work Features
• Ensures Pre/Post- • Testbench and
Synth Consistency Assertions
• Enables • Interfaces and
Performance Classes
Optimizations • Sequences
and Events
Reuse of Syntax/Concepts
• Sampling for assertions and clocking domains
• Method syntax
• Queues use common concat/array operations
• Constraints in classes and procedural code
66
SystemVerilog Benefits for VHDL Users
• Many VHDL modeling features are in SystemVerilog
• Don’t have to give up high-level data types
• Some features (enums) extended beyond VHDL
capabilities
• Mixed-HDL environments are a reality
• Higher-level data types supported across boundary
• Continue to use VHDL legacy blocks
• Easier to adopt SystemVerilog incrementally
• Industry-Standard Verification Language works
with VHDL designs
• Constrained random data generation
• Object-oriented
• Assertions
• SystemVerilog supports Design for Verification
• Interfaces and assertions capture design intent
• Efficient and intuitive interactions between testbench and
assertions 67
 Evolution of Verification Productivity
Unified
Language

Formal
Testbench
Assertions C++
Unified
Coverage Mixed-
Mixed-HDL Platforms

Unified
Methodology Axes of Verification Productivity

68