Instruction Set Of 8085 Microprocessor

S.No Instruction Operation Byte Addressing Example

Mode
1. MVI r,data(8) r  8 bit data 2 Immediate MVI A,20h
2. MVI M,data(8) (HL)  8 bit data 2 Immediate MVI M,40h
3. MOV rd,rs rd  rs 1 Register Mov C,A
4. MOV M,rs (HL)  rs 1 Register,Indirect MOV M,A
5. MOV rd,M rd  (HL) 1 Register,Indirect MOV B,M
6. LXI rp,data(16) rp  data(16) 3 Immediate LXI B,1020h
7. STA addr (addr)  A 3 Direct STA 8000h
8. LDA addr A  (addr) 3 Direct LDA 8000h
9. SHLD addr (addr)  L 3 Direct SHLD 2500h
(addr)  H
10. LHLD addr L  (addr) 3 Direct LHLD 2500h
H  (addr+1)
11. STAX rp (rp)  A 1 Register,Indirect STAX B
12. LDAX rp A  rp 1 Register,Indirect LDAX D
13. XCHG H D 1 Register XCHG
L E
14. ADD r Ar+A 1 Register ADD B
15. ADD M A  HL + A 1 Register,Indirect ADD M
16. ADI data(8) A  A + data(8) 2 Immediate ADI 20h
17. ADC r A  A + r + cy 1 Register ADC A
18. ADC M A  A + (HL) + Cy 1 Register,Indirect ADC M
19. ACI data(8) A  A + Cy + data(8) 2 Immediate ACI 20h
20. DAD Rr HL  HL + rp 1 Register DAD B
21. SUB r AA–r 1 Register SUB B
22. SUB M A  A – (HL) 1 Register,Indirect SUB M
23. SUI data(8) A  A – data(8) 2 Immediate SUI 20h
24. SBB r AA–r–B 1 Register SBB B
25. SBB M A  A – (HL) – B 1 Register,Indirect SBB M
26. SBI data(8) A  A – data(8) – B 2 Immediate Sbi 20H
27. DAA A(BCD)  A(Binary) DAA
28. INR r r  data in r + 1 1 Register INR B
29. INR M (HL)  (HL) + 1 1 Register INR M
30. INX rp rp  rp + 1 1 Register INX B
31. DCR r r  data in r - 1 1 Register DCR B
32. DCR M (HL)  (HL) – 1 1 Register DCR M
33. DCX rp rp  rp – 1 1 Register DCX B
34. ANA r AA r 1 Register ANA B
35. ANA M AA (HL) 1 Register,Indirect ANA M
36. ANI data(8) A  A data(8) 2 Immediate ANI 8000h
37. XRA r AA r 1 Register XRA B
38. XRA M A  A (HL) 1 Register,Indirect XRA M
39. XRI data(8) A  A data(8) 2 Immediate XRI 8000h
40. ORA r AAUr 1 Register ORA B
41. ORA M AAUM 1 Register ORA M
42. ORI data(8) A  A U data(8) 2 Immediate ORI 20h
43. CMP r A --- r 1 Register CMP D
44. CMP M A --- (HL) 1 Register CMP M
45. CPI data(8) A --- data(8) 2 Immediate CPI 20h
46. STC Cy  1 1 Implied STC
47. CMC Cy  1 Implied CMC
48. CMA A 1 Implied CMA

49. RLC 1 Implied RLC

50. RRC 1 Implied RRC

51. RAL 1 Implied RAL

52. RAR 1 Implied RAR

53. PUSH rp SP  SP – 1, SP  rpH Register,Indirect PUSH B

SP  SP - 1,(SP)  rpL
54. PUSH PSW SP  SP - 1,(SP)  A 1 Register,Indirect PUSH PSW
SP  SP – 1,
(SP)  flag register
55. POP rp rpL  (SP),Sp  SP + 1 1 Register,Indirect POP A
rpH  (SP),SP  SP + 1
flag register  (SP)
56. POP PSW SP  SP + 1,A (SP), 1 Register,Indirect POP PSW
SP  SP + 1
57. SPHL SP  HL 1 Register SPHL
58. XTHL L (SP),H (SP+1) 1 Register,Indirect XTHL
59. JMP addr PC  addr 3 Direct JMP 8000h
60. J cond addr If cond. is true,PCaddr 3 Immediate J
61. PCHL PC  HL 1 Register PCHL
CALL addr (SP – 1)PCh 3 Immediate CALL 800h
62.
63. If cond true,(SP-1)PCh,
CALL cond addr (SP-2)PCl,SPSP-2, 3 Immediate
PCaddr
64. RET PCl(SP),PCh(SP+1), 1 Register,Indirect RET
SPSP+2
65. RET cond If cond. true, PCl(SP), 1 Register,Indirect RET
 PCh(SP+1),SPSP+2
66. RST n (SP-1)PCh,(SP-2)PCl, 1 Register,Indirect RST 8
SPSP-2,PC(nx8) in hex
67. IN addr A  (addr) 2 Direct IN 8000h
68. OUT addr (addr)  A 2 Direct OUT 8000h
69. EI IE(F/F)  1 1 ----- EI
70. DI IE(F/F)  0 1 ----- DI
71. NOP No Operation 1 ----- NOP
72. HLT Halts the processor 1 ----- HLT
73. SIM Serial Input Mask 1 ----- SIM
74. RIM Read Interrupt Mask 1 ----- RIM