13.
Sequential Circuit Timing
Objectives
This section covers several timing considerations encountered
in the design of synchronous sequential circuits. It has the
following objectives:
Define the following global timing parameters and show
how they can be derived from the basic timing parameters
of flip-flops and gates.
Maximum Clock Frequency
Maximum allowable clock skew
Global Setup and Hold Times
Discuss ways to control the loading of data into registers
and show why gating the clock signal to do this is a poor
design practice.
Elec 326 13.1 Sequential Circuit Timing
Reading Assignment
Much of the information in this section is not in the Brown
& Vranesic text. There is material on clock skew in section
10.3. That section also discusses the effects of gating the
clock.
Elec 326 13.2 Sequential Circuit Timing
13.1. Maximum Clock Frequency
The clock frequency for a synchronous sequential
circuit is limited by the timing parameters of its flip-
flops and gates. This limit is called the maximum
clock frequency for the circuit. The minimum clock
period is the reciprocal of this frequency.
Relevant timing parameters
Gates:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Flip-Flops:
Propagation delays: min tPLH, min tPHL, max tPLH, max tPHL
Setup time: tsu
Hold time: th
Elec 326 13.3 Sequential Circuit Timing
Example
D Q Q
CK Q
TW ≥ max tPFF + tsu
For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns
TW ≥ max (max tPLH + tsu, max tPHL + tsu)
TW ≥ max (25+20, 40+20) = 60
Elec 326 13.4 Sequential Circuit Timing
Example
D Q Q
CK
TW ≥ max tPFF + max tPINV + tsu
Elec 326 13.5 Sequential Circuit Timing
Example
0
Q0 D Q
Q1
D Q MUX
1
Q Q
CK
TW ≥ max tPFF + max tPMUX + tsu
Elec 326 13.6 Sequential Circuit Timing
Example
Paths from Q1 to Q1: None
Paths from Q1 to Q2: TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns
TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns
Paths from Q2 to Q1: TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns
Paths from Q2 to Q2: TW ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns
TW ≥ 47 ns
Elec 326 13.7 Sequential Circuit Timing
Clock Skew
If a clock edge does not arrive at different flip-flops at
exactly the same time, then the clock is said to be skewed
between these flip-flops. The difference between the times
of arrival at the flip-flops is said to be the amount of clock
skew.
Clock skew is due to different delays on different paths
from the clock generator to the various flip-flops.
Different length wires (wires have delay)
Gates (buffers) on the paths
Flip-Flops that clock on different edges (need to invert clock for
some flip-flops)
Gating the clock to control loading of registers (a very bad idea)
Elec 326 13.8 Sequential Circuit Timing
Example (Effect of clock skew on clock rate)
Clock C2 skewed after C1
D2 Q2
D Q
Q1 D Q
C2
C1 Q
Q
CK
TW ≥ max TPFF + max tOR + tsu TW ≥ max TPFF + max tOR + tsu - min tINV
(if clock not skewed, i.e., tINV = 0) (if clock skewed, i.e., tINV > 0)
Elec 326 13.9 Sequential Circuit Timing
Clock C1 skewed after C2
D2 Q2
D Q
Q1 D Q
C2
C1 Q
Q
CK
TW ≥ max TPFF + max tOR + tsu
(if clock not skewed, i.e., tINV = 0)
TW ≥ max TPFF + max tOR + tsu + max tINV
(if clock skewed, i.e., tINV > 0)
Elec 326 13.10 Sequential Circuit Timing
Summary of maximum clock frequency calculations
Q1 D2
D Q D Q
Logic
C1 Network C2
TW
TW
C1
C1 tSK = tINV
tSK = tINV C2
C2
Q1
Q1
D2
D2
tPFF tOR
tPFF tOR tsu
tsu
C2 skewed after C1: TW ≥ max TPFF + max tNET + tsu - min tINV
C2 skewed before C1: TW ≥ max TPFF + max tNET + tsu + max tINV
Elec 326 13.11 Sequential Circuit Timing
Example
tXY = Network delay from X to Y
tXD = Network delay from X to D
tQY = Network delay from Q to Y
tQD = Network delay from Q to D
For each of the following two connections find
The minimum clock period
The maximum and minimum delay from CLK to YOUT
Elec 326 13.12 Sequential Circuit Timing
Circuit 1:
n≥2
t = Network delay from X to Y
XY
t = Network delay from X to D
XD
t = Network delay from Q to Y
QY
t = Network delay from Q to D
QD
Minimum Clock Period:
Tw ≥ max tPFF + max tQY + (n-2) max tXY +max tXD + tsu ≥ TW
Tw ≥ max tPFF + max tQD + tsu
Maximum Delay:
TCY ≤ max tPFF + max tQY + (n-1) max tXY
Minimum Delay:
TCY ≥ min tPFF + min tQY
Elec 326 13.13 Sequential Circuit Timing
Circuit 2:
n≥2
t = Network delay from X to Y
XY
t = Network delay from X to D
XD
t = Network delay from Q to Y
QY
t = Network delay from Q to D
QD
Minimum Clock Period:
Tw ≥ max tPFF + max tXD + tsu
Tw ≥ max tPFF + max tQD + tsu
Maximum Delay:
TCY ≤ max tPFF + max (max tXY, max tQY)
Minimum Delay:
TCY ≥ min tPFF + min (min tXY, min tQY)
Elec 326 13.14 Sequential Circuit Timing
13.2. Maximum Allowable Clock Skew
How much skew between C1 and C2 can be tolerated
in the following circuit?
D Q
Q1 D2 D Q
Q Q
C1 C2
Case 1: C2 delayed after C1
tPFF > th + tSK
tSK < min tPFF - th
Elec 326 13.15 Sequential Circuit Timing
Case 2: C1 delayed from C2
D Q
Q1 D2 D Q
Q Q
C1 C2
Elec 326 13.16 Sequential Circuit Timing
How does additional delay between the flip-flops
affect the skew calculations?
tSK ≤ min tPFF - th
tsk ≤ min tPFF + min tMUX - th
Elec 326 13.17 Sequential Circuit Timing
Summary of allowable clock skew calculations
tSK + th ≤ tPFF + tNET
tSK ≤ min tPFF + min tNET - th
Elec 326 13.18 Sequential Circuit Timing
Example: What is the minimum clock period for the
following circuit under the assumption that the clock
C2 is skewed after C1 (i.e., C2 is delayed from C1)?
N2
D1 Q1 D2 Q2
D Q N1 D Q
Q Q
C1 C2
Elec 326 13.19 Sequential Circuit Timing
N2
D1 Q1 D2 Q2
D Q N1 D Q
Q Q
C1 C2
First calculate the maximum allowable clock skew.
tSK < min tPFF + min tN1 - th
Next calculate the minimum clock period due to the path
from Q1 to D2.
TW > max tPFF + max tN1 + tsu - min tSK
Finally calculate the minimum clock period due to the path
from Q2 to D1
TW > max tPFF + max tN1 + tsu + max tSK
TW > max tPFF + max tN2 + tsu + (min tPFF + min tN1 - th)
TW > max tPFF + min tPFF + max tN2 + min tN1 + tsu - th
Elec 326 13.20 Sequential Circuit Timing
13.3. Global Setup Time, Hold Time and
Propagation Delay
Global setup and hold times (data delayed)
X NET D D Q
CK
CLK Q
TSU = tsu + max tNET TH = th - min tNET
Elec 326 13.21 Sequential Circuit Timing
Global setup & hold time (clock delayed)
D D Q
CK
CLK Q
TSU = tsu - min tC TH = th + max tC
Elec 326 13.22 Sequential Circuit Timing
Global setup & hold time (data & clock delayed)
X NET D D Q
CK
CLK Q
TSU = tsu + max tNET - min tC TH = th - min tNET + max tC
Elec 326 13.23 Sequential Circuit Timing
Global propagation delay
D Q
Q
NET Y
CK
CLK Q
TP = tC + tFF + tNET
Elec 326 13.24 Sequential Circuit Timing
Summary of global timing parameters
TSU = tsu + max tPN - min tPC ≤ tsu + max tPN
TH = th + max tPC - min tPN ≤ th + max tPC
TP = tPFF + tPN + tPC
Elec 326 13.25 Sequential Circuit Timing
Example
Find TSU and TH for input signal LD relative to CLK.
LD Q
D Q
D CK
CLK Q
TSU = tsu +max tNET - min tC
= tsu + max tINV + max tNAND + max tNAND - min tINV
TH = th - min tNET + max tC
= th - min tNAND - min tNAND + max TINV
Elec 326 13.26 Sequential Circuit Timing
13.4. Register load control (gating the clock)
A very bad way to add a load control signal LD to a
register that does not have one is shown below
D D Q
LD CK
Q
CLK
The reason this is such a bad idea is illustrated by the
following timing diagram.
The flip-flop sees two rising edges and will trigger
twice. The only one we want is the second one.
Elec 326 13.27 Sequential Circuit Timing
If LD was constrained to only change when the clock was low,
then the only problem would be the clock skew.
Elec 326 13.28 Sequential Circuit Timing
If gating the clock is the only way to control the
loading of registers, then use the following approach:
D D Q
CLK Q
LD
There is still clock skew, but at least we only have one
triggering edge.
Elec 326 13.29 Sequential Circuit Timing
The best way to add a LD control signal is as follows:
LD
D Q
D
CLK Q
Elec 326 13.30 Sequential Circuit Timing
13.5. Synchronous System Structure and Timing
Elec 326 13.31 Sequential Circuit Timing
13.6. Tips & Tricks
Use timing diagrams to determine the timing properties of
sequential circuits
13.7. Pitfalls
Using typical timing values from the data sheet (use
only max and/or min values)
Gating the clock
Elec 326 13.32 Sequential Circuit Timing
13.8 Review
How the flip-flop and gate timing parameters affect
the maximum possible clock frequency.
How clock skew affect maximum possible clock
frequency.
How the delay of logic between flip-flops affects the
maximum allowable clock skew.
How flip-flop setup and hold times are translated by
the combinational logic delays to get global setup and
hold times.
The detrimental effect of gating the clock signal.
Elec 326 13.33 Sequential Circuit Timing
