EE 577B: VLSI Design Projects Class
Lecture 4: Intro to Verilog
Dr. Jeff Draper,
Ming Hsieh Department of Electrical Engineering
University of Southern California
Course Announcements
Homework
1 due now, Jan 28, 5pm
(10
minute grace period, -10 points at 5:10 and every
10 minutes afterwards)
Homework
Due
2 assigned today
Feb 6, 5pm
Course
web site
http://www.uscden.net
Email
06/15/16
TA/Mentor if you have any problems
EE 577B
Course Announcements
Homework
2 posted on web site today
Due
5pm, Feb 6
Get
started early to stabilize your Verilog environment
Refer
to tutorials on course web site
Follow instructions on electronic submission
Email
TA/Mentor with any questions
TA: Aditya
Deshpande, [email protected]
Mentor: Harpreet Bhatia, [email protected]
Last day to add/drop without penalty is Friday,
February 1
06/15/16
EE 577B
EE577B Grade (Tentative)
Homework:
20 - 25% (5% for each assignment)
Project Part 1: 10 - 15%
Project Part 2: 15 - 20%
Project Part 3: 25%
Project Part 4: 10%
Project Presentation: 10%
Note:
Project will probably require teaming into 2person teams (start considering teammate choices!)
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EE 577B
Tentative Semester Schedule
Assignment
Assignment Date
Due Date
HW1 (577A review)
Jan 16
Jan 28
HW2 (Verilog)
Jan 28
Feb 6
HW3 (More Verilog)
Feb 6
Feb 20
HW4 (Synthesis)
Feb 20
Feb 27
P1 (Verilog)
Feb 27
Mar 13
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EE 577B
Potential Info for Career Fair
Skills and tools you will use in this class
RTL specification
in Verilog
Synopsys: Design Compiler (synthesis), Primetime
(static timing analysis)
Cadence: NC-Sim (simulation), First Encounter
(place&route), Conformal (logical equivalence
checking)
Project
candidates:
Pipelined processor, network-on-chip router,
pipelined FPU, pipelined multi-media
extension unit, multi-core processor, etc
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Lecture Plan for next few weeks
Todays lecture:
Intro to Verilog
Needed for remaining homework assignments
and first phase(s) of project
More Verilog
concepts/sources
Semester Project Intro
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EE 577B
Motivation for Verilog Modeling
Architecture
Description
First step in design flow is
translating text description
of architecture to a
hardware description
language
HDL Specification
(Behavioral, Structural)
Synopsys Synthesis
Needed for signal-level
detailed description and
verification of device
operation
(Structural)
Cadence Place & Route
(Physical)
Mentor Physical Verification
(DRC, LVS, etc)
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Verilog References
References
A Verilog
HDL Primer
J.
Bhasker
Verilog HDL: A Guide to Digital Design and
Synthesis
Samir
Palnitkar
Many on-line references
Look
06/15/16
at VLSI CAD Tools web site
http://www-scf.usc.edu/~ee577/
EE 577B
What is Verilog?
Verilog
is a hardware description language
(HDL) for modeling, specifying, and verifying
the design of digital systems.
History
Proprietary
language at Gateway Design Automation
(now Cadence) in 1983
Public
IEEE
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domain in 1990
standard in 1995
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Verilog Features
Verilog
can model designs at several levels:
Behavioral
Algorithmic
RTL (register
transfer level)
Dataflow
Structural
Gate
Switch
Hybrid
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mixture of levels
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Verilog Identifiers
An
identifier is any sequence of letters, digits,
$, _ (underscore)
First
character must be a letter or _
Examples
Count,
COUNT, _R2_D2, FIVE$
Identifiers
are case-sensitive
Many reserved keywords cannot be used
Example:
always (however ALWAYS is okay, but
obviously not recommended!)
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Comments and Format
Comments
(similar to C++)
Use
delimiter /* to start a multi-line comment and */ to end
Use
// for a single-line comment which ends at the line end
Side
note be liberal with comments in your project code!!!
Verilog
is free-format
Constructs
may be on one line or spread across lines
No distinction between different types of white space
(space, newline, tab, etc)
Example: always #50 clk = ~clk;
is the same as
always
#50 clk = ~clk;
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Value Sets and Constants
Verilog
supports 4 basic values:
: logic-0 or false
: logic-1 or true
(or x) : unknown
(or z) : high-impedance
types of constants
Integer
Real
String
Probably will be using only integers for course project.
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May use strings in error messages.
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Integer Constants
Two
notations for specification of integers
Simple
decimal
Sequence of digits with optional leading + or
Examples: 32, -15
Base format notation
[size]base
Number of bits in constant indicated by size
base is o or O for octal, b or B for binary, d or D for decimal, h or
H for hexadecimal
value is sequence of digits valid for specified base
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value
Values a through f (for hexadecimal base) are case-insensitive
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Base Format Notation Peculiarities
A number in
base format notation is always an
unsigned number
Size specification is optional
Size defaults to number of bits in value
If
size is larger than number of value bits
Number is left-padded with 0s, xs, or, zs
If
size is smaller than number of value bits
Leftmost value bits are truncated
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Base Format Notation Examples
5O37
// 5-bit octal
4d2 // 4-bit decimal
4b1x_01 // 4-bit binary ( _ has no effect but can be
// used for readability)
7hx // xxxxxxx in binary (x-extended)
4d-4 // Not legal: value cannot be negative
8 h 2A // spaces allowed between size and character
// and between base and value
3 b001 // not legal: no space allowed between and //
base b
(2+3)d10 // Not legal; size cannot be an expression
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Base Format Notation Examples
hAF // 8-bit hex value since no size given
o721
// 9-bit octal value
6b10
// 000010, padded to the left with 0s
6bx01 // xxxx01, padded to the left with xs
3b110011 // same as 3b011, truncation
5h0fff
// same as 5h1f, truncation
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Data Types
Verilog
supports 2 basic data types
Nets
Specify
physical connection between structural
elements
Do not store values
Registers
Represent
abstract data storage elements
Value is saved from one assignment to the next
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Data Types: Nets
Net
value is determined by value of its
driver(s)
Usually
specified by continuous assignment statement
or gate output
Defaults
to z if undriven
Examples
wire Rdy, Start; // two 1-bit wire nets
wire [2:0] addr; // 3-bit vector wire net
Many
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net types besides wire will study later
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Data Types: Registers
Register value
assigned only within
always statement
initial statement
Default value of x
Five
different register types: reg, integer, time, real,
realtime
Will
mostly use reg in this class
Examples
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reg [0:31] opA; // opA is a 32-bit register
reg gt, lt;
// gt and lt are 1-bit registers
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Memories
In Verilog,
memories are modeled as arrays of
registers
reg [msb:lsb] mem1 [first_index:last_index];
index is analogous to the memory address
Examples
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reg [0:31] imem [0:255]; /* imem is an array of 256 32-bit
registers models a memory with 8 address bits and 32 data
bits */
reg cond_codes [0:4]; // an array of five 1-bit registers
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Assigning Values to Memories
Can
be done explicitly one entry at a time
reg [0:3] lut [0:3];
lut[0] = 4h0;
lut[1] = 4h1;
Better way
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is to use system tasks:
$readmemb (loads binary values from external file)
$readmemh (loads hex values from external file)
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$readmemh Example
File
lut.fill contains
0 F 5 A
After
execution of
reg [0:3] lut [0:3];
$readmemh (lut.fill, lut)
lut[0] = 0, lut[1] = F, lut[2] = 5, lut[3] = A
Can
specify starting and ending index
$readmemh (lut.fill, lut, 0, 3)
Load
file can specify address of each entry
@0 0
@1 F
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Parameters
Parameters
Typically
are constants not variables
used to specify widths or delays of variables
Parameters
can be assigned a value only once,
using a parameter declaration
parameter BYTE = 8, BIT = 1, TPHL = 2;
Useful
to put parameter declarations at
beginning of Verilog file to support quick
changes
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Operators
Operator types
Arithmetic
(+, -, *, /, %)
Relational
(<, <=, >, >=)
Equality
(= =, !=, = = = , ! = =)
Logical
(&&, ||, !)
Bitwise
(~, &, |, ^, ~^)
Reduction
Shift
(&, ~&, |, ~|, ^, ~^)
(<<, >>)
Conditional
(?:)
Concatenation
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and replication
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Operator Precedence (highest first)
Entries
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in same block have equal precedence
+, -
unary plus, minus
!, ~
unary logical negation, bit-wise negation
&, ~&
reduction and, nand
^, ~^
reduction xor, xnor
|, ~|
reduction or, nor
*, /, %
multiply, divide, modulus
+, -
binary plus, minus
<<, >>
left shift, right shift
<, <=
less than, less than or equal to
>, >=
greater than, greater than or equal to
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Operator Precedence (contd)
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= =, !=
logic equality, inequality
===
case equality
!= =
case inequality
&
bitwise and
^, ~^
bitwise xor, xnor
bitwise or
&&
logical and
||
logical or
?:
conditional operator
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Operator Summary
All
operators associate left to right except for
conditional operator
Examples:
a + b c is evaluated as (a + b) c
A ? B : C ? D : E is evaluated A ? B : (C ? D : E)
Parentheses
can be used to change order of
precedence
Most operators have same meaning as in
similar languages (e.g., C or C++)
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Operator Evaluation with x or z
If
any bit of an operand in arithmetic operation is x
or z, entire result is x
Example:
4b10x1 + 4b0111 evaluates to 4bxxxx
Result
of relational operator is true (value 1) or false
(value 0)
Result
is x if any bit in either operand is x or z
Examples:
23 > 45 evaluates to false (value 0)
52 < 12hxFF evaluates to x
Many
other operators evaluate to x if operands
contain x or z
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Equality Operators
Result
is 0 if comparison is false, otherwise result is 1
For case comparisons, values x and z are compared
strictly as values, with no interpretation
Result
must be 0 or 1, not x
For logical
comparisons, values x and z have usual
interpretations and result may be unknown (x value)
Example: data1 = 4b11x0; data2 = 4b11x0;
data1 == data2 evaluates to x
data1 === data2 evaluates to true (value 1)
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Bitwise Operators
Same
as in C language operate bit-by-bit on
input operands and produce vector result
Some trickery involving x and z but pretty
straightforward
Examples
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&
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Reduction Operators
Operate
on all bits of a single operand and produce a
1-bit result
& - if any bit is 0, result is 0; else if any bit is x or z, result is
x; else result is 1
| - if any bit is 1, result is 1; else if any bit is x or z, result is x;
else result is 0
^ - if any bit is x or z, result is x; else if there are even number
of 1s, result is 0; else result is 1
Examples:
A = 4b0110; B = 4b0100;
| B evaluates to 1, & B evaluates to 0, ~^ A evaluates to 1
Reduction
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nor ( ~| ) useful for zero detect
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Concatenation and Replication
Concatenation
joins bits from smaller
expressions to form larger expressions
Form:
{ expr1, expr2, , exprN}
Example:
wire [0:7] op1, op2; wire [0:15] stage;
assign stage = { op1, op2}; // concatenate op1 with op2
Replication
Form:
{ rep_number {expr}}
Example:
assign stage = {{8{op1[0]}}, op1}; // sign extension
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Assignment Types
Continuous
Used
for assigning values to nets
Useful
for dataflow style of modeling
Procedural
Used
assignment
for assigning values to registers
Useful
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assignment
for RTL style of modeling
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Continuous Assignment
Form:
assign [delay] LHS_target = RHS_expr ;
Example
wire [0:3] out, in1, in2;
assign #5 out = in1 & in2; // bitwise and of 4-bit vectors with 5
// time unit delay
When
is assignment executed?
Whenever
the RHS_expr changes value, the assignment to
LHS_target is executed delay time units later
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If no delay is specified, assignment occurs with zero delay
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Continuous Assignment Delays
Continuous
assignment delays possess an inertial delay
behavior
Changes
in the RHS_expr occurring within the delay interval are
filtered out and do not effect the LHS_target
Example
wire out, in1, in2;
assign #5 out = in1 & in2;
At time 0, let in1 and in2 = 1
At time 5, out evaluates to 1
At time 6, let in1 change to 0
At time 8, let in1 change back to 1
No change on output since input changes back before delay!
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Procedural Assignment
Form:
LHS_target = [delay] RHS_expr ; // (blocking form)
LHS_target <= [delay] RHS_expr ; // (non-blocking form)
Must
occur within initial or always procedural
constructs
When is assignment executed?
In
relation to surrounding statements within the procedural
construct that contains it
Timing
control of procedural construct and delay values also
have an effect
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initial Statement
Begins
execution at start of simulation (time 0) and
executes only once
Form:
initial procedural_statement
Example
reg clr, preset;
initial
begin
clr = 0;
preset = 0;
end
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always Statement
Begins
execution at start of simulation (time 0) and
executes repeatedly
Form:
always [timing_control] procedural_statement
Example
reg Q;
wire D, clk;
always @(posedge clk)
Q = D;
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Procedural Assignment Delays
Blocking procedural assignment are executed in sequence
(assuming sequential block statement); delays accumulate
RHS_expr evaluation of non-blocking procedural
assignments within same block executed concurrently;
delays overlap
Example
reg c, d;
reg a, b;
initial
initial
begin
begin
a = #7 0; // occurs at time 7
c <= #7 0; // occurs at time 7
b = #5 1; // occurs at time 12
d <= #5 1; // occurs at time 5
end
end
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Assignment Summary
Procedural
Continuous
Occurs inside always or initial
statement
Occurs within module
Drives registers
Drives nets
Uses = or <= assignment symbol
Uses = assignment symbol
No assign keyword (except in case of
procedural continuous assignment)
Uses assign keyword
Executes with respect to surrounding
statements
Executes concurrently with other
statements
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Other Procedural Statements
Conditional
just like C
if-else if- else construct
Two
types of case statements
case just like C
x and z treated as explicit literals and must match exactly
casex and casez
x and z treated as dont-cares
Example
casez (sel)
2b1? : out = 0; // ? Can be used for z, matches if sel is 10, 11, 1z
2b01 : out = 1;
default : out = x;
endcase
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Other Procedural Statements
Loop
statements
for loop just like C
while loop just like C
If the while condition is an x or z, it is treated as a
false (0) value and the while loop is exited
repeat loop of the form
repeat ( loop_count ) procedural statement
forever loop of the form
forever procedural statement
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Block Statements
Two
types
Sequential delimiters begin and end
Statements executed sequentially in given order
Delay values are relative to simulation time of execution of
previous statement (except with intra-statement delays of
non-blocking assignments)
Block is exited upon execution completion of final statement
Parallel delimiters fork and join
Statements execute concurrently
Delay values are relative to time when block starts executing
Control passes out of the block when all statements have
completed
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Module
Basic
unit of description in Verilog is the
module
A module describes
Functionality
Ports
or structure of a design
through which it connects with other modules
Modules
provide the mechanism for
hierarchical designs
A module
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may be instantiated within another module
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Module Syntax
module module_name ( port_list )
port declarations: input, output, inout, reg
internal declarations: reg, wire, parameter, function, task,
Statements: initial, always, module instantiation, gate instantiation,
continuous assignment
endmodule
Example
module HA (A, B, S, C);
input A, B;
output S, C;
assign #3 S = A ^ B;
assign #2 C = A & B;
endmodule
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Module Ports
A port
inout is a bidirectional port
Ports
are nets by default
output port may be redeclared as reg
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may be declared input, output, or inout
reg declaration must have the same size as the port
declaration
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Module Port Association
For module
By
instantiation, port associations can be:
position
Order of ports in the instantiation and module definition
defines association
By name
Instantiation port expression and definition port name are
both given
Order is not important
Association styles cannot be mixed within the same
instantiation
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Module Port Association Example
module HA (A, B, S, C);
input A, B;
output S, C;
assign S = A ^ B;
assign C = A & B;
endmodule
module FA (P, Q, Cin, Sum, Cout);
input P, Q, Cin;
output Sum, Cout;
wire S1, C1, C2;
HA h1 (P, Q, S1, C1); // association by position
HA h2 (.A(Cin), .S(Sum), .B(S1), .C(C2)); // association by name
assign Cout = C1 | C2;
endmodule
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Unconnected Module Ports
Unconnected
ports are specified by leaving
port expression blank
Example
DFF d1 (.Q(QS), .Qbar(), .Data(D), .Preset(),
.Clock(CK)); // by name
DFF d2 ( QS, , D, , CK); // by position
Unconnected
inputs are driven to z
Unconnected outputs are simply unused
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Different Port Lengths
When
module port definition has different bit
length than instantiation port expression
Port
matching is performed by:
unsigned right justification when port expression
length contains fewer bits than port definition
truncation when port expression length contains
more bits than port definition
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Different Port Lengths Example
module Child (Pa, Py);
input [4:0] Pa;
output [2:0] Py;
endmodule
module Top;
Pa 4 3 2 1 0
Bdl
1 2
Py 2 1 0
Mpr 2 3 4 5 6
wire [1:2] Bdl;
wire [2:6] Mpr;
Child C1 (Bdl, Mpr);
endmodule
Pa[4:2] are undriven and thus have the value z
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Behavioral Modeling Example: FSM
State
machine guidelines
Develop
separate blocks for:
State memory
Next-state logic
Output logic
Take care of reset appropriately
Use
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parameters for state assignments
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Behavioral Coding Example: FSM
fsmin = 0
fsmin = 0
fsmin = 1
SEE1
fsmout = 1
SEE0
fsmout = 0
fsmin = 1
module FSM (rst, clk, fsmin, fsmout);
input rst, clk, fsmin;
output fsmout;
reg fsmout;
parameter SEE0 = 1b0, SEE1 = 1b1;
reg state, next_state;
// state memory block
always @(posedge clk)
if (rst)
state <= SEE0;
else
state <= next_state;
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// next state logic block
always @(fsmin)
case (fsmin)
1b1: next_state = SEE1;
1b0: next_state = SEE0;
default: next_state =
state;
endcase
// output logic block
always @(state)
case (state)
SEE0: fsmout = 1b0;
SEE1: fsmout = 1b1;
default: fsmout = 1bx;
endcase
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EE 577B Course Resources
Some
other Verilog resources
Quick
reference and examples from previous
semesters (courtesy of Nestor Tzartzanis)
http://www-scf.usc.edu/~ee577/cad_tools.html
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Course Plan for next few weeks
Lectures
More Verilog
concepts
Floating-point
Project
arithmetic tutorial
description
Homework
2 due Feb 6
Homework 3 (more Verilog concepts) will be
assigned Feb 6
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Quick Tools Demo
TA Aditya
Deshpande will provide a quick
tools demo for the remainder of todays lecture
time
58
