TMS320C6x

Addendum to the TMS320 DSP

Development Support Reference Guide

Addendum

1997

Digital Signal Processing Solutions

Printed in U.S.A., August 1997

SPRU226

TMS320C6x
Addendum
TMS320C6x Addendum to the TMS320 DSP
Development Support Reference Guide

Literature Number: SPRU226

August 1997

Printed on Recycled Paper

IMPORTANT NOTICE
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Copyright 1997, Texas Instruments Incorporated

Preface

Read This First

About This Manual

This addendum to the TMS320 DSP Development Support Reference Guide
(DSRG) adds information on development support available from Texas
Instruments for the TMS320C6x digital signal processors. Device names are
abbreviated in this book; for example, TMS320C6x is referred to as C6x.
The chapters in this addendum do not map directly to the TMS320 DSP
Development Support Reference Guide because the C6x chapter (Chapter 1 of
this addendum) should be inserted between chapters 10 and 11 of the DSRG.
The remaining chapters of this addendum provide supplemental information for
other chapters of the DSRG.

How to Use This Manual

This document contains the following chapters:
Chapter 1, TMS320C6x Devices, describes the main features of the
TMS320C6x devices. This chapter should be considered an insert between
Chapters 10 and 11 of the TMS320 DSP Development Support Reference
Guide.
Chapter 2, Tools, describes the code-generation, evaluation, and debug tools
for the TMS320C6x devices. This type of information appears in Chapters 15
and 16 of the TMS320 DSP Development Support Reference Guide.
Chapter 3, Technical Support and Documentation, describes the workshops,
web site, documentation, and third-party support available for the TMS320C6x
devices. This type of information appears in Chapters 17 and 18 of the
TMS320 DSP Development Support Reference Guide.

Related Documentation From Texas Instruments

The following books describe the TMS320C6x devices and related support
tools. To obtain a copy of any of these TI documents, call the Texas
iii

Related Documentation From Texas Instruments

Instruments Literature Response Center at (800) 4778924. When ordering,

please identify the book by its title and literature number.

TMS320C6x Assembly Language Tools Users Guide (literature number

SPRU186) describes the assembly language tools (assembler, linker,
and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging
directives for the C6x generation of devices.
TMS320C62xx CPU and Instruction Set Reference Guide (literature
number SPRU189) describes the C62xx CPU architecture, instruction
set, pipeline, and interrupts for the TMS320C62xx digital signal
processors.
TMS320C6x C Source Debugger Users Guide (literature number
SPRU188) tells you how to invoke the C6x simulator and emulator
versions of the C source debugger interface. This book discusses
various aspects of the debugger, including command entry, code
execution, data management, breakpoints, profiling, and analysis.
TMS320C6x Optimizing C Compiler Users Guide (literature number
SPRU187) describes the C6x C compiler. This C compiler accepts ANSI
standard C source code and produces assembly language source code
for the C6x generation of devices. This book also describes the
assembly optimizer, which helps you optimize your assembly code.
TMS320C62xx Peripherals Reference Guide (literature number SPRU190)
describes common peripherals available on the TMS320C62xx digital
signal processors. This book includes information on the internal data
and program memories, the external memory interface (EMIF), the host
port, serial ports, direct memory access (DMA), clocking and
phase-locked loop (PLL), and the power-down modes.
TMS320C62xx Programmers Guide (literature number SPRU198)
describes ways to optimize C and assembly code and includes
application program examples.
TMS320C62xx Technical Brief (literature number SPRU197) gives an
introduction to the C62xx digital signal processor, development tools,
and third-party support.
TMS320C6201 Digital Signal Processor Data Sheet (literature number
SPRS051) describes the features of the TMS320C6xx and provides
pinouts, electrical specifications, and timings for the device.

iv

Trademarks

Trademarks
Classico, MicroLite, and Virtuoso Nano are trademarks of Eonic Systems, Inc.
Code Composer and Code Maestro are trademarks of Go DSP Corporation.
EVP is a trademark of D2 Technologies.
InvisiLink is a trademark of ViaDSP, Inc.
PC is a trademark of International Business Machines Corporation.
Solaris, SunOS, and Sun-3 are trademarks of Sun Microsystems, Inc.
320 Hotline On-line, cDSP, TI, VelociTI, XDS510, and XDS510WS are
trademarks of Texas Instruments Incorporated.
Windows, Windows 95, and Windows NT are registered trademarks of
Microsoft Corporation.

Read This First

If You Need Assistance

If You Need Assistance . . .

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Mail: Texas Instruments Incorporated
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Note:

vi

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When calling a Literature Response Center to order documentation, please specify the literature number of the
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Contents

Contents
1

TMS320C6x Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Describes the devices and lists the key features of the TMS320C6x devices.
1.1
1.2
1.3

1.4

1.5

TMS320C6x Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Describes the tools that support development and evaluation of code for the C6x.
2.1

2.2

Code-Generation Tools (Chapter 15 Addendum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 C Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Assembly Optimizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Evaluation Tools (Chapter 16 Addendum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Debugger Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2 Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-2
2-2
2-2
2-2
2-3
2-4
2-5
2-5

Technical and Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

Describes the web site, documentation available, and third-party support.
3.1
3.2

TMS320C6x Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.3.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.3.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.1 Data-Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.4.2 Program-Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5.1 External Memory Interface (EMIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5.2 Direct-Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.5.3 Host-Port Interface (HPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.5.4 Power-Down Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.5.5 Multichannel Serial Port (MCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.5.6 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

Web Site and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
vii

Tables

Figures
11.

CPU Core With Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

Tables
31
32

viii

Contacts for Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Third-Party Support Companies and Product Area Supported . . . . . . . . . . . . . . . . . . . . . . . 3-4

Chapter 1

TMS320C6x Devices
The TMS320C6x devices are the first devices to feature VelociTI, an advanced very long instruction word (VLIW) architecture developed by Texas
Instruments, which allows performance of up to 1600 million instructions per
second (MIPS). The first device in the series is the TMS320C6201, a fixedpoint digital signal processor (DSP).

Topic

Page

1.1

TMS320C6x Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2

1.2

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.3

Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.4

Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

1.5

Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8

1-1

TMS320C6x Introduction

1.1 TMS320C6x Introduction

With a complete set of development tools, the C6x devices offer cost-effective
solutions to high-performance DSP programming challenges. The C6x development tools include a new C compiler, an assembly optimizer, and a Windows-based debugger. VelociTI combines an advanced VLIW architecture
with a high degree of parallelism to produce a device that enables applications
such as:

Unlimited Internet bandwidth

Universal wireless communications
New telephony features
Remote medical diagnostics
Automated cruise control
Personal home base station
Personalized home security

The C6x devices also can be used for improved performance on existing applications, such as:

1-2

Wireless base stations

Pooled modems and remote access servers
Next-generation xDSL modems and cable modems
Multichannel telephony platforms, including central office switches, PBXs,
and voice-messaging systems
Multimedia systems
Digital imaging

Key Features

1.2 Key Features

The TMS320C6201 is the first fixed-point processor in the C6x generation.
Following are key features of the TMS320C6201:

VelociTI advanced very long instruction word (VLIW) architecture

Load/store architecture
Instruction packing for reduced code size
100% conditional instructions for faster execution
Intuitive, reduced instruction set computing (RISC)-like instruction set

J
J
J
J

CPU

J
J
J
J
J
J
J
J
J
J
J

Eight independent functional units (including two 16-bit multipliers

with 32-bit results and six arithmetic logic units [ALUs] with 32-/40-bit
results)
32 32-bit registers
1600 million instructions per second (MIPS)
Five-ns cycle time
Up to eight 32-bit instructions per cycle
Byte-addressable 8-, 16-, 32-bit data
32-bit address range
Dual-endian support
Saturation
Normalization
Bit-field instructions (extract, clear, left most bit detection)

Memory/peripherals

J
J
J
J
J
J
J

Synchronous external memory interface (EMIF)

Two multichannel serial ports (MCSPs)
Four-channel direct memory access (DMA)
Two timers
X4 phase-locked-loop (PLL) option
Host-port interface (HPI)
1M-bit on-chip memory (divided into 2K by 256 bits of program
memory and 64K bytes of data memory)

352-pin ball-grid array package

TMS320C6x Devices

1-3

Central Processing Unit (CPU)

1.3 Central Processing Unit (CPU)

The C6x central processing unit (CPU) is the central building block of all the
TMS320C62xx devices. The CPU contains:

Program fetch unit

Instruction dispatch unit
Instruction decode unit
32 general-purpose, 32-bit registers
Two data paths, each with four functional units, including one multiplier
and three arithmetic logic units (ALUs) on each data path
Control registers
Control logic
Test, emulation, and interrupt logic

The CPU has two data paths where processing occurs. Each data path has
four functional units and a register file containing 16 32-bit registers. The
functional units execute logic, shifting, multiply, and data address operations.
All instructions operate on the registers. The two sets of data-addressing units
are exclusively responsible for all data transfers between the register files and
the memory.

1-4

Central Processing Unit (CPU)

Figure 11 shows the CPU core and peripherals for a TMS320C6201 device.

Figure 11. CPU Core With Peripherals

23

32

EMIF

Program RAM/cache
32-bit address
256-bit data
512K-bit RAM

Data RAM
32-bit address
8-, 16-, 32-bit data
512K-bit RAM

JTAG test/
emulation
control

Program/data buses

Multichannel
(T1/E1)
serial port

DMA
C62xx CPU Core

Instruction dispatch

Ch 0
Control
registers

Instruction decode
Data path 1

Data path 2

A register file

B register file

Ch 2
Control
logic
Test
Emulation

.L1 .S1 .M1 .D1

.D2 .M2 .S2 .L2

Ch 1
Peripheral bus

Program fetch

Interrupts

Ch 3
Auxiliary
channel

Multichannel
(T1/E1)
serial port

Timer

16 Data

Timer

Host
port
Power management

PLL clock
generator

1.3.1

Addressing Modes
The addressing mode options on the C62xx are either linear or circular, as
specified by the addressing-mode register (AMR).
For more information on addressing modes, see the TMS320C62xx CPU and
Instruction Set Reference Guide.
TMS320C6x Devices

1-5

Central Processing Unit (CPU)

1.3.2

Interrupts
The CPU has 14 interrupts. These are the reset interrupt, the nonmaskable
interrupt (NMI), and interrupts 415. These interrupts correspond to the
RESET, NMI, and INT4INT15 signals on the CPU boundary. In some C62xx
devices, these signals may be tied directly to pins on the device, connected
to on-chip peripherals, or may be disabled permanently by being tied inactive
on chip. Generally, RESET and NMI are connected directly to pins on the
device.
For more information on interrupts, see the TMS320C62xx CPU and Instruction Set Reference Guide (literature number SPRU189).

1-6

Internal Memory

1.4 Internal Memory

The internal memory consists of 512K bits of on-chip program / cache memory
and 512K bits of on-chip data memory. The program memory, configurable as
cache or program, is organized in 2K of 256-bit fetch packets. The C6201
fetches all instructions one fetch packet at a time. The packets are processed
at the maximum rate of one packet (eight 32-bit instructions) per CPU cycle
or at a minimum of one instruction per cycle. The internal data memory is byte
addressable by the CPU (for reads as well as writes) and supports bytes, halfwords, and full word transfers.

1.4.1

Data-Memory System
The TMS320C62xx data-memory system includes SRAM and a memory controller. The CPU can access data memory in 8-bit byte, 16-bit halfword, and
32-bit word-lengths. The data memory system supports two memory accesses per cycle. These accesses can be any combination of loads and stores
from the two data buses of the CPU. Similarly, a simultaneous internal and external memory access is supported by the data memory system. The
TMS320C62xx data memory system also supports direct-memory access
(DMA) and external host accesses. For more information on the data-memory
system, see the TMS320C62xx Peripherals Reference Guide.

1.4.2

Program-Memory System
The TMS320C62xx program-memory system includes on-chip SRAM and a
memory/cache controller. The program memory can operate as either an internal program memory or as a directly mapped program cache. There are four
modes under which the program memory system operates:

Program-memory mode
Cache-enable mode
Cache-freeze mode
Cache-bypass mode

The DMA can write data into an addressed space of program memory. The
DMA cannot read from the internal program memory in program memory
mode.
For details on cache modes, see the TMS320C62xx Peripherals Reference
Guide.

TMS320C6x Devices

1-7

Peripherals

1.5 Peripherals
In addition to on-chip memory, the TMS320C6201 contains the following
peripherals:

1.5.1

External memory interface (EMIF)

Direct-memory access (DMA) controller
Host-port interface (HPI)
Power-down logic
Two multichannel serial ports (MCSPs)
Two 32-bit timers

External Memory Interface (EMIF)

All external data accesses by the CPU or DMA pass through the external
memory interface (EMIF). The EMIF is the interface between the CPU and external memory such as synchronous dynamic random-access memory
(SDRAM), synchronous-burst static RAM (SBSRAM), and asynchronous
memory. The EMIF also provides 8-bit and 16-bit wide memory read capability
to support low-cost boot ROM memories (flash, EEPROM, EPROM, and
PROM).
The interface is programmable to adapt to a variety of setup, hold, and strobe
widths for asynchronous devices. SBSRAM supports zero-wait-state external
access once bursts have begun.
In all these types of access, the EMIF supports 8-bit, 16-bit, and 32-bit addressability for writes. All reads are performed as 32-bit transfers.
For more information on memory, see the TMS320C62xx CPU and Instruction
Set Reference Guide (literature number SPRU189). For more information on
the EMIF, see the TMS320C62xx Peripherals Reference Guide.

1.5.2

Direct-Memory Access (DMA)

The on-chip DMA offers four independent, programmable channels that can
be configured to transfer information from one location in the memory map to
another without interfering with the operation of the CPU. This allows interfacing to slow external memories and peripherals without reducing the throughput
to the CPU. The DMA controller contains its own address generators, source
and destination registers, and transfer counter. The DMA has its own bus for
addresses and data to keep the data transfers between memory and peripherals from conflicting with the CPU.

1-8

Peripherals

A DMA operation consists of a 32-bit word transfer to or from any of the three
C62xx modules:

Internal data memory

Internal program memory that is not configured as cache as a destination
of a transfer
EMIF

One of the DMA channels can be used by the processor during the boot load
startup procedure to initialize the internal program memory after reset. The
DMA channels can be used to write to internal program memory.
The boot loader uses the DMA to boot load code from off-chip memory to the
internal program memory area. An external pin (sampled at reset) selects
whether this boot load is performed. The serial port can also be used for booting.
The DMA controller can access all internal program memory, all internal data
memory, and all devices mapped to the EMIF. However, the DMA cannot use
program memory as the source of a transfer and it cannot access memories
configured as cache or memory-mapped on-chip peripheral registers.
See the data sheet for the specific device to find the memory mapping of DMA
control registers. These registers are 2-bits wide and must be accessed
through 32-bit accesses from the CPU. For more information on the DMA operations, see the TMS20C62xx Peripheral Reference Guide.

1.5.3

Host-Port Interface (HPI)

The HPI is a parallel port that can access the CPU memory space directly as
an asynchronous interface. A host (external) processor can read from and
write to the internal data memory through the 16-bit-wide access of the HPI.
The HPI can boot load the CPU as well as access the full range of the C6201
memory. Also, the HPI offers improved performance and can operate without
impacting CPU performance.
For more information on the HPI, see the TMS320C62xx Peripheral Reference Guide.

TMS320C6x Devices

1-9

Peripherals

1.5.4

Power-Down Logic
The C62xx supports three power-down modes (Idle1, 2, and 3) that can reduce system power requirements significantly. Idle1 halts the CPU except for
the interrupt logic. Idle2 halts the CPU and the peripherals (except for the interrupt logic). Idle3 halts the phase-locked loop (PLL), stopping the clock tree
from switching, which effectively halts the entire chip. Idle 3 requires a reset
to wake up the device, while the other two modes can be restored using an
interrupt or reset. For more details on the power-down logic, see the
TMS320C62xx Peripherals Reference Guide.

1.5.5

Multichannel Serial Port (MCSP)

The C6201 includes two MCSPs, supporting multivendor interface protocol
(MVIP) and timers to allow easy algorithm integration. The MCSP is based on
the standard TMS320C2x/C5x/C54x serial-port interface. In addition, it has
the ability to buffer serial samples in memory automatically with the aid of the
DMA. It also has multichannel capability compatible with the T1, E1, and MVIP
standards.
The MCSP provides:
Full-duplex communication
Double-buffered data registers
Direct interface to other devices
Clock generation or an internal programmable frequency shift clock
Multichannel transmit and receive

1.5.6

Timers
The device has two 32-bit general purpose timers that you can use to:
Time events
Count events
Generate pulses
Interrupt the CPU
Send synchronization events to the DMA

The timer has two signaling modes and can be clocked by an internal or an
external source. The timer has an I/O pin that functions as an input clock, as
an output clock, or as a general-purpose I/O pin.

1-10

Chapter 2

TMS320C6x Tools
The TMS320C6x design environment reflects the nature of the advanced very
long instruction word (VLIW) architecture. The environment includes
code-generation tools, evaluation tools, on-line help, and technical
documentation. This chapter provides addenda to Chapters 15 and 16 of the
DSRG.

Topic

Page

2.1

Code-Generation Tools (Chapter 15 Addendum) . . . . . . . . . . . . . . . . . 2-2

2.2

Evaluation Tools (Chapter 16 Addendum) . . . . . . . . . . . . . . . . . . . . . . . 2-4

2-1

Code-Generation Tools (Chapter 15 Addendum)

2.1 Code-Generation Tools (Chapter 15 Addendum)

Code-generation tools for both the PC and Sun workstations are as follows:

C compiler
Assembly optimizer
Assembler
Linker

The tools take C or assembly source code and implement many different optimizations, including software pipelining, to find and exploit the unique instruction-level parallelism of the C6x. After each step in the process, the C6x tools
allow you to evaluate the results and take appropriate steps to achieve the
most parallel code.

2.1.1

C Compiler
The C6x C compiler accepts ANSI C source code and produces C6x
assembly language source code, performing a variety of optimizations to
improve the efficiency of the compiled code. The compiler incorporates four
levels of generic and target-specific optimizations. The level of optimizations
is selectable. The optimizations specific to the C6x DSP include:

2.1.2

Software pipelining
If conversion/predicated execution
Memory address cloning
Memory address dependence elimination

Assembly Optimizer
Once the dynamic profiler identifies critical code segments that can benefit
most from being generated in assembly language, the assembly optimizer
schedules the instructions, taking into account the architectural parallelism of
the C6x DSP. The assembly optimizer allows you to write assembly code without being concerned with pipeline structure of the device or with assigning registers. The tool honors C6x latency requirements, maximizes parallel code,
and allocates registers for the unlimited number of named, virtual registers that
are available to the user. The assembly optimizer takes in linear assembly
instructions and creates an intermediate file that is input into the code generator. The code generator then produces optimized and/or software pipelined assembly code.

2.1.3

Assembler
The assembler translates assembly language source code files into machine
language common object file format (COFF) object files. The assembly files
can contain C6x assembly language instructions, assembler directives, and
macro directives.

2-2

Code-Generation Tools (Chapter 15 Addendum)

2.1.4

Linker
The linker allows you to combine COFF object files into a single executable
COFF output file. The linker allocates relocatable sections and symbols and
resolves external references between input files. It also accepts previously
linked files and library members as input.

TMS320C6x Tools

2-3

Evaluation Tools (Chapter 16 Addendum)

2.2 Evaluation Tools (Chapter 16 Addendum)

The evaluation tools include the following:

Windows-based debugger interface

Simulator
Hardware emulation board

The C6x development environment provides a new intuitive Windows 95

based graphical user interface (GUI) for debugging. The debugger interface
features windows for source, assembly, call stack, memory, registers, and
watch expressions as well as menus and tool bars. The debugger offers oneclick breakpoint setting and dialogs for editing breakpoints. The debugger also
incorporates the dynamic profiler to help users find bottlenecks and improve
code efficiency.
The profiler integrated into the C6x debugger creates cycle histograms that
are continuously updated as the code runs. It can show graphically which functions, ranges and lines in an application are performance bottlenecks. The profiler can show:

The percentage of total execution time spent in any function

The number of times a function is called
Total cycles in the application, function, or line

A timing display can be built into the application by inserting a few function calls
in the code. The resulting simple cycle counts, obtained without using the profiler or the debugger, can be printed automatically to allow you to track the
changes in execution speed of an algorithm over time. This output, while less
sophisticated, is continuously available with no further action.
TI provides scan-based emulation systems that support hardware and software debugging of target systems via a JTAG emulation cable. Scan-based
emulation is a unique, nonintrusive approach to system emulation, integration,
and debugging.
Initially, TI offers a stand-alone C6201 test and emulation board (TEB) that interfaces with the host platform through the XDS510 and XDS 510WS emulators through the IEEE Standard 1149.1 (JTAG) compliant port. The board
features a prototyping area for adding user-defined peripherals.

2-4

Evaluation Tools (Chapter 16 Addendum)

2.2.1

Debugger Interface Features

The debugger allows you to run and halt the processor; step through instructions; view and modify registers, memory values and C variables; view source
and profile code by line, by range, or by C function. Debugger features include:

2.2.2

Windows 95 interface
Menu options for entering and leaving the profiler without exiting the debugger
C input/output displays in the command window
Options for starting and halting the C6x, including single-step, step-over,
return from called function, and run and halt commands
Support for debugging in C, assembly language, or both
Identification of time-consuming sections of the program through the profiler
Memory window that displays the values of a block of memory in any format specified
Watch window that displays the values of variables in the native C format
C source window that displays the C code and highlights the current line

Simulator
The C6x simulator is a software program that uses the TMS320 debugger
graphical user interface to simulate the operation of the C6x processor on the
host processor rather than on an actual target system. It uses object code produced by the macro assembler/linker or ANSI C compiler with the debugger
interface. The simulator provides XDS510 software debug capability for the
C6x with external memory without using the DSP hardware.
Each of the simulator software programs simulates the C6x operation and allows monitoring of the state of the processor. Key features of the C6x simulator include:

Execution of user-oriented DSP programs on a host computer

Modification and inspection of registers
Data and program memory modification and display
Simulation of peripherals, caches, and pipelined timings
TMS320C6x Tools

2-5

Evaluation Tools (Chapter 16 Addendum)

Extraction of instruction-cycle timing for device performance analysis

Programmable breakpoints on instruction acquisition and error conditions
Single stepping of instructions
Additional features to the debugger interface

J
J

2-6

Memory-mapped I/O can be connected to a host file to simulate I/O

such as synchronous serial port I/O
Simulation of external interrupts

Chapter 3

Technical and Third-Party Support

TI support includes a web site, documentation, workshops, seminars, and a
hot-line. Third-party support, the products developed by other companies to
support TI devices, is also available.

Topic

Page

3.1

Web Site and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

3.2

Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3-1

Web Site and Documentation

3.1 Web Site and Documentation

Visit the web site at [Link]/sc/c6x for information, an interactive
multimedia technical overview (MeTO), documentation, and a schedule of
C6x design workshops. The MeTO describes features of the devices visually
with graphics in a point-and-click display for ease of navigation. The web site
offers a complete training schedule of design workshops and seminars.
Applications assistance and answers to frequently asked questions (FAQ) are
available.
Some documentation is available directly from the web site in down-loadable
files for printing. There is a complete list of documentation that can be ordered
in the preface of this book under Related Documentation from Texas Instruments.

3-2

Third-Party Support

3.2 Third-Party Support

TI third-party support continues with the C62xx devices. Table 31 lists the
third-party support contacts with telephone numbers and electronic mail addresses. Table 32 lists some of the companies supporting the C62xx devices
and the product areas.

Table 31. Contacts for Third-Party Support

Third-Party Contact

Phone Number

E-mail Address

Ariel Corporation

6098602900

ariel@[Link]

Cheops GmbH & Co KG

+49 8861 2369 0

100541.3370@[Link]

D2 Technologies, Inc.

8055643424

sales@[Link]

DSP Research, Inc.

4087731042

info@[Link]

DSP Software Engineering, Inc.

6172753733

info@[Link]

Eonic Systems, Inc.

3015725000

info@[Link]

GO DSP Corporation

4165996868

gdasilva@[Link]

HotHaus Technologies, Inc.

6042784300

info@[Link]

Innovative Integration, Inc.

8188656150

techsprt@[Link]

Loughborough Sound Images

+44 0 1509 634444

Pentek, Inc

2018185900

info@[Link]

Signals & Software Ltd. (SASL)

+44 181 426 9533

davem@[Link]

Sonitech, Inc.

6172356824

info@[Link]
[Link]

Spectron Microsystems

8059685100

info@[Link]
[Link]
presrel/[Link]

Spectrum Signal Processing

8006638986 or
6044215422

sales@[Link]
[Link]

ViaDSP, Inc.

5083690048

dpenny@[Link]

White Mountain DSP, Inc.

6038832430

info@[Link]

Technical and Third-Party Support

3-3

Third-Party Support

Table 32. Third-Party Support Companies and Product Area Supported

Company

Product Area

Ariel Corporation

High-performance VME64 platform and computer telephony products

Cheops GmbH & Co KG

Industrial and medical imaging and high speed/high resolution videoconferencing

D2 Technologies, Inc.

Embedded Voice Processing (EVP) computer telephony software

DSP Research, Inc.

TIGER development boards and OEM systems

DSP Software Engineering,

Inc.

Multi-channel V.34bis soft-modem and telecom software

Eonic Systems, Inc.

Real-time operating systems Virtuoso Nano, Classico, and MicroLite

Go DSP Corporation

Code Composer support and next generation development tool, Code

Maestro

HotHaus Technologies, Inc.

HausWare DSP software architecture for embedded telecommunications applications

Innovative Integration

PCI6201 DSP coprocessor for telecom, communications and data acquisition applications

Loughborough Sound
Images

PCI/C6200 signal processing platform and PCI/C6220 telecommunications/

high density DSP telephony platform

Pentek, Inc.

Scaleable multi-processor board for the VMEbus model 9134

Signals & Software Ltd.

(SASL)

Very high density ISP modem solution

ViaDSP, Inc.

InvisiLink line of software and firmware for high density computer telephony
boards

Sonitech, Inc.

SPIRIT-6000 series of high-performance board-level platforms and software development tools

Spectron Microsystems,
Inc.

SPOX real-time operating systems

Spectrum Signal Processing, Inc.

Hardware, interface silicon, and CTI software for DSPs

White Mountain DSP, Inc.

Emulation and multiplatform debug support Mountain510, Mountain510/WS

and Mountain-510/LT PCMCIA Card

3-4

Appendix
AppendixAA

Glossary
A
address: The number representing a particular memory or peripheral storage location.
ALU: Arithmetic logic unit. The high-speed CPU circuit that performs arithmetic and logic operations. Numbers are transferred from registers into
the ALU for calculation, and the results are sent back to a register.
ASIC: Application-specific integrated circuit. A custom chip designed for a
specific application. It is designed by integrating standard cells from a
library.
assembler: A software program that creates a machine-language program
from a source file that contains assembly language instructions,
directives, and macro definitions. The assembler substitutes absolute
operation codes for symbolic operation codes, and absolute or
relocatable addresses for symbolic addresses.
assembly optimizer: A software program that optimizes linear assembly
code, which is assembly code that has not been register-allocated or
scheduled. The assembly optimizer is automatically invoked with the
shell program when one of the input files has an .sa extension.

B
boot loader: A built-in segment of code that transfers code from an external
source to program memory at power up.

C
clock cycles: A repeated set of events based on the input from the external
clock.
code: A set of instructions written to perform a task; a computer program or
part of a program.
CPU: Central processing unit. The computing part that coordinates the functions of a processor.
A-1

Glossary

D
data memory: Memory accessed through the C6x RAM interface.
DMA: Direct memory access. The mechanism by which an external device
or peripheral can access the processor memory to transfer data without
the processor having to execute data movement instructions.
DRAM: Dynamic random access memory. The most common type of computer memory, usually using one transistor and a capacitor to represent
a bit. The capacitors must be energized hundreds of times per second
to maintain the charges and lose their content when the power is removed.

E
EMIF: External memory interface. The boundary between the CPU and external memory through which information is conveyed.
execute packet: A set of instructions that execute in parallel.
external interrupt: A hardware reset triggered by a pin.

F
fetch packet: A packet containing up to eight instructions held in memory
for execution by the CPU.
functional unit: An operational portion of the CPU used to compute a result.

G
global interrupt enable (GIE): A bit in the control status register (CSR) that
is used to enable or disable maskable interrupts.

H
hardware interrupt: A suspension of the processor triggered through physical connections with on-chip peripherals or external devices.
HPI: Host port interface. A 16-bit wide access port through which a host (external) processor can read from and write to internal data memory.
A-2

Glossary

I
interrupt: A condition caused either by an event external to the CPU or by
a previously executed instruction. It forces the current program to be suspended and causes the processor to execute an interrupt service routine
corresponding to the interrupt.

L
latency: The delay between when a condition occurs and when the device
reacts to the condition. Also, in a pipeline, the necessary delay between
the execution of two instructions to ensure that the values used by the
second instruction are correct.
LSB: Least significant bit. The lowest order bit in a word.

M
maskable interrupt: A hardware interrupt that can be enabled or disabled
through software.
memory interleaving: A category of techniques for increasing memory
speed.
MIPS: Million instructions per second. A unit of execution speed of a computer.
MSB: Most significant bit. The highest-order bit in a word.

N
NMI: Nonmaskable interrupt. An interrupt that can be neither masked nor
disabled.

O
overflow: A condition in which the result of an arithmetic operation exceeds
the capacity of the register used to hold that result.
Glossary

A-3

Glossary

P
parallelism: The ability to extract multiple instructions from an algorithm that
can be executed at the same time.
pipeline:

A method of executing instructions in an assembly-line fashion.

pipeline processing: A category of techniques that provide simultaneous,

or parallel, processing within the computer. It refers to overlapping
operations by moving data or instructions into a conceptual pipe with all
stages of the pipe processing simultaneously.
PLL: Phase-locked loop. A unit within a system that uses phase to lock on
to a signal to ensure synchronous clocking of digital signals.

R
RAM: Random-access memory. The primary workspace of a computer or
processor. Random means that the contents of each byte can be directly
accessed without regard to the bytes before or after it. RAM chips require
power to maintain their content.
register: A group of bits used for temporarily holding data or for controlling
or specifying the status of a device.
reset: A means of bringing the CPU to a known state by setting the registers
and control bits to predetermined values and signaling execution to start
at a specified address.
RISC: Reduced instruction set computing. A computer architecture that
minimizes chip complexity by using simple instructions.

S
SBSRAM: Synchronous burst static random-access memory.
SDRAM: Synchronous dynamic random-access memory. A high-speed
memory that can transfer bursts of noncontiguous data at 100M bytes
per second.
shifter: A hardware unit that moves bits in a word to the left or to the right
in relation to the current position.
A-4

Glossary

V
VelociTI: Architecture developed by TI that features very long instruction
words
VLIW: Very long instruction word. Architecture using words between the
sizes of 256 bits and 1024 bits.

Glossary

A-5

A-6

Index

Index

CPU
data access 1-8
power down 1-10

A
addressing-mode register

1-5

AMR. See addressing-mode register

applications, C6x

1-2

architecture
CPU 1-4
VelociTI 1-2

C
C6201 1-2
C6201 block diagram
C6201 CPU

1-5

1-3

C6201 CPU core with peripherals

C6201 key features
C6201 peripherals

1-3

C6x addressing modes

1-5

C6x circular addressing

1-5

C6x debugger

1-2

C6x key features

1-3

C6x simulator

EMIF. See external-memory interface

evaluation tools 2-4
external memory 1-8
external-memory interface 1-8

2-5
1-7

central processing unit

architecture 1-4 to 1-7
core with peripherals 1-5
clock generation
code, definition

functional units

1-10

1-4

A-1

code-generation tools

data access
CPU 1-8
DMA controller 1-8
data memory 1-7
data paths 1-4
debugger interface 2-5
development support 2-2
development tools 2-2
direct memory access 1-3, 1-7, 1-8, 1-9
DMA
See also direct memory access
controller 1-9
data access 1-8

2-5

C6x introduction

cache modes

1-5

1-3

2-2

compatibility, MVIP standards

1-10

graphical user interface 2-4

GUI. See graphical user interface

Index-1

Index

microcomputer mode, definition A-3

million instructions per second (MIPS) 1-2
multichannel serial port 1-3, 1-8, 1-10
multivendor interface protocol 1-10

H
halt CPU

1-10

host port interface

1-3

host-port interface

1-8, 1-9

HPI. See host-port interface

nonmaskable interrupt

I
idle modes

1-10

IEEE Standard 1149.1 port

J
JTAG. See IEEE Standard 1149.1

K
1-3

M
MCSP. See multichannel serial port
memory
cache controller 1-7
cache modes 1-7
data 1-7
EEPROM 1-8
EMIF 1-8
external 1-8
flash 1-8
internal 1-7
program 1-7
program-memory modes
PROM 1-8
SDRAM 1-8
Index-2

1-10

1-7

interrupts 1-6
nonmaskable 1-6

key features

optimizations 2-2

2-4

interface, multichannel serial port

internal data memory

1-6

performance 1-3
peripherals
direct memory access controller
external memory interface 1-8
host-port interface 1-8
idle modes 1-10
MCSP 1-10
multichannel serial port 1-8
power-down logic 1-8
timers 1-8, 1-10
phase-locked loop 1-3
pipeline, definition A-4
power-down logic 1-10
profiler 2-4
program memory 1-7

R
register, definition A-4
reset 1-6
definition A-4

S
1-7

simulator 2-5
software debug 2-5
SRAM 1-7
synchronous burst static RAM

1-8

1-8

Index

T
third-party support 3-3
contacts 3-3
product area 3-4
timers 1-10
tools
assembly optimizer 2-2
C compiler 2-2
debugger 2-4
evaluation 2-4
hardware emulation board
linker 2-2
profiler 2-4
simulator 2-4
transfer information 1-9

V
VelociTI 1-1, 1-2
very long instruction word (VLIW)

1-1, 1-2, 1-3

X
XDS510

2-5

2-4

Index-3

Index-4