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Yosemite RF Digital Clock Sync Overview

This document shows a block diagram of clock generation and distribution for an RF system. Key clock signals like CLK_AUX_ADC_OUT and CLK_ADC_OUT_1 are generated, isolated, and distributed to different modules. Gating cells and clock enable signals control the distribution of clocks to help with power management. The source of all digital signal processing clocks is a central CLKGEN block which generates and distributes protected and isolated clock signals.

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stephmo
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64 views1 page

Yosemite RF Digital Clock Sync Overview

This document shows a block diagram of clock generation and distribution for an RF system. Key clock signals like CLK_AUX_ADC_OUT and CLK_ADC_OUT_1 are generated, isolated, and distributed to different modules. Gating cells and clock enable signals control the distribution of clocks to help with power management. The source of all digital signal processing clocks is a central CLKGEN block which generates and distributes protected and isolated clock signals.

Uploaded by

stephmo
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EN_ADC_AUX

CLK_AUX_ADC_OUT_protected

CLK_AUX_ADC_OUT

CLK_AUX_ADC_OUT_pre_iso

0
1

Power
calculation

CLK_AUX_ADC_OUT_int

ScanMode
EN_ADC_I_RFE_1

CLK_ADC_OUT_1_pre_iso
EN_ADC_I_RFE_2

CLK_ADC_OUT_2_pre_iso
CLK_DAC_OUT_pre_iso

CLK_ADC_OUT_1

CLK_ADC_OUT_1_protected

CLK_ADC_OUT_2

CLK_ADC_OUT_2_protected

CLK_DAC_OUT

CLK_DAC_OUT_protected

CLK_ADC_OUT_1_int

0
1

EN_TDAC

Clock
Sync

CLK_ADC_OUT_2_int
CLK_DAC_OUT_int

ScanMode
Source of all
DSP clocks
CLKGEN_OUT_protected

CLKGEN_OUT

CLKGEN_OUT_pre_iso

CLKENABLE5
clk4x

VDD_DIG_LVL_1p2V

buffer

GND_DIG_LVL_1p2V

0
1

clk2xs

/4

0
1

clks

clk4x

ScanMode

sync

P_txf_clk
clku
clk2xu

CLKENABLE
clk4x

clk4x_system

sync

clk4x

CG

clk4x_system

clk4x

CG

clk4x_gated

clk2xs

CG

clk2xu

clk2xs

CG

clk2x_gated

clks

CG

clku

clks

CG

clk_gated

Isolation

LDO

0
1

clk4x_system
/2

SYSTEM
CLKENABLE2
clk4x

Subf
counter
Shadow
registers

MAIN
CLKENABLE3

sync

clk4x

sync

clk4x

CG

clk4x_gated2

clk4x

CG

clk4x_gated3

clk2xs

CG

clk2x_gatedr

clk2xs

CG

clk2x_gatedt

clks

CG

clk_gatedr

clks

CG

clk_gatedt

DIVERSITY

TX

CLKENABLE4

GPS

EN_ADC_GPS
GPS_ADC_CLK_OUT_pre_iso

GPS_ADC_CLK_OUT

CG
GPS_ADC_CLK_OUT_protected

Yosemite RF
analog

gclk4x_gated

0
1

gclk4x_gatedg

ScanMode

Yosemite RF digital

SPI
REG
Shadow

core_SCLK_Slave

P_SCLK_Slave

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