Logic Design :VerilogFSM in class design example s 1 S.
Yoder ND, 2010
CSE 20221: Logic Design
Verilog FSM Design Example
Automatic Garage Door Opener
&
Timers
Logic Design :VerilogFSM in class design example s 2 S. Yoder ND, 2010
Inputs / Outputs
Define the module interface
NAME TYPE FUNCTION
activate (A) input starts the door to go up or down or stops the motion
Up_limit (UPL) input indicates maximum upward travel
Dn_limit (DNL) input indicates maximum downward travel
Motor_up (MU) output Causes motor to run in direction to raise the door
Motor_dn (MD) output Causes motor to run in direction to lower door
Logic Design :VerilogFSM in class design example s 3 S. Yoder ND, 2010
Inputs / Outputs
NAME TYPE FUNCTION
activate (A) input starts the door to go up or down or stops the motion
Up_limit (UPL) input indicates maximum upward travel
Dn_limit (DNL) input indicates maximum downward travel
Motor_up (MU) output Causes motor to run in direction to raise the door
Motor_dn (MD) output Causes motor to run in direction to lower door
reset input Force the controller to enter into the initial state
Logic Design :VerilogFSM in class design example s 4 S. Yoder ND, 2010
State Diagram
initial
up
next
dn
next
moving
up
moving
down
A
UPL
A
DNL
A
MU
MD
UPL
UPL
A
A
A DNL
A DNL
Logic Design :VerilogFSM in class design example s 5 S. Yoder ND, 2010
Make the State Assignments
initial
up
next
dn
next
moving
up
moving
down
A
UPL
A
DNL
A
MU
MD
UP
L
UPL
A
A
A
DNL
A
DNL
Logic Design :VerilogFSM in class design example s 6 S. Yoder ND, 2010
Setup clear and state register
initial
up
next
dn
next
moving
up
moving
down
A
UPL
A
DNL
A
MU
MD
UP
L
UPL
A
A
A
DNL
A
DNL
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Describe the Behavior
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Behavior Continued
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Xilinx Verilog Test Fixture
1
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Test Bench for Clock
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Simulation Results
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Simulation Results Continued
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Xilinx Simulation Tips
Provide a means (reset signal) to initialize all
internal variables, otherwise dont care
conditions occur throughout the simulation.
always @(posedge clk)
begin
if (reset) begin
countValue =0;
clkDivOut <=0;
In the test bench code, first initialize the circuit under test.
Select the sim instance tab in the source window to bring
up internal signals to be placed in the simulator
waveform.
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CSE 20221: Logic Design
Timers, Frequency Divider Examples
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Timers
Timer
time events
divide clock frequency
provide delay
In each case the basic idea is to count clock
pulses
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Verilog Code for Timer
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Timer Simulation
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Verilog Code for Frequency Divider
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Frequency Divider Simulation
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Design of a Derived Clock
Design a 1 millisecond clock that is derived from
a 50 MHz system clock.
Design approach
Frequency divider
Divide by 50,000
Determining size (N) of counter
given division factor, DF
N = roundUp(ln DF / ln 2) -1
Parameter [N:0] countValue;
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Verilog Description
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Test Fixture
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Similation Results
