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Time Table s2

The document outlines a schedule for various labs and activities across different days of the week. On Tuesday, ESD and AICD labs are scheduled along with FPGA and LPD activities. Wednesday includes ADNCD Micro Lab, LPD, and FPGA as well as Physical Design Lab, Advanced Micro Controller Lab, and AICD. Thursday lists ADSP, AICD, and ESD along with Physical Design Lab and a seminar. Friday has ADSP, ESD, and FPGA scheduled.

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Jacob Chako
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33 views1 page

Time Table s2

The document outlines a schedule for various labs and activities across different days of the week. On Tuesday, ESD and AICD labs are scheduled along with FPGA and LPD activities. Wednesday includes ADNCD Micro Lab, LPD, and FPGA as well as Physical Design Lab, Advanced Micro Controller Lab, and AICD. Thursday lists ADSP, AICD, and ESD along with Physical Design Lab and a seminar. Friday has ADSP, ESD, and FPGA scheduled.

Uploaded by

Jacob Chako
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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mon TUE

ESD(MJB) AICD(JKR)

FPGA() LPD

LPD(ASK) ADSP

WED

ADNCD MICRO LAB(MJB)

LPD

FPGA

PHYSICAL DESIGN LAB(JKR) ADVANCED MICRO CONTROLLER LAB(MJB) AICD

THRS ADSP

AICD

ESD

PHYSICAL DSN LAB(JKR) SEMINAR

FRI

ADSP

ESD

FPGA

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