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VHDL State Machine Design Template

The document discusses the design of state machines using different styles. It provides examples of simple state machines including a BCD counter, two simple FSM examples and a string detector. It explains the design of state machines using style #1 for combinational output and style #2 for stored/synchronous output. Diagrams and VHDL code are presented for the example state machines.

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Ali Ahmad
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151 views6 pages

VHDL State Machine Design Template

The document discusses the design of state machines using different styles. It provides examples of simple state machines including a BCD counter, two simple FSM examples and a string detector. It explains the design of state machines using style #1 for combinational output and style #2 for stored/synchronous output. Diagrams and VHDL code are presented for the example state machines.

Uploaded by

Ali Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

State Machine Block Diagarm

Design of the Lower (Sequential) Section

Design of the Upper (Combinational) Section

State Machine Template for Design Style #1 Example: BCD Counter

Example: Simple FSM #1 Figure shows the states diagram of a very simple FSM. The system has two states (stateA and stateB), and must change from one to the other every time d= 1 is received. The desired output is x =a when the machine is in stateA, or x = b when in stateB. The initial (reset) state is stateA. A VHDL code for this circuit, employing design style #1, is shown below.

Design Style #2 (Stored Output)

Example: Simple FSM #2 Let us consider the design of FSM #1 example once again. However, let us say that now we want the output to be synchronous (to change only when clock rises). Since this is a Mealy machine, design style #2 is required.

Final Example: String Detector We want to design a circuit that takes as input a serial bit stream and outputs a 1 whenever the sequence 111 occurs. Overlaps must also be considered, that is, if . . . 0111110 . . . occurs, than the output should remain active for three consecutive clock cycles.

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