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Fibonacci Sequence VERILOG MODULE

This Verilog module calculates Fibonacci numbers by incrementing current and previous values on each clock pulse after reset. It contains a module that generates a clock signal and resets the Fibonacci module initially. On each clock pulse, it updates current by adding it to previous, and updates previous by subtracting it from the new current value. The output value wire displays the nth Fibonacci number calculated by the module.

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1K views3 pages

Fibonacci Sequence VERILOG MODULE

This Verilog module calculates Fibonacci numbers by incrementing current and previous values on each clock pulse after reset. It contains a module that generates a clock signal and resets the Fibonacci module initially. On each clock pulse, it updates current by adding it to previous, and updates previous by subtracting it from the new current value. The output value wire displays the nth Fibonacci number calculated by the module.

Uploaded by

deardestiny
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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VERILOG MODULE module fibonacci(clock,reset,value); input clock,reset; output [31:0]value; reg [31:0]previous,current; //Reset the circuit always@(posedge reset)

begin previous<=32d0; current<=32d1; end always@(posedge clock) begin //increment current index current=current+previous; previous=current-previous; end //Read the value of the nth fibonacci number assign value=previous; endmodule

TEST BENCH module fibtb(); reg clock,reset; wire [31:0]value; fibonacci f1(value,clock,reset); initial begin reset=1; #10 reset=0; end initial begin clock=0; forever #10 clock=~clock; end initial begin #500 $finish; end endmodule

OUTPUT

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