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AVR Assembly Examples

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100% found this document useful (16 votes)

18K views159 pages

AVR Assembly Examples

This is a pdf version of a website. It is a full of assembly example for avr

Uploaded by

Tanvir Hussain

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF or read online on Scribd

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The AVR Assembler Site

HOME Welcome to AVR

RETRO_DAN Assembler Site
ASM FORUM
ASSEMBLY
ASM MATH LANGUAGE:
TUTORIAL #1
The Mnemonic
TUTORIAL #2
Representation of
TUTORIAL #3 Machine Code.
MATH 200
Assembly Language
MATH 200b remains in use
MATH 201 because of its close
relationship to the The AVR is a family of RISC
MATH 202
underlying machine. It microcontrollers from Atmel. The AVR
MATH 32X is used by those who architecture, first conceived by two
need to compress electronic engineering students at the
MATH YX
programs into the Norwegian Institute of Technology
DIV16 XX smallest memory (NTH), has been refined and developed
DIV 24 24 space and have it by Atmel Norway, in a division founded
excecute as fast and by the chip's architects.
DIV 3216 efficiently as possible.
FLOAT 128 It can be a difficult
medium in which to
SQRT16 work. Many can forget
MATH 202 that whether done by
man or compiler, all
MATH 202
computer languages
DEC ASCII must be translated
into machine code
INT ASCII
before they can run in
HX2ASC hardware. The AVR architects, Vergard Wollan and
AVG8 222 Alf-Egil Bogen. Bogen's 1992 NTH thesis
Submit New was titled: High Speed Analog to Digital
FFT7
Routines, Updates, Converters in CMOS.
COPY 102 Bug Reports to
LPM 108 AVR Assembler
Forum at: http://avr.x.
EPROM 100 am
SER EPROM
DFLASH AT45 Most high-level
languages for the AVR
FLASH CARD core accomplish this A RetroDan (HWMNBN) Site
VFX SMIL by translating
programs into
VFX MEM Assembler
SORT 220 Instructions first. The
resultant Assembler
CRC 236
Program is then
XMODEM REC converted to machine-
UART 304 code instructions. The
process may be
UART 305 automated and appear
UART 128 transparent to the
programmer. This is
UART BUFF how the C compilers
USB 232 work.
AVR ISP
THE TWO-PASS
ISP 2313 ASSEMBLER
ISP 1200
Since assembly
AVR SPI
language statements
I2C 300 have a one-to-one
I2C 302 correspondence with
binary instructions it
I2C TWI26 seems only logical to
I2C/TWI 128 simply translate
assembly instructions
I2C/TWI AT8 directly into binary
DALLAS-1W machine code, one-at-
a-time.
DALLAS CRC
ETHNET 8019 This method does not
TEA work due to forward
references and jumps
ADC 128 to lables that have not
ADC 10B been defined yet. This
is the reason most
ADC 400
assemblers are the
ADC 401 two-pass type.
THERM 232
The primary function
IRD 410 of pass-one is to build
LCD HD44 up a symbol table that
contain all the
LCD 2313
constants and labels
LCD44 2313 along with their
KBD 240 values.

MUX 242 The second-pass

KBD PS2 then uses this symbol
table to create the
KBD PC/128
binary machine code.
PS2 EMU
BOOT MG8
BOOT DR8
ALM CLK
CLOCK 8564 Programming the AVR
Microcontrollers in Machine
90 DAYS Language
DELAYS
CALL ID AVR
DTMF 314 << Prev | Ring Hub | Join | Rate| Next
PWM 6CH >>
PWM 10K © WebRing Inc. Search
ENCODE
STH-11
ATMEL CORP
Atmel AVR From Wikipedia, the
AVR free encyclopedia (Redirected
BUTTERFLY
from Avr) Jump to: navigation,
AVR BOOK
search The AVRs are a family of
RISC microcontrollers from Atmel.
Their internal architecture was
conceived by two students: Alf-
Egil Bogen and Vegard Wollan, at
the Norwegian Institute of
Technology (NTH] and further
developed at Atmel Norway, a
subsidiary founded by the two
architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
architecture was conceived by
two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
http://avr-asm.tripod.com/ (1 of 2)1/20/2009 8:32:57 PM
The AVR Assembler Site

architecture was conceived by

two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language

http://avr-asm.tripod.com/ (2 of 2)1/20/2009 8:32:57 PM

The AVR Assembler Site

HOME Welcome to AVR

MUX 242 The second-pass

KBD PS2 then uses this symbol
table to create the
KBD PC/128
binary machine code.
PS2 EMU
BOOT MG8
BOOT DR8
ALM CLK
CLOCK 8564 Programming the AVR
Microcontrollers in Machine
90 DAYS Language
DELAYS
CALL ID AVR
DTMF 314 << Prev | Ring Hub | Join | Rate| Next
PWM 6CH >>
PWM 10K © WebRing Inc. Search
ENCODE
STH-11
ATMEL CORP
Atmel AVR From Wikipedia, the
AVR free encyclopedia (Redirected
BUTTERFLY
from Avr) Jump to: navigation,
AVR BOOK
search The AVRs are a family of
RISC microcontrollers from Atmel.
Their internal architecture was
conceived by two students: Alf-
Egil Bogen and Vegard Wollan, at
the Norwegian Institute of
Technology (NTH] and further
developed at Atmel Norway, a
subsidiary founded by the two
architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
architecture was conceived by
two students: Alf-Egil Bogen and
Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and
further developed at Atmel
Norway, a subsidiary founded by
the two architects. Atmel recently
released the Atmel AVR32 line of
microcontrollers. These are 32-bit
RISC devices featuring SIMD and
DSP instructions, along with
many additional features for audio
and video processing, intended to
compete with ARM based
processors. Note that the use of
"AVR" in this article refers to the
8-bit RISC line of Atmel AVR
Microcontrollers. The acronym
AVR has been reported to stand
for Advanced Virtual RISC. It's
also rumoured to stand for the
company's founders: Alf and
Vegard, who are evasive when
questioned about it. Contents
[hide] 1 Device Overview 1.1
Program Memory 1.2 Data
Memory and Registers 1.3
EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official
Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine
Language Development 6.4 C
Language Development 6.5 BASIC
& Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The
AVR is a Harvard architecture
machine with programs and data
stored and addressed separately.
Flash, EEPROM, and SRAM are all
integrated onto a single die,
removing the need for external
memory (though still available on
some devices). [edit] Program
Memory Program instructions are
stored in semi-permanent Flash
memory. Each instruction for the
AVR line is either 16 or 32 bits in
length. The Flash memory is
addressed using 16 bit word
sizes. The size of the program
memory is indicated in the
naming of the device itself. For
instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR
devices are self-programmable.
[edit] Data Memory and Registers
The data address space consists
of the register file, I/O registers,
and SRAM. The AVRs have thirty-
two single-byte registers and are
classified as 8-bit RISC devices.
The working registers are mapped
in as the first thirty-two memory
spaces (000016-001F16) followed
by the 64 I/O registers (002016-
005F16). The actual usable RAM
starts after both these sections
(address 006016). (Note that the I/
O register space may be larger on
some more extensive devices, in
which case memory mapped I/O
registers will occupy a portion of
the SRAM.) Even though there are
separate addressing schemes and
optimized opcodes for register file
and I/O register access, all can
still be addressed and
manipulated as if they were in
SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM.
This is most often used for long-
term parameter storage to be
retrieved even after cycling the
power of the device. [edit]
Program Execution Atmel's AVRs
have a single level pipeline
design. The next machine
instruction is fetched as the
current one is executing. Most
instructions take just one or two
clock cycles, making AVRs
relatively fast among the eight-bit
microcontrollers. The AVR family
of processors were designed for
the efficient execution of
compiled C code. The AVR
instruction set is more orthogonal
than most eight-bit
microcontrollers, however, it is
not completely regular: Pointer
registers X, Y, and Z have
addressing capabilities that are
different from each other. Register
locations R0 to R15 have different
addressing capabilities than
register locations R16 to R31. I/O
ports 0 to 31 have different
addressing capabilities than I/O
ports 32 to 63. CLR affects flags,
while SER does not, even though
they are complementary
instructions. CLR set all bits to
zero and SER sets them to one.
(Note though, that neither CLR
nor SER are native instructions.
Instead CLR is syntactic sugar for
[produces the same machine code
as] EOR R,R while SER is
syntactic sugar for LDI R,$FF.
Math operations such as EOR
modify flags while moves/loads/
stores/branches such as LDI do
not.) [edit] Speed The AVR line
can normally support clock
speeds from 0-16MHz, with some
devices reaching 20MHz. Lower
powered operation usually
requires a reduced clock speed.
All AVRs feature an on-chip
oscillator, removing the need for
external clocks or resonator
circuitry. Because many
operations on the AVR are single
cycle, the AVR can achieve up to
1MIPS per MHz. [edit]
Development AVRs have a large
following due to the free and
inexpensive development tools
available, including reasonably
priced development boards and
free development software. The
AVRs are marketed under various
names that share the same basic
core but with different peripheral
and memory combinations. Some
models (notably, the ATmega
range) have additional
instructions to make arithmetic
faster. Compatibility amongst
chips is fairly good. See external
links for sites relating to AVR
development. [edit] Features
Current AVRs offer a wide range
of features: RISC Core Running
Many Single Cycle Instructions
Multifunction, Bi-directional I/O
Ports with Internal, Configurable
Pull-up Resistors Multiple Internal
Oscillators Internal, Self-
Programmable Instruction Flash
Memory up to 256K In-System
Programmable using ICSP, JTAG,
or High Voltage methods Optional
Boot Code Section with
Independent Lock Bits for
Protection Internal Data EEPROM
up to 4KB Internal SRAM up to 8K
8-Bit and 16-Bit Timers PWM
Channels & dead time generator
Lighting (PWM Specific)
Controller models Dedicated I²C
Compatible Two-Wire Interface
(TWI) Synchronous/
Asynchronous Serial Peripherals
(UART/USART) (As used with RS-
232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN
Controller Support USB Controller
Support Proper High-speed
hardware & Hub controller with
embedded AVR. Also freely
available low-speed (HID)
software emulation Ethernet
Controller Support Universal
Serial Interface (USI) for Two or
Three-Wire Synchronous Data
Transfer Analog Comparators
LCD Controller Support 10-Bit A/D
Converters, with multiplex of up
to 16 channels Brownout
Detection Watchdog Timer (WDT)
Low-voltage Devices Operating
Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower
Devices Atmel AVR assembler
programming language Atmel
AVR machine programming
language Atmel AVR From
Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to:
navigation, search The AVRs are a
family of RISC microcontrollers
from Atmel. Their internal
http://avr-asm.tripod.com/index.html (1 of 2)1/20/2009 8:33:30 PM
The AVR Assembler Site

architecture was conceived by

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MULTIPLY & DIVIDE (AVR 200)

The AVR Assembler Site

MULTIPLY & DIVIDE (AVR 200)

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RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 0
ASM FORUM ************************
ASM MATH ;*
;* Title: Multiply and Divide Routines
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: [email protected]
MATH 200b ;* ;* DESCRIPTION
;* This Application Note lists subroutines for the following
MATH 201 ;* Muliply/Divide applications:
MATH 202 ;*
;* 8x8 bit unsigned
MATH 32X ;* 8x8 bit signed
MATH YX ;* 16x16 bit unsigned
;* 16x16 bit signed
DIV16 XX
;* 8/8 bit unsigned
DIV 24 24 ;* 8/8 bit signed
DIV 3216 ;* 16/16 bit unsigned
;* 16/16 bit signed
FLOAT 128 ;*
SQRT16 ;* All routines are Code Size optimized implementations
;*;
MATH 202 ***************************************************************************
MATH 202 .include "1200def.inc"
DEC ASCII
rjmp RESET ;reset handle
INT ASCII
HX2ASC
;
AVG8 222 ***************************************************************************
FFT7 ;*
;* "mpy8u" - 8x8 Bit Unsigned Multiplication
COPY 102 ;*
LPM 108 ;* This subroutine multiplies the two register variables mp8u
and mc8u.
EPROM 100 ;* The result is placed in registers m8uH, m8uL
SER EPROM ;*
;* Number of words :9 + return
DFLASH AT45
;* Number of cycles :58 + return
FLASH CARD ;* Low registers used :None
;* High registers used :4 (mp8u,mc8u/m8uL,m8uH,mcnt8u)
VFX SMIL
;*
VFX MEM ;* Note: Result Low byte and the multiplier share the same
SORT 220 register.
;* This causes the multiplier to be overwritten by the result.
CRC 236 ;*
XMODEM REC ;
***************************************************************************
UART 304
UART 305 ;***** Subroutine Register Variables
UART 128
.def mc8u =r16 ;multiplicand
UART BUFF .def mp8u =r17 ;multiplier
.def m8uL =r17 ;result Low byte
USB 232
.def m8uH =r18 ;result High byte
AVR ISP .def mcnt8u =r19 ;loop counter
ISP 2313
;***** Code
ISP 1200
AVR SPI
mpy8u: clr m8uH ;clear result High byte
I2C 300 ldi mcnt8u,8 ;init loop counter
I2C 302 lsr mp8u ;rotate multiplier
I2C TWI26
m8u_1: brcc m8u_2 ;carry set
I2C/TWI 128 add m8uH,mc8u ; add multiplicand to result High
I2C/TWI AT8 byte
m8u_2: ror m8uH ;rotate right result High
DALLAS-1W byte
DALLAS CRC ror m8uL ;rotate right result L byte and
multiplier
ETHNET 8019 dec mcnt8u ;decrement loop counter
TEA brne m8u_1 ;if not done, loop more
ret
ADC 128
ADC 10B
ADC 400
ADC 401 ;
THERM 232 ***************************************************************************
;*
IRD 410 ;* "mpy8s" - 8x8 Bit Signed Multiplication
LCD HD44 ;*
;* This subroutine multiplies signed the two register variables
LCD 2313 mp8s and
LCD44 2313 ;* mc8s. The result is placed in registers m8sH, m8sL
;* The routine is an implementation of Booth's algorithm. If
KBD 240 all 16 bits
MUX 242 ;* in the result are needed, avoid calling the routine with
;* -128 ($80) as multiplicand
KBD PS2
;*
KBD PC/128 ;* Number of words :10 + return
PS2 EMU ;* Number of cycles :73 + return
;* Low registers used :None
BOOT MG8 ;* High registers used :4 (mc8s,mp8s/m8sL,m8sH,mcnt8s)
BOOT DR8 ;*
;
ALM CLK ***************************************************************************
CLOCK 8564
;***** Subroutine Register Variables
90 DAYS
DELAYS .def mc8s =r16 ;multiplicand
.def mp8s =r17 ;multiplier
CALL ID
.def m8sL =r17 ;result Low byte
DTMF 314 .def m8sH =r18 ;result High byte
PWM 6CH .def mcnt8s =r19 ;loop counter

PWM 10K ;***** Code

ENCODE
mpy8s: sub m8sH,m8sH ;clear result High byte and
STH-11 carry
ATMEL CORP ldi mcnt8s,8 ;init loop counter
m8s_1: brcc m8s_2 ;if carry (previous bit) set
AVR
add m8sH,mc8s ; add multiplicand to result
BUTTERFLY High byte
AVR BOOK m8s_2: sbrc mp8s,0 ;if current bit set
sub m8sH,mc8s ; subtract multiplicand from
result High
asr m8sH ;shift right result High byte
ror m8sL ;shift right result L byte and
multiplier
dec mcnt8s ;decrement loop counter
brne m8s_1 ;if not done, loop more
ret

;
***************************************************************************
;*
;* "mpy16u" - 16x16 Bit Unsigned Multiplication
;*
;* This subroutine multiplies the two 16-bit register variables
;* mp16uH:mp16uL and mc16uH:mc16uL.
;* The result is placed in m16u3:m16u2:m16u1:m16u0.
;*
;* Number of words :14 + return
;* Number of cycles :153 + return
;* Low registers used :None
;* High registers used :7 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/
m16u1,m16u2,
;* m16u3,mcnt16u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def mc16uL =r16 ;multiplicand low byte

.def mc16uH =r17 ;multiplicand high byte
.def mp16uL =r18 ;multiplier low byte
.def mp16uH =r19 ;multiplier high byte
.def m16u0 =r18 ;result byte 0 (LSB)
.def m16u1 =r19 ;result byte 1
.def m16u2 =r20 ;result byte 2
.def m16u3 =r21 ;result byte 3 (MSB)
.def mcnt16u =r22 ;loop counter

;***** Code

mpy16u: clr m16u3 ;clear 2 highest bytes of

result
clr m16u2
ldi mcnt16u,16 ;init loop counter
lsr mp16uH
ror mp16uL

m16u_1: brcc noad8 ;if bit 0 of multiplier set

add m16u2,mc16uL ;add multiplicand Low to byte 2 of
res
adc m16u3,mc16uH ;add multiplicand high to byte 3 of
res
noad8: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low
dec mcnt16u ;decrement loop counter
brne m16u_1 ;if not done, loop more
ret

;
***************************************************************************
;*
;* "mpy16s" - 16x16 Bit Signed Multiplication
;*
;* This subroutine multiplies signed the two 16-bit register
variables
;* mp16sH:mp16sL and mc16sH:mc16sL.
;* The result is placed in m16s3:m16s2:m16s1:m16s0.
;* The routine is an implementation of Booth's algorithm. If
all 32 bits
;* in the result are needed, avoid calling the routine with
;* -32768 ($8000) as multiplicand
;*
;* Number of words :16 + return
;* Number of cycles :210/226 (Min/Max) + return
;* Low registers used :None
;* High registers used :7 (mp16sL,mp16sH,mc16sL/m16s0,mc16sH/
m16s1,
;* m16s2,m16s3,mcnt16s)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def mc16sL =r16 ;multiplicand low byte

.def mc16sH =r17 ;multiplicand high byte
.def mp16sL =r18 ;multiplier low byte
.def mp16sH =r19 ;multiplier high byte
.def m16s0 =r18 ;result byte 0 (LSB)
.def m16s1 =r19 ;result byte 1
.def m16s2 =r20 ;result byte 2
.def m16s3 =r21 ;result byte 3 (MSB)
.def mcnt16s =r22 ;loop counter

;***** Code
mpy16s: clr m16s3 ;clear result byte 3
sub m16s2,m16s2 ;clear result byte 2 and carry
ldi mcnt16s,16 ;init loop counter
m16s_1: brcc m16s_2 ;if carry (previous bit) set
add m16s2,mc16sL ; add multiplicand Low to result
byte 2
adc m16s3,mc16sH ; add multiplicand High to
result byte 3
m16s_2: sbrc mp16sL,0 ;if current bit set
sub m16s2,mc16sL ; sub multiplicand Low from
result byte 2
sbrc mp16sL,0 ;if current bit set
sbc m16s3,mc16sH ; sub multiplicand High from
result byte 3
asr m16s3 ;shift right result and multiplier
ror m16s2
ror m16s1
ror m16s0
dec mcnt16s ;decrement counter
brne m16s_1 ;if not done, loop more
ret

;
***************************************************************************
;*
;* "div8u" - 8/8 Bit Unsigned Division
;*
;* This subroutine divides the two register variables
"dd8u" (dividend) and
;* "dv8u" (divisor). The result is placed in "dres8u" and the
remainder in
;* "drem8u".
;*
;* Number of words :14
;* Number of cycles :97
;* Low registers used :1 (drem8u)
;* High registers used :3 (dres8u/dd8u,dv8u,dcnt8u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem8u =r15 ;remainder

.def dres8u =r16 ;result
.def dd8u =r16 ;dividend
.def dv8u =r17 ;divisor
.def dcnt8u =r18 ;loop counter

;***** Code

div8u: sub drem8u,drem8u ;clear remainder and carry

ldi dcnt8u,9 ;init loop counter
d8u_1: rol dd8u ;shift left dividend
dec dcnt8u ;decrement counter
brne d8u_2 ;if done
ret ; return
d8u_2: rol drem8u ;shift dividend into
remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_3 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_1 ;else
d8u_3: sec ; set carry to be
shifted into result
rjmp d8u_1

;
***************************************************************************
;*
;* "div8s" - 8/8 Bit Signed Division
;*
;* This subroutine divides the two register variables
"dd8s" (dividend) and
;* "dv8s" (divisor). The result is placed in "dres8s" and the
remainder in
;* "drem8s".
;*
;* Number of words :27
;* Number of cycles :107/108
;* Low registers used :2 (d8s,drem8s)
;* High registers used :3 (dres8s/dd8s,dv8s,dcnt8s)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def d8s =r14 ;sign register

.def drem8s =r15 ;remainder
.def dres8s =r16 ;result
.def dd8s =r16 ;dividend
.def dv8s =r17 ;divisor
.def dcnt8s =r18 ;loop counter

;***** Code

div8s: mov d8s,dd8s ;move dividend to sign

sbrc dv8s,7 ;if MSB of divisor set

neg dv8s ; change sign of divisor
sbrc dd8s,7 ;if MSB of dividend set
neg dd8s ; change sign of divisor
sub drem8s,drem8s ;clear remainder and carry
ldi dcnt8s,9 ;init loop counter
d8s_1: rol dd8s ;shift left dividend
dec dcnt8s ;decrement counter
brne d8s_2 ;if done
sbrc d8s,7 ; if MSB of sign register set
neg dres8s ; change sign of result

ret ; return
d8s_2: rol drem8s ;shift dividend into
remainder
sub drem8u,dv8s ;remainder = remainder - divisor
brcc d8s_3 ;if result negative
add drem8u,dv8s ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8s_1 ;else
d8s_3: sec ; set carry to be
shifted into result
rjmp d8s_1

;
***************************************************************************
;*
;* "div16u" - 16/16 Bit Unsigned Division
;*
;* This subroutine divides the two 16-bit numbers
;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor).
;* The result is placed in "dres16uH:dres16uL" and the
remainder in
;* "drem16uH:drem16uL".
;*
;* Number of words :19
;* Number of cycles :235/251 (Min/Max)
;* Low registers used :2 (drem16uL,drem16uH)
;* High registers used :5 (dres16uL/dd16uL,dres16uH/dd16uH,
dv16uL,dv16uH,
;* dcnt16u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem16uL=r14
.def drem16uH=r15
.def dres16uL=r16
.def dres16uH=r17
.def dd16uL =r16
.def dd16uH =r17
.def dv16uL =r18
.def dv16uH =r19
.def dcnt16u =r20

;***** Code

div16u: clr drem16uL ;clear remainder Low byte

sub drem16uH,drem16uH;clear remainder High byte and
carry
ldi dcnt16u,17 ;init loop counter
d16u_1: rol dd16uL ;shift left dividend
rol dd16uH
dec dcnt16u ;decrement counter
brne d16u_2 ;if done
ret ; return
d16u_2: rol drem16uL ;shift dividend into
remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_3 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_1 ;else
d16u_3: sec ; set carry to be
shifted into result
rjmp d16u_1

;
***************************************************************************
;*
;* "div16s" - 16/16 Bit Signed Division
;*
;* This subroutine divides signed the two 16 bit numbers
;* "dd16sH:dd16sL" (dividend) and "dv16sH:dv16sL" (divisor).
;* The result is placed in "dres16sH:dres16sL" and the
remainder in
;* "drem16sH:drem16sL".
;*
;* Number of words :45
;* Number of cycles :252/268 (Min/Max)
;* Low registers used :3 (d16s,drem16sL,drem16sH)
;* High registers used :7 (dres16sL/dd16sL,dres16sH/dd16sH,
dv16sL,dv16sH,
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def d16s =r13 ;sign register

.def drem16sL=r14 ;remainder low
byte
.def drem16sH=r15 ;remainder high byte
.def dres16sL=r16 ;result low byte
.def dres16sH=r17 ;result high byte
.def dd16sL =r16 ;dividend low byte
.def dd16sH =r17 ;dividend high byte
.def dv16sL =r18 ;divisor low byte
.def dv16sH =r19 ;divisor high byte
.def dcnt16s =r20 ;loop counter

;***** Code

div16s: mov d16s,dd16sH ;move dividend High to sign

sbrs dd16sH,7 ;if MSB in dividend set

rjmp d16s_1
com dd16sH ; change sign of dividend
com dd16sL
subi dd16sL,low(-1)
sbci dd16sL,high(-1)
d16s_1: sbrs dv16sH,7 ;if MSB in divisor set
rjmp d16s_2
com dv16sH ; change sign of divisor
com dv16sL
subi dv16sL,low(-1)
sbci dv16sL,high(-1)
d16s_2: clr drem16sL ;clear remainder Low byte
sub drem16sH,drem16sH;clear remainder High byte and
carry
ldi dcnt16s,17 ;init loop counter

d16s_3: rol dd16sL ;shift left dividend

rol dd16sH
dec dcnt16s ;decrement counter
brne d16s_5 ;if done
sbrs d16s,7 ; if MSB in sign register set
rjmp d16s_4
com dres16sH ; change sign of result
com dres16sL
subi dres16sL,low(-1)
sbci dres16sH,high(-1)

d16s_4:
ret ; return
d16s_5: rol drem16sL ;shift dividend into
remainder
rol drem16sH
sub drem16sL,dv16sL ;remainder = remainder - divisor
sbc drem16sH,dv16sH ;
brcc d16s_6 ;if result negative
add drem16sL,dv16sL ; restore remainder
adc drem16sH,dv16sH
clc ; clear carry to be shifted into
result
rjmp d16s_3 ;else
d16s_6: sec ; set carry to be
shifted into result
rjmp d16s_3

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of
usage and to
;* verify correct verification.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code
RESET:
;---------------------------------------------------------------
;Include these lines for devices with SRAM
; ldi temp,low(RAMEND)
; out SPL,temp
; ldi temp,high(RAMEND)
; out SPH,temp ;init Stack Pointer
;---------------------------------------------------------------

;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4)

ldi mc8u,250
ldi mp8u,4
rcall mpy8u ;result: m8uH:m8uL = $03e8 (1000)

;***** Multiply Two Signed 8-Bit Numbers (-99 * 88)

ldi mc8s,-99
ldi mp8s,88
rcall mpy8s ;result: m8sH:m8sL = $ddf8 (-8712)

;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000)

ldi mc16uL,low(5050)
ldi mc16uH,high(5050)
ldi mp16uL,low(10000)
ldi mp16uH,high(10000)
rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0
;=030291a0 (50,500,000)

;***** Multiply Two Signed 16-Bit Numbers (-12345*(-4321))

ldi mc16sL,low(-12345)
ldi mc16sH,high(-12345)
ldi mp16sL,low(-4321)
ldi mp16sH,high(-4321)
rcall mpy16s ;result: m16s3:m16s2:m16s1:m16s0
;=$032df219 (53,342,745)

;***** Divide Two Unsigned 8-Bit Numbers (100/3)

ldi dd8u,100
ldi dv8u,3
rcall div8u ;result: $21 (33)
;remainder: $01 (1)

;***** Divide Two Signed 8-Bit Numbers (-110/-11)

ldi dd8s,-110
ldi dv8s,-11
rcall div8s ;result: $0a (10)
;remainder $00 (0)

;***** Divide Two Unsigned 16-Bit Numbers (50,000/60,000)

ldi dd16uL,low(50000)
ldi dd16uH,high(50000)
ldi dv16uL,low(60000)
ldi dv16uH,high(60000)
rcall div16u ;result: $0000 (0)
;remainder: $c350 (50,000)

;***** Divide Two Signed 16-Bit Numbers (-22,222/10)

ldi dd16sL,low(-22222)
ldi dd16sH,high(-22222)
ldi dv16sL,low(10)
ldi dv16sH,high(10)
rcall div16s ;result: $f752 (-2222)
;remainder: $0002 (2)

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected from

Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was
conceived by two students: Alf-Egil Bogen and Vegard Wollan, at
the Norwegian Institute of Technology (NTH] and further developed
at Atmel Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along
with many additional features for audio and video processing,
intended to compete with ARM based processors. Note that the use
of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have

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MULTIPLY & DIVIDE (AVR 200)

different addressing capabilities than register locations R16 to R31.

I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language

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MULTIPLY & DIVIDE (AVR 200)

The AVR Assembler Site

FAST MULTIPLY & DIVIDE (AVR 200b)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 0 b
ASM FORUM ************************
ASM MATH ;*
;* Title: Multiply and Divide Routines
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: [email protected]
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application Note lists subroutines for the following
MATH 202 ;* Muliply/Divide applications. Routines are straight-line
implementations
MATH 32X ;* optimized for speed:
MATH YX ;*
;* 8 x 8 = 16 bit unsigned
DIV16 XX
;* 16 x 16 = 32 bit unsigned
DIV 24 24 ;* 8 / 8 = 8 + 8 bit unsigned
DIV 3216 ;* 16 / 16 = 16 + 16 bit unsigned
;*
FLOAT 128 ;
SQRT16 ***************************************************************************

MATH 202 .include "1200def.inc"

MATH 202
rjmp RESET ;reset handle
DEC ASCII
INT ASCII ;
***************************************************************************
HX2ASC
;*
AVG8 222 ;* "mpy8u" - 8x8 Bit Unsigned Multiplication
FFT7 ;*
;* This subroutine multiplies the two register variables mp8u
COPY 102 and mc8u.
LPM 108 ;* The result is placed in registers m8uH, m8uL
;*
EPROM 100 ;* Number of words :34 + return
SER EPROM ;* Number of cycles :34 + return
;* Low registers used :None
DFLASH AT45
;* High registers used :3 (mc8u,mp8u/m8uL,m8uH)
FLASH CARD ;*
;* Note: Result Low byte and the multiplier share the same
VFX SMIL
register.
VFX MEM ;* This causes the multiplier to be overwritten by the result.
SORT 220 ;*
;
CRC 236 ***************************************************************************
XMODEM REC
;***** Subroutine Register Variables
UART 304
UART 305 .def mc8u =r16 ;multiplicand
.def mp8u =r17 ;multiplier
UART 128
.def m8uL =r17 ;result Low byte
UART BUFF .def m8uH =r18 ;result High byte
USB 232
;***** Code
AVR ISP
ISP 2313 mpy8u: clr m8uH ;clear result High byte
lsr mp8u ;shift multiplier
ISP 1200
AVR SPI brcc noad80 ;if carry set
add m8uH,mc8u ; add multiplicand to result
I2C 300 High byte
I2C 302 noad80: ror m8uH ;shift right result High
byte
I2C TWI26
ror m8uL ;rotate right result L byte and
I2C/TWI 128 multiplier
I2C/TWI AT8
brcc noad81 ;if carry set
DALLAS-1W add m8uH,mc8u ; add multiplicand to result
DALLAS CRC High byte
noad81: ror m8uH ;shift right result High
ETHNET 8019 byte
TEA ror m8uL ;rotate right result L byte and
multiplier
ADC 128
ADC 10B brcc noad82 ;if carry set
add m8uH,mc8u ; add multiplicand to result
ADC 400
High byte
ADC 401 noad82: ror m8uH ;shift right result High
THERM 232 byte
ror m8uL ;rotate right result L byte and
IRD 410 multiplier
LCD HD44
brcc noad83 ;if carry set
LCD 2313 add m8uH,mc8u ; add multiplicand to result
LCD44 2313 High byte
noad83: ror m8uH ;shift right result High
KBD 240 byte
MUX 242 ror m8uL ;rotate right result L byte and
multiplier
KBD PS2
KBD PC/128 brcc noad84 ;if carry set
PS2 EMU add m8uH,mc8u ; add multiplicand to result
High byte
BOOT MG8 noad84: ror m8uH ;shift right result High
BOOT DR8 byte
ror m8uL ;rotate right result L byte and
ALM CLK multiplier
CLOCK 8564
brcc noad85 ;if carry set
90 DAYS
add m8uH,mc8u ; add multiplicand to result
DELAYS High byte
noad85: ror m8uH ;shift right result High
CALL ID
byte
DTMF 314 ror m8uL ;rotate right result L byte and
PWM 6CH multiplier

PWM 10K brcc noad86 ;if carry set

ENCODE add m8uH,mc8u ; add multiplicand to result
High byte
STH-11 noad86: ror m8uH ;shift right result High
ATMEL CORP byte
ror m8uL ;rotate right result L byte and
AVR
multiplier
BUTTERFLY
AVR BOOK brcc noad87 ;if carry set
add m8uH,mc8u ; add multiplicand to result
High byte
noad87: ror m8uH ;shift right result High
byte
ror m8uL ;rotate right result L byte and
multiplier

ret

;
***************************************************************************
;*
;* "mpy16u" - 16x16 Bit Unsigned Multiplication
;*
;* This subroutine multiplies the two 16-bit register variables
;* mp16uH:mp16uL and mc16uH:mc16uL.
;* The result is placed in m16u3:m16u2:m16u1:m16u0.
;*
;* Number of words :105 + return
;* Number of cycles :105 + return
;* Low registers used :None
;* High registers used :6 (mp16uL,mp16uH,mc16uL/m16u0,mc16uH/
m16u1,m16u2,
;* m16u3)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def mc16uL =r16 ;multiplicand low byte

;***** Code

mpy16u: clr m16u3 ;clear 2 highest bytes of

result
clr m16u2
lsr mp16uH ;rotate multiplier Low
ror mp16uL ;rotate multiplier High

brcc noadd0 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd0: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd1 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd1: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd2 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd2: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd3 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd3: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd4 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd4: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd5 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd5: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd6 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd6: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd7 ;if carry sett

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd7: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd8 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd8: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noadd9 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noadd9: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad10 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad10: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad11 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad11: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad12 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad12: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad13 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad13: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad14 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad14: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

brcc noad15 ;if carry set

add m16u2,mc16uL ; add multiplicand Low to byte 2
of res
adc m16u3,mc16uH ; add multiplicand high to byte
3 of res
noad15: ror m16u3 ;shift right result byte 3
ror m16u2 ;rotate right result byte 2
ror m16u1 ;rotate result byte 1 and
multiplier High
ror m16u0 ;rotate result byte 0 and
multiplier Low

ret

;
***************************************************************************
;*
;* "div8u" - 8/8 Bit Unsigned Division
;*
;* This subroutine divides the two register variables
"dd8u" (dividend) and
;* "dv8u" (divisor). The result is placed in "dres8u" and the
remainder in
;* "drem8u".
;*
;* Number of words :66 + return
;* Number of cycles :50/58/66 (Min/Avg/Max) + return
;* Low registers used :1 (drem8u)
;* High registers used :2 (dres8u/dd8u,dv8u)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem8u =r15 ;remainder

.def dres8u =r16 ;result
.def dd8u =r16 ;dividend
.def dv8u =r17 ;divisor

;***** Code

div8u: sub drem8u,drem8u ;clear remainder and carry

rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_1 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_2 ;else
d8u_1: sec ; set carry to be
shifted into result

d8u_2: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_3 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_4 ;else
d8u_3: sec ; set carry to be
shifted into result

d8u_4: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_5 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_6 ;else
d8u_5: sec ; set carry to be
shifted into result

d8u_6: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_7 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_8 ;else
d8u_7: sec ; set carry to be
shifted into result

d8u_8: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_9 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_10 ;else
d8u_9: sec ; set carry to be
shifted into result

d8u_10: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_11 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_12 ;else
d8u_11: sec ; set carry to be
shifted into result

d8u_12: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_13 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_14 ;else
d8u_13: sec ; set carry to be
shifted into result

d8u_14: rol dd8u ;shift left dividend

rol drem8u ;shift dividend into remainder
sub drem8u,dv8u ;remainder = remainder - divisor
brcc d8u_15 ;if result negative
add drem8u,dv8u ; restore remainder
clc ; clear carry to be shifted into
result
rjmp d8u_16 ;else
d8u_15: sec ; set carry to be
shifted into result

d8u_16: rol dd8u ;shift left dividend

ret

;
***************************************************************************
;*
;* "div16u" - 16/16 Bit Unsigned Division
;*
;* This subroutine divides the two 16-bit numbers
;* "dd8uH:dd8uL" (dividend) and "dv16uH:dv16uL" (divisor).
;* The result is placed in "dres16uH:dres16uL" and the
remainder in
;* "drem16uH:drem16uL".
;*
;* Number of words :196 + return
;* Number of cycles :148/173/196 (Min/Avg/Max)
;* Low registers used :2 (drem16uL,drem16uH)
;* High registers used :4 (dres16uL/dd16uL,dres16uH/dd16uH,
dv16uL,dv16uH)
;*
;
***************************************************************************

;***** Subroutine Register Variables

.def drem16uL=r14
.def drem16uH=r15
.def dres16uL=r16
.def dres16uH=r17
.def dd16uL =r16
.def dd16uH =r17
.def dv16uL =r18
.def dv16uH =r19

;***** Code

div16u: clr drem16uL ;clear remainder Low byte

sub drem16uH,drem16uH;clear remainder High byte and
carry

rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_1 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_2 ;else
d16u_1: sec ; set carry to be
shifted into result

d16u_2: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_3 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_4 ;else
d16u_3: sec ; set carry to be
shifted into result

d16u_4: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_5 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_6 ;else
d16u_5: sec ; set carry to be
shifted into result

d16u_6: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_7 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_8 ;else
d16u_7: sec ; set carry to be
shifted into result

d16u_8: rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_9 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_10 ;else
d16u_9: sec ; set carry to be
shifted into result

d16u_10:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_11 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_12 ;else
d16u_11:sec ; set carry to be shifted into
result

d16u_12:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_13 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_14 ;else
d16u_13:sec ; set carry to be shifted into
result

d16u_14:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_15 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_16 ;else
d16u_15:sec ; set carry to be shifted into
result

d16u_16:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_17 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_18 ;else
d16u_17: sec ; set carry to be
shifted into result

d16u_18:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_19 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_20 ;else
d16u_19:sec ; set carry to be shifted into
result

d16u_20:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_21 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_22 ;else
d16u_21:sec ; set carry to be shifted into
result

d16u_22:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_23 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_24 ;else
d16u_23:sec ; set carry to be shifted into
result

d16u_24:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_25 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_26 ;else
d16u_25:sec ; set carry to be shifted into
result

d16u_26:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_27 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_28 ;else
d16u_27:sec ; set carry to be shifted into
result

d16u_28:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_29 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_30 ;else
d16u_29:sec ; set carry to be shifted into
result

d16u_30:rol dd16uL ;shift left dividend

rol dd16uH
rol drem16uL ;shift dividend into remainder
rol drem16uH
sub drem16uL,dv16uL ;remainder = remainder - divisor
sbc drem16uH,dv16uH ;
brcc d16u_31 ;if result negative
add drem16uL,dv16uL ; restore remainder
adc drem16uH,dv16uH
clc ; clear carry to be shifted into
result
rjmp d16u_32 ;else
d16u_31:sec ; set carry to be shifted into
result

d16u_32:rol dd16uL ;shift left dividend

rol dd16uH
ret

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Multiply Two Unsigned 8-Bit Numbers (250 * 4)

ldi mc8u,250
ldi mp8u,4
rcall mpy8u ;result: m8uH:m8uL = $03e8 (1000)

;***** Multiply Two Unsigned 16-Bit Numbers (5050 * 10,000)

ldi mc16uL,low(5050)
ldi mc16uH,high(5050)
ldi mp16uL,low(10000)
ldi mp16uH,high(10000)
rcall mpy16u ;result: m16u3:m16u2:m16u1:m16u0
;=$030291a0 (50,500,000)

;***** Divide Two Unsigned 8-Bit Numbers (100/3)

ldi dd8u,100
ldi dv8u,3
rcall div8u ;result: $21 (33)
;remainder: $01 (1)

;***** Divide Two Unsigned 16-Bit Numbers (50,000/24,995)

ldi dd16uL,low(50000)
ldi dd16uH,high(50000)
ldi dv16uL,low(24995)
ldi dv16uH,high(24995)
rcall div16u ;result: $0002 (2)
;remainder: $000a (10)

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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MULTIPLY & DIVIDE (AVR 200)

AVRs have thirty-two single-byte registers and are classified as 8-

bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language Atmel AVR From Wikipedia, the
free encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from Atmel.
Their internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released
the Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing
the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in
semi-permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed using
16 bit word sizes. The size of the program memory is indicated in
the naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data address
space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-
bit RISC devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register space
may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program Execution
Atmel's AVRs have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR family
of processors were designed for the efficient execution of compiled
C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that are
different from each other. Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
I/O ports 0 to 31 have different addressing capabilities than I/O
ports 32 to 63. CLR affects flags, while SER does not, even though
they are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces
the same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually
requires a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator
circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but
with different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good. See
external links for sites relating to AVR development. [edit] Features
Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory
up to 256K In-System Programmable using ICSP, JTAG, or High
Voltage methods Optional Boot Code Section with Independent
Lock Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous
Serial Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller Support
USB Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous Data
Transfer Analog Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating
Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR
machine programming language

http://avr-asm.tripod.com/avr200b.html (2 of 2)1/20/2009 8:35:39 PM

16 BIT MULTIPLY (AVR 201)

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16 BIT MULTIPLY (AVR 201)

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; Last change: MWL 21 Jul 99 1:34 pm
ASM FORUM
ASM MATH ;**** A P P L I C A T I O N N O T E A V R 2 0 1
***************************
TUTORIAL #1
;*
TUTORIAL #2 ;* Title : 16bit multiply routines using
TUTORIAL #3 hardware multiplier
;* Version : V1.0
MATH 200 ;* Last updated : 5 Apr, 1999
MATH 200b ;* Target : ATmega83/161/163
;*
MATH 201 ;* Support email : [email protected]
MATH 202 ;*
;* DESCRIPTION
MATH 32X ;* This application note shows a number of examples of
MATH YX how to implement
;* 16bit multiplication using hardware multiplier.
DIV16 XX
Refer to each of the
DIV 24 24 ;* funtions headers for details. The functions
DIV 3216 included in this file
;* are :
FLOAT 128 ;*
SQRT16 ;* mul16x16_16 - Multiply of two 16bits numbers
with 16bits result.
MATH 202 ;* mul16x16_32 - Unsigned multiply of two 16bits
MATH 202 numbers with 32bits
;* result.
DEC ASCII
;* muls16x16_32 - Signed multiply of two 16bits
INT ASCII numbers with 32bits
;* result.
HX2ASC
;* mac16x16_32 - Signed multiply accumulate of two
AVG8 222 16bits numbers
FFT7 ;* with a 32bits result.
;* fmuls16x16_32 - Signed fractional multiply of two
COPY 102 16bits numbers
LPM 108 ;* with 32bits result.
;* fmac16x16_32 - Signed fractional multiply
EPROM 100 accumulate of two 16bits
SER EPROM ;* numbers with a 32bits result.
;*
DFLASH AT45
;
FLASH CARD ******************************************************************************
VFX SMIL
VFX MEM ;
SORT 220 ******************************************************************************
;*
CRC 236 ;* FUNCTION
XMODEM REC ;* mul16x16_16
;* DECRIPTION
UART 304 ;* Multiply of two 16bits numbers with 16bits result.
UART 305 ;* USAGE
;* r17:r16 = r23:r22 * r21:r20
UART 128
;* STATISTICS
UART BUFF ;* Cycles : 9 + ret
;* Words : 6 + ret
USB 232
;* Register usage: r0, r1 and r16 to r23 (8 registers)
AVR ISP ;* NOTE
ISP 2313 ;* Full orthogonality i.e. any register pair can be
used as long as
ISP 1200 ;* the result and the two operands does not share
AVR SPI register pairs.
;* The routine is non-destructive to the operands.
I2C 300 ;*
I2C 302 ;
******************************************************************************
I2C TWI26
I2C/TWI 128 mul16x16_16:
I2C/TWI AT8 mul r22, r20 ; al * bl
movw r17:r16, r1:r0
DALLAS-1W mul r23, r20 ; ah * bl
DALLAS CRC add r17, r0
mul r21, r22 ; bh * al
ETHNET 8019 add r17, r0
TEA ret
ADC 128
ADC 10B ;
******************************************************************************
ADC 400
;*
ADC 401 ;* FUNCTION
THERM 232 ;* mul16x16_32
;* DECRIPTION
IRD 410 ;* Unsigned multiply of two 16bits numbers with 32bits
LCD HD44 result.
;* USAGE
LCD 2313 ;* r19:r18:r17:r16 = r23:r22 * r21:r20
LCD44 2313 ;* STATISTICS
;* Cycles : 17 + ret
KBD 240 ;* Words : 13 + ret
MUX 242 ;* Register usage: r0 to r2 and r16 to r23 (11
registers)
KBD PS2
;* NOTE
KBD PC/128 ;* Full orthogonality i.e. any register pair can be
PS2 EMU used as long as
;* the 32bit result and the two operands does not
BOOT MG8 share register pairs.
BOOT DR8 ;* The routine is non-destructive to the operands.
;*
ALM CLK ;
CLOCK 8564 ******************************************************************************
90 DAYS
mul16x16_32:
DELAYS clr r2
mul r23, r21 ; ah * bh
CALL ID
movw r19:r18, r1:r0
DTMF 314 mul r22, r20 ; al * bl
PWM 6CH movw r17:r16, r1:r0
mul r23, r20 ; ah * bl
PWM 10K add r17, r0
ENCODE adc r18, r1
adc r19, r2
STH-11 mul r21, r22 ; bh * al
ATMEL CORP add r17, r0
adc r18, r1
AVR
adc r19, r2
BUTTERFLY ret
AVR BOOK

;
******************************************************************************
;*
;* FUNCTION
;* muls16x16_32
;* DECRIPTION
;* Signed multiply of two 16bits numbers with 32bits
result.
;* USAGE
;* r19:r18:r17:r16 = r23:r22 * r21:r20
;* STATISTICS
;* Cycles : 19 + ret
;* Words : 15 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;* NOTE
;* The routine is non-destructive to the operands.
;*
;
******************************************************************************

muls16x16_32:
clr r2
muls r23, r21 ; (signed)ah *
(signed)bh
movw r19:r18, r1:r0
mul r22, r20 ; al * bl
movw r17:r16, r1:r0
mulsu r23, r20 ; (signed)ah * bl
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
mulsu r21, r22 ; (signed)bh * al
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
ret

;
******************************************************************************
;*
;* FUNCTION
;* mac16x16_32
;* DECRIPTION
;* Signed multiply accumulate of two 16bits numbers
with
;* a 32bits result.
;* USAGE
;* r19:r18:r17:r16 += r23:r22 * r21:r20
;* STATISTICS
;* Cycles : 23 + ret
;* Words : 19 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;*
;
******************************************************************************

mac16x16_32:
clr r2

muls r23, r21 ; (signed)ah *

(signed)bh
add r18, r0
adc r19, r1

mul r22, r20 ; al * bl

add r16, r0
adc r17, r1
adc r18, r2
adc r19, r2

mulsu r23, r20 ; (signed)ah * bl

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

mulsu r21, r22 ; (signed)bh * al

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

mac16x16_32_method_B: ; uses two

temporary registers
; (r4,r5), but
reduces cycles/words
; by 1
clr r2

muls r23, r21 ; (signed)ah *

(signed)bh
movw r5:r4,r1:r0

mul r22, r20 ; al * bl

add r16, r0
adc r17, r1
adc r18, r4
adc r19, r5

mulsu r23, r20 ; (signed)ah * bl

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

mulsu r21, r22 ; (signed)bh * al

sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

;
******************************************************************************
;*
;* FUNCTION
;* fmuls16x16_32
;* DECRIPTION
;* Signed fractional multiply of two 16bits numbers
with 32bits result.
;* USAGE
;* r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1
;* STATISTICS
;* Cycles : 20 + ret
;* Words : 16 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;* NOTE
;* The routine is non-destructive to the operands.
;*
;
******************************************************************************

fmuls16x16_32:
clr r2
fmuls r23, r21 ; ( (signed)ah *
(signed)bh ) << 1
movw r19:r18, r1:r0
fmul r22, r20 ; ( al * bl ) << 1
adc r18, r2
movw r17:r16, r1:r0
fmulsu r23, r20 ; ( (signed)ah *
bl ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
fmulsu r21, r22 ; ( (signed)bh *
al ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
ret

;
******************************************************************************
;*
;* FUNCTION
;* fmac16x16_32
;* DECRIPTION
;* Signed fractional multiply accumulate of two 16bits
numbers with
;* a 32bits result.
;* USAGE
;* r19:r18:r17:r16 += (r23:r22 * r21:r20) << 1
;* STATISTICS
;* Cycles : 25 + ret
;* Words : 21 + ret
;* Register usage: r0 to r2 and r16 to r23 (11
registers)
;*
;
******************************************************************************

fmac16x16_32:
clr r2

fmuls r23, r21 ; ( (signed)ah *

(signed)bh ) << 1
add r18, r0
adc r19, r1

fmul r22, r20 ; ( al * bl ) << 1

adc r18, r2
adc r19, r2
add r16, r0
adc r17, r1
adc r18, r2
adc r19, r2

fmulsu r23, r20 ; ( (signed)ah *

bl ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

fmulsu r21, r22 ; ( (signed)bh *

al ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

fmac16x16_32_method_B: ; uses two

temporary registers
; (r4,r5), but
reduces cycles/words
; by 2
clr r2

fmuls r23, r21 ; ( (signed)ah *

(signed)bh ) << 1
movw r5:r4,r1:r0
fmul r22, r20 ; ( al * bl ) << 1
adc r4, r2

add r16, r0
adc r17, r1
adc r18, r4
adc r19, r5

fmulsu r23, r20 ; ( (signed)ah *

bl ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2
fmulsu r21, r22 ; ( (signed)bh *
al ) << 1
sbc r19, r2
add r17, r0
adc r18, r1
adc r19, r2

ret

; End of File

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
http://avr-asm.tripod.com/avr201.html (1 of 2)1/20/2009 8:36:15 PM
16 BIT MULTIPLY (AVR 201)

after cycling the power of the device. [edit] Program

Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr201.html (2 of 2)1/20/2009 8:36:15 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

16 BIT MATH (AVR 202)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 2
ASM FORUM ************************
ASM MATH ;*
;* Title: 16-bit Arithmetics
TUTORIAL #1
;* Version: 1.1
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxxxx (All AVR Devices)
;*
MATH 200 ;* Support E-mail: [email protected]
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This application note lists applications for the
MATH 202 following
;* Add/Subtract/Compare operations:
MATH 32X ;*
MATH YX ;* "add16" ADD 16+16
;* "adddi16" ADD 16+Immediate(16)
DIV16 XX
;* "sub16" SUB 16-16
DIV 24 24 ;* "subi16" SUB 16-Immediate(16)
DIV 3216 ;* "cp16" COMPARE 16/16
;* "cpi16" COMPARE 16/Immediate
FLOAT 128 ;* "neg16" NEGATION 16
SQRT16 ;*
;
MATH 202 ***************************************************************************
MATH 202
.cseg
DEC ASCII
ldi r16,0x12 ;Set up some registers to
INT ASCII show usage of
ldi r17,0x34 ;the subroutines below.
HX2ASC
ldi r18,0x56 ;All expected results are
AVG8 222 presented as
FFT7 ldi r19,0x78 ;comments

COPY 102
LPM 108 ;
***************************************************************************
EPROM 100 ;*
SER EPROM ;* "add16" - Adding 16-bit registers
;*
DFLASH AT45
;* This example adds the two pairs of register
FLASH CARD variables (add1l,add1h)
;* and (add2l,add2h) The result is placed in (add1l,
VFX SMIL
add1h).
VFX MEM ;*
SORT 220 ;* Number of words :2
;* Number of cycles :2
CRC 236 ;* Low registers used :None
XMODEM REC ;* High registers used :4
;*
UART 304 ;* Note: The sum and the addend share the same
UART 305 register. This causes the
;* addend to be overwritten by the sum.
UART 128
;*
UART BUFF ;
***************************************************************************
USB 232
AVR ISP ;**** Register Variables
ISP 2313 .def add1l = r16
.def add1h = r17
ISP 1200 .def add2l = r18
AVR SPI .def add2h = r19
I2C 300 ;***** Code
I2C 302 add16: add add1l, add2l ;Add low
bytes
I2C TWI26
adc add1h, add2h ;Add high bytes
I2C/TWI 128 with carry
I2C/TWI AT8 ;Expected result is 0xAC68

DALLAS-1W
DALLAS CRC
;
ETHNET 8019 ***************************************************************************
TEA ;*
;* "addi16" - Adding 16-bit register with immediate
ADC 128 ;*
ADC 10B ;* This example adds a register variable (addi1l,
addi1h) with an
ADC 400
;* immediate 16-bit number defined with .equ-
ADC 401 statement. The result is
THERM 232 ;* placed in (addi1l, addi1h).
;*
IRD 410 ;* Number of words :2
LCD HD44 ;* Number of cycles :2
;* Low registers used :None
LCD 2313 ;* High registers used :2
LCD44 2313 ;*
;* Note: The sum and the addend share the same
KBD 240 register. This causes the
MUX 242 ;* addend to be overwritten by the sum.
;*
KBD PS2
;
KBD PC/128 ***************************************************************************
PS2 EMU
;***** Register Variables
BOOT MG8 .def addi1l = r16
BOOT DR8 .def addi1h = r17

ALM CLK ;***** Immediate 16-bit number

CLOCK 8564 .equ addi2 = 0x1234
90 DAYS
;***** Code
DELAYS addi16: subi add1l, low(-addi2) ;Add low
byte ( x -(-y)) = x + y
CALL ID
sbci add1h, high(-addi2) ;Add high byte with
DTMF 314 carry
PWM 6CH ;Expected result is 0xBE9C

PWM 10K
ENCODE
;
STH-11 ***************************************************************************
ATMEL CORP ;*
;* "sub16" - Subtracting 16-bit registers
AVR
;*
BUTTERFLY ;* This example subtracts two pairs of register
AVR BOOK variables (sub1l,sub1h)
;* from (sub2l, sub2h) The result is stored in
registers sub1l, sub1h.
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :4
;*
;* Note: The result and "sub1" share the same
register. This causes "sub1"
;* to be overwritten by the result.
;*
;
***************************************************************************

;***** Register Variables

.def sub1l = r16
.def sub1h = r17
.def sub2l = r18
.def sub2h = r19

;***** Code
sub16: sub sub1l,sub2l ;Subtract
low bytes
sbc sub1h,sub2h ;Add high byte with
carry
;Expected result is 0x4646

;
***************************************************************************
;*
;* "subi16" - Subtracting immediate 16-bit number from
a 16-bit register
;*
;* This example subtracts the immediate 16-bit number
subi2 from the
;* 16-bit register (subi1l,subi1h) The result is
placed in registers
;* subi1l, subi1h.
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :2
;*
;* Note: The result and "subi1" share the same
register. This causes
;* "subi1" to be overwritten by the result.
;*
;
***************************************************************************

;***** Register Variables

.def subi1l = r16
.def subi1h = r17

;***** Immediate 16-bit number

.equ subi2 = 0x1234

;***** Code
subi16: subi subi1l,low(subi2) ;Subtract
low bytes
sbci subi1h,high(subi2) ;Subtract high byte
with carry
;Expected result is 0x3412

;
***************************************************************************
;*
;* "cp16" - Comparing two 16-bit numbers
;*
;* This example compares the register pairs (cp1l,cp1h)
with the register
;* pairs (cp2l,cp2h) If they are equal the zero flag
is set(one)
;* otherwise it is cleared(zero)
;*
;* Number of words :2
;* Number of cycles :2
;* Low registers used :None
;* High registers used :4
;*
;* Note: The contents of "cp1" will be overwritten.
;*
;
***************************************************************************

;***** Register Variables

.def cp1l = r16
.def cp1h = r17
.def cp2l = r18
.def cp2h = r19

;***** Code
cp16: cp cp1l,cp2l ;Compare low byte
cpc cp1h,cp2h ;Compare high byte with
carry from
;previous operation
ncp16:
;Expected result is Z=0

;
***************************************************************************
;*
;* "cpi16" - Comparing 16-bit register with 16-bit
immediate
;*
;* This example compares the register pairs (cpi1l,
cpi1h) with the value
;* cpi2. If they are equal the zero flag is set(one),
otherwise it is
;* cleared(zero). This is enabled by the AVR's zero
propagation. Carry is
;* also set if the result is negative. This means that
all conditional
;* branch instructions can be used after the
comparison.
;*
;* Number of words :3
;* Number of cycles :3
;* Low registers used :None
;* High registers used :3
;*
;*
;
***************************************************************************

;***** Register Variables

.def cp1l =r16
.def cp1h =r17
.def c_tmp=r18
.equ cp2 = 0x3412 ;Immediate to compare with

;***** Code
cpi16: cpi cp1l,low(cp2) ;Compare low byte
ldi c_tmp,high(cp2) ;
cpc cp1h,c_tmp ;Compare high byte

;Expected result is Z=1, C=

;
***************************************************************************
;*
;* "neg16" - Negating 16-bit register
;*
;* This example negates the register pair (ng1l,ng1h)
The result will
;* overwrite the register pair.
;*
;* Number of words :4
;* Number of cycles :4
;* Low registers used :None
;* High registers used :2
;*
;
***************************************************************************

;***** Register Variables

.def ng1l = r16
.def ng1h = r17

;***** Code
ng16:
com ng1l ;Invert low byte ;
Calculated by
com ng1h ;Invert high byte ;
incverting all
subi ng1l,low(-1) ;Add 0x0001, low byte ;
bits then adding
sbci ng1h,high(-1) ;Add high byte ;
one (0x0001)
;Expected result is 0xCBEE

;
***************************************************************************
;*
;* End of examples.
;*
;
***************************************************************************

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
http://avr-asm.tripod.com/avr202.html (1 of 2)1/20/2009 8:37:09 PM
16 BIT MATH (AVR 202)

the ATmega range) have additional instructions to make

arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/avr202.html (2 of 2)1/20/2009 8:37:09 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

32 BIT MATH (AVR XXX)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R ? ? ?
ASM FORUM ************************
ASM MATH ;*
;* Title: 32-bit Arithmetic Routines with
TUTORIAL #1
Macrolibrary
TUTORIAL #2 ;* Project: Math32
TUTORIAL #3 ;* Version: 2.3
;* Last updated: 2003.09.15
MATH 200 ;* Create Date: 1999.10.25
MATH 200b ;* Target MCU: AT90S8515 (as well as
others AVR uC)
MATH 201 ;* (C) ATMEL Corporation (mailto:
MATH 202 [email protected])
;* Originator: (C) 1999-2003 Andre Birua
MATH 32X
(mailto:[email protected])
MATH YX ;* This Application Note absolutely
free in use anybody
DIV16 XX
;* INTERPRETATION
DIV 24 24 ;* This package of assembler subprograms is developed
DIV 3216 for integer arithmetic
;* with tracing of sign bit in 32 bits calculations and
FLOAT 128 data reloads.
SQRT16 ;* It is based on microcontroller register file to the
maximum.
MATH 202 ;* In real users projects available abundant digit
MATH 202 capacity allows to avoid
;* overflow and reduces inaccuracy of rounding errors
DEC ASCII
in chain calculations.
INT ASCII ;* Included macro definitions will increase readability
of assembler source
HX2ASC
;* at bit by bit and multibyte data operations inside
AVG8 222 AVR software model
FFT7 ;*
;* DESCRIPTION
COPY 102 ;* This Application Note lists:
LPM 108 ;* i) Math32 subroutines for the following:
;* Add/Subtract/Multiply/Divide/Complement 32 bits
EPROM 100 operands,
SER EPROM ;* Binary 16 & 24 bits operand to/back BCD conversion,
;* Binary 32 bits operand to BCD conversion,
DFLASH AT45
;* Initialization of data memory on a pattern,
FLASH CARD ;* Load/Store group of registers from/to data space;
;* ii) macro definitions call mathematical and data
VFX SMIL
transfer subroutines;
VFX MEM ;* iii) useful general macroinstructions for the AVR 8-
SORT 220 Bit RISC family
;*
CRC 236 ;* "ADD32" Add without Carry Rd32 = Rd32 +
XMODEM REC Rr32
;* "SUB32" Subtract without Carry Rd32 = Rd32 -
UART 304 Rr32
UART 305 ;* "MUL32" Multiply Unsigned Rd64 = Rd32 *
Rr32
UART 128
;* "DIV32" Divide Unsigned Rd32 = Rd32 /
UART BUFF Rr32 (Rd64)
;* "COM32" One's Complement Rd32 =
USB 232
0xffffffff - Rd32
AVR ISP ;* "NEG32" Two's Complement Rd32 =
ISP 2313 0x00000000 - Rd32
;* "BCD2bin" BCD to Binary 16 Rd16 = Rd24|Rr24
ISP 1200 ;* "BCD3bin" BCD to Binary 24 Rd24 = Rd32|Rr32
AVR SPI ;* "Bin2BCD" Binary 16 to BCD Rd24 = Rd16|Rr16
;* "Bin3BCD" Binary 24 to BCD Rd32 = Rd24|Rr24
I2C 300 ;* "Bin4BCD" Binary 32 to BCD Rd40 = Rd32|
I2C 302 Rr32 || hwrd(Rr32)&Rd16
;* "MathMem" Init Data Memory (MA) = 0x00|0xff
I2C TWI26
;* "MathLoad" Load Registers Rd32|Rr32 = (MA)
I2C/TWI 128 ;* "MathSave" Store Registers (MA) = Rd32|Rd64
I2C/TWI AT8 ;*
;* Rd64: destination registers (8) in the register file
DALLAS-1W ;* Rd32: destination (and source) registers (4) in the
DALLAS CRC register file
;* Rr32: source registers (4) in the register file
ETHNET 8019 ;* (MA): address for access to variable in the internal
TEA memory (SRAM)
;* Note: Math32 use high registers, r0 and lower 512
ADC 128 bytes of data space,
ADC 10B ;* so Rd64=r20:r27, Rd32=r20:r23, Rd24=r20:r22,
Rd16=r20:r21,
ADC 400
;* Rd40=r20:r24, Rr32=r16:r19, Rr24=r16:r18, Rr16=r16:
ADC 401 r17, MA=0:511
THERM 232 ;*
;* Number of words & cycles (Min|Max) c o
IRD 410 m m e n t s
LCD HD44 ;* "ADD32" 6 4|5 Size of Add32sign
;* "SUB32" 16 6|15 Size of Sub32sign
LCD 2313 ;* "MUL32" 24 460|556 Size of Mul32b, based on
LCD44 2313 AVR200 16x16 unsigned
;* "DIV32" 28 528|688 Size of Div32b, based on
KBD 240 AVR200 16/16 unsigned
MUX 242 ;* "COM32" 5 4|4 Part of Sub32
;* "NEG32" 9 8|8 Part of Sub32
KBD PS2
;* "BCD2bin" 26 86|89 Equivalent of AVR204, but
KBD PC/128 smaller & quicker
PS2 EMU ;* "BCD3bin" 43 38|402 Different from BCD2bin
translation algorithm
BOOT MG8 ;* "Bin2BCD" 22 19|177 Equivalent of AVR204, but
BOOT DR8 smaller & much faster
;* "Bin3BCD" 21 36|366 In the form of preamble for
ALM CLK Bin2BCD
CLOCK 8564 ;* "Bin3BCD" 40 36|333 All-sufficient expansion of
Bin2BCD
90 DAYS
;* "Bin4BCD" 37 515|671 Based on AVR204 16-bit Bin
DELAYS to BCD conversion
;* "Bin4BCD" 48 874|878 All-sufficient transform
CALL ID
instead of pre-Bin4BCD
DTMF 314 ;* "MathMem" 10 7|645 Size of MathMemLimit, max
PWM 6CH cycle for 128 bytes
;* "MathLoad" 15 41|46 Size and max cycle for Rr32
PWM 10K load
ENCODE ;* "MathSave" 14 13|78 Size and max cycle for Rd64
save
STH-11 ;* In total: 350 words Usually +7 cycles: rcall &
ATMEL CORP ret
;*
AVR
;* All routines are Code Size` optimized
BUTTERFLY implementations and debugged with
AVR BOOK ;* macrocode for AVR macro assembler version 1.30 (Jan
27 1999 01:30:00) &
;* AVR32 macro assembler version 1.30 (Sep 8
1999 01:30:00).
;* However, AVR32 macro assembler version 1.54 (Nov
14 2001 14:05:48) &
;* AVR32 macro assembler version 1.56 (May 6
2002 14:54:01)
;* generate dummy warnings: Register already defined by
the .DEF directive
;* (command option for disable this kind of warning as
yet is absent...)
;* CheckIt with AVR Studio !
;* NOTE
;* ` Bin4BCD transformations has partial loop
optimization for speed-up
;* While using Math32, it is important to consider the
allocation of the
;* microcontroller resources available for the program.
It is required:
;* - to use r0,r16..r31 with Math32;
;* - to allocate variables used in calculation in the
bottom of the memory;
;* - to use T flag as a sign bit (input, output and
temporary),
;* if you need to operate negative numbers or up-down
overflow error
;*
;* VERSION
;* 1.0 Original version (in use starting with
1999.12.22)
;* 1.1 Fixed precedence bugs if macroparameter is an
assembler expression
;* 1.2 Modify CBF & SBF & IBF macrocalls
;* 1.3 Full modification mathematical and data transfer
macronotation
;* 1.4 Optimaze for speed and code size Mul32 & Div32 &
BCD2bin & Bin2BCD
;* 2.0 Version for publication (added description, note
and demo sections)
;* 2.1 Updated Bin2BCD, added Bin4BCD conversion & XCH
macrocall
;* 2.2 Added functionally closed modifications of
Bin3&4BCD translation
;* 2.3 Added BCD3bin conversion, normalize the comment
of Bin3&4BCD
;*
;* DEMO
;* section below is a sample of macrocalls and not an
ordinary Math32 usage
;*
;
***************************************************************************

.include "8515def.inc"
.listmac ;split Toggle_mode at AVR
Studio
.cseg ;press Step_Over
etceteras of
rjmp Demo ;trace Registers and
Memory

;Words *** general macrocode for the AVR 8-Bit RISC

microcontroller ***
;2 "CLF" CLear bit Flag in register via T flag
;2 "SEF" SEt bit Flag in register via T flag
;2 "CBF" Clear Bit(s) Flag(s) in register via
temporary register
;2 "SBF" Set Bit(s) Flag(s) in register via temporary
register
;2 "IBF" Invert Bit(s) Flag(s) in register via
temporary register
;2 "OUTI" OUT port Immediate via temporary register
;4 "OUTIW" OUT port Immediate Word via temporary
register
;2 "OUTW" OUT port Word from register pair
;2 "INW" IN port Word to register pair
;3 "XCH" data eXCHange between a two registers as
exclusive OR only
;2 "MVW" MoVe register pair as Word
;2 "MVI" MoVe temporary register loaded Immediate
;4 "MOVS" MOVe direct in data Space via temporary
register
;8 "MOVSW" MOVe direct in data Space Word via temporary
register
;3 "STSI" STore direct to data Space Immediate via
temporary register
;4 "STSIW" STore direct to data Space Immediate Word
via temporary register
;4 "LDSW" LoaD direct from data Space Word to register
pair
;4 "STSW" STore direct to data Space Word from
register pair
;2 "LDIW" LoaD Immediate Word to register pair
;2 "LDDW" LoaD indirect with Displacement from data
space Word to register pair
;2 "STDW" STore indirect with Displacement to data
space Word from register pair
;2 "PUSHW" PUSH register pair (Word) on stack
;2 "POPW" POP register pair (Word) from stack

.macro CLF ; Register,Bit#

clt
bld @0,@1
.endmacro
.macro SEF ; Register,Bit#
set
bld @0,@1
.endmacro
.macro CBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][,
Bit#][,Bit#][,Bit#][,Bit#][,Bit#]
ldi @1,~(exp2(@2)|(-@3-1<0)*exp2(@3-0)|
(-@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-
1<0)*exp2(@8-0)|(-@9-1<0)*exp2(@9-0))
and @0,@1
.endmacro
.macro SBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][,
Bit#][,Bit#][,Bit#][,Bit#][,Bit#]
ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(-
@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0)
*exp2(@8-0)|(-@9-1<0)*exp2(@9-0)
or @0,@1
.endmacro
.macro IBF ; Register,RegisterH,Bit#[,Bit#][,Bit#][,
Bit#][,Bit#][,Bit#][,Bit#][,Bit#]
ldi @1,exp2(@2)|(-@3-1<0)*exp2(@3-0)|(-
@4-1<0)*exp2(@4-0)|(-@5-1<0)*exp2(@5-0)|(-@6-1<0)*exp2(@6-0)|(-@7-1<0)*exp2(@7-0)|(-@8-1<0)
*exp2(@8-0)|(-@9-1<0)*exp2(@9-0)
eor @0,@1
.endmacro
.macro OUTI ; Port,RegisterH,ConstantB
ldi @1,@2
out @0,@1
.endmacro
.macro OUTIW ; PortHL,RegisterH,ConstantW
ldi @1,high(@2)
out @0h,@1
ldi @1,low(@2)
out @0l,@1
.endmacro
.macro OUTW ; PortHL,RegisterHL
out @0h,@1h
out @0l,@1l
.endmacro
.macro INW ; RegisterHL,PortHL
in @0l,@1l
in @0h,@1h
.endmacro
.macro XCH ; Register,Register
eor @0,@1
eor @1,@0
eor @0,@1
.endmacro
.macro MVW ; RegisterHL,RegisterHL
mov @0h,@1h
mov @0l,@1l
.endmacro
.macro MVI ; RegisterL,RegisterH,ConstantB
ldi @1,@2
mov @0,@1
.endmacro
.macro MOVS ; Address,Register,Address
lds @1,@2
sts @0,@1
.endmacro
.macro MOVSW ; Address,Register,Address
lds @1,@2
sts @0,@1
lds @1,(@2)+1
sts (@0)+1,@1
.endmacro
.macro STSI ; Address,RegisterH,ConstantB
ldi @1,@2
sts @0,@1
.endmacro
.macro STSIW ; Address,RegisterH,ConstantW
ldi @1,low(@2)
sts @0,@1
ldi @1,high(@2)
sts (@0)+1,@1
.endmacro
.macro LDSW ; RegisterHL,Address
lds @0l,@1
lds @0h,(@1)+1
.endmacro
.macro STSW ; Address,RegisterHL
sts (@0)+1,@1h
sts @0,@1l
.endmacro
.macro LDIW ; RegisterHL,ConstantW
ldi @0l,low(@1)
ldi @0h,high(@1)
.endmacro
.macro LDDW ; RegisterHL,RegisterPair+Displacement
ldd @0l,@1
ldd @0h,@1+1
.endmacro
.macro STDW ; RegisterPair+Displacement,RegisterHL
std @0+1,@1h
std @0,@1l
.endmacro
.macro PUSHW ; RegisterHL
push @0l
push @0h
.endmacro
.macro POPW ; RegisterHL
pop @0h
pop @0l
.endmacro

;Words ***** mathematical and data transfer macrocalls

*****
;3 "INITMEM" INITialize math data space (MEMory
variable) in 0|0xff
;3 "MATHR16" load from MATH data space to Registers r16,
r17,r18,r19
;3 "MATHR20" load from MATH data space to Registers r20,
r21,r22,r23
;3 "OPERAND" load registers as mathematical OPERAND
from math data space
;3 "RESULT2" store registers as mathematical RESULT to
math data space (call)
;3 "RESULT3" store registers as mathematical RESULT to
math data space (jump)
;1 "CNST16B" load immediate CoNSTant to r16 as Byte
;2 "CNST16W" load immediate CoNSTant to r16,r17 as Word
;3 "CNST16T" load immediate CoNSTant to r16,r17,r18 as
Three bytes
;4 "CONST16" load immediate CONSTant to r16,r17,r18,r19
as double word
;4 "CONST20" load immediate CONSTant to r20,r21,r22,r23
as double word

.macro INITMEM ; Address[,Counter(1-128)[,0|1|limit]]

ldi ZL,@0
ldi ZH,@1-1<<1|high(@0)&1
rcall MathMem@2
.endmacro
.macro MATHR16 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall R16MathLoad
.endmacro
.macro MATHR20 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall R20MathLoad
.endmacro
.macro OPERAND ; Address[,[Bitmap][,r16|r20]]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall @2MathLoad
.endmacro
.macro RESULT2 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rcall MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f)
.endmacro
.macro RESULT3 ; Address[,Bitmap]
ldi ZL,@0
ldi ZH,((-@1-1>0)*ObXXXX|@1-0)<<1|high
(@0)&1
rjmp MathSave-2*(((-@1-1>0)*ObXXXX|@1-0)
>0x7f)
.endmacro
.macro CNST16B ; ConstantB (8 bits)
ldi r16,byte1(@0)
.endmacro
.macro CNST16W ; ConstantW (16 bits)
ldi r16,byte1(@0)
ldi r17,byte2(@0)
.endmacro
.macro CNST16T ; ConstantT (24 bits)
ldi r16,byte1(@0)
ldi r17,byte2(@0)
ldi r18,byte3(@0)
.endmacro
.macro CONST16 ; ConstantD (32 bits)
ldi r16,byte1(@0)
ldi r17,byte2(@0)
ldi r18,byte3(@0)
ldi r19,byte4(@0)
.endmacro
.macro CONST20 ; ConstantD (32 bits)
ldi r20,byte1(@0)
ldi r21,byte2(@0)
ldi r22,byte3(@0)
ldi r23,byte4(@0)
.endmacro

;
***************************************************************************
;# # # # # # # # # Assign Math32 Symbol and
Notation # # # # # # # # #
;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;*
;* Add32[sign], Sub32[sign], Mul32[b|w|t], Div32[b|w|
t] :
;* operand1
operand2 result
;* r20r21r22r23 +|-|*|/ r16r17r18r19 =
r20r21r22r23[r24r25r26r27]
;*
;* Com32, Neg32 : Bin2BCD20,
BCD2bin20 :
;* operand result
operand result
;* r20r21r22r23 >>> r20r21r22r23 r20r21[r22]
>>> r20r21[r22]
;*
;* BCD3bin, Bin3BCD, Bin4BCD : Bin2BCD16,
BCD2bin16 :
;* operand result
operand result
;* r16...r23 >>> r20r21r22[r23[r24]] r16r17
[r18] >>> r20r21[r22]
;*
;
***************************************************************************
.set ObXXXX=0b1111 ;default load & store memory
variable bitmap upon
;little-endian format of numbers, i.e. abs.address(LSB)
< abs.address(MSB)

;
***************************************************************************
;*
;* Initialize Memory in Math Data Space
;*
;* First 512+127 bytes of data space can be initialize
in 0 or 0xff
;* Limit: if Flag T==1 then EachMemoryByte=0 else
EachMemoryByte=0xff
;*
;
***************************************************************************
.def MathPattern=r28 ;YL
.def MathCounter=r29 ;YH

MathMemLimit: brts MathMem0x0 ;

MathMem0x1: ser MathPattern ;
cpse ZH,ZH ;skip next
instruction
MathMem0x0: clr MathPattern ;
mov MathCounter,ZH ;copy counter
cbr ZH,0xfe ;Z points to math
data space
NextMemByte: st Z+,MathPattern ;
subi MathCounter,2 ;
brcc NextMemByte ;while
MathCounter>=0
ret ;
.equ MathMem=MathMem0x0 ;default initialize memory call

;
***************************************************************************
;*
;* Registers Load from Math Data Space
;*
;* Load: r16r17r18r19r20r21r22r23 from first 512+3
bytes of data space
;* operand2 operand1 (max starting
address: 0x1ff)
;*
;
***************************************************************************
.def MathBmp=r26 ;only XL,XH from high registers
.def MathTmp=r27 ;do not keep useful data or not
used below

R16MathLoad: ldi YL,16 ;Y points

to operand2 LSB
cpse ZH,ZH ;skip next
instruction
R20MathLoad: ldi YL,20 ;Y points
to operand1 LSB
clr YH ;
mov MathBmp,ZH ;copy bitmap
cbr ZH,0xfe ;Z points to math
data space
sbr MathBmp,0xe0 ;it is possible in
each macrocall
MathLoadNext: lsr MathBmp ;
clr MathTmp ;load 0 to temp
register
sbrc MathBmp,0 ;if bit 0 bitmap
not clear
ld MathTmp,Z+ ; load operand
from memory to temp
st Y+,MathTmp ;store temp to math
register
sbrc MathBmp,4 ;
rjmp MathLoadNext ;while bit 4 of
bitmap not clear
ret ;
.equ MathLoad=R20MathLoad ;default registers load call

;
***************************************************************************
;*
;* Registers Save to Math Data Space
;*
;* Save: r20r21r22r23r24r25r26r27 to first 512
+7 bytes of data space
;* result (remainder) (max starting
address: 0x1ff)
;*
;
***************************************************************************
.def MathBmp=r0 ;all high registers keep useful
data or used below

sec ;
cpse ZH,ZH ;skip next
instruction
R20MathSave: clc ;
mov MathBmp,ZH ;copy bitmap
cbr ZH,0xfe ;Z points to math
data space
ror MathBmp ;now bitmap have
all 8 bits
ldi YL,20 ;Y points to result
LSB
MathSaveNext: clr YH ;
ld YH,Y+ ;in order to not
use other registers
sbrc MathBmp,0 ;if bit 0 bitmap
not clear
st Z+,YH ; store
result byte to memory
lsr MathBmp ;
brne MathSaveNext ;while not empty
bitmap
ret ;
.equ MathSave=R20MathSave ;default registers save call

;
***************************************************************************
;*
;* Add32 == 32+32 Bit Unsigned Addition
;*
;* add1L::add1H + add2L::add2H = add1L::add1H
;* item item sum
;* r20r21r22r23 + r16r17r18r19 = r20r21r22r23
;*
;
***************************************************************************
.def add20 = r16 ; item 2 byte 0 (LSB)
.def add21 = r17 ; item 2 byte 1
.def add22 = r18 ; item 2 byte 2
.def add23 = r19 ; item 2 byte 3 (MSB)
.def add10 = r20 ; item 1 byte 0 (LSB)
.def add11 = r21 ; item 1 byte 1
.def add12 = r22 ; item 1 byte 2
.def add13 = r23 ; item 1 byte 3 (MSB)

Add32sign: brts Sub32sign ;

Add32: add add10,add20 ;Add low
bytes
adc add11,add21 ;Add higher bytes
with carry
adc add12,add22 ;
adc add13,add23 ;
ret ;

;
***************************************************************************
;*
;* Sub32 == 32-32 Bit Unsigned Subtraction
;*
;* sub1L::sub1H - sub2L::sub2H = sub1L::sub1H
;* minuend subtrahend difference
;* r20r21r22r23 - r16r17r18r19 = r20r21r22r23
;*
;
***************************************************************************
.def sub20 = r16 ; subtrahend byte 0 (LSB)
.def sub21 = r17 ; subtrahend byte 1
.def sub22 = r18 ; subtrahend byte 2
.def sub23 = r19 ; subtrahend byte 3 (MSB)
.def sub10 = r20 ; minuend byte 0 (LSB)
.def sub11 = r21 ; minuend byte 1
.def sub12 = r22 ; minuend byte 2
.def sub13 = r23 ; minuend byte 3 (MSB)

Sub32sign: clt ;sign +

Sub32: sub sub10,sub20 ;Subtract
low bytes
sbc sub11,sub21 ;Subtract higher
bytes with carry
sbc sub12,sub22 ;
sbc sub13,sub23 ;
brcc Return32u ;return clear carry
if result>=0
set ;sign -
Neg32: subi sub10,1 ;if result<0
sbci sub11,0 ; neg result
sbci sub12,0 ;
sbci sub13,0 ; (dec result)
Com32: com sub10 ; &
com sub11 ; (com result)
com sub12 ;
com sub13 ; return set
carry after com
Return32u: ret ;

;
***************************************************************************
;*
;* Mul32 == 32x32 Bit Unsigned Multiplication
;*
;* mp32uL::mp32uH x mc32uL::mc32uH = m32uL::m32uH
;* multiplier multiplicand result
;* r20r21r22r23 x r16r17r18r19 =
r20r21r22r23r24r25r26r27
;*
;
***************************************************************************
.def mc32u0 =r16 ; multiplicand byte 0 (LSB)
.def mc32u1 =r17 ; multiplicand byte 1
.def mc32u2 =r18 ; multiplicand byte 2
.def mc32u3 =r19 ; multiplicand byte 3 (MSB)
.def mp32u0 =r20 ; multiplier byte 0 (LSB)
.def mp32u1 =r21 ; multiplier byte 1
.def mp32u2 =r22 ; multiplier byte 2
.def mp32u3 =r23 ; multiplier byte 3 (MSB)
.def m32u0 =r20 ; result byte 0 (LSB)
.def m32u1 =r21 ; result byte 1
.def m32u2 =r22 ; result byte 2
.def m32u3 =r23 ; result byte 3
.def m32u4 =r24 ; result byte 4
.def m32u5 =r25 ; result byte 5
.def m32u6 =r26 ; result byte 6
.def m32u7 =r27 ; result byte 7 (MSB)
.def mcnt32u =r28 ; loop counter

Mul32b: clr mc32u1 ;multiplicand is

one byte
Mul32w: clr mc32u2 ;
two bytes
Mul32t: clr mc32u3 ;
three bytes
Mul32: clr m32u7 ;clear 4
highest bytes of result
clr m32u6 ;
clr m32u5 ;
sub m32u4,m32u4 ;and carry
ldi mcnt32u,33 ;init loop counter
m32u_loop: ror m32u3 ;rotate result and
multiplier
ror m32u2 ;
ror m32u1 ;
ror m32u0 ;
dec mcnt32u ;decrement loop
counter
breq Return32u ;if counter zero
return
brcc m32u_skip ;if bit 0 of
multiplier set
add m32u4,mc32u0 ; add
multiplicand to result
adc m32u5,mc32u1 ;
adc m32u6,mc32u2 ;
adc m32u7,mc32u3 ;
m32u_skip: ror m32u7 ;shift right result
byte 7
ror m32u6 ;rotate right result
ror m32u5 ;
ror m32u4 ;
rjmp m32u_loop ;

;
***************************************************************************
;*
;* Div32 == 32/32 Bit Unsigned Division
;*
;* dd32uL::dd32uH / dv32uL::dv32uH = dres32uL::dres32uH
(drem32uL::drem32uH)
;* dividend divisor
result remainder
;* r20r21r22r23 / r16r17r18r19 =
r20r21r22r23 r24r25r26r27
;*
;
***************************************************************************
.def dv32u0 =r16 ; divisor byte 0 (LSB)
.def dv32u1 =r17 ; divisor byte 1
.def dv32u2 =r18 ; divisor byte 2
.def dv32u3 =r19 ; divisor byte 3 (MSB)
.def dres32u0 =r20 ; result byte 0 (LSB)
.def dres32u1 =r21 ; result byte 1
.def dres32u2 =r22 ; result byte 2
.def dres32u3 =r23 ; result byte 3 (MSB)
.def dd32u0 =r20 ; dividend byte 0 (LSB)
.def dd32u1 =r21 ; dividend byte 1
.def dd32u2 =r22 ; dividend byte 2
.def dd32u3 =r23 ; dividend byte 3 (MSB)
.def drem32u0 =r24 ; remainder byte 0 (LSB)
.def drem32u1 =r25 ; remainder byte 1
.def drem32u2 =r26 ; remainder byte 2
.def drem32u3 =r27 ; remainder byte 3 (MSB)
.def dcnt32u =r28 ; loop counter

Div32b: clr dv32u1 ;divisor is one byte

Div32w: clr dv32u2 ; two
bytes
Div32t: clr dv32u3 ; three
bytes
Div32: clr drem32u0 ;clear 4
lower remainde byte
clr drem32u1 ;
clr drem32u2 ;
sub drem32u3,drem32u3;and carry
ldi dcnt32u,33 ;init loop counter
d32u_loop: rol dd32u0 ;shift left dividend
rol dd32u1 ;
rol dd32u2 ;
rol dd32u3 ;
dec dcnt32u ;decrement loop
counter
breq Com32 ;if counter zero
invert result
rol drem32u0 ;shift dividend
into remainder
rol drem32u1 ;
rol drem32u2 ;
rol drem32u3 ;
sub drem32u0,dv32u0 ;remainder =
remainder - divisor
sbc drem32u1,dv32u1 ;
sbc drem32u2,dv32u2 ;
sbc drem32u3,dv32u3 ;
brcc d32u_loop ;clear carry to be
shifted into res
add drem32u0,dv32u0 ;if result negative
adc drem32u1,dv32u1 ; restore
remainder
adc drem32u2,dv32u2 ;
adc drem32u3,dv32u3 ;
rjmp d32u_loop ; set carry to be
shifted into res

;
***************************************************************************
;*
;* BCD2bin == BCD to 16-Bit Binary Conversion
;*
;* fBCD0:fBCD1:fBCD2 >>> tbinL:tbinH
;* dec hex
;* r16r17r18 >>> r20r21
;*
;
***************************************************************************
.def fBCD0 =r16 ; BCD value digits 0 and 1
.def fBCD1 =r17 ; BCD value digits 2 and 3
.def fBCD2 =r18 ; BCD value digit 4 (MSD is
lowermost nibble)
.def mp10L =r20 : Low byte of number to be
multiplied by 10
.def mp10H =r21 ; High byte of number to be
multiplied by 10
.def tbinL =r20 ; Low byte of binary result
(same as mp10L)
.def tbinH =r21 ; High byte of binary
result (same as mp10H)
.def copyL =r22 ; temporary register
.def copyH =r23 ; temporary register

BCD2bin20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
BCD2bin16: cbr fBCD2,0xf0 ;mask away upper
nibble of fBCD2
mov mp10L,fBCD2 ;mp10L:mp10H = MSD
clr mp10H ;
clr fBCD2 ;for adci mp10H,0
below
rcall mul10bcd ;fBCDX = fBCD1
mov fBCD1,fBCD0 ;fBCDX = fBCD0
mul10bcd: ;mp10L:mp10H=10(10*mp10L:mp10H+highnibble
(fBCDX))+lownibble(fBCDX)
rcall mul10add ;10*mp10L:mp10H
+highnibble(fBCDX)
mul10add: ;mp10L:mp10H = 10*mp10L:mp10H+lownibble(fBCDX)
lsl mp10L ;multiply original
by 2
rol mp10H ;
mov copyL,mp10L ;make copy (x2)
mov copyH,mp10H ;
lsl copyL ;multiply copy by 2
(x4)
rol copyH ;
lsl copyL ;multiply copy by 2
(x8)
rol copyH ;
add mp10L,copyL ;add copy to
original (x10)
adc mp10H,copyH ;
swap fBCD1 ;fBCDX
upper<=>lower nibble
mov copyL,fBCD1 ;
andi copyL,0x0f ;mask away upper
nibble
add mp10L,copyL ;add lower nibble
adc mp10H,fBCD2 ;high byte of
result + carry
ret ;
.equ BCD2bin=BCD2bin20 ;default registers BCD to BIN
call

;
***************************************************************************
;*
;* BCD3bin == BCD to 24-Bit Binary Conversion
;*
;* fBCD0:fBCD1:fBCD2:fBCD3 >>> tbin0:tbin1:tbin2
;* dec hex
;* r16r17r18r19 >>> r20r21r22
;*
;
***************************************************************************
.def fBCD0 =r16 ; BCD value digits 0 and 1
.def fBCD1 =r17 ; BCD value digits 2 and 3
.def fBCD2 =r18 ; BCD value digits 4 and 5
.def fBCD3 =r19 ; BCD value digits 6 and 7
(MSD is 0|1)
.def tbin0 =r20 ; binary value byte 0 (LSB)
.def tbin1 =r21 ; binary value byte 1
.def tbin2 =r22 ; binary value byte 2 (MSB)

BCD3bin20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
mov r19,r23 ;
BCD3bin16: ldi tbin0,0xca ;digit-to-
digit presetting
ldi tbin1,0x1b ;-
1111110=0xef0bba
ldi
tbin2,0xff ;0xff1bca=0xef0bba-0xefeff0
sbrc fBCD3,4 ; delete
decimal correction
subi fBCD3,6 ; if
NUMBER<10000000 always
bcdbin_106: subi tbin0,byte1(-1000*1000) ;addit
tbin,10^6
sbci tbin1,byte2(-1000*1000) ;
sbci tbin2,byte3(-1000*1000) ;
subi fBCD3,0x01 ;
brcc bcdbin_106 ;
bcdbin_105: subi tbin0,byte1(-100*1000) ;addit
tbin,10^5
sbci tbin1,byte2(-100*1000) ;
sbci tbin2,byte3(-100*1000) ;
subi fBCD2,0x10 ;
brcc bcdbin_105 ;
bcdbin_104: subi tbin0,byte1(-10*1000) ;addit
tbin,10^4
sbci tbin1,byte2(-10*1000) ;
sbci tbin2,byte3(-10*1000) ;
subi fBCD2,0x01 ;
brhc bcdbin_104 ;
bcdbin_103: subi tbin0,byte1(-1000) ;addit
tbin,10^3
sbci tbin1,byte2(-1000) ;
sbci tbin2,byte3(-1000) ;
subi fBCD1,0x10 ;
brcc bcdbin_103 ;
bcdbin_102: subi tbin0,byte1(-100) ;addit
tbin,10^2
sbci tbin1,byte2(-100) ;
sbci tbin2,byte3(-100) ;
subi fBCD1,0x01 ;
brhc bcdbin_102 ;
bcdbin_101: subi tbin0,byte1(-10) ;addit
tbin,10^1
sbci tbin1,byte2(-10) ;
sbci tbin2,byte3(-10) ;
subi fBCD0,0x10 ;
brcc bcdbin_101 ;addit
tbin,0xefeff0+LSD
add tbin0,fBCD0 ; addend of
tbin1 & tbin2 is
adc tbin1,fBCD1 ;
arbitrarily chosen const
adc tbin2,fBCD2 ; (pre take
off from tbin)
ret

http://avr-asm.tripod.com/math32x.html (1 of 3)1/20/2009 8:37:55 PM

16 BIT MATH (AVR 202)

.equ BCD3bin=BCD3bin20 ;default registers BCD to BIN

call

;
***************************************************************************
;*
;* Bin2BCD == 16-bit Binary to BCD conversion
;*
;* fbinL:fbinH >>> tBCD0:tBCD1:tBCD2
;* hex dec
;* r16r17 >>> r20r21r22
;*
;
***************************************************************************
.def fbinL =r16 ; binary value Low byte
.def fbinH =r17 ; binary value High byte
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digit 4 (MSD is
lowermost nibble)

Bin2BCD20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
Bin2BCD16: ldi tBCD2,0xff ;initialize digit 4
binbcd_4: inc tBCD2 ;
subi fbinL,low(10000);subiw fbin,10000
sbci fbinH,high(10000)
brcc binbcd_4 ;
ldi tBCD1,0x9f ;initialize digits
3 and 2
binbcd_3: subi tBCD1,0x10 ;
subi fbinL,low(-1000);addiw fbin,1000
sbci fbinH,high(-1000)
brcs binbcd_3 ;
binbcd_2: inc tBCD1 ;
subi fbinL,low(100) ;subiw fbin,100
sbci fbinH,high(100) ;
brcc binbcd_2 ;
ldi tBCD0,0xa0 ;initialize digits
1 and 0
binbcd_1: subi tBCD0,0x10 ;
subi fbinL,-10 ;addi fbin,10
brcs binbcd_1 ;
add tBCD0,fbinL ;LSD
binbcd_ret: ret ;
.equ Bin2BCD=Bin2BCD20 ;default registers BIN to BCD
call

;
***************************************************************************
;*
;* Bin4BCD == 32-bit Binary to BCD conversion
[ together with Bin2BCD ]
;*
;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2:
tBCD3:tBCD4
;* hex dec
;* r18r19r20r21 >>> r20r21r22r23r24
;*
;
***************************************************************************
.def fbin0 =r18 ; binary value byte 0 (LSB)
.def fbin1 =r19 ; binary value byte 1
.def fbin2 =r20 ; binary value byte 2
.def fbin3 =r21 ; binary value byte 3 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
(same as fbin2)
.def tBCD1 =r21 ; BCD value digits 2 and 3
(same as fbin3)
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
.def tBCD4 =r24 ; BCD value digits 8 and 9
(MSD)

Bin4BCD: rcall Bin2BCD20 ;

clr tBCD3 ;initial highest
bytes of result
ldi tBCD4,0xfe ;
binbcd_loop: subi tBCD0,-0x33 ;add 0x33
to digits 1 and 0
sbrs tBCD0,3 ;if bit 3 clear
subi tBCD0,0x03 ; sub 3
sbrs tBCD0,7 ;if bit 7 clear
subi tBCD0,0x30 ; sub $30
subi tBCD1,-0x33 ;add 0x33 to digits
3 and 2
sbrs tBCD1,3 ;if bit 3 clear
subi tBCD1,0x03 ; sub 3
sbrs tBCD1,7 ;if bit 7 clear
subi tBCD1,0x30 ; sub $30
subi tBCD2,-0x33 ;add 0x33 to digits
5 and 4
sbrs tBCD2,3 ;if bit 3 clear
subi tBCD2,0x03 ; sub 3
sbrs tBCD2,7 ;if bit 7 clear
subi tBCD2,0x30 ; sub $30
lsl fbin0 ;
rol fbin1 ;shift lower word
rol tBCD0 ;through all bytes
rol tBCD1 ;
rol tBCD2 ;
rol tBCD3 ;
rol tBCD4 ;
brmi binbcd_loop ;7 shifts w/o
correction of MSD
rol fbinH ;since Bin2BCD
fbinH = 0xff
brcc binbcd_ret ; so as to do
16_lsl in total
subi tBCD3,-0x33 ;add 0x33 to digits
7 and 6
sbrs tBCD3,3 ;if bit 3 clear
subi tBCD3,0x03 ; sub 3
sbrs tBCD3,7 ;if bit 7 clear
subi tBCD3,0x30 ; sub $30
subi tBCD4,-0x03 ;add 0x03 to digit
8 only
sbrs tBCD4,3 ;if bit 3 clear
subi tBCD4,0x03 ; sub 3
rjmp binbcd_loop ;

;
***************************************************************************
;*
;* Bin4BCD == 32-bit Binary to BCD conversion
;*
;* fbin0:fbin1:fbin2:fbin3 >>> tBCD0:tBCD1:tBCD2:
tBCD3:tBCD4
;* hex dec
;* r16r17r18r19 >>> r20r21r22r23r24
;*
;
***************************************************************************
.def fbin0 =r16 ; binary value byte 0 (LSB)
.def fbin1 =r17 ; binary value byte 1
.def fbin2 =r18 ; binary value byte 2
.def fbin3 =r19 ; binary value byte 3 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
.def tBCD4 =r24 ; BCD value digits 8 and 9
(MSD)

Bin4BCD20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
mov r19,r23 ;
Bin4BCD16: clr tBCD0 ;initial result (5
bytes)
clr tBCD1 ; & shift
clr tBCD2 ; loop
ldi tBCD3,0xfe ;
counter
ldi
tBCD4,0xff ; too
rjmp binbcd_jump ;for speed-up and
skip of MSD corr
binbcd_876: subi tBCD4,-0x03 ;add 0x03 to digit
8 only
sbrs tBCD4,3 ;if bit 3 clear
subi tBCD4,0x03 ; sub 3
subi tBCD3,-0x33 ;add 0x33 to digits
7 and 6
sbrs tBCD3,3 ;if bit 3 clear
subi tBCD3,0x03 ; sub 3
sbrs tBCD3,7 ;if bit 7 clear
subi tBCD3,0x30 ; sub $30
binbcd_54: subi tBCD2,-0x33 ;add 0x33 to digits
5 and 4
sbrs tBCD2,3 ;if bit 3 clear
subi tBCD2,0x03 ; sub 3
sbrs tBCD2,7 ;if bit 7 clear
subi tBCD2,0x30 ; sub $30
binbcd_3210: subi tBCD1,-0x33 ;add 0x33
to digits 3 and 2
sbrs tBCD1,3 ;if bit 3 clear
subi tBCD1,0x03 ; sub 3
sbrs tBCD1,7 ;if bit 7 clear
subi tBCD1,0x30 ; sub $30
subi tBCD0,-0x33 ;add 0x33 to digits
1 and 0
sbrs tBCD0,3 ;if bit 3 clear
subi tBCD0,0x03 ; sub 3
sbrs tBCD0,7 ;if bit 7 clear
subi tBCD0,0x30 ; sub $30
binbcd_jump: lsl fbin0 ;
rol fbin1 ;
rol fbin2 ;
rol fbin3 ;shift input value
rol tBCD0 ;through all bytes
rol tBCD1 ;
rol tBCD2 ;
rol tBCD3 ;
rol tBCD4 ;
brcs binbcd_3210 ;16_lsl w/o
correction of dig_87654
inc fbin0 ;
brpl binbcd_54 ;+7_lsl w/o
correction of dig_876
sbrs fbin2,0 ;
rjmp binbcd_876 ;32_lsl in total
(fbin = 0x1ffff)
ret ;

;
***************************************************************************
;*
;* Bin3BCD == 24-bit Binary to BCD conversion
[ together with Bin2BCD ]
;*
;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3
;* hex dec
;* r16r17r18 >>> r20r21r22r23
;*
;
***************************************************************************
.def fbin0 =r16 ; binary value byte 0 (LSB)
.def fbin1 =r17 ; binary value byte 1
.def fbin2 =r18 ; binary value byte 2 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
(MSD)

Bin3BCD: ldi tBCD3,0xff ;initialize

digits 7 and 6
binbcd_7: inc tBCD3 ;
subi fbin0,byte1(10000*100) ;subit
fbin,1000000
sbci fbin1,byte2(10000*100) ;
sbci fbin2,byte3(10000*100) ;
brcc binbcd_7 ;
subi tBCD3,-6 ; delete
decimal correction
sbrs tBCD3,4 ; if
NUMBER<10000000 always
subi tBCD3,6 ;
ldi tBCD2,0x9f ;initialize
digits 5 and 4
binbcd_6: subi tBCD2,0x10 ;
subi fbin0,byte1(-10000*10) ;addit
fbin,100000
sbci fbin1,byte2(-10000*10) ;
sbci fbin2,byte3(-10000*10) ;
brcs binbcd_6 ;
binbcd_5: inc tBCD2 ;
subi fbin0,byte1(10000) ;subit
fbin,10000
sbci fbin1,byte2(10000) ;
sbci fbin2,byte3(10000) ;
brcc binbcd_5 ;
rjmp binbcd_3-1 ;initialize
digits 3 and 2

;
***************************************************************************
;*
;* Bin3BCD == 24-bit Binary to BCD conversion
;*
;* fbin0:fbin1:fbin2 >>> tBCD0:tBCD1:tBCD2:tBCD3
;* hex dec
;* r16r17r18 >>> r20r21r22r23
;*
;
***************************************************************************
.def fbin0 =r16 ; binary value byte 0 (LSB)
.def fbin1 =r17 ; binary value byte 1
.def fbin2 =r18 ; binary value byte 2 (MSB)
.def tBCD0 =r20 ; BCD value digits 0 and 1
.def tBCD1 =r21 ; BCD value digits 2 and 3
.def tBCD2 =r22 ; BCD value digits 4 and 5
.def tBCD3 =r23 ; BCD value digits 6 and 7
(MSD)

Bin3BCD20: mov r16,r20 ;for compatibility

with Math32
mov r17,r21 ;
mov r18,r22 ;
Bin3BCD16: ldi tBCD3,0xfa ;initialize
digits 7 and 6
binbcd_107: subi tBCD3,-0x10 ;
subi fbin0,byte1(10000*1000) ;subit
fbin,10^7
sbci fbin1,byte2(10000*1000) ;
sbci fbin2,byte3(10000*1000) ;
brcc binbcd_107 ;
binbcd_106: dec tBCD3 ;
subi fbin0,byte1(-10000*100) ;addit
fbin,10^6
sbci fbin1,byte2(-10000*100) ;
sbci fbin2,byte3(-10000*100) ;
brcs binbcd_106 ;
ldi tBCD2,0xfa ;initialize
digits 5 and 4
binbcd_105: subi tBCD2,-0x10 ;
subi fbin0,byte1(10000*10) ;subit
fbin,10^5
sbci fbin1,byte2(10000*10) ;
sbci fbin2,byte3(10000*10) ;
brcc binbcd_105 ;
binbcd_104: dec tBCD2 ;
subi fbin0,byte1(-10000) ;addit
fbin,10^4
sbci fbin1,byte2(-10000) ;
sbci fbin2,byte3(-10000) ;
brcs binbcd_104 ;
ldi tBCD1,0xfa ;initialize
digits 3 and 2
binbcd_103: subi tBCD1,-0x10 ;
subi fbin0,byte1(1000) ;subiw
fbin,10^3
sbci fbin1,byte2(1000) ;
brcc binbcd_103 ;
binbcd_102: dec tBCD1 ;
subi fbin0,byte1(-100) ;addiw
fbin,10^2
sbci fbin1,byte2(-100) ;
brcs binbcd_102 ;
ldi tBCD0,0xfa ;initialize
digits 1 and 0
binbcd_101: subi tBCD0,-0x10 ;
subi fbin0,10 ;subi
fbin,10^1
brcc binbcd_101 ;
add tBCD0,fbin0 ;LSD
ret ;

;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Demo: ;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-)(-:-)(-;-)
(-:-)(-;-)(-:-)(-;-)(-:-)

;
***************************************************************************
;$ $ $ $ $ $ $ $ $ Illustrations with comments
field $ $ $ $ $ $ $ $ $
;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.dseg
Variable: .byte 4
VarWord1: .byte 2
VarWord2: .byte 2
Result: .byte 8
.equ Address1 =VarWord1
.equ Address2 =VarWord2
.equ Address =Variable
.set Constant =0x4321

.cseg
.def Temp =r16
.def TempL =r16
.def TempH =r17
.def Flags =r15
.equ _Flag1 =1
.equ _Flag2 =2
.equ _Flag3 =3
.equ _signResult=0

;*** OUTI, OUTIW, OUTW, INW

outiw SP,Temp,RAMEND ;initialize 16-bit
Stack Pointer
outi TCNT0,Temp,0 ;clear Timer/
Counter0 (8-bit)
inw Temp,TCNT1 ;read Timer/
Counter1 (16-bit)
outw TCNT1,Temp ;write Timer/
Counter1 (16-bit)

;*** CLF, SEF, CBF, SBF, IBF

clf Flags,_Flag1 ;clear (0)
bit _Flag1
bld Flags,_Flag2 ; and
bit _Flag2
cbf Flags,Temp,_Flag1,_Flag2 ;clear
both at once
sef Flags,_Flag1 ;set (1)
bit _Flag1
bld Flags,_Flag2 ; and
bit _Flag2
sbf Flags,Temp,_Flag1,_Flag2 ;set both
at once
ibf Flags,Temp,_Flag1,_Flag2,_Flag3 ;
invert of 3 flags
ibf TempL,TempH,0,2,4,6 ;invert
only even bits

;*** XCH, MVW, MVI, MOVS, MOVSW

xch TempL,TempH ;swap in Temp
register pair
xch Temp,r0 ;swap bytes r0 &
Temp
mvw X,Y ;copy of Y register pair
into X pair
mvw Z,Temp ;copy of TempL&TempH into Z
register pair
mvi Flags,Temp,exp2(_Flag1)|1<<_Flag2 ;
initialize flags
mvi r0,Temp,Constant ;load to
low register (0-15)
movs Address1,Temp,Address2 ;copy of
one memory byte
movsw Address1,Temp,Address2 ;copy of
two memory bytes

;*** STSI, STSIW, LDSW, STSW

stsi Address,Temp,Constant ;initialize
of one memory byte
stsiw Address,Temp,Constant ;initialize
of two memory bytes
ldsw Temp,Address1 ;copy of two memory
bytes
stsw Address2,Temp ; via Temp
register pair

;*** LDIW, LDDW, STDW

ldiw Temp,Constant ;initialize of
register pair
ldiw Z,Address ;initialize of
address pointer
lddw Temp,Z+(Address1-Address) ;copy of
two memory bytes
stdw Z+(Address2-Address),Temp ; via
Temp register pair

;*** PUSHW, POPW

pushw Y ;copy of Y register
pair
popw X ; into X register
pair
ldiw Temp,Maths
pushw Temp
ret ;equ jmp Maths
Maths:
;***** INITMEM
InitMem Address ;clear 128 bytes
(latest Address+127)
InitMem Address,0 ;equ InitMem Address
InitMem Address,0,0 ;equ InitMem Address
InitMem Address,,1 ;for 128 bytes each:
=0xff
InitMem Address,1 ;clear one byte at
Address
InitMem Address1,Address2-Address1+2,Limit
;limitation: if bit_T=0 then 4_bytes:=0xff
else 4_bytes:=0
ldi MathPattern,0xab
InitMem Address,,+1 ;128_bytes:=0xab
doubly, but possibly

;***** MATHR16, MATHR20, OPERAND

Operand Address ;equ MathR20
Address,obXXXX
MathR20 Address ;equ Operand Address
.set ObXXXX=0b11
MathR16 Address ;equ Operand
Address,0b0011,r16
.set ObXXXX=0b1111 ;default
Operand Address,,r16 ;equ MathR16
Address,obXXXX
Operand Address,,r20 ;equ MathR20
Address,obXXXX
Operand Address,0b11 ;equ MathR20
Address,0b0011
Operand Address,0b11,r16;equ MathR16
Address,0b0011
;load data with displacement (equ *256, *65536,
*16777216)
MathR20 Address,0b0110 ;(data word)
<<8
MathR16 Address,0b1000 ;(data byte)
<<24

;***** CONST20, CONST16, CNST16T

; WARNING: AVRASM ver. 1.30 don't understand 32 bits
constants, but all it
; expressions are internally 32 bits (the higher
versions of assembler
; directly operate on value up to 0xffffffff)
Const20 0x76543210 ;error
v1.30 (0x00003210)
Const20 1985229328 ;error
v1.30 (12816)
Const16 0x7654<<16|0x3210 ;ok
(0x76543210)
Cnst16t 0x7654*1024*1024+0x1234 ;ok
(0x401234)

;***** CNST16B, CNST16W

Cnst16b Constant ;equ Const16 byte1
(Constant)
rcall Div32b ; rcall Div32 ;
but briefly
Cnst16w Constant<<1 ;non-equ Const16
Constant<<1
rcall Mul32w ; rcall
Mul32 ;word overflow

;***** RESULT2, RESULT3

Result2 Address ;equ Result2
Address,obXXXX
;store data with displacement
(equ /256, /65536, /16777216 and more)
Result2 Address,1<<7 ;(byte
result)>>56
Result2 Address,0b111100 ;(double
word result)>>16
Result2 Address,obXXXX<<4 ;(double
word result)>>32
rjmp JointTail+3
JointTail: Result3 Address,0xff ;equ Result2
Address,0b11111111
rcall JointTail ;concluding RET
inside Result call

;******* register pairs

.def AL=r16
.def AH=r17
.def BL=r18
.def BH=r19
.def CL=r20
.def CH=r21
.def DL=r22
.def DH=r23
.def WL=r24
.def WH=r25
ldiw C,0 ;equ
ldiw D,0x7654 ; Const20
0x7654<<16
ldiw A,0x3210 ;equ Cnst16w 0x3210
ldi AL,0x10 ;equ Cnst16b 0x10
mvw A,C ;copy of Const20
mvw B,D ; into Const16
adiw WL,1 ;as well as "adiw" for X,Y,
Z register pairs
sbiw WL,1 ;as well as "sbiw" for X,Y,
Z register pairs

;******* testing calculations

InitMem Variable,4,1 ;
0xffffffff to memory

Operand Variable
Const16 0xffff<<16|0xffff
rcall Mul32 ;
0xffffffff * 0xffffffff
Result2 Result,0b11111111 ;
0xfffffffe00000001

Operand Variable
Const16 0x1010<<16|0x1010
rcall Div32 ;
0xffffffff / 0x10101010
Result2 Result,0b11111111 ; 0xf
(0x0f0f0f0f)

Operand Variable,0b111
Cnst16t 0x00ff<<16|0xffff
rcall Div32t ;
0xffffff / 0xffffff
Result2 Result ; 0x1 (0x0
no rollout)

Operand Variable,0b1100
Cnst16w 0xffff
rcall Div32w ;
0xffff0000 / 0xffff
Result2 Result ; 0x10000
(0x0 no rollout)

;******* data translations 16-bit (overall maximum

65535=0xffff)
;result Rd16|24
Const20 0x2748
rcall BCD2bin ;02748 = 0x0abc
Cnst16t 6<<16|0x5535
rcall BCD2bin16 ;65535 = 0xffff
Result2 Address,0b11
rcall Bin2BCD ;0xffff = 65535
Cnst16w 0xabba
rcall Bin2BCD16 ;0xabba = 43962

;******* data translations 32-bit (overall maximum

655359999=0x270fffff)
;BCD2Bin
stsiw Variable,Temp,0x5432 ;
stsiw Variable+2,Temp,0x9876 ;BCD
98765432 >>>
Operand Variable,0b11
rcall BCD2bin
pushw C ;temporary result
always is 2 bytes
Operand Variable+2,0b11 ;or 0b111 if BCD
have all 5 digits
rcall BCD2bin
ldiw D,0
Cnst16w 10000
rcall Mul32w
popw A ;B pair by this
time =0
rcall Add32
Result2 Result,0b1111 ;>>> HEX
0x05e30a78
;Bin2BCD
stsiw Variable,Temp,0xffff ;
stsiw Variable+2,Temp,0x270f ;HEX
0x270fffff >>>
Operand Variable,0b1111
Cnst16w 10000 ;remainder always
is 2 bytes
rcall Div32w ; as
temporary result
rcall Bin2BCD
Result2 Result+2,0b111
mvw A,W ;W pair do not
changed beyond
rcall Bin2BCD16
Result2 Result,0b11 ;>>> BCD
655359999

;******* 32-bit Bin4BCD conversion (overall maximum

4294967295=0xffffffff)
;result Rd40
ldi YL,18 ;one more dishonest
trick
Operand Variable,0b1111,1+
rcall Bin4BCD ;0x270fffff >>>
655359999
Const20 0x1234<<16|0x5678
Result2 18
rcall Bin4BCD ;0x12345678 >>>
305419896
Const16 0xab98<<16|0xfedc
mvw C,A
rcall Bin4BCD ;0xfedcab98 >>>
4275874712
InitMem Variable,3,1 ; 0xffffff to memory
MathR20 Variable,0b111
MathR16 Variable,0b111
rcall Mul32t ;(0xffffff)^2 =
0xfffffe000001
Result2 18,0b111100 ; /65536 =
0xfffffe00
rcall Bin4BCD ;0xfffffe00 >>>
4294966784

;******* data translations 32-bit (overall maximum

4294967295=0xffffffff)
;Bin4BCD20
Operand Variable,0b1111
rcall Bin4BCD20 ;0x27ffffff >>>
671088639
Const20 0x1234<<16|0x5678
rcall Bin4BCD20 ;0x12345678 >>>
305419896
ldiw D,0
ldiw C,0xab
rcall Bin4BCD20 ; 0xab >>> 171
;Bin4BCD16
rcall Bin4BCD16 ; 0x1ffff >>>
131071
Const16 0xfedc<<16|0xab98
rcall Bin4BCD16 ;0xfedcab98 >>>
4275874712
InitMem Variable,4,1
MathR16 Variable,0b1111
rcall Bin4BCD16 ;0xffffffff >>>
4294967295

;******* data translations 24-bit (overall maximum

16777215=0xffffff)
;BCD3bin
Const20 $1670<<16|$2650
rcall BCD3bin ;16702650 >>>
0xfedcba
ldiw B,0
ldiw A,9
rcall BCD3bin16 ;00000009 >>>
0x000009 (fastest)
ldiw D,0x1599
ldiw C,0x9990
rcall BCD3bin20 ;15999990 >>>
0xf423f6 (slowest)
;Bin3BCD
Const16 0x98<<16|0x967f
rcall Bin3BCD ;0x98967f >>>
09999999
rcall Bin3BCD ;0xffff09 >>>
16776969
Cnst16t $0d00*256+$df22
rcall Bin3BCD ;0x0ddf22 >>>
00909090 (fastest)
Cnst16t $f500*256+$871d
rcall Bin3BCD ;0xf5871d >>>
16090909 (slowest)
;Bin3BCD20
MathR20 Variable,0b111
rcall Bin3BCD20 ;0xffffff >>>
16777215
rcall Bin3BCD20 ;0x777215 >>>
07827989
Const20 $a600*256+$75a2
rcall Bin3BCD20 ;0xa675a2 >>>
10909090 (slowest)
;Bin3BCD16
Cnst16t $8a00*256+$b75d
rcall Bin3BCD16 ;0x8ab75d >>>
09090909 (fastest)
ldi AH,0xff
rcall Bin3BCD16 ; 0xffff >>> 65535
ldi AL,0
rcall Bin3BCD16 ;0x000000 >>>
00000000

;******* formula recalculation: Result=(VarWord1-

0xfff)/7+VarWord2/0x100
;VarWordX>=0
InitMem Variable,16 ;clear
VarWordX & Result
rcall Formula ; -
0x249.0000 as result

ldiw Temp,0xabcd ;these 2

lines are not equ
stsw VarWord1,Temp ;stsiw
VarWord1,Temp,0xabcd
stsw VarWord2,Temp
rcall Formula ; 0x16ed.
cd00 as result

stsiw VarWord1,Temp,0x00ff
stsiw VarWord2,Temp,0xff00
rcall Formula ; -
0x125.9249 as result

stsiw VarWord1,Temp,0x0f0f
stsiw VarWord2,Temp,0xf0f0
rcall Formula ; 0x00ce.
a6dc as result

InitMem VarWord1,4,1 ;
0x2349.2392 at the end
ldiw Temp,Demo
pushw Temp ;getting
into demo loop
Formula:
MathR20 VarWord1,0b1100
Const16 0xfff<<16
rcall Sub32sign
Cnst16b 7
rcall Div32b
Result2 16 ;faster than call
MathR16 20
MathR16 20 ;included for
comparison only
MathR20 VarWord2,0b110
rcall Add32sign
bld Flags,_signResult
Result3 Result
.exit
;
***************************************************************************
;*
;* REMARK
;* Sometimes expression as macroparameter must be
enclosed in parentheses,
;* because they not are always present in above
macrocalls
;* (remember about the priority of AVR assembler
operators).
;* Accommodate oneself to ATmega: MOVW instruction e.
g., etc.
;*
;
***************************************************************************
;Feedback: please, include abbr."Math32" in Your e-mail
subject line (!spam)
;from time to time it is possible mailbox overflow &|
shut-down - I am sorry
;to make mention of http://www.i.com.ua/~birua when
occasion offers - Thanks
;All the best & good luck!

Programming the AVR Microcontrollers in Machine Language

AVR
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Atmel AVR From Wikipedia, the free encyclopedia (Redirected

have different addressing capabilities than register locations

R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language

http://avr-asm.tripod.com/math32x.html (3 of 3)1/20/2009 8:37:55 PM

AVR MATH YX

ALM CLK ;***** Immediate 16-bit number

;***** Register Variables

.def sub1l = r16
.def sub1h = r17
.def sub2l = r18
.def sub2h = r19

;***** Code
sub16: sub sub1l,sub2l ;Subtract
low bytes
sbc sub1h,sub2h ;Add high byte with
carry
;Expected result is 0x4646

;***** Register Variables

.def subi1l = r16
.def subi1h = r17

;***** Immediate 16-bit number

.equ subi2 = 0x1234

;***** Code
subi16: subi subi1l,low(subi2) ;Subtract
low bytes
sbci subi1h,high(subi2) ;Subtract high byte
with carry
;Expected result is 0x3412

;***** Register Variables

.def cp1l = r16
.def cp1h = r17
.def cp2l = r18
.def cp2h = r19

;***** Code
cp16: cp cp1l,cp2l ;Compare low byte
cpc cp1h,cp2h ;Compare high byte with
carry from
;previous operation
ncp16:
;Expected result is Z=0

;***** Register Variables

.def cp1l =r16
.def cp1h =r17
.def c_tmp=r18
.equ cp2 = 0x3412 ;Immediate to compare with

;***** Code
cpi16: cpi cp1l,low(cp2) ;Compare low byte
ldi c_tmp,high(cp2) ;
cpc cp1h,c_tmp ;Compare high byte

;Expected result is Z=1, C=

;***** Register Variables

.def ng1l = r16
.def ng1h = r17

;
***************************************************************************
;*
;* End of examples.
;*
;
***************************************************************************

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

AVR
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© WebRing Inc. Search

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
http://avr-asm.tripod.com/mathyx.html (1 of 2)1/20/2009 8:38:35 PM
AVR MATH YX

the ATmega range) have additional instructions to make

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AVR MATH YX

The AVR Assembler Site

DIV16 XX PACKAGE
HOME
RETRO_DAN
ASM FORUM ; DIVISION ROUTINES with scaled reciprocals for constants
ASM MATH ; (all functions optimized for speed, ~ <36 cycles w/o push/pop)
TUTORIAL #1
; Target: AVR MCUs with hardware multiplier ("mul" instruction)
TUTORIAL #2 ; Author: Andreas Lenze ([email protected])
TUTORIAL #3 ; Feb. 2003

MATH 200 ;div. by n: n: scaled reciprocal: shift count:

MATH 200b
;Div16_3 3 1010101010101011 AAAB 17
MATH 201 ;Div16_5 5 1100110011001101 CCCD 18
MATH 202 ;Div16_6 6 1010101010101011 AAAB 18
;Div16_7 7 10010010010010011 19 -> 17 bits req'd,(MSB=1,rest 2493h)
MATH 32X
;Div16_7a 7 1001001001001001 9249 18 -> needs correction for accurate
MATH YX result
;Div16_9 9 1110001110001111 E38F 19
DIV16 XX
;Div16_10 10 1100110011001101 CCCD 19
DIV 24 24 ;Div16_11 11 1011101000101111 BA2F 19
DIV 3216 ;Div16_12 12 1010101010101011 AAAB 19
;Div16_13 13 1001110110001010 9D8A 19
FLOAT 128 ;Div16_14 14 10010010010010011 20 -> 17 bits req'd,(MSB=1,rest 2493h)
SQRT16 ;Div16_15 15 1000100010001001 8889 19
;Div16_17 17 1111000011110001 F0F1 20
MATH 202 ;Div16_18 18 1110001110001111 E38F 20
MATH 202 ;Div16_19 19 0110101111001011 6BCB 19
;Div16_20 20 1100110011001101 CCCD 20
DEC ASCII
;Div16_21 21 1100001100001011 C30B 20 -> needs correction for accurate
INT ASCII result
;Div16_22 22 1011101000101111 BA2F 20
HX2ASC
;Div16_23 23 1011001000010101 B215 20 -> needs correction for accurate
AVG8 222 result
FFT7
;D16_nn(by) 2-23 -> "C-style" function with macro 'Div16by' to perform a
COPY 102 ; constants division with all divisors from 2 to 23. Price
LPM 108 ; tag for the comfort is ~50 cycles / ~50 words overhead

EPROM 100 ; NOTE: Other divisor constants like /24 etc. can easily be created by
SER EPROM ; modifying the shift count in "Q = Q >> x": add 1 shift right for
; 'divisor x 2' (e.g. for "/24" we need a total of 20 instead of
DFLASH AT45
; the 19 shifts needed for "/12")
FLASH CARD
; If the remainder of the division is not needed, the multiply/subtract
VFX SMIL
; operation after the comment
VFX MEM ;
SORT 220 ; r19:r18 now "Q" (= result >> xx)

CRC 236 ; R = A - xx*Q (start removal

XMODEM REC ; ldi r16,xx
; ....
UART 304 ; sbc XH,YH (end removal)
UART 305 ;
; may be omitted to save another 9 cycles / 7 words
UART 128
; (* not applicable for 'Div16_7a' - remainder is always needed *)
UART BUFF ;
; "Div16_7a" and "Div16_21/3" demonstrate and use the 'approximate and
USB 232
correct'
AVR ISP ; technique which may be necessary for some larger divisors (e.g. /21, /23)
ISP 2313
;---------------------------------------------------------------------------
ISP 1200
AVR SPI ;***************************************************************************
;*
I2C 300 ;* Function "Div16_3"
I2C 302 ;* Divides an unsigned 16 bit word (XH:XL) by 3
;* Returns quotient in YH:YL and remainder in XL
I2C TWI26
;*
I2C/TWI 128 ;* Author: Andreas Lenze ([email protected])
I2C/TWI AT8 ;* Equations by D: W. Jones:
;*
DALLAS-1W ;* Reciprocal mul w. extra precision:
DALLAS CRC ;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xAAAB;
ETHNET 8019 ;* unsigned int Q; /* the quotient */
TEA ;*
;* Q = ((A * 0xAAAB) >> 17)
ADC 128 ;*
ADC 10B ;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
ADC 400
;*
ADC 401 ;* words: 36 (w. push/pop = 10 words)
THERM 232 ;* cycles: 48 (w. push/pop = 16 cycles)
;*
IRD 410 ;* Note: Hardware multiplier required ("mul" instruction)
LCD HD44 ;*
;***************************************************************************
LCD 2313
LCD44 2313 Div16_3:
push r2
KBD 240 push r19
MUX 242 push r18
push r17
KBD PS2
KBD PC/128 ldi YH,0xAA ; scaled reciprocal for /3
PS2 EMU ldi YL,0xAB

BOOT MG8 ; Q = A * 0xAAAB

BOOT DR8 ; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
ALM CLK mul XH, YH ; ah * bh
CLOCK 8564 movw r19:r18, r1:r0
mul XL, YL ; al * bl
90 DAYS
mov r17,r1 ; r0 to [rXX] is superfluous
DELAYS mul XH, YL ; ah * bl
add r17, r0
CALL ID
adc r18, r1
DTMF 314 adc r19, r2
PWM 6CH mul YH, XL ; bh * al
add r17, r0
PWM 10K adc r18, r1
ENCODE adc r19, r2
STH-11 ; Q = Q >> 16: use r19:r18 as word
ATMEL CORP ; Q = Q >> 1
lsr r19 ; do the last shift
AVR
ror r18
BUTTERFLY
AVR BOOK ; r19:r18 now "Q" (= result >> 17)
; R = A - 3*Q;
ldi r17,3 ; multiply r19:r18 by 3
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_3 ------------------------------------------

;***************************************************************************
;*
;* Function "Div16_5"
;* Divides an unsigned 16 bit word (XH:XL) by 5
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xCCCD;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xCCCD) >> 18)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 54 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_5:
push r2
push r19
push r18
push r17

ldi YH,0xCC ; scaled reciprocal for /5

ldi YL,0xCD

; Q = A * 0xCCCD
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 2
lsr r19 ; do the last 2 shifts
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 18)

; R = A - 5*Q;
ldi r17,5 ; multiply r19:r18 by 5
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_5 ------------------------------------------

;***************************************************************************
;*
;* Function "Div16_6"
;* Divides an unsigned 16 bit word (XH:XL) by 6
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xAAAB;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xAAAB) >> 18)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 54 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_6:
push r2
push r19
push r18
push r17

ldi YH,0xAA ; scaled reciprocal for /6

ldi YL,0xAB

; Q = A * 0xAAAB
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 2
lsr r19 ; do the last 2 shifts
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 18)

; R = A - 6*Q;
ldi r17,6 ; multiply r19:r18 by 6
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_6 ------------------------------------------

;***************************************************************************
;*
;* Function "Div16_7"
;* Divides an unsigned 16 bit word (XH:XL) by 7
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x2493;
;* unsigned int Q; /* the quotient */
;*
;* Q = (((A * 0x2493) >> 16) + A) >> 3 -> 17 bits reciprocal!
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_7:
push r2
push r19
push r18
push r17

ldi YH,0x24 ; scaled reciprocal for /7

ldi YL,0x93

; Q = A * 0x2493
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q + A
add r18,XL
adc r19,XH

; Q = Q >> 3
ror r19 ; do the last 3 shifts, including
ror r18 ; carry (!) from previous addition
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 7*Q;
ldi r17,7 ; multiply r19:r18 by 7
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_7 ------------------------------------------

;***************************************************************************
;*
;* Function "Div16_7a"
;* Divides an unsigned 16 bit word (XH:XL) by 7
;* Call with 16 bit number in XH:XL
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* (Equations partly by D. W. Jones)
;*
;* Reciprocal multiplication w. extra precision:
;* (This version uses correction to achieve the required precision)
;* unsigned int R; /* remainder */
;* unsigned int long A; /* dividend */
;* unsigned int long Q; /* quotient */
;*
;* Q = ((A * 0x9249) >> 18)
;*
;* /* Q = A/7 or Q+1 = A/7 for all A <= 65535 */
;* /* correct Q and calculate remainder */
;* R = A - 7*Q
;* if (R >= 7) {
;* R = R - 7;
;* Q = Q + 1;
;* }
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 59 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_7a:
push r2
push r19
push r18 ; Tmp3
push r17 ; Tmp2

ldi YH,0x92 ; scaled reciprocal for /7

ldi YL,0x49 ; (16 bit only, 0/-1 error possible)

; Q = A * 0x9249
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 2
lsr r19 ; 2 shifts remaining
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 18)

; R = A - 7*Q;
ldi r17,7 ; multiply r19:r18 by 7
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of current Q

; XH:XL now "R":

; if (R >= 7)
; R = R - 7;
; Q = Q + 1;
cpi XL,0x07
brlo PC+3
subi XL,7
adiw YL,1

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_7a -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_9"
;* Divides an unsigned 16 bit word (XH:XL) by 9
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xE38F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xE38F) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_9:
push r2
push r19
push r18
push r17

ldi YH,0xE3 ; scaled reciprocal for /9

ldi YL,0x8F

; Q = A * 0xE38F
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 9*Q;
ldi r17,9 ; multiply r19:r18 by 9
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_9 ------------------------------------------

;***************************************************************************
;*
;* Function "Div16_10"
;* Divides an unsigned 16 bit word (XH:XL) by 10
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xCCCD;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xCCCD) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_10:
push r2
push r19
push r18
push r17

ldi YH,0xCC ; scaled reciprocal for /10

ldi YL,0xCD

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 10*Q;
ldi r17,10 ; multiply r19:r18 by 10
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_10 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_11"
;* Divides an unsigned 16 bit word (XH:XL) by 11
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xBA2F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xBA2F) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_11:
push r2
push r19
push r18
push r17

ldi YH,0xBA ; scaled reciprocal for /11

ldi YL,0x2F

; Q = A * 0xBA2F
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 11*Q;
ldi r17,11 ; multiply r19:r18 by 11
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_11 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_12"
;* Divides an unsigned 16 bit word (XH:XL) by 12
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xAAAB;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xAAAB) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_12:
push r2
push r19
push r18
push r17

ldi YH,0xAA ; scaled reciprocal for /12

ldi YL,0xAB

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 12*Q;
ldi r17,12 ; multiply r19:r18 by 12
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_12 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_13"
;* Divides an unsigned 16 bit word (XH:XL) by 13
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x9D89;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0x9D8A) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_13:
push r2
push r19
push r18
push r17

ldi YH,0x9D ; scaled reciprocal for /13

ldi YL,0x8A

; Q = A * 0x9D8A
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 13*Q;
ldi r17,13 ; multiply r19:r18 by 13
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_13 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_14"
;* Divides an unsigned 16 bit word (XH:XL) by 14
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x2493;
;* unsigned int Q; /* the quotient */
;*
;* Q = (((A * 0x2493) >> 16) + A) >> 4 -> 17 bits reciprocal!
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 40 (w. push/pop = 8 words)
;* cycles: 44 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_14:
push r2
push r19
push r18
push r17

ldi YH,0x24 ; scaled reciprocal for /7, /14

ldi YL,0x93

; Q = A * 0x2493
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0

http://avr-asm.tripod.com/div16xx.html (1 of 3)1/20/2009 8:39:37 PM

AVR MATH YX

mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q + A
add r18,XL
adc r19,XH

; Q = Q >> 4
ror r19 ; do the last 4 shifts, including
ror r18 ; carry (!) from previous addition
lsr r19
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 20)

; R = A - 14*Q;
ldi r17,14 ; multiply r19:r18 by 14
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_14 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_15"
;* Divides an unsigned 16 bit word (XH:XL) by 15
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x8889;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0x8889) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_15:
push r2
push r19
push r18
push r17

ldi YH,0x88 ; scaled reciprocal for /15

ldi YL,0x89

; Q = A * 0x8889
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 15*Q;
ldi r17,15 ; multiply r19:r18 by 15
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_15 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_17"
;* Divides an unsigned 16 bit word (XH:XL) by 17
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xF0F1;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xF0F1) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 44 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_17:
push r2
push r19
push r18
push r17

ldi YH,0xF0 ; scaled reciprocal for /17

ldi YL,0xF1

; Q = A * 0xF0F1
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 17*Q;
ldi r17,17 ; multiply r19:r18 by 17
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_17 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_18"
;* Divides an unsigned 16 bit word (XH:XL) by 18
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xE38F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xE38F) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 38 (w. push/pop = 10 words)
;* cycles: 44 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_18:
push r2
push r19
push r18
push r17

ldi YH,0xE3 ; scaled reciprocal for /9 /18

ldi YL,0x8F

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 18*Q;
ldi r17,18 ; multiply r19:r18 by 18
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_18 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_19"
;* Divides an unsigned 16 bit word (XH:XL) by 19
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0x6BCA;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0x6BCB) >> 19)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_19:
push r2
push r19
push r18
push r17

ldi YH,0x6B ; scaled reciprocal for /19

ldi YL,0xCB

; Q = A * 0x6BCB
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 3
lsr r19 ; do the last 3 shifts
ror r18
lsr r19
ror r18
lsr r19
ror r18

; r19:r18 now "Q" (= result >> 19)

; R = A - 19*Q;
ldi r17,18 ; multiply r19:r18 by 18
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_19 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_20"
;* Divides an unsigned 16 bit word (XH:XL) by 20
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xCCCD;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xCCCD) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_20:
push r2
push r19
push r18
push r17

ldi YH,0xCC ; scaled reciprocal for /10, /20

ldi YL,0xCD

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 20*Q;
ldi r17,20 ; multiply r19:r18 by 20
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_20 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_21"
;* Divides an unsigned 16 bit word (XH:XL) by 21
;* Call with 16 bit number in XH:XL
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* (Equations partly by D. W. Jones)
;*
;* Reciprocal multiplication w. extra precision:
;* (uses correction to achieve the required precision)
;* unsigned int R; /* remainder */
;* unsigned int long A; /* dividend */
;* unsigned int long Q; /* quotient */
;*
;* Q = ((A * 0xC30B) >> 20)
;*
;* /* Q = A/21 or Q+1 = A/21 for all A <= 65535 */
;* /* correct Q and calculate remainder */
;* R = A - 21*Q
;* if (R >= 21) {
;* R = R - 21;
;* Q = Q + 1;
;* }
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 40 (w. push/pop = 8 words)
;* cycles: 52 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_21:
push r2
push r19
push r18
push r17

ldi YH,0xC3 ; scaled reciprocal for /21

ldi YL,0x0B ; (16 bit only, 0/-1 error possible)

; Q = A * 0xC30B
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 21*Q;
ldi r17,21 ; multiply r19:r18 by 21
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of current Q

; XH:XL now "R":

; if (R >= 21)
; R = R - 21;
; Q = Q + 1;
cpi XL,0x15
brlo PC+3
subi XL,21
adiw YL,1

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_21 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_22"
;* Divides an unsigned 16 bit word (XH:XL) by 22
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* Equations by D: W. Jones:
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = 0xBA2F;
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * 0xBA2F) >> 20)
;*
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 46 (w. push/pop = 16 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_22:
push r2
push r19
push r18
push r17

ldi YH,0xBA ; scaled reciprocal for /11, /22

ldi YL,0x2F

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 22*Q;
ldi r17,22 ; multiply r19:r18 by 22
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_22 -----------------------------------------

;***************************************************************************
;*
;* Function "Div16_23"
;* Divides an unsigned 16 bit word (XH:XL) by 23
;* Call with 16 bit number in XH:XL
;* Returns quotient in YH:YL and remainder in XL
;*
;* Author: Andreas Lenze ([email protected])
;* (Equations partly by D. W. Jones)
;*
;* Reciprocal multiplication w. extra precision:
;* (uses correction to achieve the required precision)
;* unsigned int R; /* remainder */
;* unsigned int long A; /* dividend */
;* unsigned int long Q; /* quotient */
;*
;* Q = ((A * 0xB215) >> 20)
;*
;* /* Q = A/23 or Q+1 = A/23 for all A <= 65535 */
;* /* correct Q and calculate remainder */
;* R = A - 1*Q
;* if (R >= 23) {
;* R = R - 23;
;* Q = Q + 1;
;* }
;* Uses: high regs: 7 (r17, r18, r19, X, Y)
;* low regs: 3 (r0, r1, r2)
;*
;* words: 36 (w. push/pop = 8 words)
;* cycles: 59 (w. push/pop = 20 cycles)
;*
;* Note: Hardware multiplier required ("mul" instruction)
;*
;***************************************************************************

Div16_23:
push r2
push r19
push r18
push r17

ldi YH,0xB2 ; scaled reciprocal for /23

ldi YL,0x15 ; (16 bit only, 0/-1 error possible)

; Q = A * 0xB215
; (r19:r18:r17[:rXX] = XH:XL * YH:YL)
clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to [rXX] is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; Q = Q >> 4
swap r18 ; do the last 4 shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19

; r19:r18 now "Q" (= result >> 20)

; R = A - 23*Q;
ldi r17,23 ; multiply r19:r18 by 23
mul r18, r17 ; al * bl
sub XL,r0
clr XH
movw YL,r18 ; make copy of currentQ

; XH:XL now "R":

; if (R >= 23)
; R = R - 23;
; Q = Q + 1;
cpi XL,0x17
brlo PC+3
subi XL,23
adiw YL,1

; XL holds "R"
; YH:YL holds "Q"
pop r17
pop r18
pop r19
pop r2

ret

; End of function Div16_23 -----------------------------------------

;***************************************************************************
; macro definition to call/use "division by xx" - module (D16_nn)
macro Div16by
push r20
ldi r20,@0
call D16_nn
pop r20
.endm
;***************************************************************************

;***************************************************************************
;*
;* Function "D16_nn"
;* Divides an unsigned 16 bit word by [2] -> [23]
;* Note: divisor 2, 4, 8, 16 options are provided for remainder calculation
;* and (for ease-of-use) to cover the complete divisors range (2-23)
;*
;* Call with dividend loaded to XH:XL (high/low bytes)
;* Returns quotient in YH:YL and remainder in XL
;*
;* Usage: define the macro "Div16by" prior to using the function,
;* use macro with divisor as parameter, e.g. "Div16by 17" to
;* divide XH:XL by 17 decimal
;*
;* .macro Div16_by
;* push r20
;* ldi r20,@0
;* call D16_nn
;* pop r20
;* .endm
;*
;* Author: Andreas Lenze ([email protected])
;* Feb. 2003
;* Equations mostly by D. W. Jones
;*
;* Reciprocal mul w. extra precision:
;* unsigned int A;
;* unsigned int scaled_reciprocal = xxxx
;* unsigned int Q; /* the quotient */
;*
;* Q = ((A * scaled_reciprocal) >> 16) >> nn
;* or
;* Q = (((A * scaled_reciprocal) >> 16) + A) >> nn -> for /7 and /14
;*
;* /* special case: use correction for Q (e.g. for /21, /23) */
;* if (R >= divisor)
;* R = R - divisor;
;* Q = Q + 1;
;*
;* div. by n: scaled reciprocal: shift count:
;*
;* 2 - 1
;* 3 1010101010101011 AAAB 17
;* 4 - 2
;* 5 1100110011001101 CCCD 18
;* 6 1010101010101011 AAAB 18
;* 7 10010010010010011 19 -> 17 bits req'd,(MSB=1,rest 2493h)
;* 8 - 3
;* 9 1110001110001111 E38F 19
;* 10 1100110011001101 CCCD 19
;* 11 1011101000101111 BA2F 19
;* 12 1010101010101011 AAAB 19
;* 13 1001110110001010 9D8A 19
;* 14 10010010010010011 20 -> 17 bits req'd,(MSB=1,rest 2493h)
;* 15 1000100010001001 8889 19
;* 16 - 4
;* 17 1111000011110001 F0F1 20
;* 18 1110001110001111 E38F 20
;* 19 0110101111001011 6BCB 19
;* 20 1100110011001101 CCCD 20
;* 21 1100001100001011 C30B 20 -> needs correction for accurate
result
;* 22 1011101000101111 BA2F 20
;* 23 1011001000010101 B215 20 -> needs correction for accurate
result
;*
;* Uses: high regs: 11 (r16, r17, r18, r19, r20, X, Y, Z)
;* low regs: 3 (r0, r1, r2)
;* regs 16-20 saved, all others destroyed
;* T-flag destroyed (cleared)
;*
;* words: 97 (incl. 5 words for macro)
;* cycles: 85-111 (w. call/ret & macro), typically 102
;* table bytes: 66
;*
;* Target: AVR MCUs with hardware multiplier ("mul" instruction and
;* "lpm rd,Z/Z+" functionality required)
;*
;***************************************************************************

D16_nT:
; look-up table for D16_nn: 3 bytes per entry, range for divisor "2" to "23"
; data format: 2 bytes scaled reciprocal (word, high/low), 3rd byte
"flags"
.cseg
.db 0x00, 0xFF, 0x01, 0xAA, 0xAB, 0x01, 0x00, 0xFF, 0x02, 0xCC, 0xCD, 0x02,
0xAA, 0xAB
;
by /2 /3 /4 /5 /6

.db 0x02, 0x24, 0x93, 0x13, 0x00, 0xFF, 0x03, 0xE3, 0x8F, 0x03, 0xCC, 0xCD,
0x03, 0xBA
;
by /7 /8 /9 /10 /11

.db 0x2F, 0x03, 0xAA, 0xAB, 0x03, 0x9D, 0x8A, 0x03, 0x24, 0x93, 0x14, 0x88,
0x89, 0x03
;by /12 /13 /14 /15

.db 0x00, 0xFF, 0x04, 0xF0, 0xF1, 0x04, 0xE3, 0x8F, 0x04, 0x6B, 0xCB, 0x03,
0xCC, 0xCD
;
by /16 /17 /18 /19 /20

.db 0x04, 0xC3, 0x0B, 0x04, 0xBA, 0x2F, 0x04, 0xB2, 0x15, 0x04
;by /21 /22 /23

D16_nn:
push r19 ; save scrap regs
push r18
push r17
push r16

clt ; make sure T-flag is cleared

push r20 ; save divisor
cpi r20,24 ; exit if divisor > 23
brsh D16_0
subi r20,2
brmi D16_0 ; exit if divisor <= 1

ldi ZH,high(D16_nT*2)
ldi ZL,low(D16_nT*2)
clr r2
mov r1,r20
lsl r20 ; x2 (3 bytes per entry)
add r20,r1 ; + org value = x3
add ZL,r20 ; point Z to divisor's data table position
adc ZH,r2

lpm YH,Z+ ; scaled reciprocal for /xx

lpm YL,Z+ ; Z now points at flags
cpi YL,0xFF ; low byte "FFh" in the scaled_reciprocal data
; indicates divisor 2, 4, 8, 16 -> no 'mul' req.
brne D16_1 ; != FFh -> mul required
mov r19,XH ; FFh: no div., shifts only: move input
mov r18,XL ; to "result registers" and go to shifts
rjmp D16_2 ; directly (saves ~18 cycles)

D16_0: pop r20 ; clean up stack before exit

rjmp D16_Err ; intermediate label (avoid "out of reach" for
brxx)

; Q = A * scaled_reciprocal
; (r19:r18:r17:r16 = XH:XL * YH:YL)
D16_1: clr r2
mul XH, YH ; ah * bh
movw r19:r18, r1:r0
mul XL, YL ; al * bl
mov r17,r1 ; r0 to r16 is superfluous
mul XH, YL ; ah * bl
add r17, r0
adc r18, r1
adc r19, r2
mul YH, XL ; bh * al
add r17, r0
adc r18, r1
adc r19, r2

; Q = Q >> 16: use r19:r18 as word

; do the remaining shifts
D16_2: lpm r20,Z ; fetch "flag"

cpi r20,3 ; flag = 3 -> 3 normal shifts required

breq D16_6 ; (div. 8, 9, 10, 11, 12, 13, 15, 19)

cpi r20,4 ; flag = 4 -> 4 normal shifts required

breq D16_3 ; (div. 16, 17, 18, 20, 21, 22, 23)

cpi r20,2 ; flag = 2 -> 2 normal shifts required

breq D16_7 ; (div. 4, 5, 6)

cpi r20,1 ; flag = 1 -> 1 normal shift required

breq D16_8 ; (div. 2, 3)

cpi r20,0x14 ; flag = 4spec -> 4 special shifts required

breq D16_5 ; (div. 14, extra addition, 1st shift w. carry)

cpi r20,0x13 ; flag = 3spec -> 3 special shifts required

breq D16_4 ; (div. 7, extra addition, 1st shift w. carry)
rjmp D16_Err ; no valid flags, exit

; Q = Q >> 4
D16_3: swap r18 ; 4 normal shifts
swap r19
andi r18,0x0F
eor r18,r19
andi r19,0x0F
eor r18,r19
rjmp D16_9

http://avr-asm.tripod.com/div16xx.html (2 of 3)1/20/2009 8:39:37 PM

AVR MATH YX

; Q = (Q + A) >> 3-4
D16_4: set
D16_5: add r18,XL ; (Q + A)
adc r19,XH
ror r19 ; 3-4 "special" shifts, include
ror r18 ; carry from previous addition into 1st shift
D16_6: lsr r19
ror r18
D16_7: lsr r19
ror r18
brts D16_9 ; if T-flag set, skip this shift
D16_8: lsr r19
ror r18

; r19:r18 now "Q" (= result >> yy)

; R = A - xx*Q;
D16_9: pop r16 ; multiply r19:r18 by divisor

mul r18, r16 ; al * bl

sub XL,r0
clr XH
movw YL,r18 ; make copy of Q

; XL = "R" (remainder)
; /* use correction - can be omitted if /21, /23 are not used */
; if (R >= divisor)
; R = R - divisor;
; Q = Q + 1;
cp XL,r16
brlo PC+3
sub XL,r16
adiw YL,1

; YH:YL = "Q" (quotient, result)

D16_Err:clt ; make sure T-flag is cleared
pop r16 ; restore regs
pop r17
pop r18
pop r19
ret

; End of function D16_nn -------------------------------------------

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

http://avr-asm.tripod.com/div16xx.html (3 of 3)1/20/2009 8:39:37 PM

AVR MATH YX

The AVR Assembler Site

24 BIT BY 24 BIT DIVISION ROUTINE

HOME
RETRO_DAN
;******** div24u ***********
ASM FORUM ;*Division 24/24
ASM MATH ;* Dividend(dvd)
;* Result = ---------------
TUTORIAL #1
;* Divisor(dvr)
TUTORIAL #2 ;*
TUTORIAL #3 ;*

MATH 200 .def rem24L =r3

MATH 200b .def rem24M =r4
.def rem24H =r5
MATH 201 .def result24L =r9
MATH 202 .def result24M =r10
.def result24H =r11
MATH 32X
.def dvd24L =r9
MATH YX .def dvd24M =r10
.def dvd24H =r11
DIV16 XX
.def dvr24L =r12
DIV 24 24 .def dvr24M =r13
DIV 3216 .def dvr24H =r14

FLOAT 128 ;Unsigned Division 24bit/24bit

SQRT16
div24u: clr rem24L ;clear remainder Low byte
MATH 202 clr rem24M ;clear remainder mid byte
MATH 202 sub rem24H,rem24H ;clear remainder High byte and
carry
DEC ASCII
ldi rLoopCnt1,25 ;init loop counter
INT ASCII
d16u_1: rol dvd24L ;shift left dividend
HX2ASC
rol dvd24M
AVG8 222 rol dvd24H
FFT7 dec rLoopCnt1 ;decrement counter
brne d16u_2 ;if done
COPY 102 ret ; return
LPM 108
d16u_2: rol rem24L ;shift dividend into remainder
EPROM 100 rol rem24M
SER EPROM rol rem24H
sub rem24L,dvr24L ;remainder = remainder - divisor
DFLASH AT45
sbc rem24M,dvr24M ;
FLASH CARD sbc rem24H,dvr24H
brcc d16u_3 ;if result negative
VFX SMIL
add rem24L,dvr24L ; restore remainder
VFX MEM adc rem24M,dvr24M
SORT 220 adc rem24H,dvr24H
clc ; clear carry to be shifted into result
CRC 236 rjmp d16u_1 ;else
XMODEM REC d16u_3: sec ; set carry to be shifted into result
rjmp d16u_1
UART 304
UART 305 ret
UART 128
UART BUFF
USB 232
AVR ISP
ISP 2313
ISP 1200
AVR SPI
I2C 300
I2C 302
I2C TWI26 Programming the AVR Microcontrollers in Machine Language
I2C/TWI 128
I2C/TWI AT8 AVR
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ADC 128
Atmel AVR From Wikipedia, the free encyclopedia
ADC 10B
ADC 400 (Redirected from Avr) Jump to: navigation, search The AVRs
ADC 401 are a family of RISC microcontrollers from Atmel. Their
THERM 232
internal architecture was conceived by two students: Alf-Egil
IRD 410
LCD HD44 Bogen and Vegard Wollan, at the Norwegian Institute of
LCD 2313 Technology (NTH] and further developed at Atmel Norway, a
LCD44 2313
subsidiary founded by the two architects. Atmel recently
KBD 240
MUX 242 released the Atmel AVR32 line of microcontrollers. These are
KBD PS2 32-bit RISC devices featuring SIMD and DSP instructions,
KBD PC/128
along with many additional features for audio and video
PS2 EMU
BOOT MG8 processing, intended to compete with ARM based
BOOT DR8 processors. Note that the use of "AVR" in this article refers
ALM CLK
to the 8-bit RISC line of Atmel AVR Microcontrollers. The
CLOCK 8564
90 DAYS acronym AVR has been reported to stand for Advanced
DELAYS Virtual RISC. It's also rumoured to stand for the company's
CALL ID
founders: Alf and Vegard, who are evasive when questioned
DTMF 314
PWM 6CH
about it. Contents [hide] 1 Device Overview 1.1 Program
PWM 10K Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
ENCODE
Program Execution 1.5 Speed 2 Development 3 Features 4
STH-11
ATMEL CORP
Footnotes 5 See also 6 External Links 6.1 Atmel Official
AVR Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
BUTTERFLY
AVR BOOK
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored
and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line
is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost
all AVR devices are self-programmable. [edit] Data Memory
and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-
two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the
64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities
that are different from each other. Register locations R0 to
R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different
addressing capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while
SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires
a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the
free and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C Compatible
Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are
evasive when questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External
Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space
consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in
as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory
mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access,
all can still be addressed and manipulated as if they were in
SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions
take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of
processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to
31 have different addressing capabilities than I/O ports 32 to
63. CLR affects flags, while SER does not, even though they
are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while
SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires
a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the
free and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C Compatible
Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported
to stand for Advanced Virtual RISC. It's also rumoured to
stand for the company's founders: Alf and Vegard, who are
evasive when questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External
Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space
consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified
as 8-bit RISC devices. The working registers are mapped in
as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual
usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory
mapped I/O registers will occupy a portion of the SRAM.)
Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access,
all can still be addressed and manipulated as if they were in
SRAM. [edit] EEPROM Almost all devices have on-die
EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the
device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is
fetched as the current one is executing. Most instructions
take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of
processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it
is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to
31 have different addressing capabilities than I/O ports 32 to
63. CLR affects flags, while SER does not, even though they
are complementary instructions. CLR set all bits to zero and
SER sets them to one. (Note though, that neither CLR nor
SER are native instructions. Instead CLR is syntactic sugar
for [produces the same machine code as] EOR R,R while
SER is syntactic sugar for LDI R,$FF. Math operations such
as EOR modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices
reaching 20MHz. Lower powered operation usually requires
a reduced clock speed. All AVRs feature an on-chip
oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR
are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the
free and inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator Lighting
(PWM Specific) Controller models Dedicated I²C Compatible
Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485,
and more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/div2424.html (1 of 2)1/20/2009 8:40:09 PM
AVR MATH YX

http://avr-asm.tripod.com/div2424.html (2 of 2)1/20/2009 8:40:09 PM

AVR MATH YX

The AVR Assembler Site

32 BIT BY 16 BIT DIVISION ROUTINE

HOME
RETRO_DAN
;divide r21:r18/refH:refL result in XH:
ASM FORUM XL
ASM MATH __DIVD21U:
CLR XL
TUTORIAL #1
CLR XH
TUTORIAL #2 CLR R0
TUTORIAL #3 CLR R1
LDI R17,32
MATH 200 __DIVD21U1:
MATH 200b LSL R18
ROL R19
MATH 201 ROL R20
MATH 202 ROL R21
ROL XL
MATH 32X
ROL XH
MATH YX ROL R0
ROL R1
DIV16 XX
SUB XL,scaleL
DIV 24 24 SBC XH,scaleH
DIV 3216 SBC R0,zeroreg
SBC R1,zeroreg
FLOAT 128 BRCC __DIVD21U2
SQRT16 ADD XL,scaleL
ADC XH,scaleH
MATH 202 ADC R0,zeroreg
MATH 202 ADC R1,zeroreg
RJMP __DIVD21U3
DEC ASCII
__DIVD21U2:
INT ASCII SBR R18,1
__DIVD21U3:
HX2ASC
DEC R17
AVG8 222 BRNE __DIVD21U1
FFT7 mov XL, r19
mov XH, r18 ; result in X
COPY 102
LPM 108 ret

EPROM 100
SER EPROM
DFLASH AT45
FLASH CARD
VFX SMIL
VFX MEM
SORT 220
CRC 236
XMODEM REC
UART 304 Programming the AVR Microcontrollers in Machine Language
UART 305
UART 128 AVR
UART BUFF << Prev | Ring Hub | Join | Rate| Next
USB 232 >>
© WebRing Inc. Search
AVR ISP
ISP 2313
ISP 1200
Atmel AVR From Wikipedia, the free encyclopedia
AVR SPI
I2C 300
(Redirected from Avr) Jump to: navigation, search
I2C 302 The AVRs are a family of RISC microcontrollers
I2C TWI26
from Atmel. Their internal architecture was
I2C/TWI 128
I2C/TWI AT8
conceived by two students: Alf-Egil Bogen and
DALLAS-1W Vegard Wollan, at the Norwegian Institute of
DALLAS CRC
Technology (NTH] and further developed at Atmel
ETHNET 8019
TEA
Norway, a subsidiary founded by the two architects.
ADC 128 Atmel recently released the Atmel AVR32 line of
ADC 10B
microcontrollers. These are 32-bit RISC devices
ADC 400
ADC 401
featuring SIMD and DSP instructions, along with
THERM 232 many additional features for audio and video
IRD 410
processing, intended to compete with ARM based
LCD HD44
LCD 2313
processors. Note that the use of "AVR" in this
LCD44 2313 article refers to the 8-bit RISC line of Atmel AVR
KBD 240 Microcontrollers. The acronym AVR has been
MUX 242
KBD PS2
reported to stand for Advanced Virtual RISC. It's
KBD PC/128 also rumoured to stand for the company's founders:
PS2 EMU Alf and Vegard, who are evasive when questioned
BOOT MG8
BOOT DR8
about it. Contents [hide] 1 Device Overview 1.1
ALM CLK Program Memory 1.2 Data Memory and Registers
CLOCK 8564 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
90 DAYS
DELAYS
Development 3 Features 4 Footnotes 5 See also 6
CALL ID External Links 6.1 Atmel Official Links 6.2 AVR
DTMF 314 Forums & Discussion Groups 6.3 Machine
PWM 6CH
PWM 10K
Language Development 6.4 C Language
ENCODE Development 6.5 BASIC & Other AVR Languages 6.6
STH-11 AVR Butterfly Specific 6.7 Other AVR Links [edit]
ATMEL CORP
AVR
Device Overview The AVR is a Harvard architecture
BUTTERFLY machine with programs and data stored and
AVR BOOK
addressed separately. Flash, EEPROM, and SRAM
are all integrated onto a single die, removing the
need for external memory (though still available on
some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either
16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers
The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O
register space may be larger on some more
extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.)
Even though there are separate addressing
schemes and optimized opcodes for register file
and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM.
This is most often used for long-term parameter
storage to be retrieved even after cycling the power
of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of
processors were designed for the efficient
execution of compiled C code. The AVR instruction
set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each
other. Register locations R0 to R15 have different
addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry.
Because many operations on the AVR are single
cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due
to the free and inexpensive development tools
available, including reasonably priced development
boards and free development software. The AVRs
are marketed under various names that share the
same basic core but with different peripheral and
memory combinations. Some models (notably, the
ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is
fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal,
Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG,
or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller
models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,
RS-485, and more) Serial Peripheral Interface (SPI)
CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language Atmel
AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are
a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded
by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-
bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for
audio and video processing, intended to compete
with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC.
It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5
Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6
AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture
machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM
are all integrated onto a single die, removing the
need for external memory (though still available on
some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either
16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers
The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O
register space may be larger on some more
extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.)
Even though there are separate addressing
schemes and optimized opcodes for register file
and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM.
This is most often used for long-term parameter
storage to be retrieved even after cycling the power
of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of
processors were designed for the efficient
execution of compiled C code. The AVR instruction
set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each
other. Register locations R0 to R15 have different
addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry.
Because many operations on the AVR are single
cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due
to the free and inexpensive development tools
available, including reasonably priced development
boards and free development software. The AVRs
are marketed under various names that share the
same basic core but with different peripheral and
memory combinations. Some models (notably, the
ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is
fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal,
Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG,
or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller
models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,
RS-485, and more) Serial Peripheral Interface (SPI)
CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language Atmel
AVR machine programming language Atmel AVR
From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are
a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded
by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-
bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for
audio and video processing, intended to compete
with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC.
It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device
Overview 1.1 Program Memory 1.2 Data Memory and
Registers 1.3 EEPROM 1.4 Program Execution 1.5
Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2
AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6
AVR Butterfly Specific 6.7 Other AVR Links [edit]
Device Overview The AVR is a Harvard architecture
machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM
are all integrated onto a single die, removing the
need for external memory (though still available on
some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either
16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers
The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these
sections (address 006016). (Note that the I/O
register space may be larger on some more
extensive devices, in which case memory mapped I/
O registers will occupy a portion of the SRAM.)
Even though there are separate addressing
schemes and optimized opcodes for register file
and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM.
This is most often used for long-term parameter
storage to be retrieved even after cycling the power
of the device. [edit] Program Execution Atmel's
AVRs have a single level pipeline design. The next
machine instruction is fetched as the current one is
executing. Most instructions take just one or two
clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of
processors were designed for the efficient
execution of compiled C code. The AVR instruction
set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely
regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each
other. Register locations R0 to R15 have different
addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects
flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches
such as LDI do not.) [edit] Speed The AVR line can
normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry.
Because many operations on the AVR are single
cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due
to the free and inexpensive development tools
available, including reasonably priced development
boards and free development software. The AVRs
are marketed under various names that share the
same basic core but with different peripheral and
memory combinations. Some models (notably, the
ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is
fairly good. See external links for sites relating to
AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-
up Resistors Multiple Internal Oscillators Internal,
Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG,
or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller
models Dedicated I²C Compatible Two-Wire
Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,
RS-485, and more) Serial Peripheral Interface (SPI)
CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed
(HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D
Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices
Atmel AVR assembler programming language Atmel
AVR machine programming language
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AVR MATH YX

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AVR MATH YX

The AVR Assembler Site

FLOATING POINT MATH

HOME
RETRO_DAN
;***************************************************************************
ASM FORUM ;
ASM MATH ; File Name :'Main.asm"
; Title :Matmatikai rutinok, test verzio
TUTORIAL #1
; Date :2003.07.16.
TUTORIAL #2 ; Version :1.0.0
TUTORIAL #3 ; Support telephone :+36-70-333-4034
; Support fax :
MATH 200 ; Support Email :[email protected]
MATH 200b ; Target MCU :ATmega128
;
MATH 201 ;***************************************************************************
MATH 202 ; D E S C R I P T I O N
;
MATH 32X
;
MATH YX ;***************************************************************************
; M O D I F I C A T I O N H I S T O R Y
DIV16 XX
;
DIV 24 24 ;
DIV 3216 ; rev. date who why
; ---- ---------- --- -----------------------------------
FLOAT 128 ; 0.01 2003.07.16 VFX Creation, mult
SQRT16 ; 0.02 2004.03.30 VFX Add float add & sub
;
MATH 202 ;
MATH 202 ;***************************************************************************
;Hardware
DEC ASCII
;***************************************************************************
INT ASCII ;*
;* f=external 16MHz (t=-.--ns)
HX2ASC
;*
AVG8 222 ;***************************************************************************
FFT7 ;
;
COPY 102 ;
LPM 108 .include "m128def.inc"

EPROM 100 ;***************************************************************************

SER EPROM ;* Const Def
DFLASH AT45
FLASH CARD ;**************************************************************************
;* Hardware Def.
VFX SMIL
;
VFX MEM
SORT 220 ;***************************************************************************
;** VARIABLES
CRC 236 .DSEG
XMODEM REC
;***************************************************************************
UART 304 .ESEG
UART 305
;***************************************************************************
UART 128
;**** I N T E R R U P T S
UART BUFF ;****
;***************************************************************************
USB 232
.CSEG
AVR ISP
ISP 2313 RESET: CLI ;GLOBAL INTERRUP DIS.

ISP 1200 ldi R16, high(RAMEND) ;setup stack

AVR SPI out SPH,R16
ldi R16, low(RAMEND)
I2C 300 out SPL,R16
I2C 302
I2C TWI26
;PI/2 = 81 49 0F DA A2 Sign bit!!!
I2C/TWI 128 ;1,570796326734125614166259765625
I2C/TWI AT8
ldi R24,0x81 ;exponens
DALLAS-1W ldi R23,0xC9 ;mantissa
DALLAS CRC ldi R22,0x0F
ldi R21,0xDA
ETHNET 8019 ldi R20,0xA2
TEA mov R6,R24
mov R5,R23
ADC 128 mov R4,R22
ADC 10B mov R3,R21
mov R2,R20
ADC 400
ADC 401 ; const
THERM 232 ;0,79411764699034392833709716796875

IRD 410 ldi R24,0x80 ;exponens

LCD HD44 ldi R23,0x4b ;mantissa
ldi R22,0x4b
LCD 2313 ldi R21,0x4b
LCD44 2313 ldi R20,0x4b
KBD 240
MUX 242 ; rcall multiply
KBD PS2
rcall addition
KBD PC/128
PS2 EMU veges:
rjmp veges
BOOT MG8
BOOT DR8
; -----------------------------
ALM CLK ; Prepare to multiply or divide
CLOCK 8564 ; -----------------------------
; This routine is called in succession from multiply and divide to prepare
90 DAYS
; two mantissas by setting the leftmost bit that is used for the sign.
DELAYS ; m1: R25, R24:R21
; m2: R6, R5:R2
CALL ID
;
DTMF 314 ; T flag = Sign of result
PWM 6CH ; R6,R24 corrected exponent
; R5,R23 restored sign bit of mantissa
PWM 10K ;
ENCODE ; cycles + (RET) = Cycles
STH-11 PREP_Mul_Div:
ATMEL CORP mov R16,R5
eor R16,R23
AVR
bst R16,7 ;T flag = result sign bit
BUTTERFLY
AVR BOOK ldi R16,0xA0 ;Binary point offset is 0x20 to
integer number
ldi R17,0x80 ;MSB sign bit

tst R24
brne PREP_MD01 ;First number is floating point format
add R24,R16
rjmp PREP_MD02

PREP_MD01:
or R23,R17 ;restore msb bit
PREP_MD02:
tst R6
brne PREP_MD03 ;Second number is floating point format
add R6,R16
rjmp PREP_MD04

PREP_MD03:
or R5,R17 ;restore msb bit
PREP_MD04:
sub R24,R17
sub R6,R17 ;shift zero point by 0x80 (back
to 2's complement)
ret

; ------------------------------
; THE 'MULTIPLICATION' OPERATION
; ------------------------------
; (offset: $04 'multiply')
;
; m1: R6, R5:R2
; m2: R24, R23:R20
; -------------------
; Res: R6, R5:R2
;
; cycles + (RET) = Cycles
;
multiply:
rcall PREP_Mul_Div

mov R0,R2
or R0,R3
or R0,R4
or R0,R5
breq Res_Zero
mov R0,R20
or R0,R21
or R0,R22
or R0,R23
breq Res_Zero

rcall mult32
clr R7
rcall Normalize
sub R6,R16 ;shift exponent by
normalized value
brcs NumberTooBig
add R6,R24 ;2^x *2^y = 2^(x+y)
brvs NumberTooBig
ldi R16,0x80
sub R6,R16 ;set offset by 0x80

rcall Round
brcs NumberTooBig

ldi R17,0xFF
bld R17,7 ;get result sign bit
and R5,R17 ;set result sign bit

clc
ret
NumberTooBig:
sec
ret

Res_Zero:
clr R2
clr R3
movw R4,R2
clr R6
clc
ret

;***************************************************
;* Mutiply 32x32 -> 64 bit
;*
;* R23:R20 x R5:R2 -> R15:R8
;*
;* 86 cycles + 4 (RET) = 90 Cycles
;*
mult32:
clr R16
mul R20,R2
movw R8,R0
clr R10
clr R11
movw R12,R10
movw R14,R10
mul R21,R2
add R9,R0
adc R10,R1
mul R22,R2
add R10,R0
adc R11,R1
mul R23,R2
add R11,R0
adc R12,R1

mul R20,R3
add R9,R0
adc R10,R1
adc R11,R16
adc R12,R16
adc R13,R16
mul R21,R3
add R10,R0
adc R11,R1
adc R12,R16
adc R13,R16
mul R22,R3
add R11,R0
adc R12,R1
adc R13,R16
mul R23,R3
add R12,R0
adc R13,R1

mul R20,R4
add R10,R0
adc R11,R1
adc R12,R16
adc R13,R16
adc R14,R16
mul R21,R4
add R11,R0
adc R12,R1
adc R13,R16
adc R14,R16
mul R22,R4
add R12,R0
adc R13,R1
adc R14,R16
mul R23,R4
add R13,R0
adc R14,R1

mul R20,R5
add R11,R0
adc R12,R1
adc R13,R16
adc R14,R16
adc R15,R16
mul R21,R5
add R12,R0
adc R13,R1
adc R14,R16
adc R15,R16
mul R22,R5
add R13,R0
adc R14,R1
adc R15,R16
mul R23,R5
add R14,R0
adc R15,R1
ret

;**********************************************************
; R15:R8:R7 -> R15:R12
; R16 - 64-exponent
Normalize:
ldi R17,64 ;max 64 bitet kell vegigrotalni
Norm0: tst R15
brne Norm1
mov R15,R14
mov R14,R13
mov R13,R12
mov R12,R11
mov R11,R10
mov R10,R9
mov R9,R8
mov R8,R7
clr R7
subi R17,8
cpi R17,8
brne Norm0
Norm1:
;legnagyobb
helyiertek felrotalasa bit7-ig
sbrc R15,7
rjmp Norm2
lsl R7
rol R8
rol R9
rol R10
rol R11
rol R12
rol R13
rol R14
rol R15
dec R17
brne Norm1
Norm2:
ldi R16,64
sub R16,R17
;R16-ban az
exponens
ret

; -------------------------------
; THE 'PREPARE TO ADD' SUBROUTINE
; -------------------------------
; This routine is called twice by addition to prepare the two numbers.
; The sign bit is tested before being set to the implied state.
; Negative numbers are twos complemented.
;
; m1: R6, R5:R2 -> R6, R7:R5:R2
; m2: R24, R23:R20 -> R24, R25:R23:R20
; R25,R7 -> sign
;
PREP_ADD:
clr R25
clr R7
ldi R16,0x80

tst R24
brne Prep_Add1
mov R24,R16

;ide jon majd a normalas R23:R20

rjmp M1Pos

Prep_Add1:
bst R23,7 ;test the sign bit
or R23,R16 ;set it to implied state
brtc M1Pos ;jump if positive number
NEG_M1:
clr R8
clr R9
movw R10,R8
movw R12,R8 ;clear result regs

sub R8,R20 ;complement

sbc R9,R21 ;add in initial carry
or from prev operation
sbc R10,R22
sbc R11,R23
sbc R12,R13
movw R20,R8
movw R22,R10
mov R25,R12
M1Pos:

tst R6
brne Prep_Add2
mov R6,R16

;ide jon majd a normalas R5:R2

rjmp M2Pos

Prep_Add2:
bst R5,7 ;test the sign bit
or R5,R16 ;set it to implied state
brtc M2Pos ;jump if positive number
NEG_M2:
clr R8
clr R9
movw R10,R8
movw R12,R8 ;clear result regs

sub R8,R2 ;complement

sbc R9,R3 ;add in initial carry
or from prev operation
sbc R10,R4
sbc R11,R5
sbc R12,R13
movw R2,R8
movw R4,R10
mov R7,R12
M2Pos:
ret ;return

; -------------------------
; THE 'SHIFT FP Right' SUBROUTINE
; -------------------------
; In: mantissa R7:R5:R2
; Exponent : R6
; Shift right by R16
;
; Out: R17,R15,R14,R13,R12,R11,R10,R9,R8,R7
; s s s s s m m m m g
SHIFT_FP:
movw R12,R2
movw R14,R4
mov R17,R7
clr R7
clr R8
clr R9
movw R10,R8

tst R16
brne Shift_fp1
ret ;diff
== 0 no rota
Shift_fp1:
cpi R16,0x21 ;diff>33 bit
brcc ADDEND_0 ;we add 0 to 1st param

EIGHT_SHIFT:
cpi R16,8
brcs ONE_SHIFT
mov R7,R8
mov R8,R9
mov R9,R10
mov R10,R11
mov R11,R12
mov R12,R13
mov R13,R14
mov R14,R15
mov R15,R17
bst R17,7 ;negative
number?
clr R17
brtc SHIFT_FP2
ser R17
SHIFT_FP2: subi R16,8
rjmp EIGHT_SHIFT

ONE_SHIFT: bst R17,7 ;store sign bit

lsr R17
ror R15
ror R14
ror R13
ror R12
ror R11
ror R10
ror R9
ror R8
ror R7
bld R17,7 ;set back to
sign bit
dec R16
brne ONE_SHIFT
ret
ADDEND_0:
clr R7
clr R8
clr R9
movw R10,R8
movw R12,R8
movw R14,R8
movw R16,R8
ret

; ---------------------------
; THE 'SUBTRACTION' OPERATION
; ---------------------------
; (offset: $03 'subtract')

; m1: R6, R5:R2

; m2: R24, R23:R20
; -------------------
; Res: R6, R5:R2
;
; Subtraction is done by switching the sign byte/bit of the second
; number and continuing into addition.

subtract:
tst R24
brne Sub_NoZero
mov R0,R20
or R0,R21
or R0,R22
or R0,R23
brne addition
ret ;x - 0 = x
Sub_NoZero:
ori R23,0x80 ;make to negative

; ------------------------
; THE 'ADDITION' OPERATION
; ------------------------
; (offset: $0F 'addition')
;
; m1: R6, R5:R2
; m2: R24, R23:R20
; -------------------
; Res: R6, R5:R2
;
; cycles + (RET) = Cycles
;
addition:
rcall PREP_ADD
cp R24,R6 ;exp.
M1 < M2?
brcc SHIFT_LEN ;to SHIFT_LEN

movw R8,R2 ; exchange M1 &

M2
movw R2,R20
movw R20,R8

movw R8,R4
movw R4,R22
movw R22,R8

movw R8,R6
movw R6,R24
movw R24,R8
SHIFT_LEN:
mov R16,R24
sub R16,
R6 ;length of shift
mov R6,R24
rcall SHIFT_FP

; R17,R15,R14,R13,R12,R11,R10,R9,R8,
R7
; s m m m m m m m m g
; + R25,R23,R22,R21,R20 0 0 0 0
0
;---------------------------------------
; R17,R15,R14,R13,R12,R11,R10,R9,R8,
R7

add R12,R20
adc R13,R21
adc R14,R22
adc R15,R23
adc R17,R25
brlt NoAdd_Overf1

inc R6
brne Add_Rota
rjmp Add_Rep_6
Add_Rota:
ldi R16,1
rcall ONE_SHIFT

NoAdd_Overf1:
mov R20,R17 ;store sign
bst R17,7 ;sign =
positive?
brtc Add_Pos

clr R0 ;negate
clr R1
movw R2,R0
sub R0,R7
mov R7,R0
movw R0,R2

sbc R0,R8
sbc R1,R9
movw R8,R0

movw R0,R2
sbc R0,R10
sbc R1,R11
movw R10,R0

movw R0,R2
sbc R0,R12
sbc R1,R13
movw R12,R0

movw R0,R2
sbc R0,R14
sbc R1,R15
movw R14,R0

mov R0,R2
sbc R0,R17
mov R17,R0

Add_Pos:
tst R17
breq Add_Norm
inc R6
brne Add_Rota1
rjmp Add_Rep_6
Add_Rota1:
ldi R16,1
rcall ONE_SHIFT
rjmp Add_Pos

Add_Norm:
rcall Normalize

bst R15,7
brts Add_Norm1 ;ha 7. =0 ,akkor nincs mit tenni

rjmp Res_Zero

Add_Norm1:
sub R6,R16
breq Add_Rep_6
brcs Add_Rep_6

rcall Round
brcs Add_Rep_6

bst R20,7
brts Add_NegResult
ldi R16,0x7F
and R5,R16 ;make pos sign

Add_NegResult:
clc
ret

Add_Rep_6:
sec ;
overflow error
ret

Round:
movw R4,R14
movw R2,R12

;ide jon majd a kerekites

mov R0,R2
or R0,R3
or R0,R4
or R0,R5
brne Round1
clr R6
Round1:
clc
ret

Programming the AVR Microcontrollers in Machine Language

address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

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AVR MATH YX

The AVR Assembler Site

16 SQUARE ROOT ROUTINE

HOME
RETRO_DAN
;
ASM FORUM *****************************************************************************
ASM MATH ;*
;* sqrt16 V 1.00
TUTORIAL #1
;*
TUTORIAL #2 ;* r16 - SQUARE LOW BYTE
TUTORIAL #3 ;* r17 - SQUARE HIGH BYTE
;*
MATH 200 ;* r18,19 - SQRT, returned in r16
MATH 200b ;*
;* Low registers used : None
MATH 201 ;* High registers used : r16 - r19, r24, r25,
MATH 202 r26
;*
MATH 32X
;
MATH YX *****************************************************************************
.area text
DIV16 XX
_sqrt16::
DIV 24 24 st -y,r18
DIV 3216 st -y,r19
st -y,r24
FLOAT 128 st -y,r25
SQRT16 st -y,r26
ldi r24,0 ; remainder low
MATH 202 ldi r25,0 ; remainder high
MATH 202 ldi r18,0 ; divisor low
ldi r19,0 ; divisor high
DEC ASCII
ldi r26,8 ; loop count
INT ASCII sqrt16loop:
lsl r18 ; divisor <<= 1
HX2ASC
rol r19
AVG8 222 lsl r16 ; shift two msb's into remainder
FFT7 rol r17
rol r24
COPY 102 rol r25
LPM 108 lsl r16
rol r17
EPROM 100 rol r24
SER EPROM rol r25
cp r18,r24 ; divisor < remainder ?
DFLASH AT45
cpc r19,r25
FLASH CARD brcc sqrt16bitdone
inc r18 ; divisor++, lsb = 0
VFX SMIL
sub r24,r18 ; remainder -= divisor
VFX MEM sbc r25,r19
SORT 220 inc r18 ; divisor++, bit_1 = 0
sqrt16bitdone:
CRC 236 dec r26 ; decrement loop count
XMODEM REC brne sqrt16loop ; branch if not done
lsr r19 ; root = divisor / 2
UART 304 ror r18
UART 305 mov r16,r18
ld r26,y+
UART 128
ld r25,y+
UART BUFF ld r24,y+
ld r19,y+
USB 232
ld r18,y+
AVR ISP ret
ISP 2313
ISP 1200
AVR SPI
I2C 300
I2C 302
I2C TWI26
I2C/TWI 128
I2C/TWI AT8
DALLAS-1W
DALLAS CRC
Programming the AVR Microcontrollers in Machine Language
ETHNET 8019
TEA AVR
ADC 128 << Prev | Ring Hub | Join | Rate| Next
ADC 10B >>
ADC 400 © WebRing Inc. Search
ADC 401
THERM 232
IRD 410
Atmel AVR From Wikipedia, the free encyclopedia
LCD HD44 (Redirected from Avr) Jump to: navigation, search The
LCD 2313 AVRs are a family of RISC microcontrollers from Atmel.
LCD44 2313
KBD 240
Their internal architecture was conceived by two students:
MUX 242 Alf-Egil Bogen and Vegard Wollan, at the Norwegian
KBD PS2 Institute of Technology (NTH] and further developed at
KBD PC/128
PS2 EMU
Atmel Norway, a subsidiary founded by the two architects.
BOOT MG8 Atmel recently released the Atmel AVR32 line of
BOOT DR8 microcontrollers. These are 32-bit RISC devices featuring
ALM CLK
CLOCK 8564
SIMD and DSP instructions, along with many additional
90 DAYS features for audio and video processing, intended to
DELAYS compete with ARM based processors. Note that the use of
CALL ID
DTMF 314
"AVR" in this article refers to the 8-bit RISC line of Atmel
PWM 6CH AVR Microcontrollers. The acronym AVR has been
PWM 10K reported to stand for Advanced Virtual RISC. It's also
ENCODE
STH-11
rumoured to stand for the company's founders: Alf and
ATMEL CORP Vegard, who are evasive when questioned about it.
AVR Contents [hide] 1 Device Overview 1.1 Program Memory
BUTTERFLY
AVR BOOK 1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and
SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers
and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved
even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C
code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0
to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR
is syntactic sugar for [produces the same machine code
as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/
loads/stores/branches such as LDI do not.) [edit] Speed
The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the
AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and
inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface
(SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-voltage
Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers
from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many
additional features for audio and video processing,
intended to compete with ARM based processors. Note
that the use of "AVR" in this article refers to the 8-bit RISC
line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and
SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers
and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved
even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C
code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0
to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR
is syntactic sugar for [produces the same machine code
as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/
loads/stores/branches such as LDI do not.) [edit] Speed
The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the
AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and
inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface
(SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-voltage
Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers
from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices
featuring SIMD and DSP instructions, along with many
additional features for audio and video processing,
intended to compete with ARM based processors. Note
that the use of "AVR" in this article refers to the 8-bit RISC
line of Atmel AVR Microcontrollers. The acronym AVR has
been reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory
1.2 Data Memory and Registers 1.3 EEPROM 1.4 Program
Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official
Links 6.2 AVR Forums & Discussion Groups 6.3 Machine
Language Development 6.4 C Language Development 6.5
BASIC & Other AVR Languages 6.6 AVR Butterfly Specific
6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data
stored and addressed separately. Flash, EEPROM, and
SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the
device itself. For instance, the ATmega64x line has
64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers,
and SRAM. The AVRs have thirty-two single-byte registers
and are classified as 8-bit RISC devices. The working
registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers
(002016-005F16). The actual usable RAM starts after both
these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in
which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register
file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most
often used for long-term parameter storage to be retrieved
even after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or
two clock cycles, making AVRs relatively fast among the
eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C
code. The AVR instruction set is more orthogonal than
most eight-bit microcontrollers, however, it is not
completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0
to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even
though they are complementary instructions. CLR set all
bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR
is syntactic sugar for [produces the same machine code
as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/
loads/stores/branches such as LDI do not.) [edit] Speed
The AVR line can normally support clock speeds from 0-
16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing
the need for external clocks or resonator circuitry.
Because many operations on the AVR are single cycle, the
AVR can achieve up to 1MIPS per MHz. [edit] Development
AVRs have a large following due to the free and
inexpensive development tools available, including
reasonably priced development boards and free
development software. The AVRs are marketed under
various names that share the same basic core but with
different peripheral and memory combinations. Some
models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility
amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs
offer a wide range of features: RISC Core Running Many
Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple
Internal Oscillators Internal, Self-Programmable Instruction
Flash Memory up to 256K In-System Programmable using
ICSP, JTAG, or High Voltage methods Optional Boot Code
Section with Independent Lock Bits for Protection Internal
Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and
16-Bit Timers PWM Channels & dead time generator
Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface
(SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with
embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal
Serial Interface (USI) for Two or Three-Wire Synchronous
Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels
Brownout Detection Watchdog Timer (WDT) Low-voltage
Devices Operating Down to 1.8v Multiple Power-Saving
Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language

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AVR MATH YX

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16 BIT MATH (AVR 202)

The AVR Assembler Site

BCD MATH (AVR 204)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 0 4 ************************
ASM FORUM ;*
ASM MATH ;* Title: BCD Arithmetics
;* Version: 1.1
TUTORIAL #1
;* Last updated: 97.07.04
TUTORIAL #2 ;* Target: AT90Sxxxx (All AVR Devices)
TUTORIAL #3 ;*
;* Support E-mail: [email protected]
MATH 200 ;*
MATH 200b ;* DESCRIPTION
;* This Application Note lists subroutines for the following Binary Coded
MATH 201 ;* Decimal arithmetic applications:
MATH 202 ;*
;* Binary 16 to BCD Conversion (special considerations for AT90Sxx0x)
MATH 32X
;* Binary 8 to BCD Conversion
MATH YX ;* BCD to Binary 16 Conversion
;* BCD to Binary 8 Conversion
DIV16 XX
;* 2-Digit BCD Addition
DIV 24 24 ;* 2-Digit BCD Subtraction
DIV 3216 ;*
;***************************************************************************
FLOAT 128
SQRT16 .include "8515def.inc"

MATH 202 rjmp RESET ;reset handle

MATH 202
;***************************************************************************
DEC ASCII
;*
INT ASCII ;* "bin2BCD16" - 16-bit Binary to BCD conversion
;*
HX2ASC
;* This subroutine converts a 16-bit number (fbinH:fbinL) to a 5-digit
AVG8 222 ;* packed BCD number represented by 3 bytes (tBCD2:tBCD1:tBCD0).
FFT7 ;* MSD of the 5-digit number is placed in the lowermost nibble of tBCD2.
;*
COPY 102 ;* Number of words :25
LPM 108 ;* Number of cycles :751/768 (Min/Max)
;* Low registers used :3 (tBCD0,tBCD1,tBCD2)
EPROM 100 ;* High registers used :4(fbinL,fbinH,cnt16a,tmp16a)
SER EPROM ;* Pointers used :Z
;*
DFLASH AT45
;***************************************************************************
FLASH CARD
;***** Subroutine Register Variables
VFX SMIL
VFX MEM .equ AtBCD0 =13 ;address of tBCD0
SORT 220 .equ AtBCD2 =15 ;address of tBCD1

CRC 236 .def tBCD0 =r13 ;BCD value digits 1 and 0

XMODEM REC .def tBCD1 =r14 ;BCD value digits 3 and 2
.def tBCD2 =r15 ;BCD value digit 4
UART 304 .def fbinL =r16 ;binary value Low byte
UART 305 .def fbinH =r17 ;binary value High byte
.def cnt16a =r18 ;loop counter
UART 128
.def tmp16a =r19 ;temporary value
UART BUFF
;***** Code
USB 232
AVR ISP bin2BCD16:
ISP 2313 ldi cnt16a,16 ;Init loop counter
clr tBCD2 ;clear result (3 bytes)
ISP 1200 clr tBCD1
AVR SPI clr tBCD0
clr ZH ;clear ZH (not needed for AT90Sxx0x)
I2C 300 bBCDx_1:lsl fbinL ;shift input value
I2C 302 rol fbinH ;through all bytes
rol tBCD0 ;
I2C TWI26
rol tBCD1
I2C/TWI 128 rol tBCD2
I2C/TWI AT8 dec cnt16a ;decrement loop counter
brne bBCDx_2 ;if counter not zero
DALLAS-1W ret ; return
DALLAS CRC
bBCDx_2:ldi r30,AtBCD2+1 ;Z points to result MSB + 1
ETHNET 8019 bBCDx_3:
TEA ld tmp16a,-Z ;get (Z) with pre-decrement
;----------------------------------------------------------------
ADC 128 ;For AT90Sxx0x, substitute the above line with:
ADC 10B ;
; dec ZL
ADC 400
; ld tmp16a,Z
ADC 401 ;
THERM 232 ;----------------------------------------------------------------
subi tmp16a,-$03 ;add 0x03
IRD 410 sbrc tmp16a,3 ;if bit 3 not clear
LCD HD44 st Z,tmp16a ; store back
ld tmp16a,Z ;get (Z)
LCD 2313 subi tmp16a,-$30 ;add 0x30
LCD44 2313 sbrc tmp16a,7 ;if bit 7 not clear
st Z,tmp16a ; store back
KBD 240 cpi ZL,AtBCD0 ;done all three?
MUX 242 brne bBCDx_3 ;loop again if not
rjmp bBCDx_1
KBD PS2
KBD PC/128
PS2 EMU
;***************************************************************************
BOOT MG8 ;*
BOOT DR8 ;* "bin2BCD8" - 8-bit Binary to BCD conversion
;*
ALM CLK ;* This subroutine converts an 8-bit number (fbin) to a 2-digit
CLOCK 8564 ;* BCD number (tBCDH:tBCDL).
;*
90 DAYS
;* Number of words :6 + return
DELAYS ;* Number of cycles :5/50 (Min/Max) + return
;* Low registers used :None
CALL ID
;* High registers used :2 (fbin/tBCDL,tBCDH)
DTMF 314 ;*
PWM 6CH ;* Included in the code are lines to add/replace for packed BCD output.
;*
PWM 10K ;***************************************************************************
ENCODE
;***** Subroutine Register Variables
STH-11
ATMEL CORP .def fbin =r16 ;8-bit binary value
.def tBCDL =r16 ;BCD result MSD
AVR
.def tBCDH =r17 ;BCD result LSD
BUTTERFLY
AVR BOOK ;***** Code

bin2bcd8:
clr tBCDH ;clear result MSD
bBCD8_1:subi fbin,10 ;input = input - 10
brcs bBCD8_2 ;abort if carry set
inc tBCDH ;inc MSD
;---------------------------------------------------------------------------
; ;Replace the above line with this one
; ;for packed BCD output
; subi tBCDH,-$10 ;tBCDH = tBCDH + 10
;---------------------------------------------------------------------------
rjmp bBCD8_1 ;loop again
bBCD8_2:subi fbin,-10 ;compensate extra subtraction
;---------------------------------------------------------------------------
; ;Add this line for packed BCD output
; add fbin,tBCDH
;---------------------------------------------------------------------------
ret

;***************************************************************************
;*
;* "BCD2bin16" - BCD to 16-Bit Binary Conversion
;*
;* This subroutine converts a 5-digit packed BCD number represented by
;* 3 bytes (fBCD2:fBCD1:fBCD0) to a 16-bit number (tbinH:tbinL).
;* MSD of the 5-digit number must be placed in the lowermost nibble of
fBCD2.
;*
;* Let "abcde" denote the 5-digit number. The conversion is done by
;* computing the formula: 10(10(10(10a+b)+c)+d)+e.
;* The subroutine "mul10a"/"mul10b" does the multiply-and-add operation
;* which is repeated four times during the computation.
;*
;* Number of words :30
;* Number of cycles :108
;* Low registers used :4 (copyL,copyH,mp10L/tbinL,mp10H/tbinH)
;* High registers used :4 (fBCD0,fBCD1,fBCD2,adder)
;*
;***************************************************************************

;***** "mul10a"/"mul10b" Subroutine Register Variables

.def copyL =r12 ;temporary register

.def copyH =r13 ;temporary register
.def mp10L =r14 ;Low byte of number to be multiplied by
10
.def mp10H =r15 ;High byte of number to be multiplied
by 10
.def adder =r19 ;value to add after multiplication

;***** Code

mul10a: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high

nibble
swap adder
mul10b: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" low
nibble
mov copyL,mp10L ;make copy
mov copyH,mp10H
lsl mp10L ;multiply original by 2
rol mp10H
lsl copyL ;multiply copy by 2
rol copyH
lsl copyL ;multiply copy by 2 (4)
rol copyH
lsl copyL ;multiply copy by 2 (8)
rol copyH
add mp10L,copyL ;add copy to original
adc mp10H,copyH
andi adder,0x0f ;mask away upper nibble of adder
add mp10L,adder ;add lower nibble of adder
brcc m10_1 ;if carry not cleared
inc mp10H ; inc high byte
m10_1: ret

;***** Main Routine Register Variables

.def tbinL =r14 ;Low byte of binary result (same as

mp10L)
.def tbinH =r15 ;High byte of binary result (same as
mp10H)
.def fBCD0 =r16 ;BCD value digits 1 and 0
.def fBCD1 =r17 ;BCD value digits 2 and 3
.def fBCD2 =r18 ;BCD value digit 5

;***** Code

BCD2bin16:
andi fBCD2,0x0f ;mask away upper nibble of fBCD2
clr mp10H
mov mp10L,fBCD2 ;mp10H:mp10L = a
mov adder,fBCD1
rcall mul10a ;mp10H:mp10L = 10a+b
mov adder,fBCD1
rcall mul10b ;mp10H:mp10L = 10(10a+b)+c
mov adder,fBCD0
rcall mul10a ;mp10H:mp10L = 10(10(10a+b)+c)+d
mov adder,fBCD0
rcall mul10b ;mp10H:mp10L = 10(10(10(10a+b)+c)+d)+e
ret

;***************************************************************************
;*
;* "BCD2bin8" - BCD to 8-bit binary conversion
;*
;* This subroutine converts a 2-digit BCD number (fBCDH:fBCDL) to an
;* 8-bit number (tbin).
;*
;* Number of words :4 + return
;* Number of cycles :3/48 (Min/Max) + return
;* Low registers used :None
;* High registers used :2 (tbin/fBCDL,fBCDH)
;*
;* Modifications to make the routine accept a packed BCD number is indicated
;* as comments in the code. If the modifications are used, fBCDH shall be
;* loaded with the BCD number to convert prior to calling the routine.
;*
;***************************************************************************

;***** Subroutine Register Variables

.def tbin =r16 ;binary result

.def fBCDL =r16 ;lower digit of BCD input
.def fBCDH =r17 ;higher digit of BCD input

;***** Code

BCD2bin8:
;--------------------------------------------------------------------------
;| ;For packed BCD input, add these two lines
;| mov tbin,fBCDH ;copy input to result
;| andi tbin,$0f ;clear higher nibble of result
;--------------------------------------------------------------------------

BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1

brcs BCDb8_1 ;if carry not set
;--------------------------------------------------------------------------
;| ;For packed BCD input, replace the above
;| ;two lines with these.
;| subi fBCDH,$10 ;MSD = MSD - 1
;| brmi BCDb8_1 ;if Zero flag not set
;--------------------------------------------------------------------------
subi tbin,-10 ; result = result + 10
rjmp BCDb8_0 ; loop again
BCDb8_1:ret ;else return

;***************************************************************************
;*
;* "BCDadd" - 2-digit packed BCD addition
;*
;* This subroutine adds the two unsigned 2-digit BCD numbers
;* "BCD1" and "BCD2". The result is returned in "BCD1", and the overflow
;* carry in "BCD2".
;*
;* Number of words :19
;* Number of cycles :17/20 (Min/Max)
;* Low registers used :None
;* High registers used :3 (BCD1,BCD2,tmpadd)
;*
;***************************************************************************

;***** Subroutine Register Variables

.def BCD1 =r16 ;BCD input value #1

.def BCD2 =r17 ;BCD input value #2
.def tmpadd =r18 ;temporary register

;***** Code

BCDadd:
ldi tmpadd,6 ;value to be added later
add BCD1,BCD2 ;add the numbers binary
clr BCD2 ;clear BCD carry
brcc add_0 ;if carry not clear
ldi BCD2,1 ; set BCD carry
add_0: brhs add_1 ;if half carry not set
add BCD1,tmpadd ; add 6 to LSD
brhs add_2 ; if half carry not set (LSD <= 9)
subi BCD1,6 ; restore value
rjmp add_2 ;else
add_1: add BCD1,tmpadd ; add 6 to LSD
add_2: swap tmpadd
add BCD1,tmpadd ;add 6 to MSD
brcs add_4 ;if carry not set (MSD <= 9)
sbrs BCD2,0 ; if previous carry not set
subi BCD1,$60 ; restore value
add_3: ret ;else
add_4: ldi BCD2,1 ; set BCD carry
ret

;***************************************************************************
;*
;* "BCDsub" - 2-digit packed BCD subtraction
;*
;* This subroutine subtracts the two unsigned 2-digit BCD numbers
;* "BCDa" and "BCDb" (BCDa - BCDb). The result is returned in "BCDa", and
;* the underflow carry in "BCDb".
;*
;* Number of words :13
;* Number of cycles :12/17 (Min/Max)
;* Low registers used :None
;* High registers used :2 (BCDa,BCDb)
;*
;***************************************************************************

;***** Subroutine Register Variables

.def BCDa =r16 ;BCD input value #1

.def BCDb =r17 ;BCD input value #2

;***** Code

BCDsub:
sub BCDa,BCDb ;subtract the numbers binary
clr BCDb
brcc sub_0 ;if carry not clear
ldi BCDb,1 ; store carry in BCDB1, bit 0
sub_0: brhc sub_1 ;if half carry not clear
subi BCDa,$06 ; LSD = LSD - 6
sub_1: sbrs BCDb,0 ;if previous carry not set
ret ; return
subi BCDa,$60 ;subtract 6 from MSD
ldi BCDb,1 ;set underflow carry
brcc sub_2 ;if carry not clear
ldi BCDb,1 ; clear underflow carry
sub_2: ret

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of usage and to
;* verify correct operation.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code

RESET:
ldi temp,low(RAMEND)
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)

;***** Convert 54,321 to 2.5-byte packed BCD format

ldi fbinL,low(54321)
ldi fbinH,high(54321)
rcall bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321

;***** Convert 55 to 2-byte BCD

ldi fbin,55
rcall bin2BCD8 ;result: tBCDH:tBCDL = 0505

;***** Convert $065535 to a 16-bit binary number

ldi fBCD2,$06
ldi fBCD1,$55
ldi fBCD0,$35
rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535)

;***** Convert $0403 (43) to an 8-bit binary number

ldi fBCDL,3
ldi fBCDH,4
rcall BCD2bin8 ;result: tbin = $2b (43)

;***** Add BCD numbers 51 and 79

ldi BCD1,$51
ldi BCD2,$79
rcall BCDadd ;result: BCD2:BCD1=$0130

;***** Subtract BCD numbers 72 - 28

ldi BCDa,$72
ldi BCDb,$28
rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44

;***** Subtract BCD numbers 0 - 90

ldi BCDa,$00
ldi BCDb,$90
rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
http://avr-asm.tripod.com/avr204.html (1 of 2)1/20/2009 8:42:33 PM
16 BIT MATH (AVR 202)

share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language

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16 BIT MATH (AVR 202)

The AVR Assembler Site

BCD MATH (AVR 204)

MATH 202 rjmp RESET ;reset handle

CRC 236 .def tBCD0 =r13 ;BCD value digits 1 and 0

;***** "mul10a"/"mul10b" Subroutine Register Variables

.def copyL =r12 ;temporary register

;***** Code

mul10a: ;***** multiplies "mp10H:mp10L" with 10 and adds "adder" high

;***** Main Routine Register Variables

.def tbinL =r14 ;Low byte of binary result (same as

mp10L)
.def tbinH =r15 ;High byte of binary result (same as
mp10H)
.def fBCD0 =r16 ;BCD value digits 1 and 0
.def fBCD1 =r17 ;BCD value digits 2 and 3
.def fBCD2 =r18 ;BCD value digit 5

;***** Code

;***** Subroutine Register Variables

.def tbin =r16 ;binary result

.def fBCDL =r16 ;lower digit of BCD input
.def fBCDH =r17 ;higher digit of BCD input

;***** Code

BCDb8_0:subi fBCDH,1 ;fBCDH = fBCDH - 1

;***** Subroutine Register Variables

.def BCD1 =r16 ;BCD input value #1

.def BCD2 =r17 ;BCD input value #2
.def tmpadd =r18 ;temporary register

;***** Code

;***** Subroutine Register Variables

.def BCDa =r16 ;BCD input value #1

.def BCDb =r17 ;BCD input value #2

;***** Code

;
****************************************************************************
;*
;* Test Program
;*
;* This program calls all the subroutines as an example of usage and to
;* verify correct operation.
;*
;
****************************************************************************

;***** Main Program Register variables

.def temp =r16 ;temporary storage variable

;***** Code

RESET:
ldi temp,low(RAMEND)
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp ;init Stack Pointer (remove for AT90Sxx0x)

;***** Convert 54,321 to 2.5-byte packed BCD format

ldi fbinL,low(54321)
ldi fbinH,high(54321)
rcall bin2BCD16 ;result: tBCD2:tBCD1:tBCD0 = $054321

;***** Convert 55 to 2-byte BCD

ldi fbin,55
rcall bin2BCD8 ;result: tBCDH:tBCDL = 0505

;***** Convert $065535 to a 16-bit binary number

ldi fBCD2,$06
ldi fBCD1,$55
ldi fBCD0,$35
rcall BCD2bin16 ;result: tbinH:tbinL = $ffff (65,535)

;***** Convert $0403 (43) to an 8-bit binary number

ldi fBCDL,3
ldi fBCDH,4
rcall BCD2bin8 ;result: tbin = $2b (43)

;***** Add BCD numbers 51 and 79

ldi BCD1,$51
ldi BCD2,$79
rcall BCDadd ;result: BCD2:BCD1=$0130

;***** Subtract BCD numbers 72 - 28

ldi BCDa,$72
ldi BCDb,$28
rcall BCDsub ;result: BCDb=$00 (positive result), BCDa=44

;***** Subtract BCD numbers 0 - 90

ldi BCDa,$00
ldi BCDb,$90
rcall BCDsub ;result: BCDb=$01 (negative result), BCDa=10

forever:rjmp forever

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
share the same basic core but with different peripheral and memory
combinations. Some models (notably, the ATmega range) have additional
instructions to make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC Core Running
Many Single Cycle Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal Oscillators
Internal, Self-Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog
Comparators LCD Controller Support 10-Bit A/D Converters, with multiplex
of up to 16 channels Brownout Detection Watchdog Timer (WDT) Low-
voltage Devices Operating Down to 1.8v Multiple Power-Saving Sleep
Modes picoPower Devices Atmel AVR assembler programming language
Atmel AVR machine programming language Atmel AVR From Wikipedia,
the free encyclopedia (Redirected from Avr) Jump to: navigation, search
The AVRs are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen and Vegard
Wollan, at the Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two architects.
Atmel recently released the Atmel AVR32 line of microcontrollers. These
are 32-bit RISC devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of "AVR" in this
article refers to the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced Virtual RISC. It's
also rumoured to stand for the company's founders: Alf and Vegard, who
are evasive when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4 Footnotes 5 See
also 6 External Links 6.1 Atmel Official Links 6.2 AVR Forums & Discussion
Groups 6.3 Machine Language Development 6.4 C Language Development
6.5 BASIC & Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die, removing the need
for external memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-permanent Flash
memory. Each instruction for the AVR line is either 16 or 32 bits in length.
The Flash memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O registers (002016-
005F16). The actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on some more
extensive devices, in which case memory mapped I/O registers will occupy
a portion of the SRAM.) Even though there are separate addressing
schemes and optimized opcodes for register file and I/O register access, all
can still be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is most often used
for long-term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs have a single
level pipeline design. The next machine instruction is fetched as the
current one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit microcontrollers.
The AVR family of processors were designed for the efficient execution of
compiled C code. The AVR instruction set is more orthogonal than most
eight-bit microcontrollers, however, it is not completely regular: Pointer
registers X, Y, and Z have addressing capabilities that are different from
each other. Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31 have
different addressing capabilities than I/O ports 32 to 63. CLR affects flags,
while SER does not, even though they are complementary instructions.
CLR set all bits to zero and SER sets them to one. (Note though, that
neither CLR nor SER are native instructions. Instead CLR is syntactic
sugar for [produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit] Speed The
AVR line can normally support clock speeds from 0-16MHz, with some
devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations
on the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz.
[edit] Development AVRs have a large following due to the free and
inexpensive development tools available, including reasonably priced
development boards and free development software. The AVRs are
marketed under various names that share the same basic core but with
different peripheral and memory combinations. Some models (notably, the
ATmega range) have additional instructions to make arithmetic faster.
Compatibility amongst chips is fairly good. See external links for sites
relating to AVR development. [edit] Features Current AVRs offer a wide
range of features: RISC Core Running Many Single Cycle Instructions
Multifunction, Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-Programmable
Instruction Flash Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section with
Independent Lock Bits for Protection Internal Data EEPROM up to 4KB
Internal SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated I²C
Compatible Two-Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB Controller Support
Proper High-speed hardware & Hub controller with embedded AVR. Also
freely available low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD Controller Support
10-Bit A/D Converters, with multiplex of up to 16 channels Brownout
Detection Watchdog Timer (WDT) Low-voltage Devices Operating Down to
1.8v Multiple Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia (Redirected
from Avr) Jump to: navigation, search The AVRs are a family of RISC
microcontrollers from Atmel. Their internal architecture was conceived by
two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian Institute
of Technology (NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the Atmel AVR32
line of microcontrollers. These are 32-bit RISC devices featuring SIMD and
DSP instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2
Development 3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other AVR
Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with programs and
data stored and addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external memory
(though still available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each instruction
for the AVR line is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the ATmega64x
line has 64Kbytes of Flash. Almost all AVR devices are self-programmable.
[edit] Data Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The working registers
are mapped in as the first thirty-two memory spaces (000016-001F16)
followed by the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that the I/O register
space may be larger on some more extensive devices, in which case
memory mapped I/O registers will occupy a portion of the SRAM.) Even
though there are separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all devices
have on-die EEPROM. This is most often used for long-term parameter
storage to be retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline design. The
next machine instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs relatively fast
among the eight-bit microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register
locations R0 to R15 have different addressing capabilities than register
locations R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while SER does not,
even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for [produces the same
machine code as] EOR R,R while SER is syntactic sugar for LDI R,$FF.
Math operations such as EOR modify flags while moves/loads/stores/
branches such as LDI do not.) [edit] Speed The AVR line can normally
support clock speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external clocks or
resonator circuitry. Because many operations on the AVR are single cycle,
the AVR can achieve up to 1MIPS per MHz. [edit] Development AVRs have a
large following due to the free and inexpensive development tools
available, including reasonably priced development boards and free
development software. The AVRs are marketed under various names that
http://avr-asm.tripod.com/id77.html (1 of 2)1/20/2009 8:43:13 PM
16 BIT MATH (AVR 202)

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16 BIT MATH (AVR 202)

The AVR Assembler Site

DECIMAL TO ASCII ROUTINE

HOME
RETRO_DAN
; universal signed, unsigned decimal number to ASCII
ASM FORUM convert
ASM MATH ; MSB -> LSB = r23:r22 ZH:ZL
_print24bit: ; Print unsigned 24 bit
TUTORIAL #1
values
TUTORIAL #2 clr r23
TUTORIAL #3 rjmp _prnum

MATH 200 _printsdecw: ; Print signed decimal (16

MATH 200b bit)
sbrs zh,7 ; Is the number < 0 ?
MATH 201 rjmp _printdecw ; No, print 0 to 32767
MATH 202 ser r22
ser r23
MATH 32X
rjmp _printsdecdw
MATH YX
_printdecb: ; Print (8 bit) value
DIV16 XX
clr zh
DIV 24 24
DIV 3216 _printdecw: ; Print unsigned decimal
(16 bit)
FLOAT 128 clr r22
SQRT16 clr r23

MATH 202 _printsdecdw: ; Print signed decimal (32

MATH 202 bit)
sbrs r23,7
DEC ASCII
rjmp _printdecdw
INT ASCII com zl
com zh
HX2ASC
com r22
AVG8 222 com r23
FFT7 subi zl,-1
sbci zh,-1
COPY 102 sbci r22,-1
LPM 108 sbci r23,-1
ldi r24,'-'
EPROM 100 rcall _putchar
SER EPROM
_printdecdw: ; Print unsigned decimal
DFLASH AT45
(32 bit)
FLASH CARD _prnum:
push yl
VFX SMIL
push yh
VFX MEM clr r1
SORT 220 clr r2
clr r3
CRC 236 clr r4
XMODEM REC clr r5
ldi r20,32
UART 304 _prnum1:
UART 305 ldi yl,1
clr yh
UART 128
ldi r21,5
UART BUFF _prnum2:
ldi r25,51
USB 232
ld r24,y
AVR ISP add r24,r25
ISP 2313 sbrc r24,7
andi r25,15
ISP 1200 sbrc r24,3
AVR SPI andi r25,240
sub r24,r25
I2C 300 st y+,r24
I2C 302 dec r21
brne _prnum2
I2C TWI26
lsl zl
I2C/TWI 128 rol zh
I2C/TWI AT8 rol r22
rol r23
DALLAS-1W rol r1
DALLAS CRC rol r2
rol r3
ETHNET 8019 rol r4
TEA rol r5
dec r20
ADC 128 brne _prnum1
ADC 10B clt
ldi zl,6
ADC 400
clr zh
ADC 401 _prnum3:
THERM 232 ld r24,-z
rcall _prnum5
IRD 410 cpi zl,2
LCD HD44 brsh _prnum3
brts _prnum4
LCD 2313 set
LCD44 2313 mov r24,r1
rcall _prnum6
KBD 240 _prnum4:
MUX 242 pop yh
pop yl
KBD PS2
ret
KBD PC/128 _prnum5:
PS2 EMU push r24
swap r24
BOOT MG8 rcall _prnum6
BOOT DR8 pop r24
_prnum6:
ALM CLK andi r24,0x0f ; convert to ASCII and
CLOCK 8564 eliminate leading zeros
subi r24,-'0'
90 DAYS
brts _putchar
DELAYS cpi r24,'0'
brne _prnum7
CALL ID
; if you want leading spaces for nice format, add
DTMF 314 here "ldi r24, ' ' rjmp _putchar
PWM 6CH ret
_prnum7:
PWM 10K set
ENCODE _putchar:
rjmp _my_output_char_routine ; RS232, LCD, I2C
STH-11 etc, etc...
ATMEL CORP
AVR
BUTTERFLY
AVR BOOK

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia

(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their
internal architecture was conceived by two students: Alf-Egil
Bogen and Vegard Wollan, at the Norwegian Institute of
Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently
released the Atmel AVR32 line of microcontrollers. These are
32-bit RISC devices featuring SIMD and DSP instructions,
along with many additional features for audio and video
processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC &
Other AVR Languages 6.6 AVR Butterfly Specific 6.7 Other
AVR Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line
is either 16 or 32 bits in length. The Flash memory is
addressed using 16 bit word sizes. The size of the program
memory is indicated in the naming of the device itself. For
instance, the ATmega64x line has 64Kbytes of Flash. Almost
all AVR devices are self-programmable. [edit] Data Memory
and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-
two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first
thirty-two memory spaces (000016-001F16) followed by the 64
I/O registers (002016-005F16). The actual usable RAM starts
after both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify
flags while moves/loads/stores/branches such as LDI do not.)
[edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards
and free development software. The AVRs are marketed
under various names that share the same basic core but with
different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle
Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available
low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete
with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to
stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction for
the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists
of the register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify
flags while moves/loads/stores/branches such as LDI do not.)
[edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards
and free development software. The AVRs are marketed
under various names that share the same basic core but with
different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle
Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available
low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the
Norwegian Institute of Technology (NTH] and further
developed at Atmel Norway, a subsidiary founded by the two
architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional
features for audio and video processing, intended to compete
with ARM based processors. Note that the use of "AVR" in
this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to
stand for Advanced Virtual RISC. It's also rumoured to stand
for the company's founders: Alf and Vegard, who are evasive
when questioned about it. Contents [hide] 1 Device Overview
1.1 Program Memory 1.2 Data Memory and Registers 1.3
EEPROM 1.4 Program Execution 1.5 Speed 2 Development 3
Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel
Official Links 6.2 AVR Forums & Discussion Groups 6.3
Machine Language Development 6.4 C Language
Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview
The AVR is a Harvard architecture machine with programs
and data stored and addressed separately. Flash, EEPROM,
and SRAM are all integrated onto a single die, removing the
need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are
stored in semi-permanent Flash memory. Each instruction for
the AVR line is either 16 or 32 bits in length. The Flash
memory is addressed using 16 bit word sizes. The size of the
program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of
Flash. Almost all AVR devices are self-programmable. [edit]
Data Memory and Registers The data address space consists
of the register file, I/O registers, and SRAM. The AVRs have
thirty-two single-byte registers and are classified as 8-bit
RISC devices. The working registers are mapped in as the
first thirty-two memory spaces (000016-001F16) followed by
the 64 I/O registers (002016-005F16). The actual usable RAM
starts after both these sections (address 006016). (Note that
the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic
sugar for LDI R,$FF. Math operations such as EOR modify
flags while moves/loads/stores/branches such as LDI do not.)
[edit] Speed The AVR line can normally support clock speeds
from 0-16MHz, with some devices reaching 20MHz. Lower
powered operation usually requires a reduced clock speed.
All AVRs feature an on-chip oscillator, removing the need for
external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards
and free development software. The AVRs are marketed
under various names that share the same basic core but with
different peripheral and memory combinations. Some models
(notably, the ATmega range) have additional instructions to
make arithmetic faster. Compatibility amongst chips is fairly
good. See external links for sites relating to AVR
development. [edit] Features Current AVRs offer a wide range
of features: RISC Core Running Many Single Cycle
Instructions Multifunction, Bi-directional I/O Ports with
Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash
Memory up to 256K In-System Programmable using ICSP,
JTAG, or High Voltage methods Optional Boot Code Section
with Independent Lock Bits for Protection Internal Data
EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM
Specific) Controller models Dedicated I²C Compatible Two-
Wire Interface (TWI) Synchronous/Asynchronous Serial
Peripherals (UART/USART) (As used with RS-232,RS-485, and
more) Serial Peripheral Interface (SPI) CAN Controller
Support USB Controller Support Proper High-speed hardware
& Hub controller with embedded AVR. Also freely available
low-speed (HID) software emulation Ethernet Controller
Support Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer
(WDT) Low-voltage Devices Operating Down to 1.8v Multiple
Power-Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/decascii.html (1 of 2)1/20/2009 8:44:04 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/decascii.html (2 of 2)1/20/2009 8:44:04 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

INTEGER TO ASCII ROUTINE

HOME
RETRO_DAN
;
ASM FORUM ******************************************************************************
ASM MATH ; Author : Nay Oo
; DESCRIPTION :
TUTORIAL #1
; - This program convert an integer number to ASCII
TUTORIAL #2 ; AVR Newbie Learning program
TUTORIAL #3 ; - The integer Range (0..127)
; - You can use AVRStudio 4 simulator to see the
MATH 200 register
MATH 200b ; contents (recommended)
;
MATH 201 ; uController : AT90S8515
MATH 202 ; Development Board : STK500
;
MATH 32X
;
MATH YX ;
; AUTHOR NOTE:
DIV16 XX
; This file was written by me to educate myself in
DIV 24 24 AVR
DIV 3216 ; Initial ideas was gathered from the http://www.
avrbeginners.net/
FLOAT 128 ; Please do refer to them for more indept
SQRT16 theroritical aspects.
;
MATH 202 ; After the convertion is done, you can send these
MATH 202 ASCII coded
; numbers to UART,USB, LCD interface, etc.
DEC ASCII
;
INT ASCII ; If you have any thing to discuss about this file,
you can contact
HX2ASC
; me via my personal email : [email protected]
AVG8 222 ;
FFT7 ;
******************************************************************************
COPY 102
LPM 108 ;* Include Microcontroller Device specific file
.include "8515def.inc"
EPROM 100
SER EPROM ;* Register Variable Declaration Here
.def temp = r16 ; temporary storage
DFLASH AT45
register
FLASH CARD .def intval = r17 ; the variable which
stores the integer value
VFX SMIL
.def HundredCounter = r18 ; eg. 127 = '1'
VFX MEM .def TenthCounter = r19 ; eg. 127 = '2'
SORT 220 .def OneCounter = r20 ; eg. 127 = '7'

CRC 236 ;* Integer Value

XMODEM REC .equ Number=127 ; You can change
any number from 0 to 127
UART 304
UART 305
.org 0x0000
UART 128
rjmp RESET ; program reset vector
UART BUFF
USB 232
;* Integer to ASCII converter subrountine here
AVR ISP IntToASCII:
ISP 2313 cpi intVal,100 ;
brge DivideBy100 ; jump if
ISP 1200 (intVal>=100)
AVR SPI cpi intVal,10
brge DivideBy10 ; jump if
I2C 300 (intVal>=10)
I2C 302 mov OneCounter,IntVal
add HundredCounter,temp ; here, we got
I2C TWI26
there single digits
I2C/TWI 128 add TenthCounter,temp ; from that, we
I2C/TWI AT8 convert them to
add OneCounter,temp ; ASCII values !!!
DALLAS-1W ret
DALLAS CRC
DivideBy100:
ETHNET 8019 subi intVal,100
TEA inc HundredCounter
rjmp IntToASCII
ADC 128
ADC 10B DivideBy10:
subi intVal,10
ADC 400
inc TenthCounter
ADC 401 rjmp IntToASCII
THERM 232
IRD 410 ;* Main Program Starts here
LCD HD44 RESET:
ldi temp,low(RAMEND) ; STACK pointer
LCD 2313 location
LCD44 2313 out SPL,temp ; started
from the
KBD 240 ldi temp,high(RAMEND) ; end of SRAM
MUX 242 out SPH,temp ; RAMEND
is declared in 8515def.inc file
KBD PS2
KBD PC/128 ldi HundredCounter,0 ; set counters
PS2 EMU values to zero
ldi TenthCounter,0 ;
BOOT MG8 ldi OneCounter,0 ;
BOOT DR8 ldi temp,48 ; ASCII =
Number + 48
ALM CLK ;
CLOCK 8564 In ASCII table, we can see that '0' is 48 (0x30)
;
90 DAYS
therefore, need to add 48 to the single digits
DELAYS
ldi intVal,Number
CALL ID
rcall IntToASCII ; subroutine call
DTMF 314 ;
PWM 6CH which convert integer value to
;
PWM 10K ASCII value
ENCODE
forever: rjmp forever ; infinite loop
STH-11
ATMEL CORP
AVR
BUTTERFLY
AVR BOOK

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia (Redirected from Avr)
Jump to: navigation, search The AVRs are a family of RISC microcontrollers
from Atmel. Their internal architecture was conceived by two students: Alf-
Egil Bogen and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary founded by the
two architects. Atmel recently released the Atmel AVR32 line of
microcontrollers. These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio and video
processing, intended to compete with ARM based processors. Note that the
use of "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development
3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development
6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word sizes. The
size of the program memory is indicated in the naming of the device itself.
For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will occupy a portion of
the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost
all devices have on-die EEPROM. This is most often used for long-term
parameter storage to be retrieved even after cycling the power of the device.
[edit] Program Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register locations
R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR development.
[edit] Features Current AVRs offer a wide range of features: RISC Core
Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices
Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the Atmel
AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio
and video processing, intended to compete with ARM based processors.
Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development
3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development
6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word sizes. The
size of the program memory is indicated in the naming of the device itself.
For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will occupy a portion of
the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost
all devices have on-die EEPROM. This is most often used for long-term
parameter storage to be retrieved even after cycling the power of the device.
[edit] Program Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register locations
R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR development.
[edit] Features Current AVRs offer a wide range of features: RISC Core
Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices
Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs are a family of
RISC microcontrollers from Atmel. Their internal architecture was conceived
by two students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel Norway, a
subsidiary founded by the two architects. Atmel recently released the Atmel
AVR32 line of microcontrollers. These are 32-bit RISC devices featuring
SIMD and DSP instructions, along with many additional features for audio
and video processing, intended to compete with ARM based processors.
Note that the use of "AVR" in this article refers to the 8-bit RISC line of Atmel
AVR Microcontrollers. The acronym AVR has been reported to stand for
Advanced Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned about it.
Contents [hide] 1 Device Overview 1.1 Program Memory 1.2 Data Memory
and Registers 1.3 EEPROM 1.4 Program Execution 1.5 Speed 2 Development
3 Features 4 Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language Development
6.4 C Language Development 6.5 BASIC & Other AVR Languages 6.6 AVR
Butterfly Specific 6.7 Other AVR Links [edit] Device Overview The AVR is a
Harvard architecture machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available on some
devices). [edit] Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is either 16 or 32
bits in length. The Flash memory is addressed using 16 bit word sizes. The
size of the program memory is indicated in the naming of the device itself.
For instance, the ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and SRAM. The
AVRs have thirty-two single-byte registers and are classified as 8-bit RISC
devices. The working registers are mapped in as the first thirty-two memory
spaces (000016-001F16) followed by the 64 I/O registers (002016-005F16).
The actual usable RAM starts after both these sections (address 006016).
(Note that the I/O register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will occupy a portion of
the SRAM.) Even though there are separate addressing schemes and
optimized opcodes for register file and I/O register access, all can still be
addressed and manipulated as if they were in SRAM. [edit] EEPROM Almost
all devices have on-die EEPROM. This is most often used for long-term
parameter storage to be retrieved even after cycling the power of the device.
[edit] Program Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is executing.
Most instructions take just one or two clock cycles, making AVRs relatively
fast among the eight-bit microcontrollers. The AVR family of processors
were designed for the efficient execution of compiled C code. The AVR
instruction set is more orthogonal than most eight-bit microcontrollers,
however, it is not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other. Register locations
R0 to R15 have different addressing capabilities than register locations R16
to R31. I/O ports 0 to 31 have different addressing capabilities than I/O ports
32 to 63. CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native instructions. Instead
CLR is syntactic sugar for [produces the same machine code as] EOR R,R
while SER is syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from 0-16MHz, with
some devices reaching 20MHz. Lower powered operation usually requires a
reduced clock speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS per MHz. [edit]
Development AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development
boards and free development software. The AVRs are marketed under
various names that share the same basic core but with different peripheral
and memory combinations. Some models (notably, the ATmega range) have
additional instructions to make arithmetic faster. Compatibility amongst
chips is fairly good. See external links for sites relating to AVR development.
[edit] Features Current AVRs offer a wide range of features: RISC Core
Running Many Single Cycle Instructions Multifunction, Bi-directional I/O
Ports with Internal, Configurable Pull-up Resistors Multiple Internal
Oscillators Internal, Self-Programmable Instruction Flash Memory up to
256K In-System Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for Protection
Internal Data EEPROM up to 4KB Internal SRAM up to 8K 8-Bit and 16-Bit
Timers PWM Channels & dead time generator Lighting (PWM Specific)
Controller models Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/USART) (As used
with RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed hardware &
Hub controller with embedded AVR. Also freely available low-speed (HID)
software emulation Ethernet Controller Support Universal Serial Interface
(USI) for Two or Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of up to 16
channels Brownout Detection Watchdog Timer (WDT) Low-voltage Devices
Operating Down to 1.8v Multiple Power-Saving Sleep Modes picoPower
Devices Atmel AVR assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/intascii.html (1 of 2)1/20/2009 8:44:37 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/intascii.html (2 of 2)1/20/2009 8:44:37 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

TWO HEX TO ASCII ROUTINES

HOME
RETRO_DAN
ASM FORUM ;-----------------------------------------------
ASM MATH ; HEX TO ASCII
;-----------------------------------------------
TUTORIAL #1
;I think, this was the smallest (only 10 words).
TUTORIAL #2
TUTORIAL #3 ;input: R16 = 8 bit value 0 ... 255
;output: R18, R17, R16 = digits
MATH 200 ;bytes: 20
MATH 200b ;
bcd:
MATH 201 ldi r18, -1 + '0'
MATH 202 _bcd1:
inc r18
MATH 32X
subi r16, 100
MATH YX brcc _bcd1
ldi r17, 10 + '0'
DIV16 XX
_bcd2:
DIV 24 24 dec r17
DIV 3216 subi r16, -10
brcs _bcd2
FLOAT 128 sbci r16, -'0'
SQRT16 ret

MATH 202
MATH 202 ;
**********************************************************************************************
DEC ASCII
;E. Seah
INT ASCII ;03/24/01
;HEX-TO-ASCII conversion subroutine
HX2ASC
;"high" registers : 4 (3 if "value" can be "low"
AVG8 222 register)
FFT7 ;"low" registers : 0 (1 if "value" can be "low" register)
;program words : 22+1 (including return)
COPY 102 ;
LPM 108 ;description : convert 0x00<="value"<=0xff to 3 digits of
ASCII in "hundreds","tens" and "ones"
EPROM 100 ;
SER EPROM _h2a: ldi hundreds,200 ;init hundreds for hundreds cp
loop
DFLASH AT45
ldi ones,2 ;init ones for hundreds cp loop
FLASH CARD
a100: cp value,hundreds
VFX SMIL
brlo sub100 ;if value=hundreds
VFX MEM sub value,hundreds ;remove 100s from value
SORT 220 subi ones,-0x30 ;?00<=x<=?99, 1st digit is '?'
mov hundreds,ones
CRC 236 ldi tens,90 ;init tens for tens cp loop
XMODEM REC ldi ones,9 ;init ones for tens cp loop
a10: cp value,tens
UART 304 brlo sub10 ;if value=tens
UART 305 sub value,tens ;remove 10s from value
subi ones,-0x30 ;?0<=x<=?9, 2nd digit is '?'
UART 128
mov tens,ones
UART BUFF
mov ones,value ;3rd digit is the remainder
USB 232
subi ones,-0x30 ;'ones' in ASCII
AVR ISP
ISP 2313 ret

ISP 1200 sub100: subi hundreds,100 ;for compare with value

AVR SPI subi ones,1 ;use ones as temp storage for 1st digit
rjmp a100
I2C 300
I2C 302 sub10: subi tens,10 ;for compare with value
subi ones,1 ;use ones as temp storage for 2nd digit
I2C TWI26
rjmp a10
I2C/TWI 128
I2C/TWI AT8
DALLAS-1W
DALLAS CRC
ETHNET 8019
TEA
ADC 128
ADC 10B
ADC 400
ADC 401
THERM 232 Programming the AVR Microcontrollers in Machine Language
IRD 410
LCD HD44 AVR
LCD 2313 << Prev | Ring Hub | Join | Rate| Next
LCD44 2313 >>
KBD 240 © WebRing Inc. Search
MUX 242
KBD PS2
KBD PC/128
Atmel AVR From Wikipedia, the free encyclopedia (Redirected
PS2 EMU from Avr) Jump to: navigation, search The AVRs are a family of
BOOT MG8 RISC microcontrollers from Atmel. Their internal architecture
BOOT DR8
ALM CLK
was conceived by two students: Alf-Egil Bogen and Vegard
CLOCK 8564 Wollan, at the Norwegian Institute of Technology (NTH] and
90 DAYS further developed at Atmel Norway, a subsidiary founded by
DELAYS
CALL ID
the two architects. Atmel recently released the Atmel AVR32
DTMF 314 line of microcontrollers. These are 32-bit RISC devices
PWM 6CH featuring SIMD and DSP instructions, along with many
PWM 10K
ENCODE
additional features for audio and video processing, intended to
STH-11 compete with ARM based processors. Note that the use of
ATMEL CORP "AVR" in this article refers to the 8-bit RISC line of Atmel AVR
AVR
BUTTERFLY
Microcontrollers. The acronym AVR has been reported to stand
AVR BOOK for Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM
1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links
[edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a
single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash.
Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR
family of processors were designed for the efficient execution
of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is
not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31
have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI
do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and
free development software. The AVRs are marketed under
various names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated
I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand
for Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM
1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links
[edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a
single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash.
Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR
family of processors were designed for the efficient execution
of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is
not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31
have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI
do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and
free development software. The AVRs are marketed under
various names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated
I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language Atmel AVR From Wikipedia, the free encyclopedia
(Redirected from Avr) Jump to: navigation, search The AVRs
are a family of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with many
additional features for audio and video processing, intended to
compete with ARM based processors. Note that the use of
"AVR" in this article refers to the 8-bit RISC line of Atmel AVR
Microcontrollers. The acronym AVR has been reported to stand
for Advanced Virtual RISC. It's also rumoured to stand for the
company's founders: Alf and Vegard, who are evasive when
questioned about it. Contents [hide] 1 Device Overview 1.1
Program Memory 1.2 Data Memory and Registers 1.3 EEPROM
1.4 Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR Links
[edit] Device Overview The AVR is a Harvard architecture
machine with programs and data stored and addressed
separately. Flash, EEPROM, and SRAM are all integrated onto a
single die, removing the need for external memory (though still
available on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory. Each
instruction for the AVR line is either 16 or 32 bits in length. The
Flash memory is addressed using 16 bit word sizes. The size of
the program memory is indicated in the naming of the device
itself. For instance, the ATmega64x line has 64Kbytes of Flash.
Almost all AVR devices are self-programmable. [edit] Data
Memory and Registers The data address space consists of the
register file, I/O registers, and SRAM. The AVRs have thirty-two
single-byte registers and are classified as 8-bit RISC devices.
The working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive devices,
in which case memory mapped I/O registers will occupy a
portion of the SRAM.) Even though there are separate
addressing schemes and optimized opcodes for register file
and I/O register access, all can still be addressed and
manipulated as if they were in SRAM. [edit] EEPROM Almost all
devices have on-die EEPROM. This is most often used for long-
term parameter storage to be retrieved even after cycling the
power of the device. [edit] Program Execution Atmel's AVRs
have a single level pipeline design. The next machine
instruction is fetched as the current one is executing. Most
instructions take just one or two clock cycles, making AVRs
relatively fast among the eight-bit microcontrollers. The AVR
family of processors were designed for the efficient execution
of compiled C code. The AVR instruction set is more
orthogonal than most eight-bit microcontrollers, however, it is
not completely regular: Pointer registers X, Y, and Z have
addressing capabilities that are different from each other.
Register locations R0 to R15 have different addressing
capabilities than register locations R16 to R31. I/O ports 0 to 31
have different addressing capabilities than I/O ports 32 to 63.
CLR affects flags, while SER does not, even though they are
complementary instructions. CLR set all bits to zero and SER
sets them to one. (Note though, that neither CLR nor SER are
native instructions. Instead CLR is syntactic sugar for
[produces the same machine code as] EOR R,R while SER is
syntactic sugar for LDI R,$FF. Math operations such as EOR
modify flags while moves/loads/stores/branches such as LDI
do not.) [edit] Speed The AVR line can normally support clock
speeds from 0-16MHz, with some devices reaching 20MHz.
Lower powered operation usually requires a reduced clock
speed. All AVRs feature an on-chip oscillator, removing the
need for external clocks or resonator circuitry. Because many
operations on the AVR are single cycle, the AVR can achieve
up to 1MIPS per MHz. [edit] Development AVRs have a large
following due to the free and inexpensive development tools
available, including reasonably priced development boards and
free development software. The AVRs are marketed under
various names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction, Bi-
directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-System
Programmable using ICSP, JTAG, or High Voltage methods
Optional Boot Code Section with Independent Lock Bits for
Protection Internal Data EEPROM up to 4KB Internal SRAM up
to 8K 8-Bit and 16-Bit Timers PWM Channels & dead time
generator Lighting (PWM Specific) Controller models Dedicated
I²C Compatible Two-Wire Interface (TWI) Synchronous/
Asynchronous Serial Peripherals (UART/USART) (As used with
RS-232,RS-485, and more) Serial Peripheral Interface (SPI) CAN
Controller Support USB Controller Support Proper High-speed
hardware & Hub controller with embedded AVR. Also freely
available low-speed (HID) software emulation Ethernet
Controller Support Universal Serial Interface (USI) for Two or
Three-Wire Synchronous Data Transfer Analog Comparators
LCD Controller Support 10-Bit A/D Converters, with multiplex of
up to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR assembler
programming language Atmel AVR machine programming
language
http://avr-asm.tripod.com/hx2asc.html (1 of 2)1/20/2009 8:45:10 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/hx2asc.html (2 of 2)1/20/2009 8:45:10 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

8 POINT MOVING AVERAGE (AVR 222)

HOME
RETRO_DAN
;**** A P P L I C A T I O N N O T E A V R 2 2 2
ASM FORUM ************************
ASM MATH ;*
;* Title: 8-Point Moving Average Filter
TUTORIAL #1
;* Version: 1.0
TUTORIAL #2 ;* Last updated: 97.07.04
TUTORIAL #3 ;* Target: AT90Sxx1x (Devices with SRAM)
;*
MATH 200 ;* Support E-mail: [email protected]
MATH 200b ;*
;* DESCRIPTION
MATH 201 ;* This Application note shows an implementation of an
MATH 202 8-point Moving
;* Average (MAV) filter. The program filters a data
MATH 32X
array containing SIZE
MATH YX ;* elements starting at T_START. The App. note contains
a test
DIV16 XX
;* program which copies a 60-byte block of data from
DIV 24 24 program memory to
DIV 3216 ;* SRAM and filters the data. Note that the ends of the
data array are not
FLOAT 128 ;* filtered.
SQRT16 ;*
;
MATH 202 ***************************************************************************
MATH 202
.include "8515def.inc"
DEC ASCII
INT ASCII .equ SIZE =60 ;data array size
.equ TABLE_L =$60 ;Low SRAM address
HX2ASC
of first data element
AVG8 222 .equ TABLE_H =$00 ;High SRAM address
FFT7 of first data element

COPY 102 rjmp RESET ;Reset Handle

LPM 108
;
EPROM 100 ***************************************************************************
SER EPROM ;*
;* "mav8"
DFLASH AT45
;*
FLASH CARD ;* This subroutine filters SIZE bytes with the first
element in SRAM
VFX SMIL
;* location T_START. The filter routine uses an 8-byte
VFX MEM ring buffer which
SORT 220 ;* occupies working registers r0-r7. As filtering
progresses, this ring
CRC 236 ;* buffer always contains the 8-byte window to be
XMODEM REC averaged.
;*
UART 304 ;* Number of words :31 + return
UART 305 ;* Number of cycles :59 + (SIZE-7)*75 + return
;* Low registers used :11 (r0-r7,mav_tmp,AL,AH)
UART 128
;* High registers used :1 (t_size)
UART BUFF ;* Pointers used :X,Y,Z
;*
USB 232
;
AVR ISP ***************************************************************************
ISP 2313
;***** Subroutine Register Variables
ISP 1200
AVR SPI .def mav_tmp =r8 ;temprary
storage register
I2C 300 .def AL =r9 ;ring
I2C 302 buffer sum, low byte
.def AH =r10 ;ring
I2C TWI26
buffer sum, high byte
I2C/TWI 128 .def t_size =r16 ;size of
I2C/TWI AT8 table

DALLAS-1W ;***** Code

DALLAS CRC
mav8:
ETHNET 8019 clr YH
TEA clr YL ;init pointers
clr XH
ADC 128 clr XL
ADC 10B
;***** Fill ring buffer with first-8 byte data segment
ADC 400
ADC 401 mav8_1: ld mav_tmp,Z+ ;get SRAM
THERM 232 data
st Y+,mav_tmp ;store in register
IRD 410 cpi YL,8 ;got all?
LCD HD44 brne mav8_1 ;if not, loop more
sbiw ZL,5 ;Z points to first
LCD 2313 value to filter
LCD44 2313
mav8_2:
KBD 240 ;***** Find average
MUX 242 clr AH ;Clear avg High byte
clr AL ;Clear avg Low byte
KBD PS2
clr YL ;init Y-pointer
KBD PC/128 mav8_3: ld mav_tmp,Y+ ;
PS2 EMU add AL,mav_tmp ;add value to AL
adc AH,XH ;add carry to AH
BOOT MG8 (XH is zero)
BOOT DR8 cpi YL,8 ;added all ?
brne mav8_3 ;if not, loop
ALM CLK again
CLOCK 8564 lsr AH ;divide by 8
ror AL ;
90 DAYS
lsr AH ;
DELAYS ror AL ;
lsr AH ;
CALL ID
ror AL ;
DTMF 314 ldd mav_tmp,Z+5 ;get next value to
PWM 6CH buffer
st X+,mav_tmp ;store to buffer
PWM 10K andi XL,$07 ;mask away pointer
ENCODE upper bits
st Z+,AL ;store average
STH-11 dec t_size
ATMEL CORP cpi t_size,4 ;end of array?
brne mav8_2 ;if not, loop
AVR
more
BUTTERFLY ret
AVR BOOK
;
***************************************************************************
;*
;* Test Program
;*
;* This program copies 60 bytes of data from Program
memory to SRAM. It
;* then calls "mav8" to get the data filtered.
;*
;
***************************************************************************

RESET:

;***** Main program Register variables

.def temp =r16

;***** Code

ldi temp,low(RAMEND)
out SPL,temp
ldi temp,high(RAMEND)
out SPH,temp ;init Stack Pointer

;***** Memory fill

clr ZH
ldi ZL,tableend*2+1 ;Z-pointer <- ROM table end
+ 1
ldi YL,low(256*TABLE_H+TABLE_L+SIZE)
ldi YH,high(256*TABLE_H+TABLE_L+SIZE)
;Y pointer <- SRAM table
end + 1
loop: lpm ;get ROM constant
st -Y,r0 ;store in SRAM and
decrement Y-pointer
sbiw ZL,1 ;decrement Z-pointer
cpi YL,TABLE_L ;if not done
brne loop ; loop more
cpi YH,TABLE_H
brne loop

;***** Filter data

ldi ZL,TABLE_L
ldi ZH,TABLE_H
ldi T_size,SIZE
rcall mav8

forever:rjmp forever

;***** 60 ROM Constants

table:
.db 120,196
.db 78,216
.db 78,100
.db 43,39
.db 241,43
.db 62,172
.db 109,69
.db 48,184
.db 215,231
.db 63,133
.db 216,8
.db 121,126
.db 188,98
.db 168,205
.db 157,172
.db 108,233
.db 80,255
.db 252,102
.db 198,0
.db 171,239
.db 107,114
.db 172,170
.db 17,45
.db 42,55
.db 34,174
.db 229,250
.db 12,179
.db 187,243
.db 44,231
tableend:
.db 76,48

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language
http://avr-asm.tripod.com/avr222.html (1 of 2)1/20/2009 8:45:45 PM
16 BIT MATH (AVR 202)

http://avr-asm.tripod.com/avr222.html (2 of 2)1/20/2009 8:45:45 PM

16 BIT MATH (AVR 202)

The AVR Assembler Site

7 BIT FAST FOURIER TRANSFORMATION

HOME
RETRO_DAN
This is an attempt to provide some FFT-math to the AVR
ASM FORUM community. Code has been tested with AVR-Studio4.
ASM MATH Works fine! FFT-Output is about 7 bits accurate.
TUTORIAL #1
******************
TUTORIAL #2 Known limitations and problems:
TUTORIAL #3 The code assumes input Data to be in the range -127
($81)...+127($FF).
MATH 200
MATH 200b Input-data is organized in SRAM as
Data1LowByte,Data1HighByte,
MATH 201 Data2LowByte,Data2HighByte,
MATH 202 Data3LowByte,Data3HighByte,....
MATH 32X
The FFT uses "in-place" operations and produces the
MATH YX following output:
DIV16 XX
Re(f0)LowByte,Re(f0HighByte),
DIV 24 24 Im(f0)LowByte,Im(f0HighByte),
DIV 3216 Re(f1)LowByte,Re(f1HighByte),
Im(f1)LowByte,Im(f1HighByte),....
FLOAT 128
SQRT16 Thus for n=128 data points (at the moment this is the
maximum), we get 64 frequency Data points.
MATH 202 CPU time for different FFT-lengths:
MATH 202 n=32 T=4,05ms
n=64 T=9,3ms
DEC ASCII
n=128 T=20,95ms
INT ASCII
**************************
HX2ASC
Things to do:
AVG8 222 1) I hope to find some inspiration on the scaling issue
FFT7 (to allow greater input range).
2) The loop-counters are still 8bit only, so these
COPY 102 would need to be 16bit to get longer FFTs working.
LPM 108 At the moment 64 frequency bins represent maximum
resolution.
EPROM 100 3) Include amplitude calculation, because most people
SER EPROM just want to know amplitude vs. frequency and nothing more.
DFLASH AT45
FLASH CARD ;
*************************************************************
VFX SMIL
;* FFT-Programm für bis zu 128
VFX MEM Datenpunkte *
SORT 220 ;* reelle Eingangsdaten werden "in place"
transformiert *
CRC 236 ;* 128 Datenpunkte ergeben 64 Real/Imaginär-
XMODEM REC Datenpaare *
;* Programmiert von niels laugwitz für avr-
UART 304 Mikrocontroller *
UART 305 ;
*************************************************************
UART 128
;
UART BUFF ;.device ATmega8
.include "m8def.inc" ;Lade die Registerdefinitionen
USB 232
für AT-Mega8
AVR ISP .DEF temprL = r2
ISP 2313 .def temprH = r3
.DEF tempiL = r4
ISP 1200 .def tempiH = r5
AVR SPI .DEF i1 = r2 ;Benutzt in for_Schleife_i
.def i2 = r3 ;Benutzt in for_Schleife_i
I2C 300 .DEF i3 = r4 ;Benutzt in for_Schleife_i
I2C 302 .def i4 = r5 ;Benutzt in for_Schleife_i
.def sortierzeiger=r0;
I2C TWI26
.def nullwert=r6
I2C/TWI 128 .def jjende=r7
I2C/TWI AT8 .def data1 = R8
.def data2 =R9
DALLAS-1W .def data3 =R10
DALLAS CRC .def data4 =R11
.def wrL=r12
ETHNET 8019 .def wrH=r13
TEA .def wiL=r14
.def wiH=r15
ADC 128 .DEF temp =r16
ADC 10B .DEF ii =r17
.DEF jj =r18
ADC 400
.DEF mmax =r19
ADC 401 .DEF j =r20
THERM 232 .DEF istep=r21
.def i =r22
IRD 410 .DEF m =r23
LCD HD44 .def zaehler=r24
.DEF tmp_lo =r18 ;Benutzt in for_Schleife_i
LCD 2313 .DEF tmp_hi =r19 ;Benutzt in for_Schleife_i
LCD44 2313
.set nn2 =128 ;Anzahl der Datenpunkte (FFT-
KBD 240 Länge)
MUX 242 ;8 =< nn2 =< 128
.equ h1r_lo =$60
KBD PS2
.equ h1r_hi =$61
KBD PC/128 .equ h1i_lo =$62
PS2 EMU .equ h1i_hi =$63
.equ h2r_lo =$64
BOOT MG8 .equ h2r_hi =$65
BOOT DR8 .equ h2i_lo =$66
.equ h2i_hi =$67
ALM CLK .equ sramstart = $0080
CLOCK 8564
.org $0000
90 DAYS
rjmp main ;reset
DELAYS .include "avr201.asm"
CALL ID
schleife_jj_body:
DTMF 314 ;Berechnung der Indexe i und j:
PWM 6CH mov i,m
mul jj,istep ;r0 := jj*istep
PWM 10K mov i,r0
ENCODE add i,m ;i:=m+jj*istep
mov temp,i
STH-11 add temp,mmax
ATMEL CORP mov j,temp ;j:=i+mmax
;Hole data[j] und data[j+1] aus dem SRAM
AVR
ldi XH,0
BUTTERFLY ldi XL,sramstart
AVR BOOK add XL,j
adc XH,nullwert ;da das Array Data als 16bit-Werte
abgespeichert ist,
add XL,j ;muss der Index verdoppelt werden.
adc XH,nullwert
ld data1,X+ ;hole Data[j]low-byte
ld data2,X+ ;hole Data[j]High-byte
ld data3,X+ ;Hole Data[j+1]low-Byte
ld data4,X ;hole Data[j+1]High-Byte
;Berechne tempr und tempi mehrere Multiplikationen
erfordern
;etwas platz in den oberen registern. Im Moment
brauchen wir die
; nicht: Also ab auf den Stack!
push r23
push r22
push r21
push r20
push r19
push r18
push r17
push r16
;Berechne tempr
movw r21:r20,wrh:wrl
movw r23:r22,data2:data1
rcall muls16x16_32 ;tempr:=wr*data[j] (16bit signed)
MOV temprH,r18 ;we take just the middle-result-
bytes
MOV temprL,r17
movw r21:r20,wih:wil
movw r23:r22,data4:data3
rcall muls16x16_32 ;tempi:=wi*data[j+1] (16bit signed)
MOV tempiH,r18 ;we take just the middle-result-
bytes
MOV tempiL,r17
sub temprL,tempiL
sbc temprH,tempiH ;tempr := wr*data[j]-wi*data[j
+1]
;Berechne tempi
push temprL
push temprH
movw r21:r20,wrh:wrl
movw r23:r22,data4:data3
rcall muls16x16_32 ;tempr:=wr*data[j+1] (16bit
signed)
MOV temprH,r18 ;we take just the middle-result-
bytes
MOV temprL,r17
movw r21:r20,wih:wil
movw r23:r22,data2:data1
rcall muls16x16_32 ;tempi:=wi*data[j] (16bit signed)
MOV tempiH,r18 ;we take just the middle-result-
bytes
MOV tempiL,r17
add tempiL,temprL
adc tempiH,temprH ;tempi := wr*data[j+1]+wi*data
[j]
pop temprH
pop temprL
pop r16
pop r17
pop r18
pop r19
pop r20
pop r21
pop r22
pop r23
;multiplikationen beendet, Stack und Register wieder in
Ordnung

;Hole data[i] aus dem SRAM

ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
ld data3,X+ ;hole Data[i]Low-Byte
ld data4,X ;Hole Data[i]high-Byte
;data[j]:=data[i]-tempr
movw data2:data1, data4:data3
sub data1,temprL
sbc data2,temprH
ldi XH,0
ldi XL,sramstart
add XL,j
adc XH,nullwert
add XL,j
adc XH,nullwert
st X+,data1
st X,data2
;Hole data[i+1] aus dem SRAM
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
adiw XH:XL,2
ld data3,X+ ;hole Data[i+1]low-Byte
ld data4,X ;Hole Data[i+1]high-Byte
;data[j+1]:=data[i+1]-tempi
movw data2:data1, data4:data3
sub data1,tempiL
sbc data2,tempiH
ldi XH,0
ldi XL,sramstart
add XL,j
adc XH,nullwert
add XL,j
adc XH,nullwert
adiw XH:XL,2
st X+,data1
st X,data2
;data[i+1]:=data[i+1]+tempi
add data3,tempiL
adc data4,tempiH
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
adiw XH:XL,2
st X+,data3
st X,data4
;Hole data[i] aus dem SRAM
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
ld data3,X+ ;hole Data[i]low-Byte
ld data4,X ;Hole Data[i]high-Byte
;data[i]:=data[i]+tempr
add data3,temprL
adc data4,temprH
ldi XH,0
ldi XL,sramstart
add XL,i
adc XH,nullwert
add XL,i
adc XH,nullwert
st X+,data3
st X,data4
ret ;Rücksprung zur Schleife_jj
;****************************
;****** HAUPTPROGRAMM *******
;****************************
main:
;initialisieren des Stacks
ldi r16,high(RAMEND)
out spH,r16
ldi r16,low(RAMEND)
out spl,r16
sei
;Kopieren der Test-Daten ins SRAM
;Testdaten werden als 16-bit-signed abgespeichert.
;Die FFT ergibt ebenfalls 16-bit Daten,
;davon sind aber nur ca. 7 bit relevant.
ldi ZH,high(2*testdata)
ldi ZL, low(2*testdata)
clr i
blockkopieren: ;Das Kopieren der Werte erspart mir
eine
;butterfly-sort zu programmieren, simple
stupid!
LPM temp,Z+ ;Lade Werte aus der Ursprungstabelle
testdata
push ZH
push ZL
ldi ZH,high(2*speicherorte_128_werte)
ldi ZL, low(2*speicherorte_128_werte)
add ZL,i
adc ZH,nullwert
lpm sortierzeiger,Z
pop ZL
pop ZH
ldi XH,0
ldi XL,sramstart
add XL,sortierzeiger
adc XH,nullwert
add XL,sortierzeiger
adc XH,nullwert
sbrc temp,7 ;wenn temp negativ, dann
dec nullwert ;setze register nullwert ausnahmsweise
auf $FF
st X+,temp ;speichere lower-Byte zuerst
st X,nullwert ;Highbyte (enthält zunächst nur das
Vorzeichen)
;speichere alle Daten umsortiert im SRAM
clr nullwert ;setze Nullwert wieder auf Null!
inc i
cpi i,nn2
brne blockkopieren
;nun sind die daten für die FFT umsortiert und stehen
im SRAM ab
;Adresse (sramstart+2)=$0082. Für Eigene Anwendungen
sollten die Daten
;von Anfang an nach der Sortiertabelle
"speicherorte_XX_werte" geordnet
;werden. Die Werte sind im SRAM abgelegt als 16 bit
signed integer!
;dw = LOW:HIGH = value:sign
;****************************************
;hier beginnt die eigentliche FFT
ldi mmax,2
while_schleife_start:

cpi mmax,nn2 ;nn2=64

brlo while_schleife_body ;while nn2>mmax do
while_schleife_body
rjmp while_schleife_ende ;ende der while-Schleife
erreicht

while_schleife_body:
mov istep,mmax
lsl istep ;istep:=2*mmax
clr ii ;ii:=0
for_schleife_ii_start: ;for ii=1 to (mmax div 2)
inc ii
mov m,ii
lsl m ;m:=2*ii
dec m ;m:=2*ii-1
ldi temp,nn2 ;nn2=64
sub temp,m ;nn2-m
mov dd8u,temp
mov dv8u,istep
rcall div8u ;Divisionsroutine
;.def drem8u =r15 ;remainder
;.def dres8u =r24 ;result
;.def dd8u =r24 ;dividend
;.def dv8u =r25 ;divisor
mov jjende,dres8u ;jjende:=nn2-m div istep
clr jj ;jj:=0 Initialisierung für
Schleife
;Nun holen wir die Cosinuswerte
ldi ZH,high(2*cosinetab)
ldi ZL, low(2*cosinetab)
ldi zaehler,nn2
mov temp,mmax
lsr temp
pp: lsr zaehler
lsr temp
brne pp
mov temp,ii
dec temp
mul temp,zaehler
add ZL,r0
adc ZH,r1
add ZL,r0 ;addition des pointers doppelt wegen
adc ZH,r1 ;2Byte pro Tabelleneintrag
lpm wrL,Z+ ;jetzt haben wir wrL(ow)
lpm wrH,Z ;jetzt haben wir wrH(igh)
;Nun holen wir die Sinuswerte
ldi ZH,high(2*sinetab)
ldi ZL, low(2*sinetab)
ldi zaehler,nn2
mov temp,mmax
lsr temp
pq: lsr zaehler
lsr temp
brne pq
mov temp,ii
dec temp
mul temp,zaehler
add ZL,r0
adc ZH,r1
add ZL,r0 ;Addition des Pointer-Werts doppelt
wegen
adc ZH,r1 ;2Byte pro Tabelleneintrag
lpm wiL,Z+ ;jetzt haben wir wiL(ow)
lpm wiH,Z ;jetzt haben wir wiH(igh)
for_schleife_jj_start:
rcall Schleife_jj_body ;damit die Schleife mit
einer branch-instruktion
;abgeschlossen werden kann,
wird die eigentliche
;Abarbeitungsroutine mit rcall
aufgerufen.
;(Problem ist die
Sprungreichweite von brsh)
inc jj
cp jjende,jj
brsh for_schleife_jj_start
;ende der jj-Schleife
mov temp,mmax
lsr temp ;iiende:=mmax div 2
cp ii,temp
brlo for_schleife_ii_start
;hier ist das ende der for_schleife_ii
mov mmax,istep
rjmp while_schleife_start
While_schleife_ende:
; Die FFTransformation ist geschafft! Jetzt muß nur
noch richtig
; sortiert werden, da Inputdaten reelle Werte waren.
ldi i,1 ;Initialisierung von i
for_schleife_i_anfang:
inc i ;for i:=2 to ((nn2 div 4)+1)
;Berechnung der Indizes i1..i4
mov i1,i
lsl i1
dec i1 ; i1:=i+i-1
mov i2,i1
inc i2 ; i2:= i1+1
ldi temp,nn2
sub temp,i2
subi temp,-3
mov i3,temp ; i3:=nn2-i2+3
mov i4,i3
inc i4 ; i4:=i3+1
;Nun holen wir die wr
ldi ZH,high(2*cosinetab)
ldi ZL, low(2*cosinetab)
mov temp,i
dec temp
lsl temp
add ZL,temp
adc ZH,nullwert
lpm wrL,Z+ ;jetzt haben wir wrL(ow)
lpm wrH,Z ;jetzt haben wir wrH(igh)
;Nun holen wir die wi
ldi ZH,high(2*sinetab)
ldi ZL, low(2*sinetab)
mov temp,i
dec temp
lsl temp
add ZL,temp
adc ZH,nullwert
lpm wiL,Z+ ;jetzt haben wir wiL(ow)
lpm wiH,Z ;jetzt haben wir wiH(igh)
rcall for_schleife_calculus ;auch hier
Unterprogramm, damit die
;Schleife mit brlo enden
kann.
;test ob FOR_Schleife schon fertig
ldi temp,nn2
lsr temp
lsr temp
inc temp
cp i,temp
brlo for_schleife_i_anfang
for_schleife_i_exit: ;Umsortieren ist
geschafft.
nop
;here comes compensation for DC-Value.
; if DC is not important, then just skip the following
routine
rcall DC_compensation
;
***********************************************************
;now the fft is done.
;data contains real-part and imaginary-part as 16bit
values
;arranged in pairs first real, then imaginary
;
***********************************************************
ende: ;Das Werk ist vollbracht!
rjmp ende ;SCHLUSS! ENDE! AUS!

for_schleife_calculus:
;***** Berechnung von h1r und h2i
;hole Data[i1] in reg. data2:data1
ldi XH,0
ldi XL,sramstart
add XL,i1
adc XH,nullwert
add XL,i1
adc XH,nullwert
ld data1,X+ ;lower-Byte zuerst
ld data2,X ;Highbyte
;hole Data[i3] in register-pair data4:data3
ldi XH,0
ldi XL,sramstart
add XL,i3
adc XH,nullwert
add XL,i3
adc XH,nullwert
ld data3,X+ ;lower-Byte zuerst
ld data4,X ;Highbyte
asr data2
ror data1 ;data[i1]:=data[i1]/2
asr data4
ror data3 ;data[i3]:=data[i3]/2
movw tmp_hi:tmp_lo,data2:data1
add tmp_lo,data3
adc tmp_hi,data4 ;h1r:=data[i1]+data[i3]
sts h1r_lo,tmp_lo
sts h1r_hi,tmp_hi ;save h1r to sram-location
movw tmp_hi:tmp_lo,data2:data1
sub tmp_lo,data3
sbc tmp_hi,data4 ;h1r:=-1*(data[i1]-data[i3])
com tmp_lo
com tmp_hi
ldi temp,1
add tmp_lo,temp
adc tmp_hi,nullwert
sts h2i_lo,tmp_lo
sts h2i_hi,tmp_hi ;save h1r to sram-location
;***** Berechnung von h1i und h2r
;hole Data[i2] in reg. data2:data1
ldi XH,0
ldi XL,sramstart
add XL,i2
adc XH,nullwert
add XL,i2
adc XH,nullwert
ld data1,X+ ;lower-Byte zuerst
ld data2,X ;Highbyte
;hole Data[i4] in register-pair data4:data3
ldi XH,0
ldi XL,sramstart
add XL,i4
adc XH,nullwert
add XL,i4
adc XH,nullwert
ld data3,X+ ;lower-Byte zuerst
ld data4,X ;Highbyte
asr data2
ror data1 ;data[i2]:=data[i2]/2
asr data4
ror data3 ;data[i4]:=data[i4]/2
movw tmp_hi:tmp_lo,data2:data1
sub tmp_lo,data3
sbc tmp_hi,data4
sts h1i_lo,tmp_lo
sts h1i_hi,tmp_hi ;save h1i to sram-location
add data1,data3
adc data2,data4
sts h2r_lo,data1
sts h2r_hi,data2 ;save h2r to sram-location
push r23
push r22
push r21
push r20
push r19
push r18
push r17
push r16
; **** Data[i1]:=h1r+wr*h2r-wi*h2i
movw R21:R20,wrh:wrl
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wih:wil
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
sub data1,r17
sbc data2,r18
lds r18,h1r_hi
lds r17,h1r_lo
add data1,r17
adc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i1
adc XH,nullwert
add XL,i1
adc XH,nullwert
st X+,data1
st X ,data2
; **** Data[i2]:=h1i+wr*h2i+wi*h2r
movw R21:R20,wrh:wrl
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wih:wil
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
add data1,r17
adc data2,r18
lds r18,h1i_hi
lds r17,h1i_lo
add data1,r17
adc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i2
adc XH,nullwert
add XL,i2
adc XH,nullwert
st X+,data1
st X ,data2
; **** Data[i3]:=h1r-wr*h2r+wi*h2i
movw R21:R20,wih:wil
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wrh:wrl
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
sub data1,r17
sbc data2,r18
lds r18,h1r_hi
lds r17,h1r_lo
add data1,r17
adc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i3
adc XH,nullwert
add XL,i3
adc XH,nullwert
st X+,data1
st X ,data2
; **** Data[i4]:=-h1i+wr*h2i+wi*h2r
movw R21:R20,wrh:wrl
lds r23,h2i_hi
lds r22,h2i_lo
rcall muls16x16_32
mov data2,r18
mov data1,r17
movw R21:R20,wih:wil
lds r23,h2r_hi
lds r22,h2r_lo
rcall muls16x16_32
add data1,r17
adc data2,r18
lds r18,h1i_hi
lds r17,h1i_lo
sub data1,r17
sbc data2,r18
ldi XH,0
ldi XL,sramstart
add XL,i4
adc XH,nullwert
add XL,i4
adc XH,nullwert
st X+,data1
st X ,data2
pop r16
pop r17
pop r18
pop r19
pop r20
pop r21
pop r22
pop r23
ret ;ende der umfangreichen Berechnungen in
For_schleife_i

DC_compensation:
lds data1,sramstart+2
lds data2,sramstart+3
lds data3,sramstart+4
lds data4,sramstart+5
movw tmp_hi:tmp_lo,data2:data1
add data1,data3
adc data2,data4
sub tmp_lo,data3
sbc tmp_hi,data4
sts sramstart+2,data1
sts sramstart+3,data2
sts sramstart+4,tmp_lo
sts sramstart+5,tmp_hi
ret
;ende DC-kompensation

sinetab: ;Jede Tabelle 128 Werte = Anzahl

Datenpunkte
.dw 0, 13, 25, 38, 50, 62, 74, 86, 98, 109,
121, 132, 142, 152, 162, 172
.dw 181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256
cosinetab: ;überlappt mit Sinustabelle um
Speicherplatz sparen
.dw 256, 256, 255, 253, 251, 248, 245, 241, 237, 231,
226, 220, 213, 206, 198, 190
.dw 181, 172, 162, 152, 142, 132, 121, 109, 98, 86,
74, 62, 50, 38, 25, 13
.dw 0, -13, -25, -38, -50, -62, -74, -86, -98,-109,-
121,-132,-142,-152,-162,-172
.dw -181,-190,-198,-206,-213,-220,-226,-231,-237,-241,-
245,-248,-251,-253,-255,-256
.dw -256,-256,-255,-253,-251,-248,-245,-241,-237,-231,-
226,-220,-213,-206,-198,-190
.dw -181,-172,-162,-152,-142,-132,-121,-109, -98, -86, -
74, -62, -50, -38, -25, -13
.dw 0, 13, 25, 38, 50, 62, 74, 86, 98, 109,
121, 132, 142, 152, 162, 172
.dw 181, 190, 198, 206, 213, 220, 226, 231, 237, 241,
245, 248, 251, 253, 255, 256

sinetab_64: ;Jede Tabelle 64 Werte = Anzahl

Datenpunkte
.dw 0, 25, 50, 74, 98, 121, 142,162
.dw 181,198,213,226,237,245,251,255
cosinetab_64: ;überlappt mit Sinustabelle um
Speicherplatz sparen
.dw 256, 255, 251, 245, 237, 226, 213, 198
.dw 181, 162, 142, 121, 98, 74, 50, 25
.dw 0, -25, -50, -74, -98,-121,-142,-162
.dw -181,-198,-213,-226,-237,-245,-251,-255
.dw -256,-255,-251,-245,-237,-226,-213,-198
.dw -181,-162,-142,-121, -98, -74, -50, -25
.dw 0, 25, 50, 74, 98, 121, 142,162
.dw 181,198,213,226,237,245,251,255

sinetab_32: ;Jede Tabelle 32 Werte = Anzahl

Datenpunkte
.dw 0, 50, 98, 142
.dw 181, 213, 237, 251
cosinetab_32: ;überlappt mit Sinustabelle um
Speicherplatz sparen
.dw 256, 251, 237, 213
.dw 181, 142, 98, 50
.dw 0, -50, -98,-142
.dw -181,-213,-237,-251
.dw -256,-251,-237,-213
.dw -181,-142, -98, -50
.dw 0, 50, 98, 142
.dw 181, 213, 237, 251

testdata: ;128 Datenpunkte mit 7bit + sign !!

.db 1,2,3,4,5,6,7,8
.db 9,10,11,12,13,14,15,16
.db 17,18,19,20,21,22,23,24
.db 25,25,27,28,29,30,31,32
.db 33,34,35,36,37,38,39,40
.db 41,42,43,44,45,46,47,48
.db 49,50,51,52,53,54,55,56
.db 57,58,59,60,61,62,63,64
.db 65,66,67,68,69,70,71,72
.db 73,74,75,76,77,78,79,80
.db 81,82,83,84,85,86,87,88
.db 89,90,91,92,93,94,95,96
.db 97,98,99,100,101,102,103,104
.db 105,106,107,108,109,110,111,112
.db 113,114,115,116,117,118,119,120
.db 121,122,123,124,125,126,127,0

speicherorte_128_werte:
.db 1,2
.db 65,66
.db 33,34
.db 97,98
.db 17,18
.db 81,82
.db 49,50
.db 113,114
.db 9,10
.db 73,74
.db 41,42
.db 105,106
.db 25,26
.db 89,90
.db 57,58
.db 121,122
.db 5,6
.db 69,70
.db 37,38
.db 101,102
.db 21,22
.db 85,86
.db 53,54
.db 117,118
.db 13,14
.db 77,78
.db 45,46
.db 109,110
.db 29,30
.db 93,94
.db 61,62
.db 125,126
.db 3,4
.db 67,68
.db 35,36
.db 99,100
.db 19,20
.db 83,84
.db 51,52
.db 115,116
.db 11,12
.db 75,76
.db 43,44
.db 107,108
.db 27,28
.db 91,92
.db 59,60
.db 123,124
.db 7,8
.db 71,72
.db 39,40
.db 103,104
.db 23,24
.db 87,88
.db 55,56
.db 119,120
.db 15,16
.db 79,80
.db 47,48
.db 111,112
.db 31,32
.db 95,96
.db 63,64
.db 127,128

speicherorte_64_werte: ;Sortiertabelle für 64

Werte
.db 1, 2, 33, 34
.db 17, 18, 49, 50
.db 9, 10, 41, 42
.db 25, 26, 57, 58
.db 5, 6, 37, 38
.db 21, 22, 53, 54
.db 13, 14, 45, 46
.db 29, 30, 61, 62
.db 3, 4, 35, 36
.db 19, 20, 51, 52
.db 11, 12, 43, 44
.db 27, 28, 59, 60
.db 7, 8, 39, 40
.db 23, 24, 55, 56
.db 15, 16, 47, 48
.db 31, 32, 63, 64
;*********************

speicherorte_32_werte: ;Sortiertabelle für 32

Werte
.db 1, 2, 17, 18
.db 9, 10, 25, 26
.db 5, 6, 21, 22
.db 13, 14, 29, 30
.db 3, 4, 19, 20
.db 11, 12, 27, 28
.db 7, 8, 23, 24
.db 15, 16, 31, 32

;
******************************************************************************
;*
;* FUNCTION
;* muls16x16_32
;* DECRIPTION
;* Signed multiply of two 16bits numbers with 32bits
result.
;* USAGE
;* r19:r18:r17:r16 = r23:r22 * r21:r20
;* STATISTICS
;* Cycles : 19 + ret
;* Words : 15 + ret
;* Register usage: r0:r1 and r6 and r16 to r23 (11
registers)
;* NOTE
;* The routine is non-destructive to the operands.
;*
;
******************************************************************************

muls16x16_32:
; clr r6
muls r23, r21 ; (signed)ah * (signed)bh
movw r19:r18, r1:r0
mul r22, r20 ; al * bl
movw r17:r16, r1:r0
mulsu r23, r20 ; (signed)ah * bl
sbc r19, r6
add r17, r0
adc r18, r1
adc r19, r6
mulsu r21, r22 ; (signed)bh * al
sbc r19, r6
add r17, r0
adc r18, r1
adc r19, r6
ret

;
***************************************************************************
;*
;* "div8u" - 8/8 Bit Unsigned Division
;*
;* This subroutine divides the two register variables
"dd8u" (dividend) and
;* "dv8u" (divisor). The result is placed in "dres8u"
and the remainder in
;* "drem8u".
;*
;* Number of words :66 + return
;* Number of cycles :50/58/66 (Min/Avg/Max) + return
;* Low registers used :1 (drem8u)
;* High registers used :2 (dres8u/dd8u,dv8u)
;*

http://avr-asm.tripod.com/fft7.html (1 of 2)1/20/2009 8:46:26 PM

16 BIT MATH (AVR 202)

;
***************************************************************************

;***** Subroutine Register Variables

.def drem8u =r15 ;remainder

.def dres8u =r24 ;result
.def dd8u =r24 ;dividend
.def dv8u =r25 ;divisor

;***** Code

div8u: sub drem8u,drem8u ;clear remainder and

carry

rol dd8u ;shift left dividend

d8u_2: rol dd8u ;shift left dividend

d8u_4: rol dd8u ;shift left dividend

d8u_6: rol dd8u ;shift left dividend

d8u_8: rol dd8u ;shift left dividend

d8u_10: rol dd8u ;shift left dividend

d8u_12: rol dd8u ;shift left dividend

d8u_14: rol dd8u ;shift left dividend

d8u_16: rol dd8u ;shift left dividend

ret

Programming the AVR Microcontrollers in Machine Language

Atmel AVR From Wikipedia, the free encyclopedia (Redirected

from Avr) Jump to: navigation, search The AVRs are a family
of RISC microcontrollers from Atmel. Their internal
architecture was conceived by two students: Alf-Egil Bogen
and Vegard Wollan, at the Norwegian Institute of Technology
(NTH] and further developed at Atmel Norway, a subsidiary
founded by the two architects. Atmel recently released the
Atmel AVR32 line of microcontrollers. These are 32-bit RISC
devices featuring SIMD and DSP instructions, along with
many additional features for audio and video processing,
intended to compete with ARM based processors. Note that
the use of "AVR" in this article refers to the 8-bit RISC line of
Atmel AVR Microcontrollers. The acronym AVR has been
reported to stand for Advanced Virtual RISC. It's also
rumoured to stand for the company's founders: Alf and
Vegard, who are evasive when questioned about it. Contents
[hide] 1 Device Overview 1.1 Program Memory 1.2 Data
Memory and Registers 1.3 EEPROM 1.4 Program Execution
1.5 Speed 2 Development 3 Features 4 Footnotes 5 See also 6
External Links 6.1 Atmel Official Links 6.2 AVR Forums &
Discussion Groups 6.3 Machine Language Development 6.4 C
Language Development 6.5 BASIC & Other AVR Languages
6.6 AVR Butterfly Specific 6.7 Other AVR Links [edit] Device
Overview The AVR is a Harvard architecture machine with
programs and data stored and addressed separately. Flash,
EEPROM, and SRAM are all integrated onto a single die,
removing the need for external memory (though still available
on some devices). [edit] Program Memory Program
instructions are stored in semi-permanent Flash memory.
Each instruction for the AVR line is either 16 or 32 bits in
length. The Flash memory is addressed using 16 bit word
sizes. The size of the program memory is indicated in the
naming of the device itself. For instance, the ATmega64x line
has 64Kbytes of Flash. Almost all AVR devices are self-
programmable. [edit] Data Memory and Registers The data
address space consists of the register file, I/O registers, and
SRAM. The AVRs have thirty-two single-byte registers and are
classified as 8-bit RISC devices. The working registers are
mapped in as the first thirty-two memory spaces (000016-
001F16) followed by the 64 I/O registers (002016-005F16). The
actual usable RAM starts after both these sections (address
006016). (Note that the I/O register space may be larger on
some more extensive devices, in which case memory mapped
I/O registers will occupy a portion of the SRAM.) Even though
there are separate addressing schemes and optimized
opcodes for register file and I/O register access, all can still
be addressed and manipulated as if they were in SRAM. [edit]
EEPROM Almost all devices have on-die EEPROM. This is
most often used for long-term parameter storage to be
retrieved even after cycling the power of the device. [edit]
Program Execution Atmel's AVRs have a single level pipeline
design. The next machine instruction is fetched as the current
one is executing. Most instructions take just one or two clock
cycles, making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine
programming language Atmel AVR From Wikipedia, the free
encyclopedia (Redirected from Avr) Jump to: navigation,
search The AVRs are a family of RISC microcontrollers from
Atmel. Their internal architecture was conceived by two
students: Alf-Egil Bogen and Vegard Wollan, at the Norwegian
Institute of Technology (NTH] and further developed at Atmel
Norway, a subsidiary founded by the two architects. Atmel
recently released the Atmel AVR32 line of microcontrollers.
These are 32-bit RISC devices featuring SIMD and DSP
instructions, along with many additional features for audio
and video processing, intended to compete with ARM based
processors. Note that the use of "AVR" in this article refers to
the 8-bit RISC line of Atmel AVR Microcontrollers. The
acronym AVR has been reported to stand for Advanced
Virtual RISC. It's also rumoured to stand for the company's
founders: Alf and Vegard, who are evasive when questioned
about it. Contents [hide] 1 Device Overview 1.1 Program
Memory 1.2 Data Memory and Registers 1.3 EEPROM 1.4
Program Execution 1.5 Speed 2 Development 3 Features 4
Footnotes 5 See also 6 External Links 6.1 Atmel Official Links
6.2 AVR Forums & Discussion Groups 6.3 Machine Language
Development 6.4 C Language Development 6.5 BASIC & Other
AVR Languages 6.6 AVR Butterfly Specific 6.7 Other AVR
Links [edit] Device Overview The AVR is a Harvard
architecture machine with programs and data stored and
addressed separately. Flash, EEPROM, and SRAM are all
integrated onto a single die, removing the need for external
memory (though still available on some devices). [edit]
Program Memory Program instructions are stored in semi-
permanent Flash memory. Each instruction for the AVR line is
either 16 or 32 bits in length. The Flash memory is addressed
using 16 bit word sizes. The size of the program memory is
indicated in the naming of the device itself. For instance, the
ATmega64x line has 64Kbytes of Flash. Almost all AVR
devices are self-programmable. [edit] Data Memory and
Registers The data address space consists of the register file,
I/O registers, and SRAM. The AVRs have thirty-two single-byte
registers and are classified as 8-bit RISC devices. The
working registers are mapped in as the first thirty-two
memory spaces (000016-001F16) followed by the 64 I/O
registers (002016-005F16). The actual usable RAM starts after
both these sections (address 006016). (Note that the I/O
register space may be larger on some more extensive
devices, in which case memory mapped I/O registers will
occupy a portion of the SRAM.) Even though there are
separate addressing schemes and optimized opcodes for
register file and I/O register access, all can still be addressed
and manipulated as if they were in SRAM. [edit] EEPROM
Almost all devices have on-die EEPROM. This is most often
used for long-term parameter storage to be retrieved even
after cycling the power of the device. [edit] Program
Execution Atmel's AVRs have a single level pipeline design.
The next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles,
making AVRs relatively fast among the eight-bit
microcontrollers. The AVR family of processors were
designed for the efficient execution of compiled C code. The
AVR instruction set is more orthogonal than most eight-bit
microcontrollers, however, it is not completely regular:
Pointer registers X, Y, and Z have addressing capabilities that
are different from each other. Register locations R0 to R15
have different addressing capabilities than register locations
R16 to R31. I/O ports 0 to 31 have different addressing
capabilities than I/O ports 32 to 63. CLR affects flags, while
SER does not, even though they are complementary
instructions. CLR set all bits to zero and SER sets them to
one. (Note though, that neither CLR nor SER are native
instructions. Instead CLR is syntactic sugar for [produces the
same machine code as] EOR R,R while SER is syntactic sugar
for LDI R,$FF. Math operations such as EOR modify flags
while moves/loads/stores/branches such as LDI do not.) [edit]
Speed The AVR line can normally support clock speeds from
0-16MHz, with some devices reaching 20MHz. Lower powered
operation usually requires a reduced clock speed. All AVRs
feature an on-chip oscillator, removing the need for external
clocks or resonator circuitry. Because many operations on
the AVR are single cycle, the AVR can achieve up to 1MIPS
per MHz. [edit] Development AVRs have a large following due
to the free and inexpensive development tools available,
including reasonably priced development boards and free
development software. The AVRs are marketed under various
names that share the same basic core but with different
peripheral and memory combinations. Some models (notably,
the ATmega range) have additional instructions to make
arithmetic faster. Compatibility amongst chips is fairly good.
See external links for sites relating to AVR development. [edit]
Features Current AVRs offer a wide range of features: RISC
Core Running Many Single Cycle Instructions Multifunction,
Bi-directional I/O Ports with Internal, Configurable Pull-up
Resistors Multiple Internal Oscillators Internal, Self-
Programmable Instruction Flash Memory up to 256K In-
System Programmable using ICSP, JTAG, or High Voltage
methods Optional Boot Code Section with Independent Lock
Bits for Protection Internal Data EEPROM up to 4KB Internal
SRAM up to 8K 8-Bit and 16-Bit Timers PWM Channels & dead
time generator Lighting (PWM Specific) Controller models
Dedicated I²C Compatible Two-Wire Interface (TWI)
Synchronous/Asynchronous Serial Peripherals (UART/
USART) (As used with RS-232,RS-485, and more) Serial
Peripheral Interface (SPI) CAN Controller Support USB
Controller Support Proper High-speed hardware & Hub
controller with embedded AVR. Also freely available low-
speed (HID) software emulation Ethernet Controller Support
Universal Serial Interface (USI) for Two or Three-Wire
Synchronous Data Transfer Analog Comparators LCD
Controller Support 10-Bit A/D Converters, with multiplex of up
to 16 channels Brownout Detection Watchdog Timer (WDT)
Low-voltage Devices Operating Down to 1.8v Multiple Power-
Saving Sleep Modes picoPower Devices Atmel AVR
assembler programming language Atmel AVR machine