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VLSI Engineer Resume of Rudresh Aravapalli

Rudresh Aravapalli is seeking a challenging career in VLSI field. He has an M.Tech in VLSI from Sharda University with a CGPA of 7.96. His B.Tech is in electrical engineering from JNTU with 59.04%. His technical skills include VHDL, PSPICE, and beginner level experience with Xilinx. His M.Tech final year project was on class D amplifier design under Dr. Kaushik Saha of ST Microelectronics.

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87 views3 pages

VLSI Engineer Resume of Rudresh Aravapalli

Rudresh Aravapalli is seeking a challenging career in VLSI field. He has an M.Tech in VLSI from Sharda University with a CGPA of 7.96. His B.Tech is in electrical engineering from JNTU with 59.04%. His technical skills include VHDL, PSPICE, and beginner level experience with Xilinx. His M.Tech final year project was on class D amplifier design under Dr. Kaushik Saha of ST Microelectronics.

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Rudresh Aravapalli
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CURRICULUM VITAE

NAME : ADDRESS: RUDRESH ARAVAPALLI PG-136, JANAKPURI, NEW DELHI 110058

EMAIL: [Link]@[Link] MOBILE: 09871215161


_________________________________________________________________________

CAREER OBJECTIVE:
Seeking a challenging career in the field of VLSI to be a part of a competitive and challenging environment. I wish to add value through my skill set and establish myself as an asset to the organization.

ACADAMIC DETAILS:
Qualification [Link](V LSI) (regular) [Link] [E.E.E] University Institution SHARDA UNIVERSITY JNTU ADAMS ENGINEERING COLLEGE, PALVONCHA. 2009 Year of Passing 2012 Aggregate CGPA7.96

59.04%

Intermediate

BOARD OF INTERMEDIATE EDUCATION.

GOUTHAM GUDAVALLI . TRIPLAAR SCHOOL OF LEARNING,GUNTUR

2005

72%

10 class CBSE.

th

2003

73.6%

TECHNICAL SKILLS:
ANALOG Tools VHDL tools : PSPICE (ORCAD) : MODELSIM, XILINX (beginner).

PROJECTS:
([Link]) Final Year Project: CLASS D AMPLIFIER DESIGN. Under guidance - Dr. KAUSHIK SAHA Group Manager ST MICROELECTRONICS private LTD, PLOT NO.1, KNOWLEDGE PARK -3, GREATER NOIDA (UP)-201308 Email: [Link]@[Link] ([Link]) Final Year Project: Hi-Tech Power plant Security Systems by Using GSM Technology.

AREA OF INTEREST:

Low power design(analog and digital) VLSI design testing and verification

REFERENCES:

Dr. RAJEEV K. SRIVASTAVA, Group Manager, HED,


STMicroelectronics Pvt. Ltd., Greater Noida.

Dr. KAUSHIK SAHA, Group Manager, HED, ST


Microelectronics Pvt. Ltd., Greater Noida.

Prof. [Link], Emeritus Professor, HOD, School of


Engineering & Technology, Sharda University, Greater Noida.

LANGUAGES KNOWN: PERSONAL DETAILS


NAME FATHER NAME DATE OF BIRTH GENDER MARITALSTATUS NATIONALITY PASSPORT NO : : : : : : :

English, Hindi, and Telugu

RUDRESH ARAVAPALLI A .V .V. PRASADA RAO 22-07-1988 MALE UN MARRIED INDIAN H2071692

DECLARATION:
I hereby declare that all the details given above are correct to the best of my knowledge.

Place: NEW DELHI

RUDRESH ARAVAPALLI

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