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Figure from:VPR: A new packing, placement and routing tool for FPGA research

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Table 5. Channel widths required to place and route 20 large benchmark circuits. Table 5 compares the number of tracks required to place and completely route cir- cuits with VPR with the number required to place and globally route the circuits with VPR and then perform detailed routing with SEGA [23]. Table 5 also gives the size of each circuit, in terms of the number of logic blocks. The entries in the SEGA column with a =sign could not be successfully routed because SEGA ran out of memory. Using SEGA to perform detailed routing on a global route generated by V PR increases the total number of tracks required to route the circuits by over 68% vs. having VPR perform the routing completely. Clearly SEGA has difficulty routing large circuits when input pin doglegs are not allowed.

Table 5 Channel widths required to place and route 20 large benchmark circuits. Table 5 compares the number of tracks required to place and completely route cir- cuits with VPR with the number required to place and globally route the circuits with VPR and then perform detailed routing with SEGA [23]. Table 5 also gives the size of each circuit, in terms of the number of logic blocks. The entries in the SEGA column with a =sign could not be successfully routed because SEGA ran out of memory. Using SEGA to perform detailed routing on a global route generated by V PR increases the total number of tracks required to route the circuits by over 68% vs. having VPR perform the routing completely. Clearly SEGA has difficulty routing large circuits when input pin doglegs are not allowed.

Related Figures (7)

Table 1. Temperature update schedule. Finally, it was shown in [12, 13] that it is desirable to keep Raccept near 0.44 for as long as possible. We accomplish this by using the value of Raccept to control a range limiter -- only interchanges of blocks that are less than or equal to Djjmj units apart in the x and y directions are attempted. A small value of Djimit increases Raccept by ensuring that only blocks which are close together are considered for swapping. These “local swaps” tend to result in relatively small changes in the placement cost, increas- ing their likelihood of acceptance. Initially, Dj; nit is set to the entire chip. Whenever the temperature is reduced, the value of Dyjmi- is updated according to se uee ny OP ey Be | When the temperature is so high that almost any move is accepted, we are essen tially moving randomly from one placement to another and little improvement in cos is obtained. Conversely, if very few moves are being accepted (due to the temperatun being low and the current placement being of fairly high quality), there is also littl improvement in cost. With this motivation in mind, we propose a new temperatun update schedule which increases the amount of time spent at temperatures where a sig nificant fraction of, but not all, moves are being accepted. A new temperature is com puted as Trey = Tojq, where the value of a depends on the fraction of attemptec moves that were accepted (Raccept) at To1q, as Shown in Table 1.
Table 1. Temperature update schedule. Finally, it was shown in [12, 13] that it is desirable to keep Raccept near 0.44 for as long as possible. We accomplish this by using the value of Raccept to control a range limiter -- only interchanges of blocks that are less than or equal to Djjmj units apart in the x and y directions are attempted. A small value of Djimit increases Raccept by ensuring that only blocks which are close together are considered for swapping. These “local swaps” tend to result in relatively small changes in the placement cost, increas- ing their likelihood of acceptance. Initially, Dj; nit is set to the entire chip. Whenever the temperature is reduced, the value of Dyjmi- is updated according to se uee ny OP ey Be | When the temperature is so high that almost any move is accepted, we are essen tially moving randomly from one placement to another and little improvement in cos is obtained. Conversely, if very few moves are being accepted (due to the temperatun being low and the current placement being of fairly high quality), there is also littl improvement in cost. With this motivation in mind, we propose a new temperatun update schedule which increases the amount of time spent at temperatures where a sig nificant fraction of, but not all, moves are being accepted. A new temperature is com puted as Trey = Tojq, where the value of a depends on the fraction of attemptec moves that were accepted (Raccept) at To1q, as Shown in Table 1.
5 Experimental Results
5 Experimental Results
Most previous FPGA routing results have assumed that “input pin doglegs” are possible. If the connection box between an input pin and the tracks to which it con- nects consists of F, independent pass transistors controlled by F, SRAM bits, it is pos- sible to turn on two of these switches in order to electrically connect two tracks via the input pin. We will refer to this as an input pin dogleg. Commercial FPGAs, however,
Most previous FPGA routing results have assumed that “input pin doglegs” are possible. If the connection box between an input pin and the tracks to which it con- nects consists of F, independent pass transistors controlled by F, SRAM bits, it is pos- sible to turn on two of these switches in order to electrically connect two tracks via the input pin. We will refer to this as an input pin dogleg. Commercial FPGAs, however,
Table 2. Tracks required to route placements generated by A tor. Table 3 lists the number of tracks required to implement these benchmarks when new CAD tools are allowed to both place and route the circuits. The size column lists the number of logic blocks in each circuit. VPR uses 13% fewer tracks when it per- forms combined global and detailed routing than it does when SEGA is used to per- form detailed routing on a a VPR-generated global route. FPR, which performs placement and global routing simultaneously in an attempt to improve routability, requires 87% more total tracks than VPR. Finally, allowing VPR to place the circuits instead of forcing it to use the Altor placements reduces the number of tracks VPR requires to route them by 40%, indicating that VPR’s simulated annealing based placer is considerably better than the Altor min-cut placer. In this section we compare the minimum number of tracks per channel Eequifed for a successful routing by various CAD tools on a set of 9 benchmark circuits.” All the results in Table 2 are obtained by routing a placement produced by Altor [16], a min- cut based placement tool. Three of the columns consist of two-step (global then detailed) routing, while the other routers perform combined global and detailed rout- ing. VPR requires 10% fewer tracks than the second best router, and the third best router consists of VPR’s global route phase plus SEGA for detailed routing.
Table 2. Tracks required to route placements generated by A tor. Table 3 lists the number of tracks required to implement these benchmarks when new CAD tools are allowed to both place and route the circuits. The size column lists the number of logic blocks in each circuit. VPR uses 13% fewer tracks when it per- forms combined global and detailed routing than it does when SEGA is used to per- form detailed routing on a a VPR-generated global route. FPR, which performs placement and global routing simultaneously in an attempt to improve routability, requires 87% more total tracks than VPR. Finally, allowing VPR to place the circuits instead of forcing it to use the Altor placements reduces the number of tracks VPR requires to route them by 40%, indicating that VPR’s simulated annealing based placer is considerably better than the Altor min-cut placer. In this section we compare the minimum number of tracks per channel Eequifed for a successful routing by various CAD tools on a set of 9 benchmark circuits.” All the results in Table 2 are obtained by routing a placement produced by Altor [16], a min- cut based placement tool. Three of the columns consist of two-step (global then detailed) routing, while the other routers perform combined global and detailed rout- ing. VPR requires 10% fewer tracks than the second best router, and the third best router consists of VPR’s global route phase plus SEGA for detailed routing.
Table 3. Tracks required to place and route circuits. set, which does not allow input pin doglegs. When both tools are only allowed to route an Altor-generated placement V PR requires 13% fewer tracks than SROUTE. When the tools are allowed to both place and route the circuits, VPR requires 29% fewer tracks than the SPLACE/SROUTE combination. Both VPR and SPLACE are based on simulated annealing. We believe the VPR placer outperforms SPLACE partially because it handles high-fanout nets more efficiently, allowing more moves to be evalu- ated in a given time, and partially because of its more efficient annealing schedule.
Table 3. Tracks required to place and route circuits. set, which does not allow input pin doglegs. When both tools are only allowed to route an Altor-generated placement V PR requires 13% fewer tracks than SROUTE. When the tools are allowed to both place and route the circuits, VPR requires 29% fewer tracks than the SPLACE/SROUTE combination. Both VPR and SPLACE are based on simulated annealing. We believe the VPR placer outperforms SPLACE partially because it handles high-fanout nets more efficiently, allowing more moves to be evalu- ated in a given time, and partially because of its more efficient annealing schedule.
Table 4, Tracks required to place and route circuits with no input doglegs.
Table 4, Tracks required to place and route circuits with no input doglegs.