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Figure from:FPGA Design Methodology for Industrial Control Systems—A Review

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Fig. 10. Block diagram of the DTC technique.

Figure 10 Block diagram of the DTC technique.

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Fig. 1. Generic architecture of an FPGA. technology [6], [7], which is by far the most widespread [47]. However, the Flash-based technology [8], although it does not allow the same number of reconfiguration cycles by an order of magnitude, it is of interest for some stringent niche applications such as space and aircraft industries. Indeed, Flash technology preserves the configuration of the FPGA when the power is off, and as a consequence, the chip is ready to operate as soon as it is powered up. The generic architecture of an SRAM-based FPGA is presented in Fig. | [48].
Fig. 1. Generic architecture of an FPGA. technology [6], [7], which is by far the most widespread [47]. However, the Flash-based technology [8], although it does not allow the same number of reconfiguration cycles by an order of magnitude, it is of interest for some stringent niche applications such as space and aircraft industries. Indeed, Flash technology preserves the configuration of the FPGA when the power is off, and as a consequence, the chip is ready to operate as soon as it is powered up. The generic architecture of an SRAM-based FPGA is presented in Fig. | [48].
Fig. 3. Top-down design approach.
Fig. 3. Top-down design approach.
Fig. 2. Logic cell structure.
Fig. 2. Logic cell structure.
By making the assumption that the studied three-phase sys- tem is balanced (no zero-sequence component), the transforma- tion can be simplified and expressed as electrical systems. The coordinate transformation is used to transform the actual quantities of a three-phase electrical sys- tem (%,,2p,2-) into a dq reference frame that is rotating at an arbitrary angle 9 while keeping the instantaneous power equivalent. It gives
By making the assumption that the studied three-phase sys- tem is balanced (no zero-sequence component), the transforma- tion can be simplified and expressed as electrical systems. The coordinate transformation is used to transform the actual quantities of a three-phase electrical sys- tem (%,,2p,2-) into a dq reference frame that is rotating at an arbitrary angle 9 while keeping the instantaneous power equivalent. It gives
Fig. 4. Reuse and IP module libraries. Fig.5. DFG of the coordinate transformation algorithm.
Fig. 4. Reuse and IP module libraries. Fig.5. DFG of the coordinate transformation algorithm.
Fig. 6. ALU data paths of the coordinate transformation.
Fig. 6. ALU data paths of the coordinate transformation.
Fig. 7. Performance of the different ALU after synthesis.
Fig. 7. Performance of the different ALU after synthesis.
Fig. 9. Timing distribution. (a) General-purpose microcontroller, (b) DSP controller, and (c) FPGA-based controller
Fig. 9. Timing distribution. (a) General-purpose microcontroller, (b) DSP controller, and (c) FPGA-based controller
FUNCTIONAL ALGORITHM DECOMPOSITION direct torque and rotor flux control (DTRFC) with the use of space vector modulation (SVM) for induction motor drives. Indeed, due to their similar structures but also their differences, these two algorithms are good examples to show the effective- ness of an FPGA-based functional modular approach to im- plement sensorless control induction motor drives. Therefore, the chosen solution is based on a custom hardware architecture designed by assembling a set of functional building blocks. These blocks are tested and organized in a library of IP modules for easy reuse [107]. Each block is geared toward a specific algorithm function (flux estimator, hysteresis controller, etc.). A special attention is given to the algorithm refinement, which allows finding the optimum fixed-point data word length for each internal variable of the algorithm. Finally, experimental results are shown, which validate the proposed approach. Fig. 11. Block diagram of SVM-DTRFC strategy.
FUNCTIONAL ALGORITHM DECOMPOSITION direct torque and rotor flux control (DTRFC) with the use of space vector modulation (SVM) for induction motor drives. Indeed, due to their similar structures but also their differences, these two algorithms are good examples to show the effective- ness of an FPGA-based functional modular approach to im- plement sensorless control induction motor drives. Therefore, the chosen solution is based on a custom hardware architecture designed by assembling a set of functional building blocks. These blocks are tested and organized in a library of IP modules for easy reuse [107]. Each block is geared toward a specific algorithm function (flux estimator, hysteresis controller, etc.). A special attention is given to the algorithm refinement, which allows finding the optimum fixed-point data word length for each internal variable of the algorithm. Finally, experimental results are shown, which validate the proposed approach. Fig. 11. Block diagram of SVM-DTRFC strategy.
is based on torque and rotor flux control [109]. Moreover, in this case, the voltage source inverter is controlled indirectly by using the SVM in a similar way with what was proposed in [110]. This technique allows a smoother behavior of the torque regulation at steady-state operation than basic DTC. Fig. 12. DFG of the a-axis stator flux estimator.
is based on torque and rotor flux control [109]. Moreover, in this case, the voltage source inverter is controlled indirectly by using the SVM in a similar way with what was proposed in [110]. This technique allows a smoother behavior of the torque regulation at steady-state operation than basic DTC. Fig. 12. DFG of the a-axis stator flux estimator.
Fig. 14. Estimator architecture factorized by the use of A? methodology.
Fig. 14. Estimator architecture factorized by the use of A? methodology.
Fig. 15. Top view of the RTL model.
Fig. 15. Top view of the RTL model.
Fig. 16. Experimental results torque step response 0 to 4 nm, T’; = 50 ps. (a) DTC. (b) DTRFC
Fig. 16. Experimental results torque step response 0 to 4 nm, T’; = 50 ps. (a) DTC. (b) DTRFC
Fig. 19. Voltage response with control system. Fig. 18. Simulation results. The graph shows that the controller is successful in stabiliz- ing the generator system. Although there is a voltage drop of about 14% when the load resistance is decreased, this effect is counteracted by the controller, and the voltage level recovers
Fig. 19. Voltage response with control system. Fig. 18. Simulation results. The graph shows that the controller is successful in stabiliz- ing the generator system. Although there is a voltage drop of about 14% when the load resistance is decreased, this effect is counteracted by the controller, and the voltage level recovers
In this example, the rules state that the output signal wu is PB when the output condition is C!, C?, or C®. The dc output voltage is simulated during a step increase of the load current. The results in Fig. 18 show that the fuzzy logic control system is successfully correcting the tendency to fall of the output voltage Vqa-. The system is therefore able to cope with variations in V4. resulting from variable load and variable speed of operation. After the complete system was modeled and simulated using VHDL, the circuit design of the controller was synthesized and implemented into a Xilinx XC4010 FPGA for rapid prototyping. By adjusting the speed of the engine to the operating conditions, fuel consumption can be reduced while the same torque can be produced. Fig. 19 shows the voltage response when the controller is connected to the system. The desired dc voltage is set at 250 V.
In this example, the rules state that the output signal wu is PB when the output condition is C!, C?, or C®. The dc output voltage is simulated during a step increase of the load current. The results in Fig. 18 show that the fuzzy logic control system is successfully correcting the tendency to fall of the output voltage Vqa-. The system is therefore able to cope with variations in V4. resulting from variable load and variable speed of operation. After the complete system was modeled and simulated using VHDL, the circuit design of the controller was synthesized and implemented into a Xilinx XC4010 FPGA for rapid prototyping. By adjusting the speed of the engine to the operating conditions, fuel consumption can be reduced while the same torque can be produced. Fig. 19 shows the voltage response when the controller is connected to the system. The desired dc voltage is set at 250 V.