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Figure from:Hybrid Multi-FPGA Board Evaluation by permitting limited multi-hop routing

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Figure 7. Comparison with multiterminal nets.

Figure 7 Comparison with multiterminal nets.

Related Figures (7)

Figure I. Hybrid linear array partial crossbar MFB topology and architecture.
Figure I. Hybrid linear array partial crossbar MFB topology and architecture.
Figure 2. One-hop vs multi-hop routing.
Figure 2. One-hop vs multi-hop routing.
Figure 3. Estimation of multi-terminal nets into equivalent two terminal nets.
Figure 3. Estimation of multi-terminal nets into equivalent two terminal nets.
Figure 4. An iteration of heuristic. II. some nets between ith and jth FPGAs are currently routed through PCs Le., Ay >0.
Figure 4. An iteration of heuristic. II. some nets between ith and jth FPGAs are currently routed through PCs Le., Ay >0.
Table J. Programmable Connections for Various Topologies and Hops
Table J. Programmable Connections for Various Topologies and Hops
Figure 6. Programmable connections vs hops.
Figure 6. Programmable connections vs hops.