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Figure from:FPGA Implementation of Complex Multiplier Using Urdhva Tiryakbham Sutra of Vedic Mathematics

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With c6r6r5r4r3r2r1r0 being the final product [3] [4] [8]. Fig.1. Vertically crosswise multiplication of four bit binary number [3]
With c6r6r5r4r3r2r1r0 being the final product [3] [4] [8]. Fig.1. Vertically crosswise multiplication of four bit binary number [3]
Fig. 3. RTL schematic [partial] of 4-bit complex multiplier (V edic multiplier) Using the proposed algorithm 4-bit, 8-bit, and 16-bit complex multiplication is achieved. Functional verification of the code through simulation is carried out using Xilinx ISE simulator. The complete code is synthesized using Xilinx synthesis tool (XST). Table 1 indicates the device utilization summary of the Vedic complex multiplier for 4-bit, 8- bit, 16-bit multiplication. Figure 3,4 and 5 shows the RTL schematic of 16-bit complex multiplier using Vedic algorithm.
Fig. 3. RTL schematic [partial] of 4-bit complex multiplier (V edic multiplier) Using the proposed algorithm 4-bit, 8-bit, and 16-bit complex multiplication is achieved. Functional verification of the code through simulation is carried out using Xilinx ISE simulator. The complete code is synthesized using Xilinx synthesis tool (XST). Table 1 indicates the device utilization summary of the Vedic complex multiplier for 4-bit, 8- bit, 16-bit multiplication. Figure 3,4 and 5 shows the RTL schematic of 16-bit complex multiplier using Vedic algorithm.
Fig.2. Proposed methodology for complex number multiplication
Fig.2. Proposed methodology for complex number multiplication
Fig. 5. RTL schematic [partial] of 4-bit complex multiplier (Booth’s) Fig. 4.. RTL schematic [partial] of 4-bit complex multiplier (V edic multiplier)
Fig. 5. RTL schematic [partial] of 4-bit complex multiplier (Booth’s) Fig. 4.. RTL schematic [partial] of 4-bit complex multiplier (V edic multiplier)
Fig. 6. Simulation waveforms for 4-bit complex multiplication The work presented in this paper was implemented using VHDL and logic simulation was done using Xilinx ISE simulator and synthesis was done using Xilinx project navigator. The design was synthesized for Spartan3 (xc3s200-5-ft256) device. The obtained results are presented in table 1, and waveforms for 4-bit, 8-bit and 16-bit unsigned complex multiplication using Urdhva Tiryakbhyam algorithm is shown in figure 6, 7 and 8 respectively.
Fig. 6. Simulation waveforms for 4-bit complex multiplication The work presented in this paper was implemented using VHDL and logic simulation was done using Xilinx ISE simulator and synthesis was done using Xilinx project navigator. The design was synthesized for Spartan3 (xc3s200-5-ft256) device. The obtained results are presented in table 1, and waveforms for 4-bit, 8-bit and 16-bit unsigned complex multiplication using Urdhva Tiryakbhyam algorithm is shown in figure 6, 7 and 8 respectively.
Fig. 7. Simulation waveforms for 8-bit complex multiplication
Fig. 7. Simulation waveforms for 8-bit complex multiplication