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Figure from:FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL

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The circuit diagram for 32-bit LFSR with maximum length polynomial is shown in Fig. 4. The timing simulation is shown in Fig. 7.a starting from 20 ns to 85899345920 ns (85.9 sec) and we can observe here the simulation is running for a long time to complete the sequence. In the Fig. 7.b a small zooming portion is shown and it can be observed the randomness behaviour for 32 bit LFSR from 30225 ns to 30500 ns. For 32 bit LFSR using Xilinx ISE 10.1 simulator, it is taking about 3 hour duration for simulating upto | sec time duration with 20 ns clock period. As the run length is very large which is 429,49,67,295 random states, so it is taking actual 85.9 sec to complete the sequence but practically simulate with ISE 10.1 is taking about 10-12 days. Figure 4. Circuit Diagram of 32- Bit LFSR for maximum length Feedback Polynomial X* + X” + X?+ X'+1

Figure 4 The circuit diagram for 32-bit LFSR with maximum length polynomial is shown in Fig. 4. The timing simulation is shown in Fig. 7.a starting from 20 ns to 85899345920 ns (85.9 sec) and we can observe here the simulation is running for a long time to complete the sequence. In the Fig. 7.b a small zooming portion is shown and it can be observed the randomness behaviour for 32 bit LFSR from 30225 ns to 30500 ns. For 32 bit LFSR using Xilinx ISE 10.1 simulator, it is taking about 3 hour duration for simulating upto | sec time duration with 20 ns clock period. As the run length is very large which is 429,49,67,295 random states, so it is taking actual 85.9 sec to complete the sequence but practically simulate with ISE 10.1 is taking about 10-12 days. Figure 4. Circuit Diagram of 32- Bit LFSR for maximum length Feedback Polynomial X* + X” + X?+ X'+1

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The bits in the LFSR state which influence the input are called taps. A maximum-length LFSR produces an m- sequence (i.e. it cycles through all possible 2” -1 states within the shift register except the state where all bits are zero), unless it contains all zeros, in which case it will never change. The sequence of numbers generated by this method is random. The period of the sequence is (2” - 1), where n is the number of shift registers used in the design.
The bits in the LFSR state which influence the input are called taps. A maximum-length LFSR produces an m- sequence (i.e. it cycles through all possible 2” -1 states within the shift register except the state where all bits are zero), unless it contains all zeros, in which case it will never change. The sequence of numbers generated by this method is random. The period of the sequence is (2” - 1), where n is the number of shift registers used in the design.
The circuit diagram for 16-bit LFSR with maximum length polynomial is shown in Fig. 3. The timing simulation is shown in Fig. 6.a from 20 ns to 1310720 ns and also in Fig. 6.b which is a zooming view of Fig. 6.a. It shows starting simulation and simulation at the end of cycle after which the sequence starts repeating again. Figure 3. Circuit Diagram of 16- Bit LFSR with maximum length Feedback Polynomial X'* + X'4+ X84 X!'4+1
The circuit diagram for 16-bit LFSR with maximum length polynomial is shown in Fig. 3. The timing simulation is shown in Fig. 6.a from 20 ns to 1310720 ns and also in Fig. 6.b which is a zooming view of Fig. 6.a. It shows starting simulation and simulation at the end of cycle after which the sequence starts repeating again. Figure 3. Circuit Diagram of 16- Bit LFSR with maximum length Feedback Polynomial X'* + X'4+ X84 X!'4+1
Figure 2. Circuit Diagram of 8- Bit LFSR with maximum length Feedback Polynomial X* + X° + X°+X*+1 ~The’ circuit diagram for 6 bit -LFSR with maximum length polynomial is shown in Fig. 2. The timing simulation is shown in Fig. 5 from 40 ns to 5140 ns. After this clock time the random output is repeating again.
Figure 2. Circuit Diagram of 8- Bit LFSR with maximum length Feedback Polynomial X* + X° + X°+X*+1 ~The’ circuit diagram for 6 bit -LFSR with maximum length polynomial is shown in Fig. 2. The timing simulation is shown in Fig. 5 from 40 ns to 5140 ns. After this clock time the random output is repeating again.
Figure 6.b. Timing Simulation waveform of 16-Bit LFSR (Zoom image at the starting of simulation & at the end of the cycle after which it starts repeating) Figure 6.a. Timing Simulation waveform of 16-Bit LFSR (20 ns to 1310720 ns = 1310.7 us): Total 65535 periods
Figure 6.b. Timing Simulation waveform of 16-Bit LFSR (Zoom image at the starting of simulation & at the end of the cycle after which it starts repeating) Figure 6.a. Timing Simulation waveform of 16-Bit LFSR (20 ns to 1310720 ns = 1310.7 us): Total 65535 periods
Figure 5. Timing Simulation waveform of 8-Bit LFSR (40 ns to 5140 ns = 5100 ns): Total 255 periods
Figure 5. Timing Simulation waveform of 8-Bit LFSR (40 ns to 5140 ns = 5100 ns): Total 255 periods
‘igure 7.a. Timing Simulation waveform of LFSR-32 Bit (20 ns to 85899345920 ns = 85.9 sec): Total 429,49,67,295 periods
‘igure 7.a. Timing Simulation waveform of LFSR-32 Bit (20 ns to 85899345920 ns = 85.9 sec): Total 429,49,67,295 periods
Figure 7.b. Timing Simulation waveform of LFSR-32 Bit (Zooming view of Fig.7.a)
Figure 7.b. Timing Simulation waveform of LFSR-32 Bit (Zooming view of Fig.7.a)