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Figure from:VLSI implementations of communication protocols-a survey

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He has been with the Computing Systems Research Laboratory, AT&T Bell Laboratories, Murray Hill, NJ, since 1984. His research interests in- clude special-purpose architectures, parallel algorithms, and CAD.

Table 1 He has been with the Computing Systems Research Laboratory, AT&T Bell Laboratories, Murray Hill, NJ, since 1984. His research interests in- clude special-purpose architectures, parallel algorithms, and CAD.

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Fig. 1. The internal architecture of the MC68824 token bus architecture.
Fig. 1. The internal architecture of the MC68824 token bus architecture.
KRISHNAKUMAR AND SABNANI: VLSI IMPLEMENTATIONS OF COMMUNICATION PROTOCOL: via the transmit and receive FIFO buffers. The parallel processor performs the interface functions with the host processor. It consists of several blocks such as the com- mand unit, the DMA machine, and the receive unit. The command unit fetches commands from and writes status information to the memory. It also controls the DMA ma- chine. The DMA machine performs data transfer to/from the host memory. The receive unit performs for the re- ceive memory structure functions similar to that of the command unit. The receive memory structure is used to store the incoming packets. Both of these units share a microinstruction read-only memory (ROM). The serial channel performs the CSMA/CD procedure and the front- end functions of the link layer protocol. It consists of sev- eral blocks, such as the transmit byte block, the transmit bit block, the receive byte block, and the receive bit block. The transmit byte block executes commands received through the transmit FIFO and returns status information through the receive FIFO. It assembles the frames to be sent. The transmit bit block performs front-end process- ing such as serialization and encoding of data, bit-stuff- ing, CRC generation. Similarly, the receive bit machine performs bit destuffing and CRC checking and it delivers the decoded data in bytes to the receive byte machine. Further processing on these data from the receive bit ma- chine is. done by the receive byte machine which then sends it to the receive unit. The operation of various units in the 82586 controller is highly concurrent. This allows this controller to operate at a high speed.
KRISHNAKUMAR AND SABNANI: VLSI IMPLEMENTATIONS OF COMMUNICATION PROTOCOL: via the transmit and receive FIFO buffers. The parallel processor performs the interface functions with the host processor. It consists of several blocks such as the com- mand unit, the DMA machine, and the receive unit. The command unit fetches commands from and writes status information to the memory. It also controls the DMA ma- chine. The DMA machine performs data transfer to/from the host memory. The receive unit performs for the re- ceive memory structure functions similar to that of the command unit. The receive memory structure is used to store the incoming packets. Both of these units share a microinstruction read-only memory (ROM). The serial channel performs the CSMA/CD procedure and the front- end functions of the link layer protocol. It consists of sev- eral blocks, such as the transmit byte block, the transmit bit block, the receive byte block, and the receive bit block. The transmit byte block executes commands received through the transmit FIFO and returns status information through the receive FIFO. It assembles the frames to be sent. The transmit bit block performs front-end process- ing such as serialization and encoding of data, bit-stuff- ing, CRC generation. Similarly, the receive bit machine performs bit destuffing and CRC checking and it delivers the decoded data in bytes to the receive byte machine. Further processing on these data from the receive bit ma- chine is. done by the receive byte machine which then sends it to the receive unit. The operation of various units in the 82586 controller is highly concurrent. This allows this controller to operate at a high speed.
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 7, NO. 7, SEPTEMBER 1989
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 7, NO. 7, SEPTEMBER 1989
As described in this paper, controllers for several stan- dard protocols have been developed or are under devel- opment. The motivation behind this trend is progress of transmission technology and a desire to offload protocol processing from host processors to satellite units.
As described in this paper, controllers for several stan- dard protocols have been developed or are under devel- opment. The motivation behind this trend is progress of transmission technology and a desire to offload protocol processing from host processors to satellite units.