An oscilloscope can display a time-varying signal as amplitude vs. time graph; a spectrum analyzer can present the same signal as amplitude vs. frequency graph. (Amplitude vs. frequency graph of a sine wave consists of a single vertical line segment; for any periodic wave the display is a series of equally-spaced vertical lines of various heights). A wave analyzer can detect the presence of individual frequency components but does not produce a graphical display. Such a wave analyzer will be used extensively in following experiments, so details on its theory and operation follow. Fig. 4 Typical modulation pattern 1: With an ohmmeter, measure the resistance of the untapped coil, X:: _ 2: What is the approximate amplitude of the carrier frequency as compared with the two side-bands? Fig.1 FSK signal in Frequency Domain What do you observe in this first set up? How does the modulator behave? Adding synchronizing circuits in the modulator would make it rather complicated. However, instead of using two separate signal generators to generate our carrier frequencies. we can use a single oscillator to generate both. In this module we are using an XR2206 monolithic function generator chip. It is a versatile chip that generates different types o waveforms: sine waves, triangular waves, square waves, AM, FM and FSK signals. More detai on this chip is discussed in Experiment 7: Angle Modulation in Communications I. Does the graph show that the FSK spectrum is indeed a superimposition of the ASK spectra of the mark and space frequencies? Using the wave analyzer, record the approximate amplitudes of the expected frequency components of the FSK signal as indicated in the table. Instead of an analog meter, use an oscilloscope for the amplitude measurements. Set FG1 to sine, 40.00 KHz and Modulation to direct, +16 from the modulation module. Use the Modulation signal as input to the XR2206 modulator to generate a continuous-phase FSK. Sketch the frequency spectrum of the FSK signal. Activity 5: Noncoherent FSK Demodulation Activity 6: PLL FSK Demodulation PLL Demodulation The diode control voltage at A and B is applied to the center tap of each transformer, so the same voltage is applied to all diodes. If this voltage is quite small, none of the diodes conduct so the signal out is effectively isolated from the signal in. If A is sufficiently positive (~ 0.6 volts) with respect to B, only diodes a and d conduct. Current leaving point P flows through the right transformer from Q to R. However if B is sufficiently positive (~ 0.6 volts) with respect to A, only diodes b and c conduct. Current leaving point P flows in the right transformer from R to Q. So just by changing the polarity of the control voltage, the signal out is in-phase or 180° out-of-phase with the signal in. The amplitude of signa/ in must be sufficiently small so as not to turn on any diode. After modulation signa/ out may be amplified to the desired level The result gives sum and difference terms but the carrier term, cos wt, does not appear. Referring again to Fig. 2, the carrier is applied to the terminals marked Signal in, the modulation is applied to the terminals marked diode control and the modulatea carrier appears at the signal out terminals. Apart from a constant amplitude factor the Signal in term is cos o,t, But which of the possible forms shown in Fig. 6 should we use as modulation? The signal shown at left of Fig. 6, (A + M cos wmt), keeps one diode permanently conducting and the other permanently off, so signal out is only the un-modulated carrier, COS @ct. We now examine in detail these two operations implemented by our hardware dule. Activity #3: Carrier Recovery each case two data bits are used to form a single four-state di-bit, with allowed values of 00, 01, 10, 11. Bit-splitting is the process of combining two bits into a single dji-bit. The inverse process of recovering the original pair of bits from a single di-bit may be referred to as bit-joining. Fig. 1 shows a four-amplitude ASK system. Fig. 2 shows a four-phase PSK system. Fig. 3 shows a four-state system with two amplitude and two phase states. In The initial data stream to be transmitted is in the form of a time-sequence of binary digits; the duration of each bit is one bit-period. We are to convert this into two separate binary data streams, Do and Dy,, each with duration of two bit-periods. These two data streams can control a 2 to 4 multiplexer to provide four discrete states. The /ead bit of each original bit pair goes into the Dy, stream but with duration of two bit-periods. The following bit of the pair goes into the Do stream also with duration of original ¢ o 11 two bit-periods. Fig. 4 shows the formation of the Do and D, « transmission the reverse process must be performed. A block « hardware is shown in Fig. 5. Activity 2 The Bit-joiner 8: Does each bit-switch produce a pattern 2 bit-periods wide at either Do or D; but not both? 3: The parallel-in / serial-out shift register /Joads parallel data when TP6 goes low and shifts data on a low-to-high transition at TP5. Load and shift must not occur at the same time! Connect Channel #1 to TP6, Channel #2 to TP5. The display should appear somewhat like Fig. 7. At the SYNC pulse the modulation signal goes high for two bit-periods prior to the user-selected 8-bit patterns. If the clock signal is randomly interrupted, on its return the two high bits may be in a single di-bit or shared between two adjacent di-bits, resulting in slightly different screen patterns Fig.9 Block diagram of a 4-ASK demodulator The demodulation unit accepts a modulated carrier and produces as output a a/ bit, [D;, Do], and a clock signal so synchronized that its rising edge occurs at a time when both D; and Do are stable. See Fig. 9. The digitally modulated carrier at TP12 is Activity 4 Demodulating the carrier at the receiver Suppose a server is at the transmission end and an ‘IBM clone at the receive end. The CPU clock frequency of the server and the clone may be quite different, while the transmit clock controlling the data flow from server to clone is probably running at a much slower rate than the other two. The buffer is used to reconcile these timing differences. The server writes byte data into this buffer at the server CPU clock rate, while the transmitter circuitry removes bytes from the buffer at its own transmit clock rate. Digital Counter Method Suppose the X-8 clock is in error by 2% and the data stream is a series of consecutive “0” bits. On each clock cycle the timing of the Q¢ rise will also shift from the exact center of the bit period by 2%. Recall that valid data is obtained provided that the D-latch CLK input goes high, once and only once, sometime during each period; early or later is not significant. So with a 2% local clock error valid data is still obtained if there are no more than 50 successive “0” or “1” data bits. Frior tO the Serai-in/paraver-out sniit register the recelvea signal is normally fed to the input terminal of a D-latch. Its instantaneous value is transferred and held at the Q output at the rising edge of the CLK signal. For proper signal recovery the CLK signal must occur once and only once during each bit Fig. 3 D-latch period and at a time when the D input signal level is not changing. As suggested by the diagram of Fig. 2, a CLK signal occurring early, middle or late during the bit period still preserves data integrity. For the received signal the time between the falling edge of one pulse and the rising edge of the following pulse is always an integral number of bit periods. Thus edge detection is the basis for synchronizing the transmit and receive clocks. However if the transmitted signal contains an extended series of “O” or “1” symbols, there are no edges to detect so the receiver clock may lose its synchronization. The present module offers two different methods for synchronizing the receive clock to the transmit clock, using a digital counter or a phase-lock loop. Phase-lock Loop Method A voltage-controller oscillator accepts a voltage at its single input (either pure DC or the DC component of a periodic signal) and provides an output square wave of 50% duty cycle at a frequency determined by the input voltage and the configuration of an 2xternally configured RC oscillator. The loop character of the phase-lock circuit is orovided by connecting the VCO output to the B input of the phase comparator (the 2xternal signal under test is applied to the A input terminal.) With proper adjustment of ihe external capacitance, C, and resistance, R (which set the natural frequency, fo, of ihe VCO), the signal at B is forced to match that at A in frequency but not in phase. The VCO output is a square wave but the incoming signal at A may be either sinusoidal or square. Before using the PLL for clock recovery it can be helpful to examine separately and in some detail the phase comparator and VCO. Fig. 2 Block diagram of a QPSK modulator SSE GEA iw ee A SEiw wWGEEEE wt avew re Miiwet awe wwf witt ta aad | tee aaa | separate carriers differing in phase by 90°. In the BPSK module we multiplied a sine wave by —1 to produce a 180° phase shift. In this module we get the same 180° phase shift (with less expensive hardware) by passing the sine wave through an inverter, a unit-gain, inverting op-amp and use an analog version of a single-pole-double-throw switch to select the inverted or non-inverted signal. We use a bit-splitter, already studied in a previous module to produce the two trains, customarily to refer to as I (in phase, the sine signal) and Q (90° out of phase or quadrature, the cosine signal). Finally, the I and Q signals are added together to form the modulated signal. See Fig. 2. In what follows we examine the wave forms at the various test points to gain a deeper understanding of modulation process. actual circuit is unit-gain inverting op-amps. The carrier signals are 4.0 Vp_p sine waves the control signals are + 5 volts. 3: Vary the settings of the [ +] control and sweep speed. Does the number of carrier cycles per bit period change’ 5: Vary the 8-bit encoder switches and describe any change: Fig.6 A block diagram of a functional QPSK demodulator In our QPSK modulation the I and Q signal paths were treated quite separately up until the final stage; but these separate I and Q components are already mixed in the received signal we are to demodulate. It is a pleasant surprise that the original I and Q signals can be readily recovered simply by adding to this common received signal either a sine or cosine version of the original carrier. Fig. 6 presents a block diagram of the process used in the present module. It should be noted that just as for modulation we used an inverter and switch rather than a mixing, so also for demodulation we use addition rather than multiplication. Commonly available laboratory oscilloscopes cannot respond to the frequencies normally used in commercial QPSK systems, so our modules scale down frequency. At these lower frequencies addition gives cleaner results than multiplication by mixing. \n what follows we view the various waveforms. Let’s take a second look at the bit splitter. From Fig.4, notice that the splitter timing is independent of the [+4] unit output. On each high-to-/ow transition at TP1, the splitter inputs the voltage level at TP2. If information of the input modulation bits is neither to be missed nor counted twice, the individual bit duration must equal the clock period. After two successive inputs TP24 makes a /ow-to-high transition, marking the appearance of a new dibit at TP3, TP4. A aibit duration is twice that of a single bit, but one dibit contains the information of two bits. Recall that fm and the associated Nyquist bandwidth is the rate at which wave changes its form; if the wave never changes, the Nyquist bandwidth would be zero, yet such a wave could carry no useful information. The wave considered above could be in either of two states, determined by a single bit. But consider waves that at any moment could have any one of 4, 8 or 16 different forms, determined by 2, 3 or 4 information bits. Bandwidth is proportional to the rate of change of wave form, fm, and with each change of form, 2, 3, 4 of more bits of information may be transferred with no bandwidth increase. Fig. 2 16-QAM phasor and constellation diagrams A 40.00 kHz, 4.0 Vp-p sine wave carrier is obtained from FG1 of the Modulation Module, which is divided into two separate signal paths, I (In-phase) and Q(Quadrature). The Q channel carrier is phase-shifted by 90°. Apart from the initial difference in phase, the I and Q channels are identical. Each channel generates four separate sub-signals, any one of which may be selected as output by the channel multiplexer. In each channel the inverter, labeled —1x, shifts the sinusoidal signal by 180°. The two buffer amplifiers, Fig. 4 90° shift between I and Q The diagram indicates the phase of the [I+Q] signal to be 225° and the amplitude to be 1.4 units. Both these values are approximations, due to the limited size of the oscilloscope display. In the following activity you are to use this method to examine the [I+Q] signal. 4: Vary the four toggle switches through all combinations and record the phase an amplitude of the displayed [I+Q] signal. 16—QAM De-modulation 4: Explain the differences between the multimeter and Oscilloscope readings: Activity 7: The Low-pass Filters The low-pass filters in the I—- and Q-channels remove the AC component of the mixed signals and multiply the DC offset by a factor of approximately 10. Fourier analysis can represent any non-periodic signal represented by a set of sinusoidal waves with a continuous frequency spread from zero to some maximum frequency, fm. For perfect representation, fm — ~, but in practice fm is taken as the maximum frequency of interest of the sampled signal (3,000 Hz for a single telephones conversation). To introduce the sampling concept, we start by sampling a single- frequency rather than the spread of frequencies resulting from Fourier analysis. We also use the same fm symbol to represent this single frequency. Perhaps the simplest sampling method is to pass the signal through an analog on/off switch operating at frequency fs. The waveforms are shown in Fig. 1. 7: Maintain fm = 3.000 kHz but change f, = 5.000 kHz; again search for frequencies: 2: For the Sampling Signal, f; use FG2 (8.00 kHz, square, 4.0 Vp_p) connected to TP2. Function Generator. The FG1 and FG2 signals available at the blue panel terminals have an added constant 2.5 v DC offset. Our module contains an adder circuit (inputs at B and C, output at D). Recall that adder outputs contain all and only frequencies present at the inputs, unlike mixers which reject the input frequencies and provide new sum-and-difference frequencies at the output. Here we use as input to the sample-and-hold circuit the sum of sine waves from FG1 and FG2 and view the demodulated output. Activity 5: PAM for a compound signal All of this can be done by an Analog Digital Converter chip ADC0804, which accepts an analog signal that it samples at a user-determined sampling frequency, provides an adjustable ramp and comparator, and outputs an eight-bit binary measure of the pulse-width to sample-period ratio. Of course we can’t send an eight-bit byte in parallel over a single transmission path, so a parallel-in / serial-out shift register is inserted into the signal path before transmission. At the receiver-end the process is reversed. A companion serial-in / parallel-out shift register recovers the eight-bit byte and passes it along to a Digital Analog Converter chip, DAC0832 gives an analog voltage just equal to the original sampling level, essentially PAM. The original analog signal is recovered by adding a low-pass filter. Activity 10: ADC Counting
![Fig.9 Block diagram of a 4-ASK demodulator The demodulation unit accepts a modulated carrier and produces as output a a/ bit, [D;, Do], and a clock signal so synchronized that its rising edge occurs at a time when both D; and Do are stable. See Fig. 9. The digitally modulated carrier at TP12 is Activity 4 Demodulating the carrier at the receiver](https://figures.academia-assets.com/36205873/figure_037.jpg)
![actual circuit is unit-gain inverting op-amps. The carrier signals are 4.0 Vp_p sine waves the control signals are + 5 volts. 3: Vary the settings of the [ +] control and sweep speed. Does the number of carrier cycles per bit period change’ 5: Vary the 8-bit encoder switches and describe any change:](https://figures.academia-assets.com/36205873/figure_048.jpg)
![Let’s take a second look at the bit splitter. From Fig.4, notice that the splitter timing is independent of the [+4] unit output. On each high-to-/ow transition at TP1, the splitter inputs the voltage level at TP2. If information of the input modulation bits is neither to be missed nor counted twice, the individual bit duration must equal the clock period. After two successive inputs TP24 makes a /ow-to-high transition, marking the appearance of a new dibit at TP3, TP4. A aibit duration is twice that of a single bit, but one dibit contains the information of two bits.](https://figures.academia-assets.com/36205873/figure_050.jpg)
![The diagram indicates the phase of the [I+Q] signal to be 225° and the amplitude to be 1.4 units. Both these values are approximations, due to the limited size of the oscilloscope display. In the following activity you are to use this method to examine the [I+Q] signal.](https://figures.academia-assets.com/36205873/table_002.jpg)
![4: Vary the four toggle switches through all combinations and record the phase an amplitude of the displayed [I+Q] signal. 16—QAM De-modulation](https://figures.academia-assets.com/36205873/table_003.jpg)
