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Figure from:New Current-Mode Wave-Pipelined Architectures for High-Speed Analog-to-Digital Converters

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Fig. 13. (a) The measured SNDR versus conversion rate of the wave-pipelined IADC for 1-MHz analog input. (b) The measured SNDR versus analog input frequency of the wave-pipelined IADC at a 20-MS/s conversion rate.

Figure 13 (a) The measured SNDR versus conversion rate of the wave-pipelined IADC for 1-MHz analog input. (b) The measured SNDR versus analog input frequency of the wave-pipelined IADC at a 20-MS/s conversion rate.

Related Figures (15)

Fig. 1. Wave-pipelined ADC system.
Fig. 1. Wave-pipelined ADC system.
Fig. 4. Function block of the CM block. Fig. 3. Detailed structure of the wave-pipelined IADC.
Fig. 4. Function block of the CM block. Fig. 3. Detailed structure of the wave-pipelined IADC.
Fig. 2. Conceptual block diagram of the proposed 8-b wave-pipelined IADC.
Fig. 2. Conceptual block diagram of the proposed 8-b wave-pipelined IADC.
Fig. 5. (a) Four-stage example of the wave-pipelined structure. (b) Output current waveforms of the CM, stage for full-scale input swing. (c) Output current waveforms of the CM, stage for LSB scale input swing. time (T;-¢_;) plus the settling time (J; ) to reach their final stable value. During this period, the input current signal of the current mirror cannot be changed. Consequently, the time for which the input current signal must be held constant can be defined as the intrinsic delay Ti, of the current mirror. Hence, the intrinsic
Fig. 5. (a) Four-stage example of the wave-pipelined structure. (b) Output current waveforms of the CM, stage for full-scale input swing. (c) Output current waveforms of the CM, stage for LSB scale input swing. time (T;-¢_;) plus the settling time (J; ) to reach their final stable value. During this period, the input current signal of the current mirror cannot be changed. Consequently, the time for which the input current signal must be held constant can be defined as the intrinsic delay Ti, of the current mirror. Hence, the intrinsic
Fig. 6. (a) Space-timing diagram of the analog data path A. (b) Space-timing diagram of the analog data path B. to zero. Therefore, the minimum value of 77; is limited by the maximum value of intrinsic delay of the current mirror and the hold time of the current comparator. Furthermore, substituting (5) and (7) into (9) yields TJ.) in the following form: of the comparator, whereas the next LSB-swing datum requires min{Tint_3} time to set up. This constraint is expressed as
Fig. 6. (a) Space-timing diagram of the analog data path A. (b) Space-timing diagram of the analog data path B. to zero. Therefore, the minimum value of 77; is limited by the maximum value of intrinsic delay of the current mirror and the hold time of the current comparator. Furthermore, substituting (5) and (7) into (9) yields TJ.) in the following form: of the comparator, whereas the next LSB-swing datum requires min{Tint_3} time to set up. This constraint is expressed as
Fig. 7. (a) The simplified block diagram of the two-section ITWP-IADC for 4 CM stages. (b) The space-timing diagram of the two-section ITWP-IADC for 4 CM stages.
Fig. 7. (a) The simplified block diagram of the two-section ITWP-IADC for 4 CM stages. (b) The space-timing diagram of the two-section ITWP-IADC for 4 CM stages.
g. 8. Simplified block diagram of the two-section ITWP-IADC for eight CM stages. To further verify the proposed new architectures of full wave-pipelined [ADC (FWP-IADC), CMOS circuits are used to implement the ADC as a demonstrative example. The current mirror is a basic component in the proposed new architectures for the FWP-IADC. It acts as a current conveyer, an inverter, and an analog delay element. Accordingly, the design of the current mirror is crucial. Generally, high output impedance is required in the current mirror to reduce the gain error. Fig. 9(a) shows the adopted current mirror circuit with the enhanced output impedance, as proposed by Sdckinger ef al. [23]. As shown in Fig. 9(a), the capacitances Cl and C2 are added to reduce the ripple phenomenon of the input current. The MOS- FETs M9, M10, M11 and M12, with their associated current sources Ip;, Ip2, [p3, and [p4 are common-source amplifiers that provide negative feedback to the cascoded devices M1, M3, M6, and M8, respectively, and increase the output resistance of the current mirror. Assuming that the output resistances of current sources Ip2 and [py are approximately rggi9 and Tas12, respectively, the final output resistance can be written as
g. 8. Simplified block diagram of the two-section ITWP-IADC for eight CM stages. To further verify the proposed new architectures of full wave-pipelined [ADC (FWP-IADC), CMOS circuits are used to implement the ADC as a demonstrative example. The current mirror is a basic component in the proposed new architectures for the FWP-IADC. It acts as a current conveyer, an inverter, and an analog delay element. Accordingly, the design of the current mirror is crucial. Generally, high output impedance is required in the current mirror to reduce the gain error. Fig. 9(a) shows the adopted current mirror circuit with the enhanced output impedance, as proposed by Sdckinger ef al. [23]. As shown in Fig. 9(a), the capacitances Cl and C2 are added to reduce the ripple phenomenon of the input current. The MOS- FETs M9, M10, M11 and M12, with their associated current sources Ip;, Ip2, [p3, and [p4 are common-source amplifiers that provide negative feedback to the cascoded devices M1, M3, M6, and M8, respectively, and increase the output resistance of the current mirror. Assuming that the output resistances of current sources Ip2 and [py are approximately rggi9 and Tas12, respectively, the final output resistance can be written as
Fig. 9. (a) Enhanced output-impedance current mirror. (b) The simulated output current waveforms of the CM; stage in a two-section ITWP-IADC structure with full-scale step input current from 0 to 128 4A. (c) The output current waveforms of the CM; stage in a four-section ITWP-IADC structure with nonfull-scale step input current of 20 A.
Fig. 9. (a) Enhanced output-impedance current mirror. (b) The simulated output current waveforms of the CM; stage in a two-section ITWP-IADC structure with full-scale step input current from 0 to 128 4A. (c) The output current waveforms of the CM; stage in a four-section ITWP-IADC structure with nonfull-scale step input current of 20 A.
Fig. 10. (a) Second and third current-mode sub-DACs. (b) The ith sub-DAC. (c) The output transition curve of the 7th DAC.
Fig. 10. (a) Second and third current-mode sub-DACs. (b) The ith sub-DAC. (c) The output transition curve of the 7th DAC.
COMPARISON OF CMOS CURRENT-MODE PIPELINED ADCS limits of the developed architecture could be recognized. There- fore, the arbitrary-waveform-generator must be used to generate the 12-b S/H voltage. The chip was laid out to contain eight wave-pipelined stages. For simplicity, this demonstrative design included neither digital error correction nor calibration circuits. In the experimental chip of the FWP-IADC, the simple current comparator [21] is used. In Table I, the performance of the ITWP-IADC is compared with that of other known CMOS current-mode pipelined ADCs. It can be seen from that the ITWP-IADC has the superior speed performance.
COMPARISON OF CMOS CURRENT-MODE PIPELINED ADCS limits of the developed architecture could be recognized. There- fore, the arbitrary-waveform-generator must be used to generate the 12-b S/H voltage. The chip was laid out to contain eight wave-pipelined stages. For simplicity, this demonstrative design included neither digital error correction nor calibration circuits. In the experimental chip of the FWP-IADC, the simple current comparator [21] is used. In Table I, the performance of the ITWP-IADC is compared with that of other known CMOS current-mode pipelined ADCs. It can be seen from that the ITWP-IADC has the superior speed performance.
Fig. 11. (a) The circuit structure of the low-input-impedance current comparator. (b) The transition characteristic of the current comparator.
Fig. 11. (a) The circuit structure of the low-input-impedance current comparator. (b) The transition characteristic of the current comparator.
MEASURED WAVE-PIPELINED IADC CHARACTERISTICS plots the measured SNDR versus the analog input frequency for a full-scale sinusoidal input at 20 MS/s. The SNDR is seen to exceed 25.4 dB when the input frequency is between | and 10 MHz. The measured results verify the advantages of high input frequency and Nyquist-rate operation in the proposed architecture of WP-IADCs.
MEASURED WAVE-PIPELINED IADC CHARACTERISTICS plots the measured SNDR versus the analog input frequency for a full-scale sinusoidal input at 20 MS/s. The SNDR is seen to exceed 25.4 dB when the input frequency is between | and 10 MHz. The measured results verify the advantages of high input frequency and Nyquist-rate operation in the proposed architecture of WP-IADCs.
Fig. 12. Photograph of the fabricated chip.
Fig. 12. Photograph of the fabricated chip.