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Figure 5. Representation of a physical parameter (a-axis) by the spike firing rates (y-axis) of a heterogeneous population of 50 neurons. Each curve shows the firing rate of one neuron (after Eliasmith & Anderson 2003).

Figure 5 Representation of a physical parameter (a-axis) by the spike firing rates (y-axis) of a heterogeneous population of 50 neurons. Each curve shows the firing rate of one neuron (after Eliasmith & Anderson 2003).

Related Figures (6)

Figure 1. A view of the neuron cells and connections from a very small area of the cortex. Photo courtesy of the Brain Mind Institute, EPFL, Lausanne, Switzerland.
Figure 1. A view of the neuron cells and connections from a very small area of the cortex. Photo courtesy of the Brain Mind Institute, EPFL, Lausanne, Switzerland.
Figure 2. The four primary structures of a neuron. Inputs are collected via the dendrites and passed to the soma, the main body of the cell. The action potential (spike) generated in the soma propagates along the axon, where it passes through synapses to the dendrites of other neurons.
Figure 2. The four primary structures of a neuron. Inputs are collected via the dendrites and passed to the soma, the main body of the cell. The action potential (spike) generated in the soma propagates along the axon, where it passes through synapses to the dendrites of other neurons.
Figure 3. The neuron as a component. In the leaky integrate- and-fire model, input spikes are multiplied by their respective synaptic weights, summed and integrated over time. If the integral exceeds a threshold, the neuron fires and the integration restarts. The output spike may be delayed to model the propagation time along the axon.
Figure 3. The neuron as a component. In the leaky integrate- and-fire model, input spikes are multiplied by their respective synaptic weights, summed and integrated over time. If the integral exceeds a threshold, the neuron fires and the integration restarts. The output spike may be delayed to model the propagation time along the axon.
Figure 4. A solution to Izhikevich’s equations, driven by an input step function at 20 ms. The slow variable, u (lower curve), has been offset by —80 mV for clarity. This solution was obtained using a 10 bit fixed-point approximation to the equations, but is very close to the real-valued solution.
Figure 4. A solution to Izhikevich’s equations, driven by an input step function at 20 ms. The slow variable, u (lower curve), has been offset by —80 mV for clarity. This solution was obtained using a 10 bit fixed-point approximation to the equations, but is very close to the real-valued solution.
Figure 6. Organization of a SpiNNaker chip multiprocessor node, illustrating the Communications Network-on-Chip (NoC) that is used to carry spike event packets around the system. Each fascicle processors models many neurons. Packets from other nodes arrive through the receiver interfaces (‘Rx i/f’) and are merged with packets issued by the fascicle processors into a sequential stream by the arbiter. Each packet is then routed to one or several destinations, which may include other processing nodes (via the transmit interfaces—‘Tx i/f’) and/or local fascicle processors. The monitor processor carries out operating system functions and provides visibility to the user of on-chip activity.
Figure 6. Organization of a SpiNNaker chip multiprocessor node, illustrating the Communications Network-on-Chip (NoC) that is used to carry spike event packets around the system. Each fascicle processors models many neurons. Packets from other nodes arrive through the receiver interfaces (‘Rx i/f’) and are merged with packets issued by the fascicle processors into a sequential stream by the arbiter. Each packet is then routed to one or several destinations, which may include other processing nodes (via the transmit interfaces—‘Tx i/f’) and/or local fascicle processors. The monitor processor carries out operating system functions and provides visibility to the user of on-chip activity.
Figure 7. SpiNNaker system architecture. Each of the chip multiprocessor nodes is connected to its six nearest neigh- bours by bi-directional links. The left and right sides of the mesh are connected, as are the top and bottom edges, to form a two-dimensional toroidal surface.
Figure 7. SpiNNaker system architecture. Each of the chip multiprocessor nodes is connected to its six nearest neigh- bours by bi-directional links. The left and right sides of the mesh are connected, as are the top and bottom edges, to form a two-dimensional toroidal surface.