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Figure from:A novel genetic algorithm for evolvable hardware

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ihe genetic aigorithm described in this paper is intended for the design of combinational logic circuits based on a PLA structure. The key motivation for designing this algorithm is to have a fast configuration of the combinational logic circuits. The main characteristics of the proposed method are the use of several populations in parallel, and the construction of one population from the elitism’s pool (which contains the best chromosomes of each population). In order to describe the proposed algorithm, the evolution of a simple circuit is considered. Supposing that a circuit based on a PLA structure with 4 inputs should be evolved. Therefore the evolutionary algorithm should set the correct connections in the AND plane (for each interconnection the possible choices in the AND plane are “connect to 1”, “connect to 0” or “not connect’) and in the OR plane (the choices are “connected” or “not connected”). For the proposed algorithm (as reported in Figure 1) two different types of chromosomes have been considered: Figure 1. Example of chromosomes in the PLA. Two types of chromosomes are noticeable, the ch_and for the AND plane and the ch_or for the OR plane.
ihe genetic aigorithm described in this paper is intended for the design of combinational logic circuits based on a PLA structure. The key motivation for designing this algorithm is to have a fast configuration of the combinational logic circuits. The main characteristics of the proposed method are the use of several populations in parallel, and the construction of one population from the elitism’s pool (which contains the best chromosomes of each population). In order to describe the proposed algorithm, the evolution of a simple circuit is considered. Supposing that a circuit based on a PLA structure with 4 inputs should be evolved. Therefore the evolutionary algorithm should set the correct connections in the AND plane (for each interconnection the possible choices in the AND plane are “connect to 1”, “connect to 0” or “not connect’) and in the OR plane (the choices are “connected” or “not connected”). For the proposed algorithm (as reported in Figure 1) two different types of chromosomes have been considered: Figure 1. Example of chromosomes in the PLA. Two types of chromosomes are noticeable, the ch_and for the AND plane and the ch_or for the OR plane.
Figure 2. One population contains all the chromosomes (ch_and and ch_or) of the PLA.
Figure 2. One population contains all the chromosomes (ch_and and ch_or) of the PLA.
Figure 3. Evaluation mechanism for the proposed genetic algorithm. Each chromosome of all the populations will be evaluated and its fitness value is stored in the fitness’s value table.
Figure 3. Evaluation mechanism for the proposed genetic algorithm. Each chromosome of all the populations will be evaluated and its fitness value is stored in the fitness’s value table.
Figure 4. Selection mechanism.
Figure 4. Selection mechanism.
Figure 5. Reproduction mechanism. The new populations are reproduced from the best population (the population with the highest value of FVP) and from the best built population using only the mutation operator.
Figure 5. Reproduction mechanism. The new populations are reproduced from the best population (the population with the highest value of FVP) and from the best built population using only the mutation operator.
[1]. OPTIMIZATION OF THE EVOLVED LOGIC CIRCUITS
[1]. OPTIMIZATION OF THE EVOLVED LOGIC CIRCUITS
Figure 8. Logic circuit optimized by the proposed genetic algorithm. Figure 7. (a) Truth table of a logic circuit. (b) Logic circuit based on a PLA designed by the proposed genetic algorithm.
Figure 8. Logic circuit optimized by the proposed genetic algorithm. Figure 7. (a) Truth table of a logic circuit. (b) Logic circuit based on a PLA designed by the proposed genetic algorithm.
Table 2. Experimental results, three different benchmarks have used for testing the proposed algorithm “in” is the number of inputs, “out” the number of outputs “pro” the number of products or input-output combinations. FV stands for fitness value and Avg. stands for average.
Table 2. Experimental results, three different benchmarks have used for testing the proposed algorithm “in” is the number of inputs, “out” the number of outputs “pro” the number of products or input-output combinations. FV stands for fitness value and Avg. stands for average.
proposed algorithm is very efficient in terms of the number of generations. For example the average number of generations for evolving a circuit with 8 inputs (256 combinations) and 9 inputs (512 combinations) is less than 80. For the design of circuits with 10 inputs the number of “Avg. NG” refers to the average number of generations required to fully design the examined logic circuits; while “Avg. Time [s]” is the average time for the simulation in seconds. “FV” refers to the fitness value reached during the evolution stage. The experimental results show that the
proposed algorithm is very efficient in terms of the number of generations. For example the average number of generations for evolving a circuit with 8 inputs (256 combinations) and 9 inputs (512 combinations) is less than 80. For the design of circuits with 10 inputs the number of “Avg. NG” refers to the average number of generations required to fully design the examined logic circuits; while “Avg. Time [s]” is the average time for the simulation in seconds. “FV” refers to the fitness value reached during the evolution stage. The experimental results show that the
Figure 9. Number of generations required to fully evolve the OR plane of the Misex1.pla logic circuit (8 inputs and 7 outputs) using different values of thi divider (D).
Figure 9. Number of generations required to fully evolve the OR plane of the Misex1.pla logic circuit (8 inputs and 7 outputs) using different values of thi divider (D).