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Table 4 IMDCT average simulation time (10 non-sequential runs each) for the full platform and for the IP with Simulation Replay working. All images are plain color JPG images generated using GIMP with 75% of compression, no interlacing, and using integer DCT. First two are synthetic images while the others are stock photos EE ee ee ee ae ee oe ees oe ee Another advantage of Signal Replay goes beyond simulation time reduction. If a small number of testing points are enough to point out the error, simulation can be aborted without the need to wait for the execution of the other modules and, the designer can inject the offending dataset again with no extra work. Decoupling simulation also ensures that every design team has a full working testbench, impossible to be invalidated by previous errors in another module. This isolation can be compared to software sandboxes, where a DUV error does not propagate to the platform, thus allowing different teams to work on different parts of the platform simultaneously without breaking each other test environment. In fact, one core can be fully refined to the synthesizable level without any platform change. TOs en en Te Shee Ae

Table 4 IMDCT average simulation time (10 non-sequential runs each) for the full platform and for the IP with Simulation Replay working. All images are plain color JPG images generated using GIMP with 75% of compression, no interlacing, and using integer DCT. First two are synthetic images while the others are stock photos EE ee ee ee ae ee oe ees oe ee Another advantage of Signal Replay goes beyond simulation time reduction. If a small number of testing points are enough to point out the error, simulation can be aborted without the need to wait for the execution of the other modules and, the designer can inject the offending dataset again with no extra work. Decoupling simulation also ensures that every design team has a full working testbench, impossible to be invalidated by previous errors in another module. This isolation can be compared to software sandboxes, where a DUV error does not propagate to the platform, thus allowing different teams to work on different parts of the platform simultaneously without breaking each other test environment. In fact, one core can be fully refined to the synthesizable level without any platform change. TOs en en Te Shee Ae

Related Figures (9)

3.1 ReflexBox implementation
3.1 ReflexBox implementation
Computational reflection and its application to platform verification every ReflexBox invocation, it gather all the data that the user asked to reflect and compare with the last module state (stored internally). If any change occurred, the ReflexBox search for the user parameters looking for an action to take (e.g. hold the simulation waiting for an user input or just show the value).
Computational reflection and its application to platform verification every ReflexBox invocation, it gather all the data that the user asked to reflect and compare with the last module state (stored internally). If any change occurred, the ReflexBox search for the user parameters looking for an action to take (e.g. hold the simulation waiting for an user input or just show the value).
In this section we discuss two applications of our ReflexBox in platform debugging and performance evaluation.
In this section we discuss two applications of our ReflexBox in platform debugging and performance evaluation.
timers and interrupt controller) are mapped to addresses between 9 MB and 10 MB. The MMU is responsible for dealing with paging and redirecting issues. Offset redirection is done automatically, but paging should be programmed by the processor. Accesses to the memory region from 0 to 2 MB and from 3 to 10 MB are redirected to real memory through Memory Management Unit (MMU) paging. Memory addresses from 2 MB to 3 MB are redirected, without paging, to IP-core addresses from 9 MB to 10 MB. One important point is that the designers of this platform had no access to any source code except for the proces- sor model. For the remaining platform modules, all they had were the prototype headers and object files (.H and .o files).
timers and interrupt controller) are mapped to addresses between 9 MB and 10 MB. The MMU is responsible for dealing with paging and redirecting issues. Offset redirection is done automatically, but paging should be programmed by the processor. Accesses to the memory region from 0 to 2 MB and from 3 to 10 MB are redirected to real memory through Memory Management Unit (MMU) paging. Memory addresses from 2 MB to 3 MB are redirected, without paging, to IP-core addresses from 9 MB to 10 MB. One important point is that the designers of this platform had no access to any source code except for the proces- sor model. For the remaining platform modules, all they had were the prototype headers and object files (.H and .o files).
The designer created a functional description of an specialized IDCT core and connected it to the platform using a TLM interface. Inside the core, a SystemC process receives the incoming TLM requests and monitors a control register, awaiting for a non-zero value to trigger the IDCT computation. In fact, the core acts like a slave to the processor, which programs the core registers and sets the control register to signal its operation. Once the IDCT is triggered, it changes to master of the bus, racing with the processor for the memory access (and consequently for the bus). After all computation is finished, the core sets its control register back to zero, signaling the processor that the job is done, and returns to the slave state. This platform is shown in Fig. 5. The reflection mechanism was iced in this nlatform with two nurnoses First. the desioner
The designer created a functional description of an specialized IDCT core and connected it to the platform using a TLM interface. Inside the core, a SystemC process receives the incoming TLM requests and monitors a control register, awaiting for a non-zero value to trigger the IDCT computation. In fact, the core acts like a slave to the processor, which programs the core registers and sets the control register to signal its operation. Once the IDCT is triggered, it changes to master of the bus, racing with the processor for the memory access (and consequently for the bus). After all computation is finished, the core sets its control register back to zero, signaling the processor that the job is done, and returns to the slave state. This platform is shown in Fig. 5. The reflection mechanism was iced in this nlatform with two nurnoses First. the desioner
Computational reflection and its application to platform verification correcting the type-casting, all accesses were corrected and the final decoded image was presented.
Computational reflection and its application to platform verification correcting the type-casting, all accesses were corrected and the final decoded image was presented.