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Figure from:A high bit resolution FPGA implementation of a FNN with a new algorithm for the activation function

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The goal that was searched was to obtain a hardware solution that allowed the direct use of the weights,

Table 2 The goal that was searched was to obtain a hardware solution that allowed the direct use of the weights,

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Figure 1 shows a detail of the linear section approach versus the single point approach.
Figure 1 shows a detail of the linear section approach versus the single point approach.
The development of the circuit was done in the Quartus II environment. Figure 2 - Picture of the Cyclone SmartPack kit.
The development of the circuit was done in the Quartus II environment. Figure 2 - Picture of the Cyclone SmartPack kit.
Figure 3 - Logical structure of the basic processing block in the ANNP. - The basic structure is composed of the multiplier, adder and activation function (Figure 3) and must be reused several times in order to implement the ANN.
Figure 3 - Logical structure of the basic processing block in the ANNP. - The basic structure is composed of the multiplier, adder and activation function (Figure 3) and must be reused several times in order to implement the ANN.
The main window of this application that runs in MATLAB can be seen in Figure 4. Figure 4 - Main window of the debugging application.
The main window of this application that runs in MATLAB can be seen in Figure 4. Figure 4 - Main window of the debugging application.
possible to perform control action. The control strategy used was a simple Direct Inverse Control (DIC) that is represented in Figure 5. Figure 6 shows a block diagram of the connection between MATLAB and the FPGA and Table 1 shows the characteristics of the inverse models tested in the FPGA.
possible to perform control action. The control strategy used was a simple Direct Inverse Control (DIC) that is represented in Figure 5. Figure 6 shows a block diagram of the connection between MATLAB and the FPGA and Table 1 shows the characteristics of the inverse models tested in the FPGA.
To complete the analysis of the results and separate the error that is introduced by the use of the FPGA from the one introduced by the models, the same control is performed with both models in MATLAB. Figure 7 - FPGA results with ramp signal.
To complete the analysis of the results and separate the error that is introduced by the use of the FPGA from the one introduced by the models, the same control is performed with both models in MATLAB. Figure 7 - FPGA results with ramp signal.
Table 1- Resume of the characteristics of the inverse models tested in the FPGA. 5. CONCLUSION and FUTURE WORK
Table 1- Resume of the characteristics of the inverse models tested in the FPGA. 5. CONCLUSION and FUTURE WORK
The results in the form of Mean Square Error (MSE) are summarized in Table 2. As can be seen the difference obtained between the control with the FPGA and the ones simulated in MATLAB, in terms of MSE, does not exceed 5x10°. Figure 8 - FPGA results with ramp and square wave signal.
The results in the form of Mean Square Error (MSE) are summarized in Table 2. As can be seen the difference obtained between the control with the FPGA and the ones simulated in MATLAB, in terms of MSE, does not exceed 5x10°. Figure 8 - FPGA results with ramp and square wave signal.
Figure 9 - FPGA results with pseudo-random signal. This objective was successfully accomplished as was shown by the control tests done with models of a real system, where the maximum error obtained between the MATLAB and the hardware solution, using the MSE as a measure was of 5x10°.
Figure 9 - FPGA results with pseudo-random signal. This objective was successfully accomplished as was shown by the control tests done with models of a real system, where the maximum error obtained between the MATLAB and the hardware solution, using the MSE as a measure was of 5x10°.