Academia.eduAcademia.edu

Figure from:SMT8036 Based Implementation of Secured Software Defined Radio System for Adaptive Modulation Technique

See full PDFdownloadDownload figure
Fig. 3.5: Functional block diagram of ST-UC in SDR [5]. clock distributor and it is required to generate reference clock signals with ultra-low phase

Figure 3 5: Functional block diagram of ST-UC in SDR [5]. clock distributor and it is required to generate reference clock signals with ultra-low phase

Related Figures (46)

Fig. 1.1: Relationship between SDR and cognitive radio [1]. radio. This includes assisting users in dealing with the exponentially increasing array of \s a result, SDR can support multiple standards (i.e. GSM, EDGE, WCDMA, CDMA2000.
Fig. 1.1: Relationship between SDR and cognitive radio [1]. radio. This includes assisting users in dealing with the exponentially increasing array of \s a result, SDR can support multiple standards (i.e. GSM, EDGE, WCDMA, CDMA2000.
continuous design cycle. Advanced system design concepts including, simulation, code Complicated systems can be created by using mathematical models, representing system
continuous design cycle. Advanced system design concepts including, simulation, code Complicated systems can be created by using mathematical models, representing system
Fig. 2.4: Multi-core architecture for recent SDR [10] connections between different processors.
Fig. 2.4: Multi-core architecture for recent SDR [10] connections between different processors.
Fig. 2.5: Prototypes of MILS certifiable separation kernel technology [14] included certified IPv4 and IPv6 compliant protocol stacks and firewall applications. For more secure SDR system we need The ability of the computing platform to be MILS certifiable separation kernel technology to run the security layer applications which
Fig. 2.5: Prototypes of MILS certifiable separation kernel technology [14] included certified IPv4 and IPv6 compliant protocol stacks and firewall applications. For more secure SDR system we need The ability of the computing platform to be MILS certifiable separation kernel technology to run the security layer applications which
merely be shorted; otherwise each will experience a variable power envelope at its output wideband balun transformer. The core PA is designed for +20dBm maximum power. For
merely be shorted; otherwise each will experience a variable power envelope at its output wideband balun transformer. The core PA is designed for +20dBm maximum power. For
So we can get any frequency output in specified band.
So we can get any frequency output in specified band.
acknowledges cognitive engine that the specified configuration is performed. 3.2.2 Realistic SDR Architecture
acknowledges cognitive engine that the specified configuration is performed. 3.2.2 Realistic SDR Architecture
converters), ideal SDR architectures are costly.
converters), ideal SDR architectures are costly.
number of capacitors (N1, N2) employed, the better the tunability is achieved. By varying Fig. 3.4: software tuned Impedance synthesizer structure [3]. these values the impedance matching is achieved. Cognitive engine determines the values o}
number of capacitors (N1, N2) employed, the better the tunability is achieved. By varying Fig. 3.4: software tuned Impedance synthesizer structure [3]. these values the impedance matching is achieved. Cognitive engine determines the values o}
Fig. 3.6: Architecture of a DSP processor the “multiply and accumulate” operation and the important factor is memory bandwidth. The
Fig. 3.6: Architecture of a DSP processor the “multiply and accumulate” operation and the important factor is memory bandwidth. The
Some important features of the Xilinx Virtex-II FPGA are
Some important features of the Xilinx Virtex-II FPGA are
At the receiver, the received signal is multiplied by a local generated carrier and output is passed from a filter having center frequency same as we are using to operate the
At the receiver, the received signal is multiplied by a local generated carrier and output is passed from a filter having center frequency same as we are using to operate the
not continuous at bit transitions as shown in figure 4.3. This form of FSK is therefore called non-coherent or discontinuous FSK. It can be generated two signals are not coherent since ®; and ®> are not the same in general. The waveform
not continuous at bit transitions as shown in figure 4.3. This form of FSK is therefore called non-coherent or discontinuous FSK. It can be generated two signals are not coherent since ®; and ®> are not the same in general. The waveform
bit boundaries. Sunde’s FSK is a continuous phase FSK. Fig. 4.4: output waveform for sunde’s FSK or Binary FSK [38] carrier is the same as the starting phase, therefore the waveform has continuous phase at the
bit boundaries. Sunde’s FSK is a continuous phase FSK. Fig. 4.4: output waveform for sunde’s FSK or Binary FSK [38] carrier is the same as the starting phase, therefore the waveform has continuous phase at the
as its horizontal and vertical axis, respectively. The waveform of a BPSK signal is shown in
as its horizontal and vertical axis, respectively. The waveform of a BPSK signal is shown in
If the f, = m Rp = m/T, where m is an integer and Ry is the data bit rate, and the bit timing is
If the f, = m Rp = m/T, where m is an integer and Ry is the data bit rate, and the bit timing is
However, if the f, is not an integer multiple of Ry, the initial phase at a bit boundary is neither
However, if the f, is not an integer multiple of Ry, the initial phase at a bit boundary is neither
In Figure 4.8 it can be seen that with QPSK each of the four possible output phasors has 90°. The truth table 4.1 and waveforms supporting above is presented here in fig 4.9
In Figure 4.8 it can be seen that with QPSK each of the four possible output phasors has 90°. The truth table 4.1 and waveforms supporting above is presented here in fig 4.9
The received QPSK signal (-sin Wet +cos Wet) is one of the inputs to the product detector. The output is recovered carrier (sin w.t ). The output of I product detector is
The received QPSK signal (-sin Wet +cos Wet) is one of the inputs to the product detector. The output is recovered carrier (sin w.t ). The output of I product detector is
Therefore, an 8-PSK signal can undergo almost 22.5° phase shift in positive or negative
Therefore, an 8-PSK signal can undergo almost 22.5° phase shift in positive or negative
Also each phasor is of equal magnitude. The truth table showing values of output phases is Tribit input is shown in figure 4.11.
Also each phasor is of equal magnitude. The truth table showing values of output phases is Tribit input is shown in figure 4.11.
during transmission, it would most likely to be shifted to an adjacent phasor. Using the gray Table 4.2 Binary Input vs 8-psk output phase
during transmission, it would most likely to be shifted to an adjacent phasor. Using the gray Table 4.2 Binary Input vs 8-psk output phase
Table 4.3 Modulation schemes and their frequency bands.
Table 4.3 Modulation schemes and their frequency bands.
Fig. 4.12: Multi-modulation software defined radio transmitter. 4.5.2 Random number generator based Multi-Modulation SDR Transmitter.
Fig. 4.12: Multi-modulation software defined radio transmitter. 4.5.2 Random number generator based Multi-Modulation SDR Transmitter.
which selects the modulation scheme and data is given to data processing task where data is
which selects the modulation scheme and data is given to data processing task where data is
Fig. 4.13: Random number generator based Multi-modulation software defined radio transmitter. converted into analog signal.
Fig. 4.13: Random number generator based Multi-modulation software defined radio transmitter. converted into analog signal.
Fig. 4.14: Adaptive software defined radio receiver structure detection of received signal is done through selected demodulator circuit.
Fig. 4.14: Adaptive software defined radio receiver structure detection of received signal is done through selected demodulator circuit.
= Global expansion connector. (SMT370), both plugged on a PCI carrier board (SMT310Q) as shown in figure 5.1. => High bandwidth data I/O via 2 Sundance High-speed Buses (SHB).
= Global expansion connector. (SMT370), both plugged on a PCI carrier board (SMT310Q) as shown in figure 5.1. => High bandwidth data I/O via 2 Sundance High-speed Buses (SHB).
Fig. 5.3: Block diagram showing transmitter up-converter module [42]
Fig. 5.3: Block diagram showing transmitter up-converter module [42]
id filtering the RF signal at 2.4-2.5GHz as shown in figure 5.6. The module contains the RF
id filtering the RF signal at 2.4-2.5GHz as shown in figure 5.6. The module contains the RF
5.2 PROGRAMMING APPROACH ower amplifier and the low noise amplifier. The amplifier provides the necessary RF output
5.2 PROGRAMMING APPROACH ower amplifier and the low noise amplifier. The amplifier provides the necessary RF output
+ve and —ve number respectively as described in figure 5.8.
+ve and —ve number respectively as described in figure 5.8.
Fig. 5.8: Block diagram showing Communication between task This is one way to achieve pipelining in DSP because the moment our input task will accept
Fig. 5.8: Block diagram showing Communication between task This is one way to achieve pipelining in DSP because the moment our input task will accept
Figure 5.9 is a screen shot which shows two tasks one is “inp” which takes input and gives us int a,i;
Figure 5.9 is a screen shot which shows two tasks one is “inp” which takes input and gives us int a,i;
requirement. For the above described example connections will be as shown in figure 5.12. Finally output for the code is given in figure 5.13 Fig. 5.11: Code for changing the values of variables
requirement. For the above described example connections will be as shown in figure 5.12. Finally output for the code is given in figure 5.13 Fig. 5.11: Code for changing the values of variables
For logic 1 output is shown in fig 5.15
For logic 1 output is shown in fig 5.15
Fig. 5.16: Output waveform for logic 0
Fig. 5.16: Output waveform for logic 0
For logic 1 output will be as shown in figure 5.19 Fig. 5.18: Logic for BPSK For logic 0 output will be figure 5.20
For logic 1 output will be as shown in figure 5.19 Fig. 5.18: Logic for BPSK For logic 0 output will be figure 5.20
Fig. 5.23: FSK modulation (baseband)
Fig. 5.23: FSK modulation (baseband)
11). This can be seen in figure 5.24. Fig. 5.24: QPSK modulation (baseband)
11). This can be seen in figure 5.24. Fig. 5.24: QPSK modulation (baseband)
Similarly for 8-PSK, three bits per symbol period is selected to transmit. So we have 8
Similarly for 8-PSK, three bits per symbol period is selected to transmit. So we have 8
Fig 5.26: 8-PSK modulation (baseband) signals of different phase shifts. This can be seen in figure 5.26.
Fig 5.26: 8-PSK modulation (baseband) signals of different phase shifts. This can be seen in figure 5.26.
that for same BER, BPSK requires minimum SNR Fig. 5.27: BER Comparison for different modulation schemes in Adaptive SDR receiver.
that for same BER, BPSK requires minimum SNR Fig. 5.27: BER Comparison for different modulation schemes in Adaptive SDR receiver.