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Figure from:Placement and Routing for Performance-Oriented FPGA Layout

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FIGURE 5 Global-routing information (a) is used to con- struct a routing graph (b) for a Xilinx [43] 4000-series part with channel width 2.

Figure 5 Global-routing information (a) is used to con- struct a routing graph (b) for a Xilinx [43] 4000-series part with channel width 2.

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FIGURE 1 A typical FPGA architecture. implementation. In particular, FPR successfully lays out a number of large industrial benchmark circuits using smaller channel widths than other FPGA layout tools, and also optimizes source-sink pathlengths as a secondary criterion. implementation. In particular, FPR successfully
FIGURE 1 A typical FPGA architecture. implementation. In particular, FPR successfully lays out a number of large industrial benchmark circuits using smaller channel widths than other FPGA layout tools, and also optimizes source-sink pathlengths as a secondary criterion. implementation. In particular, FPR successfully
FIGURE 2 (a) Partitioning template for m=n=3; (b) a sample pointset (the source is at the upper-left); (c) one of its possible thumbnails; and (d) the associated virtual pins. - Our strategy consists of placement and global routing, followed by detailed routing. During placement and global routing, a partitioning heuristic is used to assign the logic blocks to regions in the partitioning template, minimizing
FIGURE 2 (a) Partitioning template for m=n=3; (b) a sample pointset (the source is at the upper-left); (c) one of its possible thumbnails; and (d) the associated virtual pins. - Our strategy consists of placement and global routing, followed by detailed routing. During placement and global routing, a partitioning heuristic is used to assign the logic blocks to regions in the partitioning template, minimizing
FIGURE3 All eight thumbnails for the pointset shown in the 3x3 partitioning template (source is at upper-left).
FIGURE3 All eight thumbnails for the pointset shown in the 3x3 partitioning template (source is at upper-left).
FIGURE 4 Global-routing information for a three-pin net, showing the associated logic blocks (dark squares), global route (cross-hatched region), and potential Steiner switch block (large dark square).
FIGURE 4 Global-routing information for a three-pin net, showing the associated logic blocks (dark squares), global route (cross-hatched region), and potential Steiner switch block (large dark square).
FIGURE 6 Detailed-routing solutions; (a) a KMB solution containing unnecessary parallel paths, while (b) the IKMB solution reduces total number of channel edges by 22%. The IKMB method operates by repeatedly finding candidate Steiner nodes that reduce the Our detailed-routing algorithm is based on combining a greedy, iterated heuristic [21, 25] with the KMB algorithm; we refer to this hybrid method as the Iterated-KMB (IK MB) algorithm [1]. Given a routing graph G=(V, £),anet NC V, andaset S of potential Steiner nodes, we define the savings of S with respect to N as AKMB,G(N, S)=KMBg(N) —KMBg(N U S). Intuitively, AKMBg(N, S) repre- sents the interconnect savings incurred by KMB when the Steiner nodes in S are included into the node set N to be spanned. This is illustrated in Figure 6(b), where using a candidate Steiner node from the shaded switch block results in an optimal solution. In order to efficiently find such Steiner nodes, a set of candidate Steiner nodes is determined for each net. Candidate Steiner nodes are switch- block nodes that correspond to Steiner switch blocks (Fig. 4). ~3ws.| rr
FIGURE 6 Detailed-routing solutions; (a) a KMB solution containing unnecessary parallel paths, while (b) the IKMB solution reduces total number of channel edges by 22%. The IKMB method operates by repeatedly finding candidate Steiner nodes that reduce the Our detailed-routing algorithm is based on combining a greedy, iterated heuristic [21, 25] with the KMB algorithm; we refer to this hybrid method as the Iterated-KMB (IK MB) algorithm [1]. Given a routing graph G=(V, £),anet NC V, andaset S of potential Steiner nodes, we define the savings of S with respect to N as AKMB,G(N, S)=KMBg(N) —KMBg(N U S). Intuitively, AKMBg(N, S) repre- sents the interconnect savings incurred by KMB when the Steiner nodes in S are included into the node set N to be spanned. This is illustrated in Figure 6(b), where using a candidate Steiner node from the shaded switch block results in an optimal solution. In order to efficiently find such Steiner nodes, a set of candidate Steiner nodes is determined for each net. Candidate Steiner nodes are switch- block nodes that correspond to Steiner switch blocks (Fig. 4). ~3ws.| rr
FIGURE 8 Wavefront expansion is used to “loosen” global routes when infeasibility is encountered.
FIGURE 8 Wavefront expansion is used to “loosen” global routes when infeasibility is encountered.
TABLE I Maximum channel width required by SEGA [32], GBP [42] and FPR on the benchmark circuits
TABLE I Maximum channel width required by SEGA [32], GBP [42] and FPR on the benchmark circuits
4000-Series Benchmarks
4000-Series Benchmarks
FIGURE 9 FPR solution for 9symml circuit.
FIGURE 9 FPR solution for 9symml circuit.
FIGURE 11 A general upper bound in the metric case for MST(G(@)) in terms of MST(G;)’s, d,n, and k: (a) depicts MST (Gm); (b) depicts MST(G(d)); and (c) shows how the cost of the m'* weight component of each ej; can be bounded by dm + MST(G,).
FIGURE 11 A general upper bound in the metric case for MST(G(@)) in terms of MST(G;)’s, d,n, and k: (a) depicts MST (Gm); (b) depicts MST(G(d)); and (c) shows how the cost of the m'* weight component of each ej; can be bounded by dm + MST(G,).
FIGURE 10 An example showing that MST(G(d)) can not be bounded from above by any function strictly in terms of MST(G;)’s, d, n, and k: (a) The 2-weighted graph G; (b) MST(G((1,0))) has cost 0; (c) MST(G((0,1))) has cost 0. On the other hand, MST(G((4,}))) has cost 4, which can be arbitrarily large.
FIGURE 10 An example showing that MST(G(d)) can not be bounded from above by any function strictly in terms of MST(G;)’s, d, n, and k: (a) The 2-weighted graph G; (b) MST(G((1,0))) has cost 0; (c) MST(G((0,1))) has cost 0. On the other hand, MST(G((4,}))) has cost 4, which can be arbitrarily large.
FIGURE 13 Topology of the three spanning trees MST(G2) (inner), MST (G,) (middle) and MST(G(d )) (outer) corre- sponding to (i) case 2(a), (ii) case 2(b), and (iii) 2(c).
FIGURE 13 Topology of the three spanning trees MST(G2) (inner), MST (G,) (middle) and MST(G(d )) (outer) corre- sponding to (i) case 2(a), (ii) case 2(b), and (iii) 2(c).
FIGURE 12 A tighter upper bound for 3-pin nets; (i) a 3- node 2-weighted graph, with edge weights (a,x), (b,y), and (c, z); (ii) topology of the three spanning trees MST(G)) (inner), MST(G;) (middle) and MST(G(d)) (outer) corresponding to case 1.
FIGURE 12 A tighter upper bound for 3-pin nets; (i) a 3- node 2-weighted graph, with edge weights (a,x), (b,y), and (c, z); (ii) topology of the three spanning trees MST(G)) (inner), MST(G;) (middle) and MST(G(d)) (outer) corresponding to case 1.