design technique

The Dual-Tree complex wavelet transform (DT-CWT) uses approximate Hilbert transform pairs of wavelet, which requires that the filters of each tree of the dual-tree structure should be delayed approximately one half sample from each other. However, the filters of the first (finest) scale of the transform do not obey this condition, resulting in a poor directional selectivity for the first scale. In this paper, we describe a design technique for first-scale infinite impulse response (IIR) wavelet filters, that solves this problem. Results demonstrate that a much better directional selectivity is obtained, which indicates a performance improvement for many applications that use the DT-CWT where the preservation of high-frequency information is important.

This paper is Part 3 in a three-part series of papers addressing operational techniques for applying mass integration principles to design in industry with special focus on water conservation and wastewater reduction. The presented techniques derive from merging U.S. and Danish experience with industrial applications of process integration, as a result of a recently established cooperation between the

Design techniques based upon sensitivity analysis are not usual in the current design of suspension bridges. However, sensitivity analysis has been proved to be a useful tool in the car and aircraft industries. Evaluation of sensitivity analysis is a mandatory step in the way towards an efficient automated optimum design process which would represent a huge jump in the conception

In this study, we consider the vibration mitigation problem for a structural system using a magneto-rheological (MR) damper. For this purpose, through the use of Lyapunov-based design techniques, a nonlinear adaptive controller which can compensate the parametric uncertainties related to both the structural system and the MR damper has been constructed. To overcome effects of the unmeasurable internal dynamics of the MR damper on the controller, a filterbased design has been utilized. Experimental results performed on a six-degree-of-freedom (DOF) structure installed on a shaking table, illustrating the viability and the performance of the proposed method are also included.

In this paper, a learning-based feedforward term is developed to solve a general control problem in the presence of unknown nonlinear dynamics with a known period. Since the learning-based feedforward term is generated from a straightforward Lyapunov-like stability analysis, the control designer can utilize other Lyapunov-based design techniques to develop hybrid control schemes that utilize learning-based feedforward terms to compensate for periodic dynamics and other Lyapunov-based approaches (e.g., adaptive-based feedforward terms) to compensate for nonperiodic dynamics. To illustrate this point, a hybrid adaptive/learning control scheme is utilized to achieve global asymptotic link position tracking for a robot manipulator.

A regulator design technique for uncertain motor drive systems severely affected by nonlinear friction is presented in this paper. The regulator includes an internal adaptive loop to compensate for the nonlinear friction torque. The adaptive loop is based on a simple friction model, and is adapted with respect to the measure of performance. A new, simple search algorithm for the adaptation is proposed. The friction compensation allows the design of a lower gain robust linear controller for prescribed performance specifications. The closed loop is analyzed with respect to stability and performance. A quantitative comparison is made between robust control with and without friction compensation. Experimental results are presented.

Foot problems are varied and range from simple disorders through to complex diseases and joint deformities. Wherever possible, the use of insoles, or orthoses, is preferred over surgery. Current insole design techniques are based on static measurements of the foot, despite the fact that orthoses are prevalently used in dynamic conditions while walking or running. This paper presents the design and implementation of a structured-light prototype system providing dense three dimensional (3D) measurements of the foot in motion, and its use to show that foot measurements in dynamic conditions differ significantly from their static counterparts. The input to the system is a video sequence of a foot during a single step; the output is a 3D reconstruction of the plantar surface of the foot for each frame of the input. Engineering and clinical tests were carried out for the validation of the system. The accuracy of the system was found to be 0.34 mm with planar test objects. In tests with real feet, the system proved repeatable, with reconstruction differences between trials one week apart averaging 2.44 mm (static case) and 2.81 mm (dynamic case). Furthermore, a study was performed to compare the effective length of the foot between static and dynamic reconstructions using the 4D system. Results showed an average increase of 9 mm for the dynamic case. This increase is substantial for orthotics design, cannot be captured by a static system, and its subject-specific measurement is crucial for the design of effective foot orthoses.

The DARWARS Tactical Language Training System (TLTS) helps learners acquire basic communicative skills in foreign languages and cultures. Learners practice their communication skills in a simulated village, where they must develop rapport with the local people, who in term will help them accomplish missions such as post-war reconstruction. Each learner is accompanied by a virtual aide who can provide assistance and guidance if needed, tailored to each learner's individual skills. The aide can also act as a virtual tutor as part of an intelligent tutoring system, giving the learner feedback on their performance. Learners communicate via a multimodal interface, which permits them to speak and choose gestures on behalf of their character in the simulation. The system employs video game technologies and design techniques, in order to motivate and engage learners. A version for Levantine Arabic has been developed, and versions for other languages are in the process of being developed. A first version is scheduled to be transitioned into use by US Special Forces in late 2004. The TLTS project has developed and integrated several advanced technologies, including speech recognition tailored for learner speech, motivational tutorial dialog, learner modeling, and multi-agent social simulations. The virtual aide in the game is implemented as a pedagogical agent, able to interact with learners at a motivational and social level as well as a cognitive level. Character behavior in the game is controlled by the Psychsim cognitive modeling system, that models the motivations of social agents. Multi-user authoring tools enable linguists, instructional designers, and simulation developers to collaborate in the specification and construction of lessons and simulations in multiple languages. The TLTS is part of the DARWARS Training Superiority program developing new technologies for military training.

With chip temperature being a major hurdle in microprocessor design, techniques to recover the performance loss due to thermal emergency mechanisms are crucial in order to sustain performance growth. Many techniques for power reduction in the past and some on thermal management more recently have contributed to alleviate this problem. Probably the most important thermal control technique is dynamic voltage and frequency scaling (DVS) which allows for almost cubic reduction in power with worst-case performance penalty only linear. So far, DVS techniques for temperature control have been studied at the chip level. Finer grain DVS is feasible if a Globally-Asynchronous Locally-Synchronous (GALS) design style is employed. GALS, also known as Multiple-Clock Domain (MCD), allows for an independent voltage and frequency control for each one of the clock domains that are part of the chip. There are several studies on DVS for GALS that aim to improve energy and power efficiency but not temperature. This paper proposes and analyses the usage of DVS at the domain level to control temperature in a clustered MCD microarchitecture with the goal of improving the performance of applications that do not meet the thermal constraints imposed by the designers.

As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance and non-volatility. The integration of MRAM in FPGA allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, easily realize the dynamical reconfiguration and multicontext configuration. However, the conventional MRAM technology based on Field Induced Magnetic Switching (FIMS) writing approach consumes very high power and large circuit surface, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Thermally Assisted Switching (TAS) based MRAM is then evaluated to address these issues and some design techniques for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology, some chip characteristic results have been calculated to demonstrate the expected performance of TAS-MRAM based FPGA logic circuits.

As one of the most promising Spintronics applications, MRAM combines the advantages of high writing and reading speed, limitless endurance, and nonvolatility. The integration of MRAM in FPGAs allows the logic circuit to rapidly configure the algorithm, the routing and logic functions, and easily realize the Runtime Reconfiguration (RTR) and multicontext configuration. However, the conventional MRAM technology based on the Field Induced Magnetic Switching (FIMS) writing approach consumes very high power, large circuit surfaces, and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM’s further development in memory and logic circuit. Thermally Assisted Switching (TAS)-based MRAM is then evaluated to address these issues. In this article, some design techniques, novel computing architecture, and logic components for FPGA logic circuits based on TAS-MRAM technology are presented. By using STMicroelectronics CMOS 90nm technology and a complete TAS-MTJ spice ...

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAM's further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to ...

The paper addresses the design of an autopilot for small scale helicopters to let the vertical, lateral, longitudinal and yaw attitude dynamics to track aggressive references. The paper is mostly focused on robust control aspects of helicopters. In particular the distinguish feature of the control law proposed in the paper is the ability to deal with the presence of possible severe uncertainties characterizing the physical parameters of the plant. This is achieved by using non linear control design techniques. This work enriches a number of recent works focused on autopilot design for small scale helicopters (see, besides others, , , (Isidori et al., 2003) ), motivated, on one hand, from the interest that this kind of air-vehicle has in practical applications, , and, on the other hand, from some features of the helicopter model, such as the non linearity of the dynamics and the strong coupling between the forces and torques produced by vehicle actuators, which render the system in question an ideal test-bed for testing and comparing nonlinear design techniques. Inspired by the stabilizing techniques proposed in (Isidori et al., 2003), the control structure is designed as a mix of feed-forward actions, computed according to the reference signals to be tracked and a nominal model inversion (see also (Lane et al., 1998)), (Prasad et al., 1991)), and feedback terms obtained by combining high gain and nested saturation control laws. More specifically the control law proposed is based on a cascade control structure, composed by an inner loop and an outer loop governing respectively the attitude dynamics and the lateral-longitudinal dynamics. It is shown, also by means of simulation results, how the proposed control structure is able to enforce aggressive manoeuvres, in particular the case of maneuvers performed with aggressive attitude angles is considered, showing how, even in this challenging scenario, the proposed controller is able to achieve asymptotic robustness to a number of physical parameters which are typically affected by strong uncertainties.

FLEXIBLE ASIC and application-specific standardproduct (ASSP) solutions such as smart cards, handheld computers, language translators, and telecommunication devices use embedded, electrically erasable, programmable ROM (EEPROM) extensively. EEPROM provides insystem programmability and on-chip repair capabilities for system-on-a-chip (SoC) applications, which can reduce the product's cost and development time. Moreover, an EEPROM's byte-by-byte or page-by-page write operation, high endurance, and lowpower efficiency make it more attractive than flash technology for applications requiring memory sizes up to 1 megabit. When embedded in a portable application, EEPROM operates under a wide supply voltage rangetypically 3.3 V to 1.8 V. As Figure shows, assuming the power-delay product is a good indicator, the performances of battery-operated SoCs are clearly limited at the two extremes of the supply voltage range. The higher value of the power supply means increased power consumption at the beginning of battery life, while speed degradation becomes an issue for supply voltage values below 2 V at the end of battery life. To address this variance in performance, we have developed a currentcontrolled ring oscillator (see Figure ) and cutoff circuitry, stabilizing the supply voltage, temperature, and process variations at minimal cost and enabling stable write-time pulse generation. Our word line boosting technique for read memories can prevent unacceptable current degradation despite changes in supply voltage. Coupling this boosting technique with cutoff circuitry based on address transition detection (ATD) results in an acceptable

The use of APL as a language for system design and prototyping is discussed. Benefits of APL over traditional design techniques are shown to include higher productivity, improved code reliability, superior maintainability and performance, and executable documentation. Hierarchical and hybrid approaches to modelling systems of various degrees of complexity are presented, with examples chosen from the author's experience.

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components. Index Terms-Energy conservation, energy management, optimization methods. I. INTRODUCTION M OST ELECTRONIC circuits and system designs are confronted with the problem of delivering high performance with a limited consumption of electric power. High performance is required by the increasingly complex applications (e.g., multimedia) that are running even on portable devices. Low-power consumption is required to achieve acceptable autonomy in battery-powered systems, as well as to reduce the environmental impact (e.g., heat dissipation, cooling-induced noise) and operation cost of stationary systems. In other words, achieving highly energy-efficient computation is a major challenge in electronic design. Electronic systems can be viewed as collections of components, which may be heterogeneous in nature. Some components may have mechanical parts, e.g., hard-disk drives (HDD's), or optical parts, e.g., displays. For example, a cellular telephone has a digital very large scale integration (VLSI) component, an analog radio-frequency (RF) component, and a display. Such components may be active at different times, and correspondingly consume different fractions of the telephone power budget. Similarly, main components of portable Manuscript

This paper presents a systematic design procedure for Area I Area 2 a robust damping controller based on the Linear Matrix Inequality (LMI) approach employlng a Superconducting Magnetic Energy Storage (SMES) device. The design procedure takes advantage of the multi-objective features of LMI based design techniques. The procedure is applied to enhance the damping of inter-area oscillations in a two-area four-machine test system.

This implementation paper introduces principles for the information architecture of an educational digital library, principles that address the distinction between designing digital libraries for education and designing digital libraries for information retrieval in general. Design is a key element of any successful product. Good designers and their designs put technology into the hands of the user, making the product's focus comprehensible and tangible through design. As straightforward as this may appear, the design of learning technologies is often masked by the enabling technology. In fact, they often lack an explicitly stated instructional design methodology. While the technologies are important hurdles to overcome, the report advocates learning systems that empower education-driven experiences rather than technology-driven experiences. This work describes a concept for a digital library for science, mathematics, engineering and technology education (SMETE), a library with an information architecture designed to meet learners' and educators' needs. Utilizing a constructivist model of learning, the paper presents practical approaches to implementing the information architecture and its technology underpinnings. The study proposes the specifications for the information architecture and a visual design of a digital library for communicating learning to the audience. The design methodology indicates that a scenario-driven design technique sensitive to the contextual nature of learning offers a useful framework for tailoring technologies that help empower, not hinder, the educational sector. (Contains 14 references.) (Author/AEF) Reproductions supplied by EDRS are the best that can be made from the original document.

In this paper a systematic while practical methodology has been presented for design of vehicle's semiactive suspension systems. The semi-active control strategies developed to improve vehicle ride comfort and stability generally have a switching nature. This makes the design of the controlled suspension systems difficult and highly dependent on an extensive trial and error process. The proposed methodology maps the discontinuous control system model to a continuous linear region where all the time/frequency design techniques established in the conventional control system theory can be applied. If the semiactive control system is designed to satisfy some ride/stability requirements, an inverse mapping offers control law. The effectiveness of the proposed design methodology in dealing with real industrial problems is demonstrated with experimental results.

In this paper we offer a formal, rigorous proof of the correctness of Awerbuch's algorithm for network synchronization. We specify both the algorithm and the correctness condition using the I/O automaton model, which has previously been used to describe and verify algorithms for concurrency control and resource allocation. We show that the model is also a powerful tool for reasoning about distributed graph algorithms. Our proof of correctness follows closely the intuitive arguments made by the designer of the algorithm by exploiting the model's natural support for such important design techniques as stepwise refinement and modularity. In particular, since the algorithm uses simpler algorithms for synchronization within and between 'clusters' of nodes, our proof can import as lemmas the correctness of these simpler algorithms. 1 Overview 1.1 Verification methods and models As computer science has matured as a discipline, its activity has broadened from writing programs to include reasoning about those programs: proving their correctness and efficiency, and proving bounds on the performance of any program that accomplishes the same task. Recently distributed computing has begun to broaden in this way (albeit a decade or two later than the part of computer science concerned with sequential, uniproeessor algorithms). There are several reasons why particular care is necessary to prove the correctness of algorithms when the algorithms

The paper discusses the application of Network Simulator (NS-2) in simulation of Internet-based distributed embedded systems. It envisions the pros and cons of NS-2 as a simulation tool for distributed embedded systems and suggests some design techniques to implement simulation scenarios. At the end, an example of time-delay simulation of switched Ethernet as a communication media for distributed embedded systems is presented.

A simple discrete mathematical model of a space, time and matter manifold, called a STaM, is described which is intended as a framework within which to study agents and multi-agent systems. In this paper we concentrate on two-dimensional Boolean STaMs, and report implemented algorithms for detecting agents within them. A specific example STaM is given, some experimental results presented, and conclusions drawn.

One of the biggest goals in software engineering is to create secure software. This process must begin in the design phase of the software development life cycle. While the Unified Modeling Language (UML) exists to aid engineers in designing software systems, it lacks features to integrate security aspects into that design. This paper presents an extension of UML, UMLpac, which bridges the gap between software class design and the security techniques required for that design. Security packages accomplish this goal by keeping a level of abstraction between the system class diagram and its security features. This design technique preserves the original system diagram, while maintaining in depth security features for all aspects of the system.

We introduce a design technique, Clear Panels, to design interactive mobile device applications. Using mixedfidelity prototyping, a combination of low-and high-tech materials, participants refine multiple aspects of a mobile application's design. Clear Panels supports writing and sketching via a transparent overlay affixed atop a mobile device screen. It enables design partners to refine their gesture-based interactions on actual devices. The technique has been successfully implemented in the design of children's mobile applications. The technique leverages and extends longstanding interaction design methods to include mobile and hand-held technologies. Importantly, we show it is effective in raising participants' awareness of key mobile application design issues without constraining their creativity.

We consider stiffly accurate collocation methods based on Radau nodes for the integration of initial value problems for implicit delay differential equations of the form My (t) = f t, y(t), y α 1 t, y(t) ,. .. , y α p t, y(t) , where M is a constant matrix and α i (t, y(t)) (i = 1,. .. , p) denote the deviating arguments, which are assumed to satisfy the inequalities α i (t, y(t)) t for all i. In a recent paper [Computing 67 (2001) 1-12] we have described how collocation methods based on Radau nodes can be applied to solve problems of this type. The aim of this paper is that of explaining the difficulties arising when solving the Runge-Kutta equations using stepsizes larger than delays and to design techniques able to efficiently overcome them.

In this paper a new stable high order Digital Phase Lock Loop (DPLL) design technique is proposed. This technique uses linear theory to design the DPLL. The stability of the DPLL is guaranteed by placing a restriction on the system gain. This stability boundary is found by transforming the system transfer function to the Z-domain and plotting the root locus of the LPLL for values of gain where all the system poles lie inside the unit circle. The max value of gain where all the poles lie inside the unit circle is the stability boundary. It is shown that the stability boundary of the LPLL is comparable to the stability boundary of the DPLL. Finally where the above Bessel filter system produces slow lock, gear shifting of the DPLL components is considered. This allows the DPLL to start off with a wide loop bandwidth and switch to the narrow bandwidth once the system has locked.

Design techniques for self-calibration of the digitalto-analog converter DAC in a multibit sigma-delta modulator are described. When used in conjunction with dynamic element matching, self-calibration provides linearity performance suitable for digital audio applications. The dynamic element matching circuitry provides the mechanism of determining device mismatch for self-calibration. Practical circuit details and an effective calibration method are discussed. Test results from a 1-pm CMOS test chip are presented. In this test system, a second-order loop with a 3-b quantizer achieves an 89-dB dynamic range and-91-dB harmonic distortion after calibration. In addition, a new method of detecting the presence of tones is described, using the entropy of the spectrum of the decimation filter output.

Design techniques for non-linear dynamic systems are closely related to their stability properties. Stability results can be used to design a reliable controller. This paper discusses the stability analysis of the dynamic neural network control (DNNC) The results from DNNC stability analysis will be used to define the neural network stability index (NNSI). The NNSI is a practical index which in current form can only be used with DNNC structures. The NNSI can be used to determine the optimal DNNC network structure. In addition, we will provide guidelines for the design of an optimal DNNC network structure for the conventional neural network structure for model-based control strategies. In this study, DNNC will be designed for a non-isothermal CSTR as an example of a wide class of non-linear processes. 0 1997 Elsevier Science S.A.

In order to record holographic optical elements, recursive design techniques were developed for obtaining complex aspheric wave fronts from a relatively simple hologram. We present the mathematical formalism of this technique with a specific illustration of a holographic Fourier transform, designed with complex wave fronts that were derived recursively from two previous holograms. Both the calculated and the experimental results demonstrate a holographic lens that can handle input angles of up to ±12' with essentially diffraction-limited performance.

Dual-stage servo systems have been proposed as a method for attaining increased bit densities from computer hard disk drives. To aid in controller operation, the second-stage microactuator used in a dual-stage system should operate at low voltages, feature relative position sensing, and have dynamics that interact well with the dynamics of the original drive servo. This paper describes a high-aspect ratio electrostatic microactuator modified to improve dynamic interactions, relative position sensor performance, and device yield. A multi-rate, multivariable control design technique was used to evaluate the closedloop performance of a disk drive system with a microactuator and relative position sensing. Closed-loop simulations reveal that the proposed configuration can reduce off-track position error. Addressing both hardware design and control design, this paper demonstrates the success of an integrated mechatronic approach to hard disk drive servo control.

This paper proposes an object oriented framework to model and synthesize robust multi-rate controllers for many of the trackfollowing servo configurations encountered in the hard disk drive (HDD) industry, including traditional single-stage and new dual-stage servos. The proposed object oriented software will be used to synthesize and evaluate the tracking performance of different single-stage and dual-stage servo designs, given realistic Track-Mis-Registration (TMR) budgets.

The 5-V CMOS line controller described in this paper includes audio-band AID and D/A converters and a line dc feed control block. The AID converter is a second-order singleloop delta-sigma modulator achieving 100-dB signal-to-noise ratio (SNR) with a standard deviation of 0.9 dB. The D/A converter receives 2-b words from an external digital delta-sigma modulator; it incorporates switched-capacitor (SC) and timecontinuous low-pass filters and achieves an SNR of 96 dB with a standard deviation of 0.4 dB. The dc feed control block synthesizes selectable and adjustable line feed characteristics, detects on/off hook, and controls polarity reversal. Differential SC clock generators with minimized clock feedthrough, a tonefree delta-sigma modulator, a 2-b D/A conversion without matching requirements, a two-stage amplifier with limitation of noise bandwidth, a process-tolerant current mirror biasing, and SC-customized polarity reversal characteristics are described. The circuit was designed in 2-pm CMOS technology. The die size is 15 mm'. Statistical measurements from 489 units, from eight different process lots, show the efficiency and robustness of the proposed design techniques.

This paper presents a novel design methodology for ultralow-power design using subthreshold leakage as the operating current (suitable for medium frequency of operation: tens to hundreds of millihertz). Standard design techniques suitable for superthreshold design can be used in the subthreshold region. However, in this study, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of millihertz) in the subthreshold regime of operation. Simulation results of co-design on a five-tap finite-impulse-response filter shows 2.5 improvement in throughput at iso-power compared to a conventional design.

In this paper, the position/pressure control of a hydraulic cylinder using a hydraulic transformer is studied. A hydraulic transformer based on FFC pump/motor is used as a control component to drive the cylinder with a load horizontally. The two-degree-of-freedom (2DOF) design technique is applied to obtain the positioning controller with tracking performance and robustness for uncertainties while the structure of pressure controller is given by internal model principle to compensate stepwise disturbance. With these controllers the nonlinear friction torque, the leakage of the transformer and the load force acting on the cylinder can be compensated and the experimental results show that the sufficient accuracy of position and pressure are obtained.

Our work combines and extends techniques from high-performance scientific data management and visualization to enable scientific researchers to gain insight from extremely large, complex, timevarying laser wakefield particle accelerator simulation data. We extend histogram-based parallel coordinates for use in visual information display as well as an interface for guiding and performing data mining operations, which are based upon multi-dimensional and temporal thresholding and data subsetting operations. To achieve very high performance on parallel computing platforms, we leverage FastBit, a state-of-the-art index/query technology, to accelerate data mining and multi-dimensional histogram computation. We show how these techniques are used in practice by scientific researchers to identify, visualize and analyze a particle beam in a large, time-varying dataset.

In this paper, a strength Pareto evolutionary algorithm (SPEA) based approach is proposed for designing an integrated fuzzy guidance law which consists of three fuzzy controllers. Each of these controllers is activated in a region of the interception. The distribution of the membership functions and the rules are obtained by solving a nonlinear constrained multi-objective optimization problem where final time, energy consumption, and miss distance are treated as competing objectives. Tabu search is proposed to build a library of initial feasible solutions for the multi-objective optimization algorithm. In addition, a hierarchical clustering technique is implemented to provide the decision maker with a representative and manageable Pareto-optimal set without destroying the characteristics of the trade-off front. Moreover, a fuzzy-based mechanism is employed to extract the best compromise solution over the trade-off curve. The simulation results show that the proposed design technique was able to generate a missile guidance law with satisfactory performance with the existence of noisy measurements.

The Alice1LHCb front-end chip [1,2] has been designed for the ALICE pixel and the LHCb RICH detectors. It is fabricated in a commercial 0.25 μm CMOS technology, with special design techniques to obtain radiation tolerance. The chip has been irradiated with low energy protons and heavy ions, to determine the cross-section for Single Event Upsets (SEU), and with X-rays to evaluate the sensitivity to total ionising dose. We report the results of those measurements. We also report preliminary results of measurements done with 150 GeV pions at the CERN SPS.

Network routers rely on content addressable memories (CAMs) to accelerate the process of looking up the next hop of a packet. The input for this lookup is the destination address of the packet. This article describes our implementation and evaluation of a versatile prototype for a CAM. This prototype allows the empirical evaluation of the idea of caching lookup results in a multizone cache organized according to the length of the network prefix portion of the addresses. Implementing a cache in an FPGA efficiently required the design of a new cache replacement policy, the Bank Nth Chance policy. In this article we present results from a functional simulator that allows the comparison of this new policy with existing ones such as least recently used, first in, first out and Second Chance. With a complete and functional prototype in a Xilinx Virtex 2000E device, we also report frequency of operation and occupation of the device. We present programmable logic design techniques that enable the implementation of ternary logic CAM cells, the efficient implementation of the new policy reference fields, and the pipelining of lookups.

This paper proposes a novel linear precoder design technique for single carrier single-user multiple input multiple output (MIMO) systems with frequency-domain (FD) soft cancellation (SC) minimum mean squared error (MMSE) iterative equalization where the convergence properties of the equalizer are taken into account. The proposed precoder design technique, convergence constrained precoding (CCP), minimizes the transmission power while it achieves the target mutual information for each stream after the iterations at the receiver side. We show that the optimality criterion for the proposed design can be formulated as a convex optimization problem. The results demonstrate that our proposed technique outperforms the existing linear precoding techniques by ensuring the convergence with a reduced transmission power. Furthermore, we show that with CCP we can adjust transmission according to convergence properties of the iterative equalizer in a more flexible way than, e.g., minimum sum mean squared error (MinSumMSE) and maximum information rate (MaxRate) precoding.

We have applied mixture design and response surface techniques to prepare visible light-active TiO 2 photocatalysts codoped with sulfur, carbon, and tin oxide using titanium tetraisopropoxide (TTIP), tin(IV) chloride, and thiourea, respectively, as precursors. During calcination, the S atoms replaced the Ti or O atoms in the TiO 2 structure to maintain the anatase form, whereas doping with SnO 2 promoted the anatase-to-rutile transformation. O-TiC bonds and carbonaceous species were present in the prepared samples; together with the S atoms, they were responsible for the visible light activity, which was boosted by moderate doping SnO 2 due to a declined e −-h + recombination rate. A synergic effect induced by dopants SnO 2 and S, C on the visible light activity of TiO 2 was quantitatively established for the first time through mixture design techniques and response surface methodologies. The obtained empirically quartic models describe well the main and interactive influences of the precursors on the specific surface area and visible light activity of the S, C, SnO 2-codoped TiO 2 samples.

A design technique for low-voltage, micropower continuous-time ®lters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and veri®ed by HSPICE simulations. A 5thorder Chebyshev lowpass ladder ®lter was designed and simulated. The ®lter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz±100 kHz, and it has a power dissipation of 254 nW/ pole at the cutoff frequency of 100 kHz. The ®lter was laid out using the 0.35-mm mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm 2 without the i/o pads

During recent years a tremendous number of embedded systems has been introduced into every person's household. Such systems cannot only be found inside non-critical applications like entertainment devices but also in safety or security critical implementations like smart-cards. The increasing complexity leads to the introduction of several different codesign techniques to enable the parallel design of the system's hardware and software. Especially concerning security evaluation procedures this may raise a problem of trust between the manufacturer of the hardware and the software if both are different entities. To enable a bridge between these two worlds, simulation and emulation-based approaches have been shown in literature and industry to provide abstracted information about fault-attack effects to the software developer. However, no fast and cost-effective approach is available to provide a metric about how much of a given secret is leaking from the device to its environment. Therefore, this paper proposes such a metric and an emulation-based methodology to enable an early estimation of side-channel leakage to a possible adversary. The effectiveness of our approach is shown using a common available system-onchip implementation using an open-source standard-cell library for characterization and a FPGA-based emulation platform for demonstration.