Voltage Controlled Oscillator

A CMOS voltage controlled ring oscillator based on N-stage single-ended chain of different inverter types is described in this paper. The proposal is characterized by increased frequency stability (∆ f / f < 2%) in term of power supply voltage variations in respect to standard solutions (∆ f / f > 4%). The presented results are obtained using HSpice simulation and CMOS library model, level 49, for 1.2 µm technology.

In this thesis, a CMOS 2.4 GHz Low noise amplifier (LNA) and Voltagecontrolled oscillator (VCO) was designed and simulated. These circuits were designed to operate in the 2.4GHz Industrial Scientific Medicine (ISM) band and to achieve Bluetooth and Wifi standard specifications. High-Q RF MEMS air-suspended circular spiral inductors are used in both circuits. High-Q inductors give the circuit better performance parameters including higher gain, lower noise figure and narrower bandwidth. The integration of these RF MEMS inductors onto RF circuit chips was carried out using the UV-LIGA technique and an additive pattern transfer technique such as electroplating. The LNA maintains a gain of 10dB and noise figure of 0.8dB at 2.4 GHz. With an input reflection coefficient of -10.8dB and output reflection iv coefficient of -12.93dB, the LNA matches successfully with 50Ω load at 2.4 GHz. The

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-m, 200-GHz T 290-GHz MAX SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA.

This paper reviews recent research conducted at the University of Toronto on the development of CMOS transceivers aimed at operation in the 90-170-GHz range. Unique nanoscale CMOS issues related to millimeter-wave circuit design in the 65-nm node and beyond are addressed with an emphasis on transistor and top-level layout issues, low-voltage circuit topologies, and design flow. A Doppler transceiver and two receivers fabricated in a 65-nm GPLP CMOS technology are described, along with a single pole, double throw antenna switch with better than 5-dB insertion loss and 25-dB isolation in the entire 110-170-GHz band. The first receiver has an IQ architecture with a fundamental frequency voltage-controlled oscillator, and is intended for wideband passive imaging applications at 100 GHz. The measured noise figure and downconversion gain are 7-8 and 10.5 dB, respectively, while the 3-dB bandwidth extends from 85 to 100 GHz. The second receiver has double-sideband architecture, operates in the 135-145-GHz range (the highest for CMOS receivers), and features an 8-dB gain LNA, a double-balanced Gilbert cell mixer, and a dipole antenna. The 90-94-GHz Doppler transceiver, the highest frequency reported to date in CMOS, is intended for the remote monitoring of respiratory functions. A Doppler shift of 30 Hz, produced by a slow-moving (4.8 cm/s) target located at a distance of 1 m, was measured with a transmitter output power of approximately +2 dBm and a phase noise of 90 dBc/Hz at 1 MHz offset. The range correlation effect is demonstrated for the first time in CMOS by measuring the phase noise of the received baseband signal at 10-Hz offset, clearly indicating that 1 noise has been canceled and it does not pose a problem in short-range applications, where neither a phase-locked loop nor a frequency divider are needed.

Recent results from a Swedish program for development of 60-GHz monolithic microwave integrated circuits (MMICs) for high-data-rate communication links are presented. Front-end circuits such as mixers, amplifiers, frequency multipliers, IF amplifiers with gain control, and voltage-controlled oscillators (VCOs) have been realized utilizing GaAs PHEMT and MHEMT technologies. A newly developed 7.5-GHz coupled Colpitt VCO shows a minimum phase noise of 95 dBc at 100 kHz offset. A second-harmonic 14-GHz VCO shows a minimum phase noise of less than 90 dBc at 100 kHz. A novel balanced 7-28-GHz MMIC frequency quadrupler is described and compared with a single-ended quadrupler at the same input frequencies. To demonstrate its feasibility and potential application, the quadrupler is combined with the Colpitt VCO and the output characteristics of the resulting 30-GHz MMIC source are measured. A three-stage MHEMT wide-band amplifier covering 43-64 GHz with a gain of 24 dB, a minimum noise figure of 2.5 dB, and a passband ripple of 2 dB is also described. In future 60-GHz systems for mass markets where cost is of utmost importance, Si-based technologies, especially CMOS, are highly interesting. Some recent circuit results based on a 90-nm CMOS technology are also reported.

Wireless body-area networks (WBAN) are used for communication among sensor nodes operating on, in or around the human body, e.g. for healthcare purposes. In view of energy autonomy, the total energy consumption of the sensor nodes should be minimized. Because of their low complexity, a combination of the super-regenerative (SR) principle [1-3] and OOK modulation enables ultra low power (ULP) consumption. This work presents a 2.4GHz ULP OOK single chip transceiver for WBAN applications. A block diagram of the implemented transceiver is shown in Fig. 26.3.1. Next to the direct modulation TX [4] and SR RF [5] front-ends, this work integrates analog and digital baseband, PLL functionality and additional programmability for flexible data rates, and achieves ultra-low power consumption for the overall system.

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10 11 BER.

This paper presents the design of low power Voltage Controlled Oscillator with differential stages. Circuit uses multiple pass loop architecture having primary and secondary (auxiliary feed forward) loops. In delay cell positive feedback is used with cross coupled regenerative PMOS load, due to that power consumption reduces. For best tuning range multiple delay path is used. Measurement shows that Oscillator has linear frequency voltage characteristics. This oscillator operates at 1.8V supply. After circuit designing, 2.17GHz-4.16GHz tuning rang, 2.57 GHz centre frequency with 3mw power consumption is obtained. Further to reduce power consumption of Voltage Controlled Oscillator, drain bulk connected PMOS load is used that works in sub-threshold region. If Bulk drain is connected it shows more linearity. By using Bulk drain connected transistor; Power Consumption reduces up to 165 w  and frequency is 1.6GHz with tuning range 1.13GHz-2.6GHz.

Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community. Index Terms-CMOS, detector, frequency doubler, on-chip patch antenna, Schottky barrier diode, VCO.

An integrated CMOS ultrawideband wireless telemetry transceiver for wearable and implantable medical sensor applications is reported in this letter. This high duty cycled, noncoherent transceiver supports scalable data rate up to 10 Mb/s with energy efficiency of 0.35 nJ/bit and 6.2 nJ/bit for transmitter and receiver, respectively. A prototype wireless capsule endoscopy using the proposed transceiver demonstrated in vivo image transmission of 640 × 480 resolution at a frame rate of 2.5 frames/s with 10 Mb/s data rate.

The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record of 375 GHz and associated max of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future. Index Terms-BiCMOS integrated circuits, communication systems, heterojunction bipolar transistors (HBTs), high-speed integrated circuits. N66001-02-C-8014. J.-S. Rieh was with the IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533 USA. He is now with the

The basic aim of this paper is to present several of a newly introduced current differencing buffered amplifier (CDBA)-based oscillator topologies achieving orthogonal control of oscillation condition b and oscillation frequency v 0 with a reduced number of components. A single resistor is used for adjusting their frequency, and further, this resistance is grounded, which is important from the integration point of view. Taking these considerations into account they are very suitable for voltage-controlled oscillator (VCO) implementation. ᭧

This paper presents a Low power charge pump, second order low pass filter and voltage controlled oscillator for low power phase lock loop. The paper contains the detailed circuit diagram of charge pump, loop filter and voltage control oscillator with 1.8v power supply. The design has been realized using 0.18um CMOS technology. Here current starved voltage control oscillator is use for phase lock loop.

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

This paper considers controlling motor terminal voltages using chopper method. The input DC voltage is chopped by IGBT (Insulated Gate Bipolar Transistor). PLL (Phase Locked Loop) offer a stable frequency controller system. It has been widely used in communications, instrumentation and motor controlled. We synthesis a PLL system using FPGA chip (Field Programmable Gate Array) and an analog VCO (Voltage Controlled Oscillator). Phase comparator (phase detector) and programmable counter (frequency divider) are implemented in FPGA.

On-chip frequency generators for high frequency applications suffer from degradation of key passive components, variable capacitors in particular. In this framework, frequency multipliers can play a key role, allowing the design of voltage-controlled oscillators running at a frequency lower than required with advantage in terms of signal spectral purity and frequency tuning range. In this paper we present two injection locked frequency doublers for Ku-band and F-band applications respectively. Despite differences in implementation details, the same topology where a pushpush pair injects a double frequency tone locking an autonomous differential oscillator is adopted. The circuits require limited input signal swing and provide a differential output over a broad frequency range. Dissipating 5.2 mW, the Ku-band multiplier, realized in a 0.13 m CMOS node, displays an operation bandwidth from 11 GHz to 15 GHz with a peak voltage swing on each output of 470 mV. The F-band multiplier, realized in 65 nm CMOS technology, displays an operation bandwidth from 106 GHz to 128 GHz with a peak voltage swing on each output of 330 mV and a power dissipation of 6 mW. A prototype including the multiplier, driven by a half-frequency standard LC-tank VCO, demonstrates an outstanding 13.1% tuning range around 115 GHz.

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a

A local-oscillator phase-shifting approach is introduced to implement a fully integrated 24-GHz phased-array receiver using an SiGe technology. Sixteen phases of the local oscillator are generated in one oscillator core, resulting in a raw beam-forming accuracy of 4 bits. These phases are distributed to all eight receiving paths of the array by a symmetric network. The appropriate phase for each path is selected using high-frequency analog multiplexers. The raw beam-steering resolution of the array is better than 10 for a forward-looking angle, while the array spatial selectivity, without any amplitude correction, is better than 20 dB. The overall gain of the array is 61 dB, while the array improves the input signal-to-noise ratio by 9 dB.

A simple new architecture of phase frequency detector with low power and low phase noise is presented in this paper. The proposed phase frequency detector is based on floating gate, consist of 4 transistors including one floating gate pMOS and one floating gate nMOS constructed with two GDI (gate diffusion input) cells and maintain main characteristics of conventional phase frequency detector in 180 nm technology. Floating gate based methodology reduced the power of phase frequency detector about 51%. Introduction of floating gate based phased frequency detector also reduces the number of transistor as compared with conventional phase frequency detector.

A 1.2 V 60 GHz 120 mW phase-locked loop employing a quadrature differential voltage-controlled oscillator, a programmable charge pump, and a frequency quadrupler is presented. Implemented in a 90 m CMOS process and operating at 60 GHz with a 1.2 V supply, the PLL achieves a phase noise of -91 dBc/Hz at a frequency offset of 1 MHz.

This paper deals with the design of elementary building blocks of frequency synthesizer (Phase-Locked Loop) - phase detector and voltage-controlled oscillator (VCO) in the radio frequency region (RF). They have been designed in the standard AMS 0.35µm CMOS technology, with analysis and optimisation performed using CADENCE tools (SpectreRF) and ASITIC software. The VCO was experimentally realised as test chip with A-MOS capacitance tuning circuit elements. The proposed LC oscillator is implemented in double- cross topology with the supply voltage of 2.7 V. Additionally, also a phase comparator design is discussed, implemented and investigated, as a very important part of the PLL structure for RF applications. The low phase noise PLL implementation is also presented.

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.

A novel inductor switching technique is used to design and implement a wideband LC voltage controlled oscillator (VCO) in 0.13µm CMOS. The VCO has a tuning range of 87.2% between 3.3 and 8.4 GHz with phase noise ranging from −122 to −117.2 dBc/Hz at 1MHz offset. The power varies between 6.5 and 15.4 mW over the tuning range. This results in a Power-Frequency-Tuning Normalized figure of merit (PFTN) between 6.6 and 10.2 dB which is one of the best reported to date.

This letter presents a novel Hartley low phase noise differential CMOS voltage-controlled oscillator (VCO). The low noise CMOS VCO has been implemented with the TSMC 0.18m 1P6M CMOS technology and adopts full PMOS to achieve a better phase noise performance. The VCO operates from 4.02 to 4.5 GHz with 11.3% tuning range. The measured phase noise at 1-MHz offset is about 119 dBc/Hz at 4.02 GHz and 122 dBc/Hz at 4.5 GHz. The power consumption of the VCO core is 6.75 mW.

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a common carrier onto which different ICs are mounted. Passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The "system-on-a-package" approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications.

A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( 30%) is presented. The phase noise at 1 MHz offset is 97 dBc/Hz at the center frequency (and less than 94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.

Abstract—In this paper, we describe the architecture of a new CMOS fully integrated frequency-locked loop (FLL). The proposed FLL contains a frequency-to-voltage converter (FVC), an operational amplifier (opamp) and a differential voltage-con-trolled oscillator ( ...

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 m CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78-5.19 GHz and 12.19-12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are 117 16 dBc/Hz and 112 15 dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply. Index Terms-CMOS, phase noise, series-tuned and paralleltuned LC resonator, voltage controlled oscillator (VCO).

The implementation of a fully integrated multi standard low-jitter clock generator is presented. A L� fractional-N phase-locked loop (PLL) is chosen for 0.8 to 6.3 GHz wireline Serializer-Deserializer (SerDes) transmitting clock and spread spectrum clock generator (SSCG) for Serial AT Attachment (SATA I, 11, 1lI) characterized by a spread modulation of 5000 ppm. A mUlti-range voltage-controlled oscillator (YCO) is presented to handle the wide range of operation. The PLL ex hibits less than 3.5ps rms jitter at 6.3 GHz with power consumption of7 mW from 1.2 V and 2.5 V supply. EMI reduction is 20 dB. The design has been implemented in 90 nm CMOS process and occupies an area ofO.14xO.16 mm 2 • Index Terms-Phase-locked loop (PLL), Serializer Deserializer (SerDes), Spread spectrum clock generator (SSCG).

Differential tuning in oscillators allows cancellation of common-mode bias noise and lower tuning sensitivity with respect to the most conventional single-ended tuning. However, the direct application of differential tuning increases the capacitor non-linearity and the flicker-induced phase noise. This paper analyzes quantitatively this phenomenon and proposes a novel configuration, which includes all the benefits of differential tuning with no penalty on phase noise. This circuit is fabricated in a 0.35-μm CMOS technology together with a single-end-tuned oscillator and both cover the 2.0–2.4 GHz frequency range. The measured 1/f 3 phase noise at 10 kHz offset is −71 dBc/Hz, which outperforms the companion single-end tuning oscillator by 10 dB.

In this paper, a 4.2–5.4 GHz, −Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 μm SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is −110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and −113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm2 on Si substrate, including DC and RF pads. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

An inexpensive frequency-modulated continuous-wave (FMCW) radar system is presented in this paper, which, nevertheless, meets all industrial requirements. The FMCW radar uses a low-cost nonlinear voltage-controlled oscillator (VCO), operating at an IF of 2.45 GHz to generate the frequency modulation of the radar system. This VCO signal is applied twice, first to generate the radar transmitter signal at 24 GHz, and then it is fed to a surface acoustic wave (SAW) delay line. The SAW delay line generates a fixed delay time, which corresponds with a fixed radar distance. Thus, all systematic nonlinearities and stochastic phase errors of the FMCW system can be monitored and, afterwards, can be compensated for in real time. This linearization technique leads to a significant enhancement in dynamic range for a FMCW radar system. For this FMCW system, SAW delay lines with a linear phase characteristic have been designed using a linear optimization program. The delay line consists of two chirped and weighted interdigital transducers. For high volume, low-cost, and high-yield production of the required SAW structures, with linewidths down to 0.3 m, technological improvements had to be achieved, especially in photolithography. Based on these design and fabrication techniques, delay lines at 2.45 GHz operating at the fundamental and third harmonic with bandwidths up to 800 MHz have been realized.

We have developed a 27-and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator using 0.18-m CMOS. The line-reflect-line calibrations with a microstrip-line structure, consisting of metal1 and metal6, was quite effective to extract the accurate -parameters for the intrinsic transistor on an Si substrate and realized the precise design. Using this technique, we obtained a 17-dB gain and 14-dBm output power at 27 GHz for the tuned amplifier. We also obtained a 7-dB gain and a 10.4-dBm output power with a good input and output return loss at 40 GHz. Additionally, we obtained an oscillation frequency of 52.5 GHz with phase noise of 86 dBc/Hz at a 1-MHz offset. These results indicate that our proposed technique is suitable for CMOS millimeter-wave design.

An integrated SiGe superheterodyne RX/TX pair capable of Gb/s data rates in the 60GHz band is described. The 6dB NF RX includes an image-reject LNA, a multistage down-converter with on-chip IF filters, a frequency tripler, a PLL, and baseband outputs. The 10 to 12dBm P1dBTX achieves 10% PAE in the final stage. It includes a PA, image-reject driver, multistage up-converter with on-chip filters, tripler, and PLL

We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with PDC ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz.

This paper presents an improved design of voltage
controlled oscillator (VCO)  utilizing the three differential cell
CMOS inverters for forming the ring oscillator. The differential
cell reduces the power supply fluctuations impact on the
oscillator jitter while the negative feedback from frequency to
voltage converter reduces the jitter at high frequencies. Finally
the proposed model is designed using CMOS 0.18um foundry
technology and simulated using P-Spice software. The result
shows that the proposed design improves the jitter attenuation at
different offset frequencies up to 40dB.

This paper presents voltage controlled oscillator (VCO) circuit employing MOS transistors intended for integrated transceiver, in which full compensation of process parameters variations can be obtained. This is realized by fitting on chip capacitance of LC resonator. This capacitance is used for tuning of resonant frequency. VCO output frequency is tuned by on-chip p /n-well junction varactors. The circuit topology minimizes the amount of fixed parasitic capacitance in the tank circuit. The simulation results show that the proposed VCO can reach the frequency wished to the telecommunication application. Parameters from an industrial 0.35 µm CMOS process are used for simulations. The nominal operating frequency of these oscillators is 2.4 GHz. They are designed to be resistant to supply and temperature effects. This oscillator achieves the necessary temperature and supply independence while being tunable about 2.4 GHz. Using only 2.5V of power supply and 1V of tuned voltage, the circuit shows a simulated single-output sensitivity of 565 ppm/°C at 27C temperature and -0.47%/Volt at 2V.

Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The core of a microprocessor, which includes the largest power density on the microprocessor. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. One way to overcome this limitation, available in some application domains, is to replicate the circuit block whose supply voltage is being reduced in order to maintain the same throughput .This paper introduces a design aspects for low power phase locked loop using VLSI technology. This phase locked loop is designed using latest 45nm process technology parameters, which in turn offers high speed performance at low power. The main novelty related to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnect dielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design

— An extremely low power low phase noise CMOS LC voltage controlled oscillator (VCO) has been fully integrated in a commercial 0.18 µm CMOS process. To achieve low power and low phase noise, a complementary NMOS and PMOS cross-coupled differential LC ...

One way of performing indoor localization of objects is by means of Angle of Arrival (AoA). This technology is based on a phased antenna array which estimates the angle of arrival of an incident wave transmitted by a mobile node. This is achieved by measuring the relative phase shifts between the received signals. This paper presents the construction of a Phase Locked Loop (PLL) which synchronizes on the carrier transmitted by the mobile node in order to provide a carrier at exactly the same frequency and a reference phase to the receiving antenna elements. The PLL is designed to operate at 2.4 GHz which holds additional challenges. Since, at this frequency, the most commonly available phase detectors are of the frequency insensitive EXOR type, the PLL will, besides the standard PLL building blocks, such as phase detector , a loop filter and a voltage controlled oscillator, need a sweep circuit. On top of that, sufficient amplification and filtering of the received signal will be mandatory.

This paper presents a low-jitter charge-pump phase-locked loop (PLL) built in standard 90-nm CMOS for 1 to 10 Gb/s wireline SerDes transmitter clocking. The PLL employs a programmable dual-path loop filter with integral path and resistorless sample-reset proportional path that are independently controlled for flexible setting of closed-loop bandwidth and peaking. Frequency is synthesized by a digitally calibrated LC-VCO achieving 45% calibration tuning range with inversion-mode nMOS varactors and area-efficient helical inductors. Following calibration, 4.8% hold range compensates for VCO sensitivity to supply voltage and temperature drift. The PLL exhibits 0.81 ps rms jitter at 10 Gb/s. Critical for ASICs integrating noisy digital cores and multiple SerDes channels, design considerations to minimize jitter induced by supply noise are described. Deep-submicron CMOS effects on design are also examined to improve manufacturability and performance.

This paper deals with the system and circuit-level aspects of an ultra-low-power robust wireless node for an asymmetric wireless link. A single building block TX front-end for a frequency hopping spread spectrum (FHSS) transmitter implemented in silicon-on-anything (SOA) bipolar technology is presented. It is realized with a directly modulated RF cascoded Colpitts power voltage-controlled oscillator (VCO), a frequency locked loop for center frequency calibration, and a digital pre-distortion algorithm for accurate frequency bins synthesis. The TX front-end draws only 1 mA at 18 dBm output power. By combining digital system techniques for frequency hopping and merging the VCO and the power amplifier (PA), a robust solution is obtained for indoor ultra-low-power wireless links. The proposed pre-distortion concept allows reduction of the hardware complexity, while the combination of a cascode output buffer and a common-collector Colpitts VCO allows us to reduce the complete FHSS front-end to a single building block that directly drives the antenna through a balun. A dedicated digital algorithm on the receiver side reduces the center frequency offset from a maximum value of 8.2 MHz to less than 8 ppm avoiding the use of any crystal on the transmitter side. Precision in the hopping synthesis is obtained by employing a ST-DFT based demodulator with differential encoding and an offset sending technique. The novel FHSS-predistortion concept has been verified by realizing a full wireless link that achieves a bit error rate better than 1.1% at 25 dBm output power while transmitting across an 8 meters indoor non-line-of-sight (NLOS) path.

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

This paper reports a K-band voltage-controlled oscillator based on room-temperature ferroelectric varactors. The circuit is realised as a hybrid module where flip-chip transistors are mounted on a silicon substrate with integrated ferroelectric varactors and passive circuitry. The size of the module is 4.7×2.2 mm 2 . The measured centre frequency is 16.5 GHz with a linear tunability of 6.7% and an output power of 3 dBm±1 dB over then tuning range. The measured phase noise at centre frequency is -95 dBc/Hz at 100 kHz offset. Another version of the oscillator is measured operating at 19.6 GHz with a tunability of 3.3% and a phase noise of -102 dBc/Hz at 100 kHz offset.