Vlsi physical design

In this new technology era, circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new interconnection oriented clustering algorithm for combinational VLSI circuit partitioning. The proposed clustering method focuses on capturing clusters in a circuit, i.e., the groups of cells that are highly interconnected in a VLSI circuit. Therefore, the proposed clustering method can reduce the size of large-scale partitioning problems without losing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmarks—ISCAS85 benchmark suite. The experimental results show that the proposed algorithm yields results comparable to that of the rajaraman-wong optimum delay clustering approach with a faster execution time.

In this new technology era, circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new interconnection oriented clustering algorithm for combinational VLSI circuit partitioning. The proposed clustering method focuses on capturing clusters in a circuit, i.e., the groups of cells that are highly interconnected in a VLSI circuit. Therefore, the proposed clustering method can reduce the size of large-scale partitioning problems without losing partitioning solution qualities. The performance of the proposed clustering algorithm is evaluated on a standard set of partitioning benchmarks—ISCAS85 benchmark suite. The experimental results show that the proposed algorithm yields results comparable to that of the rajaraman-wong optimum delay clustering approach with a faster execution time. General Terms Clustering, Benchmark, Algorithms.

Abstmct-Given a set of input points, the rectilinear Steiner tree problem is to find a minimal length tree consisting of vertical and horizontal line segments that connects the input points, where it is possible to add new points to minimize the length of the tree. The restricted Steiner tree problem in which all the input points lie on the boundary of a rectangle frequently Occurs in VLSI physical design. Since the fastest published algorithm is cubic in the size of the point set, VLSI designers have been forced to use heuristic approximations to the length of the Steiner tree for this problem. We present a simple, practical, linear-time exact algorithm to find the Steiner tree for points lying on the boundary of a rectangle, obviating the need for some heuristic algorithms in VLSI design. The analysis of the algorithm is based on the use of a novel tie-breaking rule that should prove useful for other Steiner tree problems. ' * James P. Cohoon (M'82) received the B.S. degree in mathematics from Ramapo College of New Jersey, Mahwah, NJ in 1975, the M.S. degree in computer science from Pennsylvania State University, State College, PA in 1978, and the Ph.D. degree in computer science from the University of Minnesota, Minneapolis, M N in 1982. In 1983, he became an Assistant Professor in the Department of Computer Science at the University of Virginia, Charlottesville, VA. He is currently an Associate Professor there. His pri-COHOON el U /. : OPTIMAL STEINER TREE ALGORITHM _", mary research interests are in various aspects of computer-aided design, with particular emphasis on circuit layout. Other research interests include computational geometry, parallel algorithms, and heuristic search. Dr. Cohoon is a member of the ACM, SIGACT, SIGDA, and Upsilon Pi Epsilon. He is a member of the SIGDA Board of Directors and has served on the programming committee for IEEE International Conference on Computer-Aided Design. * rithms, with an emphasis on combinatorial applications and parallel implementations. Particular problems include graph algorithms, information dissemination in networks, parallel sorting, biological sequence analysis, Steiner trees, and new paradigms for combinatorial optimization.

A set X of vertices of an acyclic digraph D is convex if X 6= ; and there is no directed path between vertices of X which contains a vertex not in X. A set X is connected if X 6= ; and the underlying undirected graph of the subgraph of D induced by X is connected. Connected con- vex

The enormous size and complexity of current and future integrated circuits (IC's) presents a host of challenging global, combinatorial optimization problems. As IC's enter the nanometer scale, there is increased demand for scalable and adaptable algorithms for VLSI physical design: the transformation of a logicaltemporal circuit specification into a spatially explicit one. There are several key problems in physical design. We review recent advances in multiscale algorithms for three of them: partitioning, placement, and routing.

Softcover reprint of the hardcover 1 st edition 1991 The use of registered names, trademarks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use.

By applying displacement maps to slightly perturb two free-form surfaces, one can ensure exact agreement between the images in 3 of parameterdomain approximations to their curve of intersection. Thus, at the expense of slightly altering the surfaces in the vicinity of their intersection, a perfect matching of the surface trimming curves is guaranteed. This exact agreement of contiguous trimmed surfaces is essential to achieving topologically consistent solid model constructions through Boolean operations, and has a profound impact on the efficiency and reliability of applications such as meshing, rendering, and computing volumetric properties. Moreover, the control point perturbations require only the solution of a linear system for their determination. The basic principles of this approach to topologically consistent surface trimming curves are described, and example results from the implementation of a simple instance of the method are presented.

Under the in terconnect-centric design paradigm, partitioning is seen as the crucial step that de nes the interconnect 1. T o meet the performance requirement of today's complex design, performance driv enpartitioners must consider the amount of interconnect induced b y partitioning as w ellas its impact on performance. In this paper, w epro videnew performance driv enformulation for cell move based top-down multiway partitioning algorithms with consideration of the local and global in terconnect delay. In our constrained acyclic partitioning" formulation, cell moves are restricted to maintain acyclicity in partitioning solution to preven t cyclicdependency among cells in di erent partitions. In our relaxed acyclic partitioning" formulation, acyclic constraints are relaxed to give partitioners capability of minimizing cutsize and delay. Our new acyclic constraint based performance driv enmultiway partitioning algorithm FLARE obtains i 4 to 13 better delay compared to the state-of-the-art cutsize minimization based hMetis 10 at almost no increase in cutsize, and ii 84 better cutsize compared to the state-of-theart delay minimization based PRIME 2 at an expense of 16 increase in delay.

Abstmct-Given a set of input points, the rectilinear Steiner tree problem is to find a minimal length tree consisting of vertical and horizontal line segments that connects the input points, where it is possible to add new points to minimize the length of the tree. The restricted Steiner tree problem in which all the input points lie on the boundary of a rectangle frequently Occurs in VLSI physical design. Since the fastest published algorithm is cubic in the size of the point set, VLSI designers have been forced to use heuristic approximations to the length of the Steiner tree for this problem. We present a simple, practical, linear-time exact algorithm to find the Steiner tree for points lying on the boundary of a rectangle, obviating the need for some heuristic algorithms in VLSI design. The analysis of the algorithm is based on the use of a novel tie-breaking rule that should prove useful for other Steiner tree problems. ' * James P. Cohoon (M'82) received the B.S. degree in mathematics from Ramapo College of New Jersey, Mahwah, NJ in 1975, the M.S. degree in computer science from Pennsylvania State University, State College, PA in 1978, and the Ph.D. degree in computer science from the University of Minnesota, Minneapolis, M N in 1982. In 1983, he became an Assistant Professor in the Department of Computer Science at the University of Virginia, Charlottesville, VA. He is currently an Associate Professor there. His pri-COHOON el U /. : OPTIMAL STEINER TREE ALGORITHM _", mary research interests are in various aspects of computer-aided design, with particular emphasis on circuit layout. Other research interests include computational geometry, parallel algorithms, and heuristic search. Dr. Cohoon is a member of the ACM, SIGACT, SIGDA, and Upsilon Pi Epsilon. He is a member of the SIGDA Board of Directors and has served on the programming committee for IEEE International Conference on Computer-Aided Design. * rithms, with an emphasis on combinatorial applications and parallel implementations. Particular problems include graph algorithms, information dissemination in networks, parallel sorting, biological sequence analysis, Steiner trees, and new paradigms for combinatorial optimization.

This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's VLSI physical design. The new method is based on a sensitivitybased conjugate gradient (CG) approach. But we adopt several new techniques, which significantly improve the efficiency of the optimization process. First, we propose an efficient search step scheme to replace the time-consuming line search phase in conventional conjugate gradient method for decap budget optimization. Second, instead of optimizing an entire large circuit, we partition the circuit into a number of smaller subcircuits and optimize them separately by exploiting the locality of adding decaps. Third, we apply time-domain merged adjoint method to compute the sensitivity information and show that the partitioning-based merged adjoint method leads to better results than the flat merged adjoint method with the improved search scheme. Experimental results show that the proposed algorithm achieves at least 10X speed-up over the similar decap allocation methods reported so far with similar budget quality, and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations.

The growing complexity in the electronic hardware now necessitates in improving the performance of searching algorithms. Genetic algorithms do not guarantee global optimum solution to NP-Hard problems but are generally good at finding acceptable solution to problems. In complex combinatorial spaces, hybridization with other optimization techniques can greatly improve the efficiency of search. Memetic algorithm (MA) is an improvisation over genetic algorithms (GA) that combines global and local search by using evolutionary algorithms to perform exploration while the local search methods are used for exploitation. Here, exploitation is the process of visiting entirely new regions of a search space where the gain can also be high. This paper discusses the (MAs) as a solution to Standard Cell Placement (SCP) problem and procedures are laid down to strike a balance between genetic search and local search in MAs. A comparison of MA with the already established results for SCP using conventional and Hybrid techniques by the author depicts improvement in the performance of SCP algorithm in terms of solution quality and computing speed. About 15% improvement in overall wire-length was observed along side it being 25% faster over the Tabu Search (TS) algorithm discussed in previous works of the author.

A new field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with a wide dynamic range greater than 20 ms has been developed to monitor the timing of various pulsed devices in the trigger timing distribution system of the KEKB injector linac. The pulsed devices are driven by feeding regular as well as any irregular (or event-based) timing pulses. For monitoring the timing as precisely as possible, a 16-ch FPGA-based TDC has been developed on a Xilinx Spartan-6 FPGA equipped on VME board with a time resolution of 1 ns. The resolution was achieved by applying a multisampling technique, and the accuracies were 2.6 ns (rms) and less than 1 ns (rms) within the dynamic ranges of 20 ms and 7.5 ms, respectively. The various nonlinear effects were improved by implementing a high-precision external clock with a built-in temperaturecompensated crystal oscillator.

With rapid advances in integrated circuit technology, wirelength has become one of the most critical and important metrics in all phases of VLSI physical design automation, especially circuit placement. As the precise wirelength for a given placement can only be known after routing, accurate and fast-to-compute wirelength estimates are required by FPGA placement algorithms. In this paper, a new model, called star+, is presented for estimating wirelength during FPGA placement. The proposed model is continuously differentiable and can be used with both analytic and iterative-improvement placement methods. Moreover, the time required to calculate incremental changes in cost incurred by moving/swapping blocks can always be computed in O(1) time. Results show that when incorporated into the well-known VPR framework and tested using the 20 MCNC benchmarks, the star+ model achieves a 6-9% reduction in critical-path delay compared with the half-perimeter wirelength (HPWL) model, while requiring roughly the same amount of computational effort. Avec les progrès rapides de la technologie des circuits intégrés, la longueur de fil est devenue l'une des mesures les plus critiques et importantes dans toutes les phases d'automatisation de conception physique VLSI, particulièrement dans le placement des circuits. Comme la longueur de fil précise pour un placement donné ne peutêtre connue qu'après routage, les estimations des longueurs de fil précises et rapidesà calculer sont exigées par des algorithmes de placement sur FPGA. Dans cet article, un nouveau modèle pourévaluer la longueur de fil pendant le placement sur FPGA, appelé star+, est présenté. Le modèle proposé est continuellement différentiable et peutêtre utilisé avec des méthodes d'amélioration des placementsà la fois analytiques et itératives. De plus, le temps nécessaire pour calculer des changements progressifs du coût engagé par se déplacement/échange des blocs peut toujoursêtre calculé dans le temps de O(1). Les résultats montrent que quand incorporé dans la structure bien connue VPR et testé en utilisant les 20 repères MCNC, le modèle star+ réalise une réduction de 6à 9 % du retard du chemin critique comparé avec le modèle demi-périmètre de la longueur de fil (HPWL), en exigeant approximativement la même quantité de calcul.

Automated floorplanning or space layout planning has been a long-standing NP-hard problem in the field of computer-aided design, with applications in integrated circuits, architecture, urbanism, and operational research. In this paper, we introduce GenFloor, an interactive design system that takes geometrical, topological, and performance goals and constraints as input and provides optimized spatial design solutions as output. As part of our work, we propose three novel permutation methods for existing space layout graph representations, namely O-Tree and B*-Tree representations. We implement our proposed floorplanning methods as a package for Dynamo, a visual programming tool, with a custom GUI and additional evaluation functionalities to facilitate designers in their generative design workflow. Furthermore, we illustrate the performance of GenFloor in two sets of case-study experiments for residential floorplanning tasks by (a) measuring the ability of the proposed system to find a known optimal solution, and (b) observing how the system can generate diverse floorplans while addressing given a constant residential design problem. Our results indicate convergence to the global optimum is achieved while offering a diverse set of solutions of a residential floorplan corresponding to local optimums of the solution landscape.

We present well known properties related to the topology of Steiner minimal trees and to the geometric position of Steiner points, and investigate their application in the main exact algorithms that have been proposed for the Euclidean Steiner problem. We discuss the difficulty in the application of properties that were very successfully applied to solve the problem in the plane, when the dimension of the space increases, and point out that the application of some geometric conditions for Steiner points is hindered when the well known implicit enumeration scheme proposed by Smith in 1992 is considered. Finally, we mention mathematicaloptimization methods as a direction to explore in the search for good formulations of inequalities that would allow the application of these restrictive geometric conditions.

Physical layout automation is very important in VLSI's field. With the advancement of semiconductor technology, VLSI is coming to VDSM (Very Deep Sub Micrometer), and the scale of the random logic IC circuits goes towards million gates. Physical design is the process of determining the physical location of active devices and interconnecting them inside the boundary of the VLSI chip.The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area [1], [5]. The VLSI placement problem is to place the object in the fixed area of die without overlap and with some cost constrain such as the wire length and area of the die. The wire length and the area optimization is the major task in the physical design. We first introduce about the major technique involved in the algorithm.

In this paper, we propose an algorithm for the channel routing problem based on genetic approach that uses a new type of mutation, called inter-cluster mutation . The performance of genetic algorithm-based channel router is improved by incorporating problem-specific ...

This paper presents a novel layout model and floorplanning tool particularly suitable for taking into account user defined layout constraints on specific sets of modules and specific locations. The user defined layout constraints can be the setting of any common topological property associated with a group of specific modules such as the neighboring property for example. Or the use of any topological regularities in a design such as regular bus structure or the use of the structural property such as the bit-sliceable or non bitsliceable feature of a module set, or their similar shape. The exploitation of these structural information helps in producing more compact layout especially for datapath oriented architectures. Moreover, in addition to the area and total wiring length, the critical path delay is systematically minimized through a global cost function. The potential candidates for the critical path computation can be specifically defined by the user. The core of the optimization process is based on Shuhted Annealing (S.A.).

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: 1) nearly invisible to human and machine inspection; 2) difficult to remove; and 3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that in the placement and routing applications considered in our methods achieve strong proofs of authorship are resistant to tampering and do not adversely influence timing.

Interconnects are vital in deep sub-micron VLSI design, as they impose constraints, such as delay, congestion, crosstalk, power dissipation and others, and consume resources. These parameters affect the efforts for obtaining a feasible solution for the global routing of multiple nets. In addition, efforts are on for exploration and use of non-Manhattan routing architectures. In this work, we focus on the specific problem of multi-net multi-pin global Y -routing for custombuilt design styles with several available routing layers. The problem is formulated as a minimum crossing Y -Steiner Minimal tree problem with multi-layer assignment. Experimental results are quite encouraging.

In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contributions include: (i) an algorithm for optimal placement of the gates or cells to minimize the possible occurrence of hot spots, (ii) results of sensitivity analysis of thermal characteristic of a layout with respect to the power densities of the modules in the layout, and identifying three classes of modules, and (iii) an algorithm for optimal placement of modules, with minimum possible occurrence of hot spots, and reasonable estimated interconnect lengths. Experimental results on randomly generated and standard benchmark instances are quite encouraging.

Dominance of on-chip power densities has become a critical design constraint in high-performance VLSI design. This is primarily due to increased technology scaling, number of components, frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entail the stacking of multiple active (device) layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the thermal placement of standard cells and gate arrays (modules) taking total wire-length as well as TSVs (through silicon via) into consideration. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of the active layers are not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer, (iv) the estimated total interconnect lengths connecting the modules of the different layers are also improved, and (v) the total number of interlayer vias is quite reasonable. Experimental results on randomly generated and standard benchmark instances are encouraging.

Solving discrete optimization problems with genetic algorithms is in many aspects di erent from the solution of continuous problems. The blindness of the algorithm during the search in the space of encodings must be abandoned, because this space is discrete and the search has to reach feasible points after the application of the gentic operators. This can be achieved by the use of a problem speci c genotype encoding, and hybrid, knowledge based techniques, which support the algorithm during the creation of the initial individuals and the following optimization process. In this paper a genetic algorithm for the layout generation of VLSI-chips is presented, which optimizes two, usually consecutively solved tasks simultaneously: together with the placement o f t h e modules, the routes for the interconnection nets are optimized.

Solving discrete optimization problems with genetic algorithms is in many aspects different from the solution of continuous problems. The blindness of the algorithm during the search in the space of encodings must be abandoned, because this space is discrete and the search has to reach feasible points after the application of the gentic operators. This can be achieved by the use of a problem specific genotype encoding, and hybrid, knowledge based techniques, which support the algorithm during the creation of the initial individuals and the following optimization process. In this paper a genetic algorithm for the layout generation of VLSI-chips is presented, which optimizes two, usually consecutively solved tasks simultaneously: together with the placement of the modules, the routes for the interconnection nets are optimized. INTRODUCTION One of the main feature of a genetic algorithm applied to an optimization problem is the fact, that it does not deal with the problem itself, but w...

Genetic algorithms have proven to be a wellsuited technique for solving selected combinatorial optimization problems. When solving real-world problems, often the main task is to find a proper representation for the candidate solutions. Strings of elementary data types with standard genetic operators may tend to create infeasible individuals during the search because of the discrete and often constrained search space. This article introduces a generally applicable representation for two-dimensional combinatorial placement and packing problems. Empirical results are presented for two constrained placement problems, the facility layout problem and the generation of VLSI macro-cell layouts. For multi-objective optimization problems, common approaches often deal with the different objectives in different phases, thus are unable to efficiently solve the global problem. Due to a tree-structured genotype representation and hybrid, problem-specific operators, the proposed approach is able to deal with different constraints and objectives in one optimization step.

Circuit partitioning is a fundamental problem in very large-scale integration (VLSI) physical design automation. In this brief, we present a new connectivity-based clustering algorithm for VLSI circuit partitioning. The proposed clustering method focuses on capturing natural clusters in a circuit, i.e., the groups of cells that are highly interconnected in a circuit. Therefore, the proposed clustering method can reduce the

—Power consumption is an important issue in modern high-frequency and low power design. Multi-bit flip-flops are used to reduce the clock system power. The scaling with multiple supply voltage is an effective way to minimize the dynamic power consumption. In this paper, we propose an effective multi-bit flip-flops merging approach to deal with the clock network power minimization problem and an placement method to avoid placing flip-flops in the congestion bins. Moreover, the proposed approach can be applied to both single and multiple supply voltage designs. Experimental results show that our approach can reduced the clock power up to 25%. In addition, for multiple supply voltage designs, the proposed approach can reduce the number of level shifters significantly.

The objectives in this paper are twofold: design an approach for the netlist partitioning problem using the cooperative multilevel search paradigm introduced by Toulouse et al. and study the effectiveness of this paradigm for solving combinatorial optimization problems, in particular, those arising in the very large scale integration (VLSI) computer-aided design (CAD) area. The authors present a cooperative multilevel search algorithm CoMHP and describe a parallel implementation on the SGI O2000 system. Experiments on ISPD98 benchmark suite of circuits show, for four-way and eight-way partitioning, a reduction of 3% to 15% in the size of hyperedge cuts compared to those obtained by hMETIS. Bisections of hypergraphs based on the algorithm also outperform hMETIS, although more modestly. The authors present experimental results to demonstrate that the cooperation scheme plays a key role in the performance of CoMHP. In fact, the improvement in the quality of the solutions produced by CoMHP is to a large extent independent of the partitioners used in the implementation of CoMHP. The experimental results also demonstrate the effectiveness of the cooperative multilevel search paradigm for solving the netlist partitioning problem and show that the cooperative multilevel search strategy can be used as a paradigm for designing effective solution techniques for combinatorial optimization problems such as those arising in the VLSI CAD area.

Solving discrete optimization problems with genetic algorithms is in many aspects different from the solution of continuous problems. The blindness of the algorithm during the search in the space of encodings must be abandoned, because this space is discrete and the search has to reach feasible points after the application of the gentic operators. This can be achieved by the use of a problem specific genotype encoding, and hybrid, knowledge based techniques, which support the algorithm during the creation of the initial individuals and the following optimization process. In this paper a genetic algorithm for the layout generation of VLSI-chips is presented, which optimizes two, usually consecutively solved tasks simultaneously: together with the placement of the modules, the routes for the interconnection nets are optimized. INTRODUCTION One of the main feature of a genetic algorithm applied to an optimization problem is the fact, that it does not deal with the problem itself, but w...

Genetic algorithms have proven to be a wellsuited technique for solving selected combinatorial optimization problems. When solving real-world problems, often the main task is to find a proper representation for the candidate solutions. Strings of elementary data types with standard genetic operators may tend to create infeasible individuals during the search because of the discrete and often constrained search space. This article introduces a generally applicable representation for two-dimensional combinatorial placement and packing problems. Empirical results are presented for two constrained placement problems, the facility layout problem and the generation of VLSI macro-cell layouts. For multi-objective optimization problems, common approaches often deal with the different objectives in different phases, thus are unable to efficiently solve the global problem. Due to a tree-structured genotype representation and hybrid, problem-specific operators, the proposed approach is able to deal with different constraints and objectives in one optimization step.

Abstract. Given a set N of n terminals in the first quadrant of the Euclidean plane E2, find a minimum length directed tree rooted at the origin o, connecting to all terminals in N, and consisting of only horizontal and vertical arcs oriented from left to right or from bottom to top. This problem is ...

The task of VLSI physical design is to produce the layout of an
integrated circuit. The layout problem in VLSI-design can be
broken up into the subtasks partitioning, floor planning, placement
and routing. Routing can be classified into two types. One is
Global routing and another one is detailed routing. In detailed
routing, the Connections between blocks or cells, respectively,
have to be generated under consideration of certain constraints,
e.g., different Nets are not allowed to intersect because such
intersections produce short circuits. As routing is NP-complete, in
general it cannot be solved exactly within reasonable time bounds
for large Problem instances. Some problems are arises during the
routing process .The routing constraints are Minimize total wire
length, Minimize knees in path, Meet timing budget. To overcome
these problems Memetic algorithm has been used. Combining
global and local search is a strategy used by many successful
hybrid optimization approaches. Memetic Algorithms (MAs) are
Evolutionary Algorithms (EAs) that apply some sort of local
search to further improve the fitness of individuals in the
population. Memetic Algorithms have been shown to be very
effective in solving many hard combinatorial optimization
problems. This algorithm combines Genetic Algorithms and
advanced local search to solve VLSI circuit Routing. The effect of
local search, clustering and good initial solution on the overall
Memetic algorithm by using the circuit routing as a paradigm.

We present some fundamental flexibility properties for minimum length networks (known as Steiner minimum trees) interconnecting a given set of points in an environment in which edge segments are restricted to £ uniformly oriented directions. These networks are referred to as £ -SMTs. They promise to play an increasingly important role in the future of optimal wire routing in VLSI physical design, particularly for the next generation of VLSI circuits.

In modern VLSI designs, power consumed by
clocking is one of the major issue. Hence, in this paper propose
an algorithm for reducing the power consumption by replacing
some flip-flops with fewer multi-bit flip-flops without affecting
the performance of the original circuit. The flip-flop
replacement leading to violation of timing and placement
capacity constraints. Some techniques are proposed to avoid
this problem. Manhattan distance and co-ordinate
transformation used to identify those flip-flops that can be
merged and their legal regions. Then, a combination table is
built to enumerate all possible combinations. Finally, the flipflops
are merged in hierarchical manner. According to the
experimental results, our algorithm significantly reduces clock
power by 20-30% and besides power reduction minimizing the
total wire length is also considered.

Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction. The underlying idea behind MSV is the trade-off between power saving and performance. In this paper, we present an effective voltage assignment technique based on dynamic programming. Given a netlist without reconvergent fanouts, the dynamic programming can guarantee an optimal solution for the voltage assignment. We then generate a level shifter for each net that connects two blocks in different voltage domains, and perform power-network aware floorplanning for the MSV design. Experimental results show that our floorplanner is very effective in optimizing power consumption under timing constraints.

We study an NP-complete (and MaxSNP-hard) communication problem on tree networks, the so-called Multicut in Trees: given an undirected tree and some pairs of nodes of the tree, find out whether there is a set of at most k tree edges whose removal separates all given pairs of nodes. Multicut has been intensively studied for trees as well as for general graphs mainly from the viewpoint of polynomialtime approximation algorithms. By way of contrast, we provide a simple fixed-parameter algorithm for Multicut in Trees showing fixed-parameter tractability with respect to parameter k. Moreover, based on some polynomial-time data reduction rules which appear to be of particular interest from an applied point of view, we show a problem kernel for Multicut in Trees by an intricate mathematical analysis.

Floorplanning is a crucial phase in VLSI physical design. The subsequent placement and routing of the cells/modules are coupled very closely with the quality of the floorplan. A widely used technique for floorplanning is simulated annealing. It gives very good floorplanning results but has major limitation in terms of run time. For circuit sizes exceeding tens of modules simulated annealing is not practical. Floorplanning forms the core of many synthesis applications. Designers need faster prediction of system metrics to quickly evaluate the effects of design changes. Early prediction of metrics is imperative for estimating timing and routability. In this work we propose a constructive technique for predicting floorplan metrics. We show how to modify the existing top-down partitioning-based floorplanning to obtain a fast and accurate floorplan prediction. The prediction gets better as the number of modules and flexibility in the shapes increase. We also explore applicability of the traditional sizing theorem when combining two modules based on their sizes and interconnecting wirelength. Experimental results show that our prediction algorithm can predict the area/length cost function normally within 5-10% of the results obtained by simulated annealing and is, on average, 1000 times faster.

We consider the problem of maximizing the revenue raised from tolls set on the arcs of a transportation network, under the constraint that users are assigned to toll-compatible shortest paths. We first prove that this problem is strongly NP-hard. We then provide a polynomial time algorithm with a worst-case precision guarantee of 1 2 log 2 m T + 1, where m T denotes the number of toll arcs. Finally, we show that the approximation is tight with respect to a natural relaxation by constructing a family of instances for which the relaxation gap is reached.

We consider the problem of maximizing the revenue raised from tolls set on the arcs of a transportation network, under the constraint that users are assigned to toll-compatible shortest paths. We first prove that this problem is strongly NP-hard. We then provide a polynomial time algorithm with a worst-case precision guarantee of ${1/2}\log_2 m_T+1$, where $m_T$ denotes the number of toll arcs. Finally we show that the approximation is tight with respect to a natural relaxation by constructing a family of instances for which the relaxation gap is reached.

The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges, especially in the power-ring synthesis. Unlike the previous works that form the power rings as the enclosing bounding boxes of voltage islands, we enable power rings alignment to the outer boundaries of voltage islands. With this new formulation, the power-ring estimation becomes more accurate during floorplanning, and the power-ring synthesis is more practical after floorplanning. In this paper, we first propose a linear-time voltage-island power-ring search algorithm to identify the power rings of voltage islands and then present a linear-time optimal power-ring corner-patching algorithm to minimize the number of corners in the power rings by using post-floorplanning whitespaces. Experimental results first demonstrate that reducing corners in power rings significantly mitigates IR drop, and then show that the proposed algorithm can reduce the number of corners by 33% on average for the GSRC floorplan benchmarks. In particular, the total running time for the 16 GSRC benchmarks is less than one second on an AMD-64 machine with a 2.2 GHz CPU and 8 GB memory.

We consider the problem of maximizing the revenue raised from tolls set on the arcs of a transportation network, under the constraint that users are assigned to toll-compatible shortest paths. We first prove that this problem is strongly NP-hard. We then provide a polynomial time algorithm with a worst-case precision guarantee of 1 2 log 2 m T + 1, where m T denotes the number of toll arcs. Finally we show that the approximation is tight * This work was done while the first author was atÉcole Polytechnique, Montréal.

Congestion is one of the fundamental issues in very large scale integration physical design. In this paper, we propose two congestion-estimation approaches for early placement stages. First, we theoretically analyze the peak-congestion value of the design and experimentally validate the estimation approach. Second, we estimate regional congestion at the early stages of top-down placement. This is done by combining the wire-length distribution model and interregion wire estimation. Both approaches are based on the well-known Rent's rule, which is previously used for wirelength estimation. This is the first attempt to predict congestion using Rent's rule. The estimation results are compared with the layout after placement and global routing. Experiments on large industry circuits show that the early congestion estimation based on Rent's rule is a promising approach.