Virtual Memory Research Papers

Compressed Caching and Modern Virtual Memory Simulation

1999

viiList of Tables xivList of Figures xviChapter 1 Introduction 11.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Why Study Virtual Memory? . . . . . . . . . . . .

descriptionView Paper arrow_downwardDownload

Tarantula: A Vector Extension to the Alpha Architecture

by Stephen Felix

2002

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. Tarantula adds to the EV8 core a vector unit... more

Figure 4. Pump structure used to accelerate stride-1 reads and writes.

Table 1. Power and area estimates for a CMP- EV8 processor and for Jarantula. The “Total” line includes a 20% extra power attributed to leakage.

Figure 6. Operations per cycle sustained in Tarantula. Each bar is broken down into Flops per cycle (FPC), Memory Operations per Cy- cle (MPC) and Other (which includes integer and scalar operations).

Figure 9. Slowdown due to disabling the stride-1 double-bandwidth mode. Figure 8. Performance Scaling when Frequency is increased to 4.8Ghz (T4) and to 10.6Ghz (T10). The latter frequency results from a 1:8 ratio to a RAMBUS chip running at 1333Mhz.

Table 2. Benchmark descriptions. Columns “Prefetch” and “DrainM” indicate whether the benchamrk uses those features.

Table 3. Characteristics of the four architec- tures under study. Note that the L2 BW refers to maximum sustainable bandwidth: for EV8, both a line read and a line write can proceed in parallel. For Tarantula, in stride-1 mode, 16 lines can be read every 4 cycles and, in par- allel, 16 lines can be written every 4 cycles. Latencies are given in cycles.

descriptionView Paper arrow_downwardDownload

Mach: a system software kernel

by Richard Sanzi and

1989, Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage

descriptionView Paper arrow_downwardDownload

Adaptive caching for demand prepaging

by Scott Kaplan

2002, ACM SIGPLAN Notices

Demand prepaging was long ago proposed as a method for taking advantage of high disk bandwidths and avoiding long disk latencies by fetching, at each page fault, not only the demanded page but also other pages predicted to be used soon.... more

descriptionView Paper arrow_downwardDownload

The comprehensive approach of QoS and the evolution of ACSE protocols in multimedia communications

by Dimitris Kanellopoulos

1996, Proceedings of Third International Conference on Electronics, Circuits, and Systems

 This paper discusses the evolution of ACSE-like protocols in the multimedia communications domain. The ACSE standard has traditionally supported numerous data applications which do not claim quality of service (QoS) guarantees. In a... more

descriptionView Paper arrow_downwardDownload

The Effects of Varied Animation in Multimedia Learning: Is the extra effort worthy?

by halimah badioze zaman

2011

Animation in multimedia is said to be beneficial to learning especially when the learning material demands visual movements. The emergence of 3- Dimensional animated visuals has extended the presentation mode in multimedia learning. It is... more

descriptionView Paper arrow_downwardDownload

The A -buffer, an antialiased hidden surface method

by Loren Carpenter

ACM SIGGRAPH Computer Graphics

The A-buffer (anti-aliased, area-averaged, accumulation buffer) is a general hidden surface mechanism suited to medium scale virtual memory computers. It resolves visibility among an arbitrary collection of opaque, transparent, and... more

descriptionView Paper arrow_downwardDownload

PERFORMANCE ANALYSIS OF MINIMUM SPANNING TREE ALGORITHMS

by IAEME Publication

2020, IAEME PUBLICATION

The Minimum-weight Spanning Tree Problem (MSTP) is one of the most well known problems of combinatorial optimization. It deals with finding the spanning tree of an undirected, connected graph, such that the sum of the weights of the... more

Figure 1 Plot of Elapsed time v/s No. of Nodes

Table 2 Virtual Memory Size for various test cases From the above graph, we can infer that, the virtual memory in the case of Prim’s algorithm remains constant for any number of nodes and edges, and varies slightly when the number of nodes and edges is increased very high. Similarly, the virtual memory in the case of Boruvka’s algorithm also remains constant for all the cases, and varies slightly in the case of very high number of nodes. On an average, the virtual memory in the case of each algorithm, increases in the following order: Kruskal’s algorithm occupied the least value of Virtual Memory Size, followed by Boruvka’s algorithm, which inturn is followed by the Least Cost MST algorithm. Prim’s algorithm was observed to occupy the maximum Virtual Memory Size.

Figure 3 Plot of Resident Set Size v/s No. of Nodes

5. OBSERVATIONS AND INFERENCE 5.1. Elapsed Time (in ms)

descriptionView Paper arrow_downwardDownload

A non-blocking locking method and performance evaluation on network of workstations

by Kunihiko Kaneko

2001, Journal of Computer Science and Technology

Estudo qualitativo cujo método foi a História de Vida. O objetivo foi analisar os fatores que influenciaram a escolha pelo parto domiciliar, assistido por enfermeira obstetra, a partir da história de vida das mulheres que vivenciaram esta... more

descriptionView Paper arrow_downwardDownload

PPT on TLB Design and Management Techniques

by Sparsh Mittal

Summary of "A Survey of Techniques for Architecting TLBs" https://www.academia.edu/29585076/A_Survey_of_Techniques_for_Architecting_TLBs

descriptionView Paper arrow_downwardDownload

Virtual Memory: Structure and Operation

by ALI S A A D O O N AHMED

2020, ALI SAADOON AHMED

This report briefly describes virtual storage, its structure, operation, and uses. Today's software is developed with virtual memory and its user-friendliness is strong and dynamic. The form of virtual memory is developed primarily based... more

throughput. This is possible due to the fact at one factor of time CPU can run just one procedure. This enables us to run more than one approach at the same time as contained body memory (RAM). But the disk plays an awful lot slower than RAM, when running a couple of or giant purposes, it is exceptional to supply beginning as a plenty bodily memory if viable due to the fact the extra RAM a computer motives the less attackable it will work. Virtual memory gives us an answer when we have forced RAM, however, if we use extra virtual memory our overall performance of the computer is altered. Secondly, to get a quick response from your computer, use a good RAM deal that you can use and follow virtual memory, thinking when it is needed due to the fact with virtual memory use every value and execution is reduced. The overview of virtual storage is described in figure 1. II. DEPLOYMENT OF VIRTUAL MEMORY.

pages and each page of the request receives a special address. At a time, all the pages of a method are no longer instituted into the foremost memory solely some of the pages associated to the pages are added into most important memory due to the fact at one factor of time a CPU does not want all the pages in the essential computer storage for the execution of the application solely some of the pages are needed, final pages can be wreaked on the demand of CPU. When the CPU calls for these pages that are not at hand in the fundamental memory; it is called out of the page. Page fault capacity the demand page referenced using the CPU is no longer usable in the important memory and it is to be searched in the secondary memory. Whenever the claim page default takes place the time obtained smaller to serve the claim page default is known as the default page provider time. In the application page default support time when the required application page is in the secondary memory, we must forward this application page from the secondary memory to the vital memory. Figure 2 shows the pagination pattern of the virtual memory. BBRe SAEUVECAINE, BOSMNGEEY V EINE USAR LVEEUIVERINGE Demand-paged virtual memory is the central way in which pages are linked up and released. The application continues until it matches a numeric address that the application page tables cannot map. There was no attempt to create a request page for that digital page. The failure is known as a request page failure. On fault, the

Figure 3. The layout of the virtual memory. IV. PAGE REPLACEMENT ALGORITHMS

descriptionView Paper arrow_downwardDownload

Enhancing security in the memory management unit

by Jean-Didier Legat

1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium

We propose an hardware solution to several security problems that are difficult to solve on classical processor architectures, like licensing, electronic commerce, or software privacy. The memory management unit which provides... more

descriptionView Paper arrow_downwardDownload

Virtual memory and backing storage management in multiprocessor operating systems using object-oriented design techniques

by Roy Campbell

ACM SIGPLAN Notices

The Choices operating system architecture [3, 4, 15] uses class hierarchies and object-oriented programming to facilitate the construction of customized operating systems for shared memory and networked multiprocessors. The software is... more

descriptionView Paper arrow_downwardDownload

A Survey of Techniques for Architecting TLBs

by Sparsh Mittal

Translation lookaside buffer (TLB) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high-end servers. Since TLB is accessed very frequently and a TLB miss is extremely... more

descriptionView Paper arrow_downwardDownload

The pintos instructional operating system kernel

by Ben Pfaff and

2009, ACM SIGCSE Bulletin

Tool paper Tool paper • Series of 4 projects that provide backbone of lab component that accompanies OS course lab component that accompanies OS course • Suitable for Junior/Senior/1 st Grad students • Used by several institutions • Used... more

descriptionView Paper arrow_downwardDownload

An overview of the Spring system

by Panagiotis Kougiouris

1994, Proceedings of COMPCON '94

Spring is a highly modular, distributed, object-oriented operating system. This paper describes the goals of the Spring system and provides overviews of the Spring object model, the security model, and the naming architecture.... more

descriptionView Paper arrow_downwardDownload

Applying Memory Forensics to Rootkit Detection

by Ivan Nesterow

2014

Volatile memory dump and its analysis is an essential part of digital forensics. Among a number of various software and hardware approaches for memory dumping there are authors who point out that some of these approaches are not resilient... more

descriptionView Paper arrow_downwardDownload

Operating system questions with their answers (Part 2) (Memory management, Virtual memory, Processes synchronization) Part two

by Qasim M O H A M M E D Hussein

2015, Operating system questions with their answers (Part 2) (Memory management, Virtual memory, Processes synchronization)

Part Two: It includes questions about topics in the operating system with their answers. The topics are Main memory, Virtual memory, and Processes synchronization. Notes: 1: If this published useful for you, my recommend or follow it. 2:... more

descriptionView Paper arrow_downwardDownload

Mach: a system software kernel

by Hideyuki Tokuda

1990, Computing Systems in Engineering

needs and technology, Unix has been modified to provide a staggering number of different mechanisms for managing ob-The Mach operating system can be used as a system software kernel which can support a variety of operating jects and... more

descriptionView Paper arrow_downwardDownload

Modular design of mechatronic systems with function modeling

by Mustafa Erden

2010, Mechatronics

This paper develops a modularization scheme based on the functional model of a system. The modularization approach makes use of the function-behavior-state (FBS) model of the system to derive the entity relations. The design structure... more

Fig. 2. Schematic description of the steps of modularization using the FBS model.

RO I The DSM matrix gives the relations between the components of the system. The components can be related to each other for vari- ous reasons. Spatial placement of the components, energy, infor- mation and material transfer between the components can be such reasons [21]. These dependencies are delineated in the FBS In Fig. 3, a sample FBS model diagram is given for a Vacuvin Wine Saver. This simple system is chosen to describe the FBS mod- eling and the modularization to be performed. The figure consists of four layers. In the functional layer the functional decomposition of the system is given in a hierarchical way. The lowest level func- tions need to be associated with physical behaviors. This is per- formed in the behavior layer. The entities in this layer are the physical behaviors that can realize the associated functions. In the third layer the behaviors are associated with physical entities. The behaviors are the result of the change of state of the entities; hence this is the state level. It can be the case that a behavior is realized by more than one entity. Therefore there is no one-to- one correspondence between the functions and physical entities. Fig. 3. The FBS model of a Vacuvin Wine Saver, and the DSM matrix for the relations of its entities.

Fig. 4. An example of constructing the colors of the function/behavior nodes based on their connection to the component modules. The oval nodes represent the functions/ behavior; the rectangular nodes represent the components. G represents the one level acyclic-directed-connections from the component to function/behavior nodes. The DMM is the domain mapping matrix associating the components with the modules.

Fig. 5. One of the DUT Formula Student cars (a) and its shifting system (b) [Pictures by Jorrit Lousberg].

Fig. 6. The initial DSM_r constructed based on the direct relations between the components.

Fig. 7. The FBS model of the shifting system of the DUT Formula Student car. The functions are shown as rounded rectangles, behaviors as red rounded rectangles, components as white rectangles, and the direct relations between the components as green diamonds. The names of the relations are excluded due to limitations on the space; instead numbers are given sequentially. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

Fig. 8. The DSM_r after modularization. The three modules that are generated by the clustering algorithm are shown in rectangles

Fig. 9. The embedding of the DSM_r based clustering on the FBS model by graph coloring. In Fig. 10, the initial DSM_b of the shifting system is given. The entries of this matrix take continues values in the range [0, 1]. The values are derived from the behavior level connections, based on the strength of the relation from one component to the other. The diagonal entries are again filled with 1, designating that a com- ponent is related with itself in the highest degree. Most of the high valued relations (0.6) correspond to some direct relations given in

Fig. 11. The DSM_r after modularization. The three modules that are generated by the clustering algorithm are shown in rectangles.

Fig. 12. The embedding of the DSM_b based clustering on the FBS model by graph coloring.

Fig. 10. The initial DSM_r constructed based on the relations between the components through the behavioral level.

descriptionView Paper arrow_downwardDownload

Applying Memory Forensics to Rootkit Detection

by Igor Korkin and

Volatile memory dump and its analysis is an essential part of digital forensics. Among a number of various software and hardware approaches for memory dumping there are authors who point out that some of these approaches are not resilient... more

descriptionView Paper arrow_downwardDownload

Algoritma Page Replacement & Pengalokasian Frame

by rio agus permana

Menjelaskan tentang apa itu Page Replacement ? mengapa Diperlukan ? & bagaimana Algoritma yang digunakan dalam Page Replacement itu sendiri

descriptionView Paper arrow_downwardDownload

Power-aware network swapping for wireless palmtop PCs

by Alessandro Bogliolo

2006, Mobile Computing, IEEE …

Virtual memory is considered to be an unlimited resource in desktop or notebook computers with high storage capabilities. However, in wireless mobile devices, like palmtops and personal digital assistants (PDAs), storage memory is limited... more

descriptionView Paper arrow_downwardDownload

Malicious Shellcode Detection With Virtual Memory Snapshots

by Adam Champion

2010

descriptionView Paper arrow_downwardDownload

Pilot: an operating system for a personal computer

by Hugh Lauer

1980, Communications of the ACM

The Pilot operating system provides a single-user, single-language environment for higher level software on a powerful personal computer. Its features include virtual memory, a large "fiat" file system, streams, network communication... more

descriptionView Paper arrow_downwardDownload

Automatic vs. explicit memory management: Settling the performance debate

by Matthew Hertz

2004

While garbage collection's software engineering benefits are indisputable, its performance impact remains controversial. Garbage collection proponents argue that its benefits outweigh its costs, but it is widely believed that garbage... more

descriptionView Paper arrow_downwardDownload

Addressing Mechanisms for Large Virtual Memories

by James Leslie Keedy

1992, The Computer Journal

Traditionally there has been a clear distinction between computational (short-term) memory and filestore (long-term memory). This distinction has been maintained mainly due to limitations of technology. Recently there has been... more

descriptionView Paper arrow_downwardDownload

Energy-Aware Flash Memory Management in Virtual Memory System

by Hung-wei Tseng

2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems

The traditional virtual memory system is designed for decades assuming a magnetic disk as the secondary storage. Recently, flash memory becomes a popular storage alternative for many portable devices with the continuing improvements on... more

Fig. 1. The flash memory storage system architecture.

Fig. 3. Data allocation (a) without and (b) with hot-cold separation.

Fig. 4. Hot—cold separation mechanism: two-level LRU. only dead pages. Therefore, it incurs zero copying overhead if the block A is selected as the victim. As for the data allocation shown in Fig. 3(a), dead pages are distributed in two blocks. Therefore, selecting either block as the victim incurs copying overheads. Reducing garbage collection overhead has signifi- cant impact on energy since it results in less frequent garbage collection. Therefore, data allocation with locality gathering is critical for designing an energy efficient flash storage.

Fig. 6. Data allocation with/without intrapage locality. Fig. 5. Flash memory as a swap device. data that are accessed close in time to the same flash block. With the same reasoning, preserving intrapage locality is important for efficient garbage collection. Consider two data allocation methods shown in Fig. 6. Assume a main memory page con- tains eight flash pages. In Fig. 6, two flash blocks contain four main memory pages A, B, C, and D. In Fig. 6(a), flash pages in one main memory page are allocated in one block, while in Fig. 6(b), they are scattered in two blocks. Assume after a period of time, memory page A and B are swapped out. Therefore, for the data allocation in Fig. 6(a), block X contains only dead flash pages, while for the data allocation in Fig. 6(b), both block X and Y contain dead and live pages. Therefore, destroying intra- page locality could cause adverse effect on garbage collection efficiency thereby increasing overall energy consumption.

Fig. 8. Casel:n = 16,m = 4, and GC; = 20. Fig. 7. Overall flash energy consumption under different GC thresholds.

Fig. 9. Case2:n = 16,m = 4, and GC; = 25.

Fig. 10. Case3:n = 16, m = 4, and GC; = 23.

Fig. 11. Modified FTL for HotCache. not be replaced out of the HotCache in sequence. Therefore, to avoid destroying intrapage locality, we enhance the TF policy by forcing all the pages of the same virtual memory page to be replaced in sequence. The virtual page number of the victim block is recorded and a counter is used to keep track of how many HotCache blocks in the same main memory pages have been replaced. A HotCache block with the smallest timestamp x write_counts and has the same recorded virtual page number is chosen as the victim HotCache block. Once the counter reaches zero, a HotCache block with smallest timestamp x write_counts is selected as the victim. Its main memory page number is then recorded and the counter is reset. Note that since the virtual memory page number of a HotCache block can be obtained directly from the cache tag,? we do not need to record the page number of each HotCache block. The enhanced TF policy is called TF-locality (TFL).

Fig. 12. DA-GC. aa aaa * eae) Saale“ > aaa a! SY daa AR aaa ~s FTL sees a read request, and sets the corresponding in-memory flag. Note that in the conventional swap system, FTL is no aware of the swap-out events of clean pages. Therefore, tc support DA-GC, we add a swap-clean call to notify FTL the swap_out event of a clean page. The other issue that we neec to address to support DA-GC is to guarantee the write back o: those flash pages that are omitted during garbage collection. Tc achieve this, FTL notifies the kernel of the associated PID anc virtual page number of omitted flash pages with a swap_free call which sets the dirty bit of the matched PTE (page table entry). In the case of shared memory, swap_free may fail to finc the matched PTE. Assume memory page X is shared betweer process A and B. If process A is selected by the kernel to sway out page X, process A’s identifier and corresponding virtua page number are recorded in the BAM. Assume memory page X is later swapped in by process B. Since the BAM is indexec with LBAs, the in-memory flag can be set correctly. Wher the flash pages of memory page X are omitted during garbags collection, FTL calls swap_free with process A’s identifier. I process A has not read memory page X, the corresponding PTE is actually invalid. In this case, swap_free should return < failure to disable DA-GC. The other case that swap_free need: to return a failure is when a process detaches shared memory The detach operation invalidates corresponding PTEs of the shared memory. Therefore, swap_free is not able to find the matched PTEs if the associated shared page has been detached

Fig. 13. Relative energy consumption of subpaging technique in 512 B and 2 kB flash page size.

Fig. 14. The average energy consumption under different HotCache schemes (HotCache size: 512 Kk)

SARBAGE COLLECTION FREQUENCY REDUCTION OF DA-GC

Fig. 16. Combined effect of HotCache, subpaging and DA-GC. Fig. 15. Overall energy reduction of DA-GC.

Dr. Yang is the recipient of a 2000-2001 Intel Foundation Graduate Fellow- ship Award and 2005 IBM Faculty Award.

NAND FLASH CHARACTERISTICS consumption than mechanical hard drives. The characteristics of flash memory are quite different from a magnetic disk. There- fore, in this paper, we revisit virtual memory system design con- sidering limitations imposed by flash memory. In particular, we focus on the energy efficient aspect since power is the first-order design consideration for embedded systems.

DIRTY RATIO OF WORKLOADS! page. We can see that only very few applications, e.g., gqview, have high dirty ratio. For mozilla, the dirty ratio is below 50%. Therefore, writing a full victim page to flash memory is not energy efficient.

WORKLOADS USED IN OUR EXPERIMENTS AND THEIR CHARACTERISTICS TABLE III

We adopt a trace-driven simulation in this paper. Our simu- lator contains a main memory paging system and flash storage with an SRAM. We use Valgrind [9] on an x86-linux machine to collect memory traces. The applications we tested in this study are listed in Table III: kword, a word processor; mozilla, a web browser; kspread, a spreadsheet application; openoffice, a pop- ular office suite similar to Microsoft office; gqview, a image viewer. We also create multiprogramming workloads by run- ning juk, an MP3 jukebox program, with applications listed in Table III. The OS adopts the round-robin scheduling policy.

WRITE HIT RATES OF HOTCACHE MECHANISMS (HOTCACHE SIZE: 512 kB/1 MB) subpaging) assuming both the 512 B and 2 kB flash page size. We also show write reduction rates in Table VI. We can see that with a 512 B flash page, the subpaging could reduce up to 59.1% writes and 36.5% of flash energy (mozillatjuk). Since there are only few writes in gqview, the subpaging technique only reduces 1.1% of writes. Note that gqview shows slight increases in energy consumption after applying subpaging. Although subpaging reduces writes to flash memory, intrapage locality no longer exists. If the energy benefit of reducing writes through subpaging cannot compensate the adverse effect of losing intrapage locality, as in the case of gqview, subpaging could increase energy consumption. With a 2 kB flash page, the subpaging is less effective since a main memory page only contains two flash pages. The effects of subpaging depends on the dirty ratio which is defined in Section IV-A. The lower the dirty ratio is, the higher energy reduction we expect to see by adopting subpaging. In single-programming workloads, mozilla and openoffice show most significant energy reduction via subpaging since the dirty ratio of these two applications are much lower than others. Multiprogramming workloads show lower dirty ratio than single-programming ones since there are more contention for the memory resource. With a 512 B flash page, the subpaging achieves about 22.2% energy saving on

REDUCED WRITES BY SUBPAGING the average for multiprogramming workloads, and 10.4% for single-programming workloads.

AVERAGE NUMBER OF DUPLICATED PAGES AND GARBAGE COLLECTION OVERHEAD REDUCTION OF DA-GC TABLE VIII

descriptionView Paper arrow_downwardDownload

VIRTUAL MEMORY

by Candra Aditama

Sebagian besar algoritma manajemen memori memerlukan satu kebutuhan dasar yaitu instruksi yang akan dieksekusi harus berada di memori fisik. Pada beberapa kasus, keseluruhan program tidak diperlukan. Misalnya :

descriptionView Paper arrow_downwardDownload

A Methodology for Distributed Virtual Memory Improvement

by Sa'ed Abed and

2011, Communications in Computer and Information Science

In this paper, we present a methodology for managing the Distributed Virtual Memory (DVM). The methodology includes distributed algorithms for DVM management to detect the memory status which will enhance previous DVM techniques. The DVM... more

Fig. 4. Master Node Page Faults for Every Approximately 10000 Page References

descriptionView Paper arrow_downwardDownload

Grasshopper-a persistent operating system for conventional hardware

by Francis Vaughan

Object Orientation in …

descriptionView Paper arrow_downwardDownload

Tarantula

by Isaac Hernandez

2002, ACM SIGARCH Computer Architecture News

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. Tarantula adds to the EV8 core a vector unit... more

Table 1. Power and area estimates for a CMP- EV8 processor and for Tarantula. The “Total” line includes a 20% extra power attributed to leakage.

Table 4. Sustained bandwidth in MBytes/s on Tarantula for several microkernels. The “Raw” column includes all memory transactions per- formed at the RAMBUS controller, including those necessary to update the directory infor- mation. The “Streams” column reports use- ful read/write bandwidth using the STREAMS method without accounting for directory traf- fic. Table 4. Sustained bandwidth in MBytes/s on Tarantula for several microkernels. The “Raw” column includes all memory transactions per- formed at the RAMBUS controller, including those necessary to update the directory infor- mation. The “Streams” column reports use- ful read/write bandwidth using the STREAMS method without accounting for directory traf- fic.

descriptionView Paper arrow_downwardDownload

CRAMM: Virtual memory support for garbage-collected applications

by Ting Yang and

2006

Existing virtual memory systems usually work well with applications written in C and C++, but they do not provide adequate support for garbage-collected applications. The performance of garbage-collected applications is sensitive to heap... more

Figure 1: Impact of bursts of memory pressure on the per formance on the JRockit Java virtual machine, which de- grades throughput by as much as 94%.

Figure 2: The CRAMM system. The CRAMM VM system efficiently gathers detailed per-process reference informa- tion, allowing the CRAMM heap size model to choose an optimal heap size dynamically.

Figure 3: The effect of heap size on performance and work- ing set size (the number of pages needed to run with at most a 5% slowdown from paging).

Figure 4: Segmented queue page lists for one address space (file or process).

Figure 5: Virtual memory overhead (% increase in execu- tion time) without paging, across all benchmark suites and garbage collectors.

Figure 7: Static Memory Allocation: GenMS Figure 6: Static Memory Allocation: MarkSweep

Figure 8: Dynamic Memory Allocation (pseudojbb): Heap A djustment and Throughput Table 1: Dynamic Memory Allocation: Performance of A daptive vs. Non-A daptive Collectors

Wealso compare the throughput of the adaptive and non- adaptive collectors (the second row in Figure 8), by printing out the number of transactions finished as time elapses for pseudojbb. These curves show that memory pressure has much less impact on throughput when running under our adaptive collectors. It causes only a small disturbance and only for a short period of time. The total execution time of our adaptive collectors is a little longer than that of the base case, simply because they run at a much smaller heap size (and thus collect more often) when there is less Figure 9: Throughput under dynamic memory pressure, versus J Rockit and HotSpot.

Figure 10: Running Two Instances of A daptive Collectors.

Table 2: A comparison of approaches to dynamic heap sizing.

descriptionView Paper arrow_downwardDownload

A scalable bottom-up data mining algorithm for relational databases

by Giovanni Giuffrida

1998, Proceedings. Tenth International Conference on Scientific and Statistical Database Management (Cat. No.98TB100243)

Machine learning induction algorithms are difficult to scale to very large databases because of their memory-bound nature. Using virtual memory results to a significant performance degradation. To overcome such shortcomings, we developed... more

descriptionView Paper arrow_downwardDownload

Supporting task migration in multi-processor systems-on-chip: a feasibility study

by Divya Sharma

2006, Proceedings of the …

With the advent of multi-processor systems-on-chip, the interest in process migration is again on the rise both in research and in product development. New challenges associated with the new scenario include increased sensitivity to... more

descriptionView Paper arrow_downwardDownload

Tarantula: a vector extension to the alpha architecture

by Toni Juan and

2002, Computer …

descriptionView Paper arrow_downwardDownload

Distribution+ persistence= global virtual memory

by Graham Hellestrand

1992, … , Proceedings of the …

descriptionView Paper arrow_downwardDownload

Quality-augmented fusion of level-2 and level-3 fingerprint information using DSm theory

by Richa Singh

2009, International Journal of Approximate Reasoning

Existing algorithms that fuse level-2 and level-3 fingerprint match scores perform well when the number of features are adequate and the quality of images are acceptable. In practice, fingerprints collected under unconstrained environment... more

Fig. 1. (a) A poor quality fingerprint image which cannot be used for level-3 feature extraction; (b) a partial fingerprint image containing pores and ridges (level-3 features) but no minutiae (level-2 features); and (c) a fingerprint image containing both level-2 and level-3 features. ee eee eee ee ee eee eee ee oe wt et Ok Oe eee ideal, partial, and low quality fingerprints can affect the overall performance of the system. In this research, we propose a fusion algorithm to efficiently combine level-2 and level-3 fingerprint feature: by incorporating image quality. We first compute the quality score of fingerprint image using the proposec redundant discrete wavelet transform (RDWT) based quality assessment algorithm [11]. This quality scor provides the degree of imprecision for the extracted information. We then extract the level-2 and level-3 fea ures from fingerprint image using existing minutiae [12,13] and pores [7,8] based recognition algorithms These algorithms provide matching scores for both level-2 and level-3 features which are further normalizec using quality scores to generate the quality-augmented match scores. There are several fusion algorithms ir iterature that fuse two or more biometric information. These algorithms are generally based on statistica rules such as sum rule [10,14,15], min-max rule [14,15], product rule [14,15], or learning techniques [16]. Botl he existing statistical and learning based rules can not efficiently handle the imprecise and incomplete infor mation. The performance deteriorates if information on any of the features is missing or highly conflicting. Ir our approach, we efficiently fuse the imprecise and incomplete information for fingerprint recognition by applying the Dezert-Smarandache (DSm) theory of paradoxical reasoning [17,18] to the quality-augmentec match scores. DSm theory based match score fusion algorithm computes the final match score and determine: the verification accuracy. To validate the proposed algorithms, we use a database of 500 classes obtained fron

Fig. 2. Images with quality scores computed using the proposed RDWT based quality assessment algorithm. where 4: and o are mean and standard deviations of quality scores obtained from good quality training finger- print images. Normalized quality score Qyorm lies in the range of [0,1], where 0.5 represents the best quality image and 0 & | represent worst quality image. Fig. 2 shows fingerprint images of different quality and their quality scores computed using the proposed RDWT quality assessment algorithm with 3-levels of RDWT decomposition.

Fig. 3. DSm theory based fusion of quality-augmented match scores obtained from the two fingerprint verification algorithms. In the proposed DSm theory based match score fusion algorithm, we define the frame of discernment, O= 1 O scnaines Bimpostor} and Dedekind lattice, D®° = {Ooenuines impostor» ODeenuine U Gimpastors Greenline a Gimpostor'}s Further, for every input fingerprint image, each classifier assigns a label true or 1 to proposition a,a € © and the remaining classes are labeled as false or 0. Thus, there are two focal elements for each fingerprint verifi- Please cite this article in press as: M. Vatsa et al., Quality-augmented fusion of level-2 and level-3 ..., Int. J. Approx Reason. (2008), doi:10.1016/j.ijar.2008.01.009

Fig. 4. ROC plots for verification performance of minutia-based recognition algorithm, pore-based recognition algorithm, and th proposed DSm theory based match score fusion algorithm.

Fig. 5. ROC plots comparing existing fusion algorithms with the proposed quality-augmented DSm fusion algorithm for level-2 and level- 3 features.

Verification accuracy is computed with FAR = 0.01%. Comparison of verification accuracies of the proposed quality-augmented DSm fusion algorithm with existing fusion algorithms using fingerprints with varying number of features

descriptionView Paper arrow_downwardDownload

MMLite

by Alessandro Forin

1998, Proceedings of the 8th ACM SIGOPS European workshop on Support for composing distributed applications - EW 8

MMLite is a modular system architecture that is suitable for a wide variety of hardware and applications. The system provides a selection of object-based components that are dynamically assembled into a full application system. Amongst... more

One example where we found mutation to be useful was in device drivers. In one configuration on the x86 we used minimal floppy and disk drivers that called BIOS (ROM) functions to do the work. A loadable driver would later take over and mutate the BIOS driver with a real driver, transparently to the filesystem.

In this setup communication latency is important for the performance of the application using DirectX. On a 90MHz PC we measured in excess of 7,800 RPC/second between a user mode WindowsNT process and a MMLite component, with time predominantly spent in NT. Figure 5: MIDI synthesizer components.

and stubs, and perform the necessary argument marshaling and unmarshaling. A graphics component does the rendering and writes the results into a frame buffer. An audio component uses the on-board A/D converters.

The system currently runs on the x86, ARM, Philips TriMedia, and Equator Technologies’ VLIW processors. The Talisman Software Development Kit [SDK97] contains the MMLite kit, and was first shipped in July 1996 to Talisman licensees.

descriptionView Paper arrow_downwardDownload

Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS and Performance-Friendly

by Solihin Solihin

2007

In today's digital world, computer security issues have become increasingly important. In particular, researchers have proposed designs for secure processors which utilize hardware-based memory encryption and integrity verification to... more

descriptionView Paper arrow_downwardDownload

Grace: Safe multithreaded programming for C/C++

by Ting Yang

2009

The shift from single to multiple core architectures means that programmers must write concurrent, multithreaded programs in order to increase application performance. Unfortunately, multithreaded applications are susceptible to numerous... more

descriptionView Paper arrow_downwardDownload

Enhancing security in the memory management unit

by Jean-jacques Quisquater

1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium

We propose an hardware solution to several security problems that are difficult to solve on classical processor architectures, like licensing, electronic commerce, or software privacy. The memory management unit which provides... more

Figure 2 - key management example. Shaded areas are secret. More elaborate protocols can be implemented on this basis, which protect the privacy of the buyer so that he does not have to give a public key identifying him or his computer.

descriptionView Paper arrow_downwardDownload

Enix

by Yuhan Chen

2010, Proceedings of the 8th ACM Conference on Embedded Networked Sensor Systems - SenSys '10

Enix is a lightweight dynamic operating system for tightly constrained platforms for wireless sensor networks (WSN). Enix provides a cooperative threading model, which is applicable to event-based WSN applications with little run-time... more

descriptionView Paper arrow_downwardDownload

MSCSim -Multilevel and Split Cache Simulator

by Carlos Martins

2006, Proceedings. Frontiers in Education. 36th Annual Conference

Learning the various structures and levels of memory hierarchy by means of conventional procedures is a complex subject. A didactic simulator of cache memory (MSCSim) was proposed and developed as part of our undergraduate research, to... more

Therefore, accesses that generate hits at the highest hierarchical level (Figure 1) can be processed faster. The accesses that generate miss are complied with access lower hierarchical levels, which are slower and bigger. If the hit rate is very high, the hierarchy has an average access time very close to that of the high hierarchical level, therefore being faster [16]-[20].

GENERAL VIEW OF SIMULATOR AND MULTILEVEL CONFIGURATIONS. The tool allows the realize of simulations of unified cache with main memory, as well as unified cache with main and virtual memories. A split cache with any type of configuration for its different caches can be simulated. In multiple level simulation the configuration of n levels is possible, either with unified or split caches.

CHOICE OF PARAMETERS FOR SPLIT CACHE CONFIGURATION (CACHE L1 AND L2).

The generation of archives of the type memory trace can be carried out in manual or random mode. In the first (Figure 4), it is necessary to specify three fields: address, write (E) or read (L), data (D) or instruction (I). For the random generation the required fields are the total number of addresses and the lower and higher value for random generation of addresses. The resultant memory trace is saved as an .mtr extension - (Memory Trace) - text format file for future use during the simulation process.

In this simulation, the hit rate (percentage of cache hit) obtained was 18%, the occupation yield of the cache memory 88%, the major part of the cache misses (addresses not found in the accessed cache) was of the lack due to capacity fault type (55% approximately), 26 substitutions have taken place in an average access time of 422ns (Figure 6). STATISTICS AND GRAPHIC OF THE BASIC SIMULATION.

With the use of an unified cache memory, set associative two way with 4 slots, access time of 10 ns, write back policy and FIFO replacement. Only seven cache hits have taken place due to the occurrence of various cache miss substitution (Figure 5). VIEW OF A UNIFIED SET ASSOCIATIVE CACHE SIMULATION.

write back policy and FIFO replacement. The third level (cache L3) composed of 8 slots, set associative (three way), 50ns access time and write back policy, LRU replacement. In this simulation the closest processor levels has the aim to prevent the conflict between the data and the instructions for the same slots, and the lower levels reduce the penalty by each cache miss. OVERVIEW OF THE FIRST LEVEL OF DATA CACHE SIMULATION AND REMAINING ADDRESSES.

All the mentioned metrics can be viewed at any time during the simulation process at the statistics screen (Figure 6), enabling an easy comparison amongst the structures.

Due to its capability of spanning various levels of knowledge the Simulator was placed in operation at the Pontifical Catholic University of Minas Gerais, Computer

descriptionView Paper arrow_downwardDownload

Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information

by Basilio B Fraguela

2009, 2009 15th IEEE Real-Time and Embedded Technology and Applications Symposium

While caches are essential to reduce execution time and power consumption, they complicate the estimation of the Worst-Case Execution Time (WCET), crucial for many Real-Time Systems (RTS). Most research on static worst-case cache behavior... more

descriptionView Paper arrow_downwardDownload

Automatic heap sizing

by Ting Yang and

2004, Proceedings of the 4th international symposium on Memory management - ISMM '04

Heap size has a huge impact on the performance of garbage collected applications. A heap that barely meets the application's needs causes excessive GC overhead, while a heap that exceeds physical memory induces paging. Choosing the best... more

descriptionView Paper arrow_downwardDownload

Throughput Capacity of a Sequence of Queues with Blocking Due to Finite Waiting Room

by Guy Pujolle

2000, IEEE Transactions on Software Engineering

A tandem queueing system with blocking due to finite waiting room is considered. Maximum throughput is studied by an approximation for several cases. The service time can depend on the number of customers; intermediate arrivals can also... more

which is the flow conservation equation between stations i andit+1. Let us now go back to system (1). It can be rewritten asa set of recursive relations:

For WN sufficiently large, this is impossible, except if A= 0. We thus have proved that the limit value is p.. = (M/(M + 1))?.

At first sight, the system of equations (6) seems very com- plex, since m variables ;(/) are introduced at each station. It will be shown that (6) can be reduced to a system (7) which is quite comparable to systems (2) or (5). This reduction will be performed in the case where the N stations are identical, only because the notation is simpler; it is, in fact, quite general. It is not very rare that service times rendered in a station do not depend on the number of customers awaiting. For example, it is well known that the time necessary to execute a program in a computer with a virtual memory operating system is very dependent on the number of jobs in the main memory. Then, in this section, we assume that the service times are still exponentially distributed, but depend on the number of customers present at the station. The service rate of station i is now u;(/) if there are j customers at the station.

This system is quite similar to that studied in the previous paragraph. It is thus possible to put it in the recursive form:

3) Two stations are in sequence, the first with a constant service rate, the second with a service rate depending on the number of customers. Let u;(p2(i)) be the service rate of the first station (the second station). We obtain Example of Two Stations in Series

The maximum input rate is achieved for Xz =, in the usual notation. We thus have

Fig. 5. A two tandem queueing system with a maximum sojourn time

MAXIMUM THROUGHPUT FOR THE (m, /) SYSTEM

‘ig. 7. Maximum throughput of the system versus the multiprogram- ming degree. TABLE VIII

Fig. 8. A model of the MV8 node-to-node protocol.

IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, VOL. SE-5, NO. 6, NOVEMBER 1979 The basic contribution of this section is that it provides a quantitative basis for the choice of the window width of a general node-node protocol according to the values of the parameters of the system.

allows extensions that no other theoretical method can achieve for the time being. In the following paragraphs, some of these extensions are presented.

descriptionView Paper arrow_downwardDownload

Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations’ Perspective

by Jack Liu

2006, Lecture Notes in Computer Science

Intel Extended Memory 64 Technology (EM64T) and AMD 64-bit architecture (AMD64) are emerging 64-bit x86 architectures that are fully x86 compatible. Compared with the 32-bit x86 architecture, the 64-bit x86 architectures cater some new... more

descriptionView Paper arrow_downwardDownload

Grace: Safe multithreaded programming for C/C++

by Tongping Liu

2009

descriptionView Paper arrow_downwardDownload

Log In

Virtual Memory

Related Topics