Virtual Memory

Physically Dense Server Architectures by Anthony Thomas Gutierrez Chair: Trevor N. Mudge Distributed, in-memory key-value stores have emerged as one of today’s most important data center workloads. Being critical for the scalability of modern web services, vast resources are dedicated solely to key-value stores in order to ensure that quality of service guarantees are met. These resources include: many server racks to store terabytes—possibly petabytes—of key-value data, the power necessary to run all of the machines, networking equipment and bandwidth, and the data center warehouses used to house the racks. There is, however, a mismatch between the key-value store software and the commodity servers on which it is run, leading to inefficient use of resources. The primary cause of this inefficiency is the overhead incurred from processing individual network packets, which typically carry small payloads of less than a few kilobytes, and require minimal compute resources. Thus, one of ...

Hardware-design languages typically impose a rigid communication hierarchy that follows module instantiation. This leads to an undesirable side-effect where changes to a child's interface result in changes to the parents. Soft connections address this problem by allowing the user to specify connection endpoints that are automatically connected at compilation time, rather than by the user.

This paper describes a student project which is a major part of a senior level Operating Systems course at the Federal Institute of Technology in Lausanne. The project consists in conceiving and implementing an entire Operating System, where user jobs benefit from a simulated paged virtual memory on a DEC-LSI/11 based microprocessor. Students program in Portal, a modular high level language similar to Modula. The positive reactions we have obtained from our students center on satisfaction in having participated in defining specifications and having implemented an entire system themselves.

These proceedings are a collection of contributions to computer system performance, selected by the usual refereeing process from papers submitted to the symposium, as well as a few invited papers representing significant novel contributions made during the last year. They represent the thrust and vitality of the subject as well as its capacity to identify important basic problems and major application areas. The main methodological problems appear in the underlying queueing theoretic aspects, in the deterministic analysis of waiting time phenomena, in workload characterization and representation, in the algorithmic aspects of model processing, and in the analysis of measurement data. Major areas for applications are computer architectures, data bases, computer networks, and capacity planning. The international importance of the area of computer system performance was well reflected at the symposium by the presence of participants from nineteen countries. The mixture of participants was also evident in the institutions which they represented: 35% from universities, 25% from governmental research organizations, but also 30% from industry and 10% from non-research government bodies. This proves that the area is reaching a stage of maturity where it can contribute directly to progress in practical problems. The Editors. PREFACE METHODOLOGY A systematical approach to the performance modelling of computer systems M.G. KIENZLE and K.C. SEVCIK Synchronization problems in hierarchically organized multiprocessor computer systems U. HERZOG and W. HOFFMANN v COMPUTATIONAL METHODS FOR QUEUEING NETWORKS Some extensions to multiclass queueing network analysis Y. BARD Mean value analysis of queuing networks -A new look at an old problem M. REISER A computational algorithm for queue distributions via the Pblya theory of enumeration H. KOBAYASHI A direct numerical method for queueing networks W. J. STEWART APPLIED PERFORMANCE ANALYSIS Performance evaluation of the BASIS system R.P. VAN DE RIET A model of a heterogeneous multiple-minicomputer: System M2 -Performance evaluation during developments J.-J. GUILLEMAUD Regime process analysis of a virtual machine operating system W.-T.K. LIN A hybrid simulation/analytical model of a batch computer system D. ASZTALOS An approach to the construction of workload models W. MATERNA vii viii LI ST OF CONTENTS SCHEDULING TECHNIQUES Scheduling under resource constraints -Achievements and prospects J. B~AiEWICZ and J. W~GLARZ Analysis of a class of schedules for computer systems with real time applications A.A. FREDERICKS A load-sensitive scheduler for interactive systems M. RUSCHITZKA Priority batch processing for upper bounded response times U. DE CARLINI, A. MAZZEO, and C. SAVY Waiting-time distributions for deadline-oriented serving B. WALKE and W. ROSENBOHM INFORMATION SYSTEMS An example for an adaptive control method providing data base integrity' LI ST OF CONTENTS ix PERFORMANCE CONTROL Performance evaluation of a cache memory for a mini-computer M. BADEL and J. LEROUDIER Performance improvement by feedback control of the operating system A. GECK A queueing model of a timesliced priority driven task dispatching algorithm P.S. KRITZINGER, A.E. KRZESINSKI, and P. TEUNISSEN A study of a mechanism for controlling multiprogrammed memory in an interactive system A. BRANDWAJN and J .A. HERNANDEZ COMMUNICATION NETWORK MODELLING I Modelling of local computer networks O. SPANIOL A communication protocol and a problem of coupled queues L. BOGUSLAVSKII and E. GELENBE Virtual circuits versus Datagram -Usage of communication resources A. BUTRIMENKO and U. SICHRA COMMUNICATION NETWORK MODELLING II Failsafe distributed loop-free routing in communication networks A. SEGALL Sizing a message store subject to blocking criteria E. ARTHURS and J.S. KAUFMAN AUTHOR INDEX METHODOLOGY Performance of Computer Systems M. Arato, A. Butrimenko. E. Gelenbe (eds.) ©r rASA. North-Holland Pub 1i shi ng Company. r979

Operating systems are designed to manage a computer's hardware and software resources. As technology is getting developed day by day, the management of resources and the memory optimization are very important for computing to solve real-world problems has become essential. Over time, advanced researchers continue to study big problems to find solutions within minimal time. To overcome these problems of memory management there are various concepts available in operating systems like memory isolation, segmentation, paging, virtual memory, fragmentation etc. In This paper proposes a custom toy operating system in Rust programming language which aims to solve the problems occurred in memory management and found an effective way of memory optimization using the concept of paging. Because Rust offers a higher level of memory safety without relying on a garbage collector than C and C++, it ischosen over other programming languages which will help in memory optimization.

Real-time data stream processing at the edge is crucial for time-sensitive tasks within large-scale IoT systems. Task scheduling plays a key role in managing the Quality of Service (QoS), necessitating a prioritization system to distinguish between high and low-priority tasks, thus ensuring efficient data processing on edge nodes. Existing scheduling algorithms rigidly prioritize tasks deemed as high-priority, often at the expense of fairness and overall system efficiency. In this paper, we propose a Priority-aware Fair Task Scheduling (FTS-Hybrid) algorithm that addresses these challenges by managing prioritybased task execution in a controlled manner. Our task scheduling algorithm streamlines resource utilization and enhances system responsiveness, contributing to low latency and high throughput, outperforming competing techniques including First-Come-First-Serve (FCFS), Round Robin (RR), and Priority Scheduling (PS). We implemented FTS-Hybrid on Apache Storm and evaluated its performance using an open-source real-time IoT benchmark (RIoTBench). Experimental results show that the FTS-Hybrid algorithm reduces task execution latency by 24%, 31%, and 26% compared with FCFS, RR, and PS, respectively, by strategically mitigating queuing delays under dynamic workload conditions.

Improper access of data buffers is one of the most common errors in programs written in assembler, C, C++, and several other languages. Existing programs and OSs frequently access the data beyond the allocated buffers or access buffers that were already freed. Such programs and OSs may run for years before their problems can be detected because improper memory accesses frequently result in a silent data corruption. Not surprisingly, most computer worms exploit buffer overflow errors to gain complete control over computer systems. Only after recent worm epidemics, did code developers begin to realize the scale of the problem and the number of potential memory-access violations in existing code. Due to the syntax and flexibility of many programming languages, memory access violation problems cannot be detected at compile time. Tools that verify correctness before every memory access impose unacceptably high overheads. As a result, most of the developed techniques focus on preventing the hijacking of control by hackers and worms due to stack overflows. Consequently, hidden data corruption is given less attention. Memory access violations can be efficiently detected using the hardware support of the paging and virtual memory. Kefence is the general run-time solution we developed that allows to detect and avoid in-kernel overflow, underflow, and stale access problems for internal kernel buffers. Kefence is especially applicable to file system code because file systems operate at a high level of abstraction and require no direct access to the physical memory. At the same time, file systems use a large number of kernel buffers and file system errors are most harmful for users because users' persistent data can be corrupted.

Transactional Memory is a promising parallel programming model that addresses the programmability issues of lockbased applications using mechanisms that are transparent to developers. Hardware Transactional Memory (HTM) implements these mechanisms in silicon to obtain better results than fine-grain locking solutions. One of these mechanisms is data version management, that decides how and where the modifications introduced by transactions are stored to guarantee their atomicity and durability. In this paper, we show that aborts are frequent especially for applications with coarse-grain transactions and many threads, and that this severely restricts the scalability of log-based HTMs. To address this issue, we propose the use of a gated store buffer to accelerate eager version management for log-based HTM. Moreover, we propose a novel design, where the store buffer is used to perform lazy version management (similar to Rock [12]) but overflowed transactions execute with a fallback log-based HTM that uses eager version management. Assuming an infinite store buffer, we show that lazy version management is better suited to applications with finegrain transactions while eager version management is better suited to applications with coarse-grain transactions. Limiting the buffer size to 32 entries, we obtain 20.1% average improvement over log-based HTM for applications with fine-grain transactions (using lazy version management) and 54.7% for applications with coarse-grain transactions (using eager version management).

This talk reports on findings gained during roadmapping activities for automotive embedded systems development, conducted in the broader environment of the Artemis Technology Platform (). It discusses key trends in the distributed development of embedded automotive applications, and the challenges arising towards implementing such new development processes. Topics covered range from impact on real-time analysis, safety analysis, distributed control, and human-in-the-loop analysis. The talk will point out resulting research directions and research priorities.

The emergence of monitoring applications has precipitated the need for Data Stream Management Systems (DSMSs), which constantly monitor incoming data feeds (through registered continuous queries), in order to detect events of interest. In this article, we examine the problem of how to schedule multiple Continuous Queries (CQs) in a DSMS to optimize different Quality of Service (QoS) metrics. We show that, unlike traditional online systems, scheduling policies in DSMSs that optimize for average response time will be different from policies that optimize for average slowdown, which is a more appropriate metric to use in the presence of a heterogeneous workload. Towards this, we propose policies to optimize for the average-case performance for both metrics. Additionally, we propose a hybrid scheduling policy that strikes a fine balance between performance and fairness, by looking at both the average- and worst-case performance, for both metrics. We also show how our policies can be ada...

Changing trends in technologies, notably cheaper and faster memory hierarchies, have made it worthwhile to revisit many hardware-oriented design decisions made in previous decades. Hardware-oriented designs, in which one uses special- purpose hardware to perform some dedicated function, are a response to a high cost of executing instructions out of memory; when caches are expensive, slowor in scarce supply, it is a perfectly reasonable to use hardware that do not compete with user applications for cache space and do not rely on the performance of the caches. In contrast, when the caches are large enough to withstand competition between the application and operating system, the cost of executing operating system functions out of the memory subsystem decreases significantly and software-oriented designs become manageable.

The Intel iAPX 432 is an object-based microcomputer which, together with its operating system iMAX, provides a multiprocessor computer system designed around the ideas of data abstraction. iMAX is implemented in Ada and provides, through its interface and facilities, an Ada view of the 432 system. Of paramount concern in this system is the uniformity of approach among the architecture, the operating system, and the language. Some interesting aspects of both the external and internal views of iMAX are discussed to illustrate this uniform approach.

We describe a scheme for supporting huge address spaces without the need for long addresses implemented in hardware. Pointers are translated ("swizzled") from a long format to a shorter format (directly supported by normal hardware) at page fault time. No extra hardware is required beyond that normally used by virtual memory systems, and no continual software cost is incurred by presence checks or indirection of pointers. This scheme could be used to fault pages into a normal memory from a persistent store, or simply to avoid extra hardware requirements when supporting large address spaces. It exploits temporal and spatial locality in much the same way as a normal virtual memory, so its performance should be quite good.

Recent technology advancements allow for the integration of large memory structures on-die or as a diestacked DRAM. Such structures provide higher bandwidth and faster access time than off-chip memory. Prior work has investigated using the large integrated memory as a cache, or using it as part of a heterogeneous memory system under management of the OS. Using this memory as a cache would waste a large fraction of total memory space, especially for the systems where stacked memory could be as large as off-chip memory. An OS-managed heterogeneous memory system, on the other hand, requires costly usage-monitoring hardware to migrate frequently-used pages, and is often unable to capture pages that are highly utilized for short periods of time. This paper proposes a practical, low-cost architectural solution to efficiently enable using large fast memory as Part-of-Memory (PoM) seamlessly, without the involvement of the OS. Our PoM architecture effectively manages two different types of memory (slow and fast) combined to create a single physical address space. To achieve this, PoM implements the ability to dynamically remap regions of memory based on their access patterns and expected performance benefit. Our proposed PoM architecture improves performance by 18.4% and 10.5% over static mapping and an ideal OS-based migration, respectively.

This paper presents a design capture system in which schematics are translated into a procedural netlist specification language. The circuit designer draws schematics with a standard structured graphics editor that knows nothing about netlists or schematics. The translator program analyzes the structured graphics output file and translates it into a procedural netlist specification.

To enable virtual machines (VMs) with a large amount of memory to be flexibly migrated, split migration has been proposed. It divides a large-memory VM into small pieces and transfers them to multiple hosts. After the migration, the VM runs across those hosts and exchanges memory data between hosts using remote paging. For such a split-memory VM, however, it becomes difficult to securely run intrusion detection systems (IDS) outside the VM using a technique called IDS offloading. This paper proposes VMemTrans to support transparent IDS offloading for split-memory VMs. In VMemTrans, offloaded IDS can monitor a split-memory VM as if that memory were not distributed. To achieve this, VMem-Trans enables IDS running in one host to transparently access VM's remote memory. To consider a trade-off, it provides two methods for obtaining memory data from remote hosts: self paging and proxy paging. We have implemented VMemTrans in KVM and compared the execution performance between the two methods.

The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avoid many difficult bugs down the line. This paper proposes a novel approach called Cash to the array bound checking problem that exploits the segmentation feature in the virtual memory hardware of the X86 architecture. The Cash approach allocates a separate segment to each static array or dynamically allocated buffer, and generates the instructions for array references in such a way that the segment limit check in X86's virtual memory protection mechanism performs the necessary array bound checking for free. In those cases that hardware bound checking is not possible, it falls back to software bound checking. As a result, Cash does not need to pay per-reference software checking overhead in most cases. However, the Cash approach incurs a fixed setup overhead for each use of an array, which may involve multiple array references. The existence of this overhead requires compiler writers to judiciously apply the proposed technique to minimize the performance cost of array bound checking. This paper presents the detailed design and implementation of the Cash compiler, and a comprehensive evaluation of various performance tradeoffs associated with the proposed array bound checking technique. For the set of complicated network applications we tested, including Apache, Sendmail, Bind, etc., the latency penalty of Cash's bound checking mechanism is between 2.5% to 9.8% when compared with the baseline case that does not perform any bound checking.

The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avoid many difficult bugs down the line. This paper proposes a novel approach called Cash to the array bound checking problem that exploits the segmentation feature in the virtual memory hardware of the X86 architecture. The Cash approach allocates a separate segment to each static array or dynamically allocated buffer, and generates the instructions for array references in such a way that the segment limit check in X86's virtual memory protection mechanism performs the necessary array bound checking for free. In those cases that hardware bound checking is not possible, it falls back to software bound checking. As a result, Cash does not need to pay per-reference software checking overhead in most cases. However, the Cash approach incurs a fixed setup overhead for each use of an array, which may involve multiple array references. The existence of this overhead requires compiler writers to judiciously apply the proposed technique to minimize the performance cost of array bound checking. This paper presents the detailed design and implementation of the Cash compiler, and a comprehensive evaluation of various performance tradeoffs associated with the proposed array bound checking technique. For the set of complicated network applications we tested, including Apache, Sendmail, Bind, etc., the latency penalty of Cash's bound checking mechanism is between 2.5% to 9.8% when compared with the baseline case that does not perform any bound checking.

Considerable research and development has been invested in software Distributed Shared Memory (DSM). The primary focus of this work has traditionally been on high performance and consistency protocols. Unfortunately, clusters present a number of challenges for any DSM systems not solvable through consistency protocols alone. These challenges relate to the ability of DSM systems to adjust to load fluctuations, computers being added/removed from the cluster, to deal with faults, and the ability to use DSM objects larger than the available physical memory. This paper introduces the Synergy DSM System and its integration with the virtual memory, group communication and process migration services of the Genesis Cluster Operating System.

Shared last-level caches, widely used in chip-multiprocessors (CMPs), face two fundamental limitations. First, the latency and energy of shared caches degrade as the system scales up. Second, when multiple workloads share the CMP, they suffer from interference in shared cache accesses. Unfortunately, prior research addressing one issue either ignores or worsens the other: NUCA techniques reduce access latency but are prone to hotspots and interference, and cache partitioning techniques only provide isolation but do not reduce access latency. We present Jigsaw, a technique that jointly addresses the scalability and interference problems of shared caches. Hardware lets software define shares, collections of cache bank partitions that act as virtual caches, and map data to shares. Shares give software full control over both data placement and capacity allocation. Jigsaw implements efficient hardware support for share management, monitoring, and adaptation. We propose novel resource-management algorithms and use them to develop a system-level runtime that leverages Jigsaw to both maximize cache utilization and place data close to where it is used. We evaluate Jigsaw using extensive simulations of 16-and 64core tiled CMPs. Jigsaw improves performance by up to 2.2× (18% avg) over a conventional shared cache, and significantly outperforms state-of-the-art NUCA and partitioning techniques.

Considerable research and development has been invested in software Distributed Shared Memory (DSM). The primary focus of this work has traditionally been on high performance and consistency protocols. Unfortunately, clusters present a number of challenges for any DSM systems not solvable through consistency protocols alone. These challenges relate to the ability of DSM systems to adjust to load fluctuations, computers being added/removed from the cluster, to deal with faults, and the ability to use DSM objects larger than the available physical memory. This paper introduces the Synergy DSM System and its integration with the virtual memory, group communication and process migration services of the Genesis Cluster Operating System.

Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processor [6, 5]. Tarantula adds to the EV8 core a vector unit capable of 32 double-precision flops per cycle. The vector unit fetches data directly from a 16 MByte second level cache with a peak bandwidth of sixty four 64-bit values per cycle. The whole chip is backed by a memory controller capable of delivering over 64 GBytes/s of raw band- width. Tarantula extends the Alpha ISA with new vector instructions that operate on new architectural state. Salient features of the architecture and implementation are: (1) it fully integrates into a virtual-memory cache-coherent system without changes to its coherency protocol, (2) provides high bandwidth for non-unit stride memory accesses, (3) supports gather/scatter instructions efficiently, (4) fully integrates with the EV8 core with a narrow, streamlined interface, rather...

An increasing number of architectures provide virtual memory support through software-managed TLBs. However, software management can impose considerable penalties that are highly dependent on the operating system's structure and its use of virtual memory. This work explores software-managed TLB design tradeoffs and their interaction with a range of monolithic and microkernel operating systems. Through hardware monitoring and simulation, we explore TLB performance for benchmarks running on a MIPS R2000-based workstation running Ultrix, OSF/1, and three versions of Mach 3.0.

Hardware Transactional Memory (HTM) gives software developers the opportunity to write parallel programs more easily compared to any previous programming method, and yields better performance than most previous lock-based synchronizations. Current implementations of HTM perform very well with small transactions. But when a transaction overows the cache, these implementations either abort the transaction as unsuitable for HTM, and let software takeover, or revert to some much more inecient hash-like in-memory structure, usually located in the userspace. We present a fast, scalable solution that has virtually no limit on transaction size, has low transactional read and write overhead, works with physical addresses, and doesn't require any changes inside the cache subsystem. This paper presents an HTMOS-Operating System (OS) and Architecture modications that leverage the existing OS Virtual Memory mechanisms, to support unbounded transaction sizes, and provide transaction execution speed that does not decrease when transaction grows.

This paper proposes a collaborative approach in which applications can provide guidance to the operating system regarding allocation and recycling of physical memory. The operating system incorporates this guidance to decide which physical page should be used to back a particular virtual page. The key intuition behind this approach is that application software, as a generator of memory accesses, is best equipped to inform the operating system about the relative access rates and overlapping patterns of usage of its own address space. It is also capable of steering its own algorithms in order to keep its dynamic memory footprint under check when there is a need to reduce power or to contain the spillover effects from bursts in demand. Application software, working cooperatively with the operating system, can therefore help the latter schedule memory more effectively and efficiently than when the operating system is forced to act alone without such guidance. It is particularly difficul...

Fig. 1. Interactive level-set segmentation of a brain tumor from a 256 × 256 × 198 MRI with volume rendering to give context to the segmented surface. A clipping plane shows the user the source data, the volume rendering, and the segmentation simultaneously. The segmentation and volume rendering parameters are set by the user probing data values on the clipping plane.

With the development of parallel computing, distributed computing, grid computing, a new computing model appeared. The concept of computing comes from grid, public computing and SaaS. The vision of cloud computing is to reduce the cost of ...

This paper describes Grasshopper, an operating system designed to provide generic mechanisms capable of being tailored to support a wide range of persistence paradigms. A constraint placed on this design is that the system must be implementable on conventional architectures which support paged virtual memory. In this paper the basic system abstractions relating to addressing environments, processes, and protection are described. It is shown that these provide explicit support for distributed persistent objects and processes, stability, and access control. At the same time the system provides the flexibility to allow user implementation of alternate object management techniques.

The Grasshopper operating system provides a flexible environment for conducting research into orthogonal persistence. In particular, it allows user-level software to perform memory management so that new techniques may be investigated without having to modify or even reboot the kernel. We describe the facilities provided to support this and show how they are used by both the kernel and user-level software.

The Grasshopper operating system provides explicit support for orthogonal persistence. A consequence of this is that the kernel itself must, in part, be persistent. To conform to the model of persistence in Grasshopper, the kernel persistent store must provide a means to stabilise entities independently of each other and must also be able to maintain an arbitrary number of versions for each entity. The design of the kernel persistent store is constrained by the need to be very efficient and to intrude as little as possible on the code using the store. Entities in the store reside at fixed, unique virtual addresses by which they are identified. This allows standard demand paging techniques are used making the store efficient and unobtrusive. Rather than provide for the independent stabilisation of individual data structures, the store provides regions, which are variable-size sets of possibly noncontiguous virtual pages, that may be stabilised independent of each other and that may have many versions. These regions, called persistent arenas, are used by higher-level software as pools for the allocation of smaller data structures that must logically be stabilised together.

In this paper we describe a new persistent distributed operating system. The Grasshopper system is designed to allow flexibility in the way in which persistence is provided. A key element of this flexibility is concerned with issues of global consistency. The Grasshopper kernels ...

Software Distributed Shared Memory (S-DSM) systems support parallel programming by implementing a shared memory on top of distributed system. It frees programmer from communication complexities to concentrate to parallel algorithms. However, there is a drawback: current S-DSM systems waist memory on all processors. Therefore it is hard to be implemented to embedded systems, which have small resources e.g. memory. In this project, we modified an implemented S-DSM system named CVM-Coherent Virtual Machine-to support an embedded system and investigate memory consumed, in order to implement an S-DSM system supports embedded systems. The results shows that with a good selection of initial values for an S-DSM system and carefully programmed, S-DSM system can be implemented for embedded system with less memory overhead and high speedup.

Software Distributed Shared Memory (S-DSM) systems support parallel programming by implementing a shared memory on top of distributed system. It frees programmer from communication complexities to concentrate to parallel algorithms. However, there is a drawback: current S-DSM systems waist memory on all processors. Therefore it is hard to be implemented to embedded systems, which have small resources e.g. memory. In this project, we modified an implemented S-DSM system named CVM-Coherent Virtual Machine-to support an embedded system and investigate memory consumed, in order to implement an S-DSM system supports embedded systems. The results shows that with a good selection of initial values for an S-DSM system and carefully programmed, S-DSM system can be implemented for embedded system with less memory overhead and high speedup.

The difficulty of developing reliable parallel software is generating interest in deterministic environments, where a given program and input can yield only one possible result. Languages or type systems can enforce determinism in new code, and runtime systems can impose synthetic schedules on legacy parallel code. To parallelize existing serial code, however, we would like a programming model that is naturally deterministic without language restrictions or artificial scheduling. We propose deterministic consistency, a parallel programming model as easy to understand as the "parallel assignment" construct in sequential languages such as Perl and JavaScript, where concurrent threads always read their inputs before writing shared outputs. DC supports common data-and task-parallel synchronization abstractions such as fork/join and barriers, as well as non-hierarchical structures such as producer/consumer pipelines and futures. A preliminary prototype suggests that softwareonly implementations of DC can run applications written for popular parallel environments such as OpenMP with low (< 10%) overhead for some applications.

Virtual time is a new paradigm for organizing and synchronizing distributed systems which can be applied to such problems as distributed discrete event simulation and distributed database concurrency control. Virtual time provides a flexible abstraction of real time in much the same way that virtual memory provides an abstraction of real memory. It is implemented using the Time Warp mechanism, a synchronization protocol distinguished by its reliance on lookahead-rollback, and by its implementation of rollback via antimessages.

In this paper, we present a system for augmenting virtual AI characters with long-term memory, enabling them to remember facts about themselves, their world, and past experiences. We propose a memory-creation pipeline that converts raw text into condensed memories and a memory-retrieval system that utilizes these memories to generate character responses. Using a fact-checking pipeline based on GPT-4 (OpenAI), our evaluation demonstrates that the character responses are grounded in the retrieved memories and maintain factual accuracy. We discuss the implications of our system for creating engaging and consistent virtual characters and highlight areas for future research, including large language model (LLM) guardrailing and virtual character personality development.

In this paper, we evaluate an implementation of a multicache-level prefetching system under the 3rd Data Prefetching Championship framework. Our approach is based on enhancing a baseline prefetcher, Signature Path Prefetching (SPP) with a new, perceptron-based scheme of prefetch filtering. The key idea here being that by de-constraining/dethrottling the underlying prefetcher we can achieve high coverage, while using the perceptron prefetch filter to ensure high accuracy. Our evaluation on the memory intensive traces of SPEC CPU 2017 suite shows that this approach enhances the IPC of the system by 40.4% over no prefetching for a single-core configuration and by 20.3% for a four-core configuration. On the system, the winner of DPC-2 achieves the resultant speedup of 28.4% and 15.1% in single-core and four-core systems respectively.

The monitoring of virtual machines has many applications in areas such as security and systems management. A monitoring technique known as introspection has received significant discussion in the research literature, but these prior works have focused on the applications of introspection rather than how to properly build a monitoring architecture. In this paper we propose a set of requirements that should guide the development of virtual machine monitoring solutions. To illustrate the viability of these requirements, we describe the design of XenAccess, a monitoring library for operating systems running on Xen. XenAccess incorporates virtual memory introspection and virtual disk monitoring capabilities, allowing monitor applications to safely and efficiently access the memory state and disk activity of a target operating system. XenAccess' efficiency and functionality are illustrated through a series of performance tests and practical examples.

In this paper we introduce a generic teleeducation system, referred to as COSTE (COmputer Science Teleeducation Environment), to cover the distance between teaching staff and students. COSTE is an open environment which adds to the usual online courses, flexibility to define and follow them, student training with practical components, queries to the teacher, semiautomatic assessment and an automatic validation mechanism. COSTE has a client-server architecture, where the communication scheme uses the HTTP protocol with WWW browsers as clients. The current implementation efforts are directed toward the Operating Systems teaching. In this field, we provide practical units for training in CPU scheduling discilines, virtual memory management and concurrent systems programming. In this paper we will also review the results of teleeducation experiences with COSTE. Our theoretical-practical learning methodology has three different levels: an introductory course, a mid-level course, and an advanced course. The students could select the level most suitable for their knowledge, as well as draw up a syllabus on demand according to their interest. This kinds of courses need a dynamic assessment system depending on how the student is taking the course. COSTE defines a system based on hierarchical assessment units: courses, subjects and sections. Whenever students pass all the units in a level the system allows the assessment of the higher one. The assessment system allows that different units can share lower units. According to these issues we have defined a validation system so students can progress with their courses without repeating these shared units. The validation system and the hierarchical structure of a course are defined by the teacher in charge. Although students are able to select their courses and access to the contents in a no linear way, teachers can define key units with the aim of imposing an assessment order. In this way COSTE does not allow the assessment of a unit if a student has not previously passed all the corresponding key units. However, students are free to visit whatever units they want. Each unit has an assessment set which is made up of optional questions about the contents of the unit, whose answers are available on request, and mandatory questions to assess the gained knowledge of the unit by students. In order to prevent students from passing an exam by trying it constantly, COSTE offer two control mechanisms: the exam, which is based on multiple-choice questions, is set up randomly every time with a temporal stamp so tests have an expiry date. students cannot repeat the assessment of a unit immediately,

Smartphones have become essential part of our daily life. These devices now a days are not just communicative device but a powerful computer. Using these devices a large number of computationally intensive tasks can be executed with ease which were not possible. These samrtphones uses ARM (Advanced Risk Machines) based processor, which provides reasonable energy efficiency and computational power. As the smartphones are battery powered devices, energy efficiency remains a key concern and is a serious challenge for the designers. In this research paper a novel hardware architecture has been proposed which alongside increasing computational power will provide huge energy savings. The architecture leverages the problem of dark silicon to provide an energy efficient solution for the samrtphones.

The Mneme project is an investigation of techniques for integrating programming language and database features to provide better support for cooperative, information-intensive tasks such as computer-aided software engineering. The project strategy is to implement efficient, distributed, persistent programming languages. We report here on the Mneme persistent object store, a fundamental component of the project, discussing its design and initial prototype. Mneme storesobjectsin a simple and general format, preserving object identity and object interrelationships. Specific goals for the store include portability, extensibility (especially with respect to object management policies), and performance. The model of memory that the store aims at is a single, cooperatively-shared heap, distributed across a collection of networked computers. The initial prototype is intended mainly to explore performance issues and to support object-oriented persistent programming languages. We include perf...