VHDL implementation

A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. This paper presents the performance analysis of vedic multiplier such as Urdhva Tiryakbhyam and Anurupye. Since high speed 8-point Vedic multiplier architecture is quite different from the conventional method of multiplication like add and shift. The most significant aspect is that, the developed Anurupye multiplier architecture is based on proportionality, i.e Select a theoretical base which is common to both numbers and then take a proportional base to the theoretical base as acting as the working base. So the design complexity gets reduced for inputs of larger number of bits and modularity gets increased. The proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using vivado 14.1. Finally the Anurupye results are compared with Urdhava Tiryakbhyam and array multiplier to show the significant improvement in its efficiency in terms of path delay (speed) and power. The high speed processor requires high speed multipliers and the Vedic Multiplication technique is very much suitable for this purpose

Technological advancement in the hardware implementation has made it possible to add various features. Arithmetic Logic Unit, (ALU) is a simple and versatile block required in all the processors. Mostly implementation of this is not taken care for processing and not for optimization. In this paper implementation is thought of experimentation for arithmetic and logical operations. The results found are far better as compared to previous ALU. High speed and area efficient arithmetic multiplier architecture plays a vital role in Arithmetic Logic Unit (ALU) design, especially when it comes to low power implementation of Central Processing Units, Microprocessors and Microcontrollers. This work proposes a novel approach, area efficient and high speed architecture to implement a Vedic mathematics based AL unit which is based on Vedic Sutra's. The ALU obtained is compared for its performance with present ALU. It was found that the proposed methodology is faster than the existing ALU alo...

This paper presents power and area analysis of two-stage comb-based decimation structures for high decimation factors. The first stage is either in a recursive form cascaded-integrator-comb (CIC) or in a non-recursive form, while the second stage is in a recursive form. The proposed structures are compared with a single CIC structure. We demonstrated how to choose the decimation factor of the first stage in order to get simultaneously the highest possible power reduction and the lowest possible area increase, in a comparison with a single CIC structure. Additionally, the modified two-stage structure with an increased attenuation and a reduced power consumption is presented. Analysis is supported by MATLAB simulations and validated by the VHDL implementations.

Technological advancement in the hardware implementation has made it possible to add various features. Arithmetic Logic Unit, (ALU) is a simple and versatile block required in all the processors. Mostly implementation of this is not taken care for processing and not for optimization. In this paper implementation is thought of experimentation for arithmetic and logical operations. The results found are far better as compared to previous ALU. High speed and area efficient arithmetic multiplier architecture plays a vital role in Arithmetic Logic Unit (ALU) design, especially when it comes to low power implementation of Central Processing Units, Microprocessors and Microcontrollers. This work proposes a novel approach, area efficient and high speed architecture to implement a Vedic mathematics based AL unit which is based on Vedic Sutra's. The ALU obtained is compared for its performance with present ALU. It was found that the proposed methodology is faster than the existing ALU alo...

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.

Vedic mathematics is the ancient Indian system of mathematics. This paper proposed the design oh high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that has been modified to improve performance. Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. In this paper it is used for designing a high speed, low power 4X4 multiplier. In the proposed design we have reduced the number of logic levels, thus reducing the logic delay. The proposed system is design using VHDL and it is implemented through Xilinx 8.1.

Convolutional encoding with Viterbi decoding is a powerful method in many communication systems due to the excellent error control performance. The Convolutional encoder encodes the message and then the encoded bits are generated. The bits which are encoded are again sent to the Viterbi Decoder and then the decoded output is obtained. This paper targets the Design of convolutional encoder using vedic mathematics and viterbi decoder using parallel processing. In mathematics, multiplication is the most commonly used operation. Hence, vedic multiplier is used in convolutional encoder. This algorithm follows a fast multiplication process and achieves a significantly less computational complexity over its conventional multipliers. In viterbi decoder, branch metric unit and add compare select unit are designed and pipeline and parallel processing concept is used to improve processing time and save memory space. Pipeline and parallel process performs more than one operation in the given period i.e. more than one input is given to the convolutional encoder and get more than one output at viterbi decoder. The simulation and synthesis of proposed design are done through XILINX 14.5i ISE Simulator tool and coding is in VHDL. It is observed that the proposed work is better in delay (processing time) than their counterparts.

This paper describes that multiply and accumulate (MAC) unit plays a very vital role in various Digital Signal Processing applications. Speed of these applications depends on the speed of these three sub units of MAC multiply unit, adder unit and accumulator unit. In this paper the delay of 64-bit MAC unit is decreased as compared to the previous MAC units. In this Kogge Stone Adder is used as adder in design Vedic Multiplier using Urdhva Tiryakbhyam sutra. The designing of MAC unit is done under VIRTEX-4 family, XC4VFX140 device, FF1517 package and-11 speed and comparison of proposed MAC unit design is done under SPARTAN-3E family, XC3S500 device, FG320 package and-5 speed in Xilinx ISE 8.1i. The combinational path delay of the 64-bit MAC unit is 59.705ns in SPARTAN-3E family. Ancient Indian mathematics is being used for designing of multiplier unit to decrease the overall delay of the MAC unit.

In this work VHDL implementation of complex number multiplier using ancient Vedic mathematics is presented, also the FPGA implementation of 4-bit complex multiplier using Vedic sutra is done on SPARTAN 3 FPGA kit. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay. The simulation results for 4-bit, 8-bit, 16-bit and 32 bit complex number multiplication using Vedic sutra are illustrated. The results show that Urdhva Tiryakbhyam sutra with less number of bits may be used to implement multiplier efficiently in signal processing algorithms.

In this work VHDL implementation of complex number multiplier using ancient Vedic mathematics is presented, also the FPGA implementation of 4-bit complex multiplier using Vedic sutra is done on SPARTAN 3 FPGA kit. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay. The simulation results for 4-bit, 8-bit, 16-bit and 32 bit complex number multiplication using Vedic sutra are illustrated. The results show that Urdhva Tiryakbhyam sutra with less number of bits may be used to implement multiplier efficiently in signal processing algorithms.

In digital signal processing convolution is a fundamental computation that is ubiquitous in many application areas. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) methods are employed. In this paper, block convolution process is proposed using a multiplier architecture based on vertical and crosswise algorithm of Ancient Indian Vedic Mathematics and embedding it in OLA method for reducing calculations.And as the vedic multiplier is been used it is named as Vedic convolution algorithm.The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) for the FPGA , as it is being increasingly used for variety of computationally intensive applications.Simulation and synthesis is done using Xilinx.