Timing Analysis

In this paper, it is presented the simulation analysis of an enhanced algorithm for the collision resolution in shared Ethernet networks. Such algorithm, referred as high priority Binary Exponential Backoff (h-BEB), provides high priority traffic separation, enabling the support of real-time communications. One of the main features of the h-BEB algorithm is to enable the coexistence in the same network segment of Ethernet standard stations with h-BEB modified stations, by imposing higher priority for the transfer of h-BEB messages (privileged traffic). The simulation analysis shows that the proposed traffic separation guarantees a predictable and significantly smaller access delay for the h-BEB station, when compared with the access delay for standard Ethernet stations. The simulation analysis also shows that the h-BEB traffic must be tightly controlled, as it has a high interference level over the nonreal-time traffic. Otherwise, if the load generated by the h-BEB station is not closely controlled, the standard Ethernet stations may experience extended access delays.

An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.

Due to excessive reduction in the gate length, dopant concentrationsand the oxide thickness, even the slightest of variations inthese quantities can result in significant variations in the performanceof a device. This has resulted in a need for efficient andaccurate techniques for performing Statistical Analysis of circuits.In this paper we propose a methodology based on Bayesian Networksfor computing the exact probability

This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400× compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.

The inductance and coupling effects in interconnects and non-linear receiver loads has resulted in complex input signals and output loads for gates in the modern deep submicron CMOS technologies. As a result, the conventional method of timing characterization, which is based on lookup tables with input slew and output load capacitance as indices, is no longer adequate. The focus has now shifted to current source based standard cell models which are based on the fundamental property of transconductance of MOSFETs. In this paper 1 we propose a systematic methodology for obtaining a current based delay model for gates, which can accommodate both single (SIS) and multi-input (MIS) switching signals of arbitrary shape and complex non-linear output loads. We use an analytical model for the gate output current expressed as a function of the node voltages. This results in an average error less than 0.5% with maximum standard deviation of 2.5% in error when compared with SPICE for a large number of standard cells. When compared with SPICE, using the proposed models gives stage delay and output slew with an average error of less than 3% and 2% respectively for arbitrary inputs and output load combinations.

The Mars Approach ost computer systems for real-time process control must meet high standards of reliability, availability, and safety. In many of these real-time applications, the costs of a catastrophic system failure can exceed the initial investment in the computer and the controlled object. To prevent such failures, system design must guarantee performance as specified in the domains of both value and time during all anticipated operational situations. The computer system must also be designed to tolerate faults caused by environmental disturbances or a physical degradation of the hardware. Distributed computer-system architectures have gained general acceptance in the area of real-time process control. These architectures offer a significant potential for fault tolerance and functional degradation as well as for testability and extensibility. However, many of the distributed computer-system architectures presently on the market or proposed by the research community as academic prototypes (the V-Kernel,* A c ~e n t , ~ or Chorus4) do not support some key points that are essential to reliable control of real-time applications. These points are limited time validity of real-time data, predictable performance under peak load, fault tolerance, and maintainability and extensibility. Consequently, we developed the Maintainable Real-Time System, a fault-tolerant distributed system for process control. The Mars project started in 1980 at the Technische Universitat Berlin. The first prototype appeared in 1984 and demonstrated the fundamental concepts of Mars. The second academic prototype developed at the Technische Universitat Wien in Vienna has been functional since the beginning of 1988. Its main feature is predictable performance under a specified peak load. Its industrial applications include rolling mills and railway-control systems in which the controlled system imposes hard deadlines. This article presents the Mars approach to real-time process control, its architectural design and implementation, and one of its applications. But first, let's explore the characteristics of distributed real-time systems as background to this discussion. Rea It i me process control has to be timely and has to be right. Here's how one system promotes these features through a number of key functions.

The maximum flow algorithm is distinguished by the long line of successive contributions researchers have made in obtaining algorithms with incrementally better worst-case complexity. Some, but not all, of these theoretical improvements have produced improvements in practice. The purpose of this paper is to test some of the major algorithmic ideas developed in the recent years and to assess their utility on the empirical front. However, our study differs from previous studies in several ways. Whereas previous studies focus primarily on CPU time analysis, our analysis goes further and provides detailed insight into algorithmic behavior. It not only observes how algorithms behave but also tries to explain why algorithms behave that way. We have limited our study to the best previous maximum flow algorithms and some of the recent algorithms that are likely to be efficient in practice. Our study encompasses ten maximum flow algorithms and five classes of networks. The augmenting path algorithms tested by us include Dinic's algorithm, the shortest augmenting path algorithm, and the capacity scaling algorithm. The preflow-push algorithms tested by us include Karzanov's algorithm, three implementations of Goldberg-Tarjan algorithm, and three versions of Ahuja-Orlin-Tarjan excess-scaling algorithms. Among many findings, our study concludes that the preflow-push algorithms are substantially faster than other classes of algorithms, and the highest-label preflow-push algorithm is the fastest maximum flow algorithm for which the growth rate in the computational time is O(n 1 5) on four out of five of our problem classes. Further, in contrast to the results of the worst-case analysis of maximum flow algorithms, our study finds that the time to perform relabel operations (or constructing the layered networks) takes at least as much computation time as that taken by augmentations and/or pushes.

Real-time systems are being used increasingly in control applications such as in automobiles, aircraft and process control. Real-time communication protocols are designed in order to satisfy basic requirements of these systems such as reliability, safety and in time message delivery. One of the most important requirements of such critical systems is in time update of real-time data which has to be facilitated by these protocols. CAN (Controller Area Network) [1] is one of the important and common protocols which is widely used in such an environment. RDM (Round Data Mailer) [2] and RDM+ are two new protocols that have been designed to fulfill the requirements of distributed real-time systems. In this paper, we are trying to compare RDM+ and CAN protocols based on data lifetime which is the time interval between two consecutive updates of a real-time datum. The obtained results show that RDM+ performs better and provides fresher data to the consumers.

Failure of a safety-critical application on an embedded processor can lead to severe damage or even loss of life. Here we are concerned with two kinds of failure: stack overflow, which usually leads to runtime errors that are difficult to diagnose, and failure to ...

Increased outsourcing of logistical services by manufacturers has prompted reconsideration of traditional relationships between manufacturers and third party logistics firms. Firms are moving away from single transaction business arrangements and forming cooperative relationships with third party providers characterized by cooperative transactions occurring over time. Analysis of data collected from a random sample of manufacturing executives identifies operating conditions in the manufacturers' operating and strategic environment that are best suited for cooperative relationship formation in an international logistics setting.

"How to predict crime?" is an important question. But to understand the notions developed by ethnography, entrepreneurships, and timing theories, and to prove they were efficient, it is no enough. To see the future drives the policies and policymakers into a most-of-the-time undesirable situation. In general it is no true that policymakers and entrepreneurs want to believe in the prospections, which it makes very difficult prevention. However, the author develops the "three clocks theory", which is a central issue on the ability of prospection.

True critical path identification is still an issue of relevant importance in the physical design of CMOS VLSI circuits. Although delay enumeration-based timing analysis methods are independent of the number of long false paths, they are not able to identify the true critical paths of a combinational block. Hence, path enumeration-based timing analysis must be used. In this paper we present a new heuristic for ordering the objectives that need to be satisfied for declaring a path as sensitizable. The new heuristic is compared to the commonly used one, which relies on following the logical depth of the circuit. The practical results showed that the proposed heuristic tends to provide better results.

Recibido: marzo de 2014 Aceptado: septiembre de 2014 varieties 12, 15, 22, 23 and 24 with positive expression in ear weight, pods per plant, test weight and late to male and female flowering period. The stability analysis to identify yield varieties 2, 3, 6 and 22 as stable varieties but, with low yield except the variety 22 which yielded 6.4 t ha -1 and was statistically similar to the control H-139, which was selected by favourably presenting characters of plant, ear, grain yield and yield stability. The varieties 13, 20, 23 and the hybrid H-139 of high-yield, interaction with good productivity locations.

В статье рассматривается методология, технические средства и цели комплексного исследования поведения посетителя музея при помощи современных технических методов: айтрекинга (изучение точки взора) и трекинга (отслеживание перемещений). Ключевые слова: исследование посетителей, айтрекинг, окулография, тайминг и трекинг, indoor навигация, наблюдение за посетителем, исследование поведения посетителей музея

We present a new method for removing user-specified false subgraphs from timing analysis and circuit optimization. Given a timing graph and a list of specified false paths, false subpaths, or false subgraphs, we generate a new timing graph in which all specified false paths are removed using a process of node splitting and edge removal. We present the necessary and sufficient condition for splitting a node, and show that the number of nodes that must be added to the timing graph is linear with the size of the false path specification. We also present an algorithm for finding the minimum set of nodes that must be split. Since this algorithm requires exponential run time for false subpaths and false subgraphs, we present a heuristic splitting approach which has linear worst-case run time, and where the number of added nodes is linear with the size of the false path specification. The heuristic approach was implemented and results are given for large industrial circuits.

This paper presents a design methodology emphasizing early and quick timing closure for high frequency microprocessor designs. This methodology was used to design a Gigahertz class PowerPC microprocessor with 19 million transistors. Characteristics of "Timing Closure by Design" are 1) logic partitioned on timing boundaries, 2) predictable control structures (PLAs), 3) static interfaces for dynamic circuits, 4) low skew clock distribution, 5) deterministic method of macro placement, 6) simplified timing analysis, and 7) refinement method of chip integration with early timing analysis.

Often repositories of systems engineering artifacts at NASA's Jet Propulsion Laboratory (JPL) are so large and poorly structured that they have outgrown our capability to effectively manually process their contents to extract useful information. Sophisticated text mining methods and tools seem a quick, low-effort approach to automating our limited manual efforts. Our experiences of exploring such methods mainly in three areas including historical risk analysis, defect identification based on requirements analysis, and over-time analysis of system anomalies at JPL, have shown that obtaining useful results requires substantial unanticipated efforts -from preprocessing the data to transforming the output for practical applications. We have not observed any quick "wins" or realized benefit from short-term effort avoidance through automation in this area. Surprisingly we have realized a number of unexpected long-term benefits from the process of applying text mining to our repositories. This paper elaborates some of these benefits and our important lessons learned from the process of preparing and applying text mining to large unstructured system artifacts at JPL aiming to benefit future TM applications in similar problem domains and also in hope for being extended to broader areas of applications.

The network system of data exchange between the various components is an inherent element of every car. Because of the specific and different requirements for data transfer between specific devices, currently used communication protocols have different properties of performance, security, and degree of determinism. The paper presents the increasing complexity of the data exchange system based on the example of the latest requirements for digital tachographs. The article describes also the data transmission initialization methods in the context of network data exchange organization. The hybrid use of time triggering and event triggering mechanisms has been presented in relation to the operation of the CAN network under increased real-time conditions requirements implemented as TTCAN (time triggered CAN).

Unlike most olher logic programming languages, Concurrem Prolog s) does not include a sequential-AND operator to enforce serial goal (process) reduction. However, sequential process reduction is stiff possible using existing constructs. In a number of published programming examples it is achieved with the "'commit" operator. Such programs may not execute as described, but instead encounter deadlock. In this paper several examples of this are presented, the cause of the problem is diagnosed, and a solution suggested. This paper also deals with sequential process reduction in more general terms. The methods available to achieve serialization involving commit and readonly variable references are analyzed and compared. The potential for incorporat ing sequential-AND into the language is also addressed.

Reducing access times to secondary I/O devices has long been the focus of many systems researchers. With traditional disk drives, access time is the composition of seek time and rotational latency, and so many techniques to order I/O requests or place data to minimize these factors have been developed. MEMS-based storage devices are seen by many as a replacement or an augmentation for modern disk drives, but algorithms for reducing access time for MEMS-based devices are still poorly understood. These devices, based on MicroElectroMechanical systems (MEMS), use thousands of active read/write heads working in parallel on a two-dimensional non-rotating magnetic substrate, eliminating rotational latency variable from the access time equation. This leaves seek time as the dominant variable. Therefore, new data layout techniques based on minimizing the unique seek time characteristics of a MEMS-based storage device must be developed. This paper examines the qualities of a MEMS-based storage device, and based on experimental simulation, develops an understanding of the seek time characteristics on such a device. These characteristics then allow us to identify equivalent regions in which to place data for improved access.

This paper presents an evaluation of a new analysis for parallelizing compilers called predicated array data-flow analysis . This analysis extends array data-flow analysis for parallelization and privatization to associate predicates with data-flow values. These predicates can be used to derive conditions under which dependences can be eliminated or privatization is possible. These conditions can be used both to enhance compile-time analysis and to introduce run-time tests that guard safe execution of a parallelized version of a computation.As compared to previous work that combines predicates with array data-flow analysis, our approach is distinguished by two features: (1) it derives low-cost, run-time parallelization tests; and, (2) it incorporates predicate embedding and predicate extraction , which translate between the domain of predicates and data-flow values to derive more precise analysis results. We present extensive experimental results across three benchmark suites and on...

This paper presents an evaluation of a new analysis for parallelizing compilers called predicated array data-flow analysis . This analysis extends array data-flow analysis for parallelization and privatization to associate predicates with data-flow values. These predicates can be used to derive conditions under which dependences can be eliminated or privatization is possible. These conditions can be used both to enhance compile-time analysis and to introduce run-time tests that guard safe execution of a parallelized version of a computation.As compared to previous work that combines predicates with array data-flow analysis, our approach is distinguished by two features: (1) it derives low-cost, run-time parallelization tests; and, (2) it incorporates predicate embedding and predicate extraction , which translate between the domain of predicates and data-flow values to derive more precise analysis results. We present extensive experimental results across three benchmark suites and on...

This paper presents a new analysis for parallelizing compilers called predicated array data-flow analysis, whereby array dataflow analysis for parallelization and privatization is extended to associate predicates with data-flow values. These predicates can be used to derive conditions under which dependences can be eliminated or privatization is possible. These conditions, which can consist of arbitrary program statements, can be used both to enhance compile-time analysis and to introduce run-time tests that guard safe execution of a parallelized version of a computation. We have implemented predicated array data-llow analysis in the Stanford SUIF compiler. We describe features of the implementation and present experimental results that demonstrate this analysis improves the performance of three programs from the SPECgSFP benchmark suite. Derives low-cost run-time tests. It enables optimizations that cannot be proven safe at compile time, either because safety is input dependent or simply because of limitations in compile-time analysis. The compiler transforms a code segment optimistically, producing multiple versions of a computation with each version's execution guarded by an inexpensive run-time test derived from analysis.

3DIC chiplet􀀃stacking is taking the industry by storm.
It provides huge benefits in terms of logic-to-memory connection
bandwidth expansion, power reduction, and manufacturing cost
reduction. However, it brings a number of new challenges that
have to be addressed to make 3DIC solutions successful. First, we
look at the bigger picture of diverse STCO factors that have to be
resolved, and then focus on the interplay of four effects that play a
key role in 3DIC designs: thermal, power, timing, and stress, and
show their interplay. Careful analysis and balance of all four major
factors are necessary to pull off a successful 3DIC solution.

We present a new timing verification methodology that was used successfully to verify the Digital 21264 Alpha microprocessor. The 21264 design team devised a minimally constrained, aggressive circuit design style with a complex clocking methodology [1] that demanded the creation of a versatile verification tool. We introduce a tool designed for minimum and maximum timing verification of critical and race paths on full-custom circuits. This tool employs sophisticated circuit classification algorithms, a large family of delay estimation techniques, and various path traversal strategies. First pass silicon of the 21264 microprocessor successfully ran multiple operating systems and no timing problems were identified.

In the present study, the potential of fungal cells (Aspergillus tubingensis KJ650338 and Aspergillus pseudonomius MH279416) immobilized on activated carbon (AC) derived from rice husks for biosorption of dye in a continuous flow-packed bed column, was assessed. The effects of different process parameters including inlet Congo red concentration, feed flow rate, biosorbent dose, and internal column diameter on the breakthrough curves of the fixed bed sorption system were evaluated for the different treatment groups. Non-linear forms of well-established models such as Yoon-Nelson, modified dose-response, and Thomas were used to describe the data obtained from the breakthrough curves under different conditions. The results suggested that high biosorbent dose (4 g), low column diameter (1.5 cm), low initial Congo red concentration (50 mg/ml), and reduced flow rate (0.5 ml/ min) were the best conditions for biosorption of Congo red from solution. The modified dose-response model had the best correlation with the obtained data (R 2 ¼ 0.920-0.995) compared with Thomas model (R 2 ¼ 0.645-0.982) and Yoon-Nelson (R 2 ¼ 0.731-0.982). The maximum absorptive capacity (66.15 mg/g) was predicted at using modified dose-response (R 2 ¼0.987). These findings show that the dead biomasses of Aspergillus pseudonomius and Aspergillus tubingensis immobilized on powdered AC derived from rice husk could be costeffective biosorbent for Congo red removal from aqueous solution in a fixed-bed column system.

We observed Her X-1 using the Ginga observatory in the spring of 1989 with the primary intention of studying the evolution of the pulse proÐle through the course of the 35 day X-ray HIGH-LOW cycle in that source. These observations cover 16 separate days in two MAIN HIGH states and in the intervening SHORT HIGH state. We have augmented these data with four additional Ginga observations of Her X-1 taken for other purposes but useful for our study. We present light curves in the 1È37 keV energy band for the seven high states covered by these data together with a representative sample of pulse proÐles. The signal-to-noise ratio for these proÐles is generally excellent, and collectively they provide a sound base for studying the evolution of the pulse proÐle. Of particular utility is the 1989 May observation, which for the Ðrst time provides extensive coverage of a short high state at high photon counting rate. By combining pulse phase and frequency information from all three high state observations in 1989, we are able to determine the phase alignment of main high and short high pulse proÐles with high con-Ðdence. We identify components in the Her X-1 pulse proÐle by their distinctive spectral signatures, and we establish the existence of a deÐnite, repetitive pattern of pulse shape variations tied to the 35 day high-low cycle. Comparing pre-Ginga observations of pulse proÐles superposed according to the 35 day phase indicates that this pattern has persisted over the past two decades. Moreover, the pulse phase alignment of the 1989 data allows the identiÐcation of components common to the main high and short high pulse proÐles. One of the key elements of this pattern is the rapid change in pulse proÐle that occurs roughly 7 days into each main high state. In examining possible mechanisms for this interval of accelerated evolution, we are led to consider a class of models that involve dynamical changes in accretion Ñow geometry arising from neutron star obliquity. These models, however, suggest asymmetries in the X-ray illumination of the companion star that may conÑict with extensive optical observations of the Her X-1 system. By contrast, kinematic changes in the geometrical aspect of obscuring matter Ñows near or within the magnetosphere that are tied to accretion disk precession provide a mechanism that may be consistent with observations.

This paper presents a new analysis for parallelizing compilers called predicated array data-flow analysis, whereby array dataflow analysis for parallelization and privatization is extended to associate predicates with data-flow values. These predicates can be used to derive conditions under which dependences can be eliminated or privatization is possible. These conditions, which can consist of arbitrary program statements, can be used both to enhance compile-time analysis and to introduce run-time tests that guard safe execution of a parallelized version of a computation. We have implemented predicated array data-llow analysis in the Stanford SUIF compiler. We describe features of the implementation and present experimental results that demonstrate this analysis improves the performance of three programs from the SPECgSFP benchmark suite.

The aim of this feasibility and proof-of-concept study was to examine the use of a novel wearable device for automatic food intake detection to capture the full range of free-living eating environments of adults with overweight and obesity. In this paper, we document eating environments of individuals that have not been thoroughly described previously in nutrition software as current practices rely on participant self-report and methods with limited eating environment options. Methods: Data from 25 participants and 116 total days (7 men, 18 women, M age = 44 ± 12 years, BMI 34.3 ± 5.2 kg/mm 2), who wore the passive capture device for at least 7 consecutive days (≥12h waking hours/d) were analyzed. Data were analyzed at the participant level and stratified amongst meal type into breakfast, lunch, dinner, and snack categories. Out of 116 days, 68.1% included breakfast, 71.5% included lunch, 82.8% included dinner, and 86.2% included at least one snack.

Traditionally, beryllium analysis of wipe, air and bulk samples has been conducted by laboratories using highly trained personnel and expensive capital equipment. In addition, such methods are labor intensive, particularly the steps involving sample preparation. Recently a new method to determine beryllium using optical fluorescence, which can be used in the field, has been introduced. This new method uses low-cost instrumentation and set up, is simple to use, and is non-destructible, as only a small fraction of the dissolved sample is analyzed. The new method has been used for wipes, air samples, and bulk samples such as soils, rocks, sediments and fly ash. Test methods based on this technology have been approved by National Institute of Occupational Safety and Health (NIOSH) and American Society of Testing Materials (ASTM). Laboratories can also be accredited by American Industrial Hygienists' Association (AIHA). The new method meets the analytical requirements to satisfy the Department of Energy requirements and also the proposed regulations by the American Conference of Government Industrial Hygienists (ACGIH). This method is particularly beneficial for field use where the results can be obtained within two hours, allowing a more efficient use of equipment and manpower. More recently, an automated system, which uses a 96 micro-well plate to analyze the wipe and air samples, has been introduced. The samples for analysis are prepared automatically and the samples are analyzed in a plate reader. This method results in a tremendous increase in productivity, and the plate with 96 samples is read in less than three minutes, where the conventional methods may take six to ten hours to analyze similar numbers of samples. The new method is particularly suitable for facilities that annually analyze in excess of 20,000 samples. The high throughput method meets the goals of increased productivity, while also meeting the standard analytical method guidelines and the detection sensitivity requirements to meet the Department of Energy and other regulations.

Continuous and hybrid Petri nets can be seen as relaxation of discrete nets, in which the firing of some or of all transitions is approximated with a fluid model. Several analysis techniques have been presented for studying these models, using either linear programming and incidence matrix analysis, or graph theory approaches. In this paper two of such approaches, one based on linear algebra and one based on graph theory, are used to compute the steady-state firing speed and steady-state marking of continuous weighted marked graphs.

Many embedded systems operate in multiple modes, where mode switches can be both time-as well as eventtriggered. While timing and schedulability analysis of the system when it is operating in a single mode has been well studied, it is always difficult to piece together the results from different modes in order to deduce the timing properties of a multi-mode system. As a result, often certain restrictive assumptions are made, e.g., restricting the time instants at which mode changes might occur. The problem becomes more complex when both time-and event-triggered mode changes are allowed. Further, for complex systems that cannot be described by traditional periodic/sporadic event models (i.e., where event streams are more complex/bursty) modeling multiple modes is largely an open problem. In this paper we propose a model and associated analysis techniques to describe embedded systems that process multiple bursty/complex event/data streams and in which mode changes are both timeand event-triggered. Compared to previous studies, our model is very general and can capture a wide variety of real-life systems. Our analysis techniques can be used to determine different performance metrics, such as the maximum fill-levels of different buffers and the delays suffered by the streams being processed by the system. The main novelty in our analysis lies in how we piece together results from the different modes in order to obtain performance metrics for the full system. Towards this, we propose both-exact, but computationally expensive, as well as safe approximation techniques. The utility of our model and analysis has been illustrated using a detailed smart-phone case study.

This paper introduces new notions of asymptotic proofs, PT(polynomial-time)-extensions, PTM(polynomial-time Turing machine)-omega-consistency, etc. on formal theories of arithmetic including PA (Peano Arithmetic). This paper shows that P not= NP (more generally, any super-polynomial-time lower bound in PSPACE) is unprovable in a PTM-omega-consistent theory T, where T is a consistent PT-extension of PA. This result gives a unified view to the existing two major negative results on proving P not= NP, Natural Proofs and relativizable proofs, through the two manners of characterization of PTM-omega-consistency. We also show that the PTM-omega-consistency of T cannot be proven in any PTM-omega-consistent theory S, where S is a consistent PT-extension of T.

The use of such plastic inserts and other soft fastening solutions in pre-stressed concrete sleepers and crossing bearers has become widespread within the UK, Europe and the rest of the world. The stiffness of these inserts is typically an order of magnitude lower than that of the surrounding concrete and their inclusion leads to significant stress concentrations. This article quantifies the magnitude of the stress raiser and explores the potential of these elevated stress levels to lead to fracture development.

This paper describes JSpy, a system for high-level instrumentation of Java bytecode and its use with JPaX, our system for runtime analysis of Java programs. JPaX monitors the execution of temporal logic formulas and performs predicative analysis of deadlocks and data races. JSpy's input is an instrumentation specification, which consists of a collection of rules, where a rule is a predicate/action pair. The predicate is a conjunction of syntactic constraints on a Java statement, and the action is a description of logging information to be inserted in the bytecode corresponding to the statement. JSpy is built using JTrek an instrumentation package at a lower level of abstraction.

This paper presents an implementation of the AUTOSAR methodology based on two usecases, each of them are derived from an OEM need, as follows: 1) Set up of a collaborative exchange process between OEM and suppliers for the development of AUTOSAR applications. 2) Integration of AUTOSAR software components in a conventional EE architecture The role and contribution of authoring and configuration tools used in the AUTOSAR methodology will be presented and illustrated for both use cases; in particular, the paper will highlight the added value of these tools according to the process by showing their strengths and weaknesses. Mechanisms which have been used to connect proper links and to improve consistency between the various description files which are generated at each step of the AUTOSAR methodology, but also between these description files themselves and the vehicle data; the paper will describe the intrinsic merits of the technology which has been used to develop the tool suite, based on the upcoming Eclipse Framework.

Information about the size, shape, and orientation of mirror mode structures in the magnetosheath is obtained by combining data from the four Cluster spacecraft, resulting in an estimate of the form of the magnetic field magnitude spatial autocorrelation function. It is shown that the longest direction of the structures is typically inclined at around 30°from the local magnetic field direction, consistent with predictions based on linear growth theory; their smallest size is also consistent with these predictions. The ratio of the longest to shortest scales of the structures is typically 2-6, with some evidence for this value to decrease as the structures are carried downstream. This suggests that the mirror modes are generated as long structures, but gradually become isotropic, possibly as part of their nonlinear growth. In common with earlier work, we find that the direction in which the structures are shortest is typically well aligned with the local magnetopause normal, consistent with compression against this boundary. However, the maximum variance direction is not a good proxy for the long axis of the structures, typically lying around 25°f rom it.

Cluster data are used to study the statistics of a particular type of foreshock wave: quasi‐monochromatic ultra‐low‐frequency (ULF) waves with characteristic periods of 30 s in the spacecraft frame. On the basis of a large set of foreshock observations made in 2001 with spacecraft separations ∼600 km, the intrinsic properties of the waves are found using a cross‐correlation timing analysis. This method, which allows the solar wind rest frame properties of the waves to be calculated with fewer assumptions when compared to previous dual spacecraft analysis, is described in detail. The performance of minimum variance analysis (MVA) as a wave analysis tool is investigated experimentally using this multispacecraft analysis. MVA estimates of propagation direction are shown to diverge from the multispacecraft estimate in the limit of linear wave polarization. Theoretical estimates of MVA error are also compared to the observations. Previously established wave properties derived from ISEE a...

Temporal patterns (TRAP) and tandem MLP/HMM approaches incorporate feature streams computed from longer time intervals than the conventional short-time analysis. These methods have been used for challenging small- and medium-vocabulary recognition tasks, such as Aurora and SPINE. Conversational telephone speech recognition is a difficult large-vocabulary task, with current systems giving incorrect output for 20-40% of the words, depending on the

Path extracting algorithms are a very important part of timing analysis approach. In this paper we designed and developed several algorithms which can generate the K most critical paths in a non-increasing order of their delays. The effectiveness of these algorithms is shown by some experimental results.

The false path problem is often referred to as the problem of detecting the longest sensitizable path (A path which is not, a false path is a sensitizable path). The term "false path" is not clearly defined. In this paper, we first give a clear and precise definition of a false path. Then the general false path problem is formulated. The general false path problem is to detect whether a given path (not necessarily the longest one) is a false path. We present an efficient algorithm for solving the general false path problem. We also propose another algorithm which generates all the possible sensitizable paths with the delays greater than a given threshold T. The efficiency and effectiveness of the proposed algorithm are demonstrated by the experimental results.

Both long and short path delays are used to determine the valid clocking for various CMOS circuits such as single phase latching, asynchronous, and wave pipelining. Therefore, accurate estimation of both long and short path delays is very crucial in the designing and testing of high speed CMOS circuits. Most of the previous approaches in detecting long and short sensitizable paths assume that the rising and falling of gate delays are either xed or bounded. In fact the gate delay of CMOS circuits may also depend on how many and which inputs are rising or falling and the arrival times of those rising or falling inputs. For instance, the delay for a two-input CMOS NAND gate may vary as much as a factor of two based on whether one input or two inputs are changing. We shall refer a gate delay model which considers these factors as data dependent delay model. Gray, Liu and Cavin have proposed an approach based on simulation with event pruning to deal with this type of delay model 1]. In this paper, we propose several algorithms to compute the longest and shortest sensitizable path delays based on a data dependent delay model. A proposed algorithm which based on a combination of modi ed static (topological) timing analysis and path sensitization techniques seems to o er the best performance. The results obtained have shown to be more accurate than the traditional path sensitization approach based on bounded delay model. Y=max(t1+dmax(A"B), t2+dmax(AB"), min(min(t1,t2)+ , max(t1, t2))+dmax(A"B")) Under the assumption that t1 and t2 are correct rising times, this means that Y1 t1, Y2 t2. We need to prove XX Y. Since the real rising time of c may come from the following cases, 1. A"B, the rising time is x + delay(A"B) (x 2 X1, Y1]) t1 + dmax(A"B). 2. AB", the rising time is y + delay(AB")) (y 2 X2, Y2]) t2 + dmax(AB"). 3. A"B", the rising time is z+delay(A"B"), z 2 max(x1, x2), min(min(Y1, Y2)+ , max(Y1, Y2))]. Y1 and Y2 are smaller than or equal to t1 and t2 respectively, so z is not bigger than min(min(t1,t2)+ , max(t1, t2)), so z+ delay(A"B") min(min(t 1 , t 2 )+ , max(t 1 , t 2 ))+dmax(A"B"). XX Y is proved. For the falling time of G, we can prove this similarly. 2 Even though the transition delay do not satisfy monotone speedup property 4], the result obtained by the above algorithm does satisfy this property. Lemma 1 The result obtained by the algorithm for long transition delay satis es monotone speedup property. Proof This can be proved similarly to the proof of Theorem 1. We shall not present here. 2 Now we will discuss how to estimate the shortest transition path delay. Suppose that gate G has two inputs a, b and one output c and e ar , e af , e br , e bf , e cr and e cf denote the earliest possible rising and falling times of lead a, b and c respectively, then we have the following formulas for the data dependent delay model and bounded delay model. 1 G is an AND gate, under data dependent delay model e cr = min(e ar + dmin(a"b), e br + dmin(ab"), max(e ar , e br ) + dmin(a"b")) e cf = min(e af + dmin(a#b), e bf + dmin(ab#), max(max(e af , e bf )-, min(e af , e bf ))+dmin(a#b#)) under bounded delay model 10 e cr = min(t ar , t br ) + min(dmin(a"b"), dmin(ab"), dmin(a"b")) e cf = min(e af + dmin(a#b), e bf + dmin(ab#), max(max(e af , e bf )-, min(e af , e bf ))+dmin(a#b#)) 2 G is an OR gate, under data dependent delay model e cr = min(e ar +dmin(a" b), e br +dmin(ab "), max(max(e ar , e br )-, min(e ar , e br ))+dmin(a"b")) e cf = min(e af +dmin(a# b), e bf +dmin(ab#), max(e af , e bf ) + dmin(a#b#)) under bounded delay model e cr = min(e ar +dmin(a"b), e br +dmin(ab"), max(e ar , e br )+dmin(a"b")) e cf = min(e af +dmin(a#b), e bf +dmin(ab#), max(e af , e bf )+dmin(a#b#)) 3 G is a NAND gate, under data dependent delay model e cf = min(e ar +dmin(a"b), e br +dmin(ab"), max(e ar , e br )+ dmin(a"b")) e cr = min(e af +dmin(a#b), e bf +dmin(ab#), max(max(e af , e bf )-, min(e af ,e bf ))+dmin(a#b#)) under bounded delay model e cf = min(t ar , t br )+min(dmin(a"b"), dmin(ab"), dmin(a"b")) e cr = min(t af , t bf )+min(dmin(a#b), dmin(ab#), dmin(a#b#)) 4 G is a NOR gate, under data dependent delay model e cf =min(e ar +delay(a" b), e br +dmin(ab "), max(max(e ar , e br )-, min(e ar , e br ))+dmin(a"b")) e cr = min(e af +dmin(a# b), e bf +dmin(ab#), max(e af , e bf ) + dmin(a#b#)) under bounded delay model e cf = min(e ar +dmin(a"b), e br +dmin(ab"), max(e ar , e br )+dmin(a"b")) e cr = min(e af +dmin(a#b), e bf +dmin(ab#), max(e af , e bf )+dmin(a#b#)) If G is an inverter gate with input a and output c, the formulas for both the data dependent delay model and bounded delay model are: e cr = e af + dmin(a#), e cf = e ar + dmin(a") We can get similar formulas for a gate with more than 2 input leads.

Distributed systems are getting bigger and more complex. While the complexity of large-scale distributed systems has been acknowledged to be an important challenge, there has not been much work in defining or measuring system complexity. In order to defend against overwhelming system complexity, we need to be able to understand and measure complexity and then, attack the issues that cause complexity. In this paper, we define different aspects of system complexity and propose metrics for measuring these aspects. We also show how these aspects affect different kinds of people-viz. developers, administrators and end-users. Based on the aspects and metrics of complexity that we identify, we propose general guidelines that can help reduce the complexity of the system. Finally, we briefly describe how we have used some of these guidelines to reduce complexity in our middleware for autonomic ubiquitous computing environments.

During the design of microprocessor-based systems, once the system architecture has been decided and the major components (processors, memories, IO devices) have been selected from a component library, it is necessary to design interface logic to integrate the system. Such an interface design can be carried out based on the protocols used by the components. This paper addresses the problem of determining the feasibility of a design prior to synthesis. A design is called feasible if it achieves the desired functionality and satisfies the given environmental constraints. Because timing is an important aspect of a correct design, protocols are described using timed signal transition graphs, an interpreted Petri net. It is shown here that the feasibility of designs whose corresponding behavior is periodic can be studied using a technique called timing analysis for synthesis.