Task Graph

This paper presents an approach for improving the overall performance of a general purpose application running as a task graph on a many-core neuromorphic supercomputer. Our task graph framework is based on graceful degradation and amelioration paradigms that strive to achieve high reliability and performance by incorporating fault tolerance and task spawning features. The optimization is applied on an instance of the task graph by performing a soft load balancing on the data traffic between nodes in the graph. We implemented the framework and its optimization on SpiNNaker, a manycore neuromorphic platform containing a million ARM9 processing cores. We evaluate our method using several static mapping examples, where some of them were generated using an evolutionary algorithm. The experiment demonstrates that a performance improvement of up to 8.2% can be achieved when implementing our algorithm on a fully-utilized SpiNNaker communication infrastructure.

Indar Sugiarto∗, Pedro Campos†, Nizar Dahir‡, Gianluca Tempesti§ and Steve Furber¶ ∗¶School of Computer Science, University of Manchester, United Kingdom †§Department of Electronics, University of York, United Kingdom ‡IT Research and Development Center, University of Kufa, Iraq ∗¶{indar.sugiarto, steve.furber}@manchester.ac.uk, †§{pedro.campos, gianluca.tempesti}@york.ac.uk ‡[email protected]

It has been already demonstrated that cost-e ective multiprocessor designs may be obtained by combining in the same architecture processors of di erent speeds (heterogeneous architecture) so that the serial and critical portions of the application may bene t from a fast single processor. In such an environment, the problem of assigning tasks to processors becomes a very important one. This papers presents a systematic way to build static heuristic scheduling algorithms. Using this strategy, several algorithms are proposed and their performance are compared through simulation. One of the proposed algorithms is shown to achieve substantial performance gains as the degree of heterogeneity of the architecture increases.

Recent advances in network technology and the higher levels of circuit integration due to VLSI have led to widespread interest in the use of multiprocessor systems in solving many practical problems. As the hardware continues to diminish in size and cost, new possibilities are being created for systems that are heterogeneous by design. Parallel multiprocessor architectures are now feasible and provide a valid solution to the throughput rates demands of the increasing sophistication of control and/or instrumentation systems. Increasing the number of processors and the complexity of the problems to be solved makes programming multiprocessor systems more difficult and error-prone. This paper describes some parts already implemented (mainly the scheduler) of a software development tool for heterogeneous multiprocessor system that will perform automatically: code generation, execution time estimation, scheduling and handles the communication primitive insertion.

Recent advances in network technology and the higher levels of circuit integration due to VLSI have led to widespread interest in the use of multiprocessor systems in solving many practical problems. As the hardware continues to diminish in size and cost, new possibilities are being created for systems that are heterogeneous by design. Parallel multiprocessor architectures are now feasible and provide a valid solution to the throughput rates demands of the increasing sophistication of control and/or instrumentation systems. Increasing the number of processors and the complexity of the problems to be solved makes programming multiprocessor systems more difficult and error-prone. This paper describes some parts already implemented (mainly the scheduler) of a software development tool for heterogeneous multiprocessor system that will perform automatically: code generation, execution time estimation, scheduling and handles the communication primitive insertion.

Effective multicore computing requires to make efficient usage of the computational resources on a chip. Offline mapping and scheduling can be applied to improve the performance, but classical approaches require considerable a-priori knowledge of the target application. In a practical setting, precise information is often unavailable; one can then resort to approximate time and resource usage figures, but this usually requires to make conservative assumptions. The issue is further stressed if real-time guarantees must be provided. We tackle predictable and efficient non-preemptive scheduling of multi-task applications in the presence of duration uncertainty. Hard real-time guarantees are provided with limited idle time insertion, by exploiting a hybrid off-line/on-line technique known as Precedence Constraint Posting (PCP). Our approach does not require probability distributions to be specified, relying instead on simple and cheaper-toobtain information (bounds, average values). The method has been tested on synthetic applications/platforms and compared with an off-line optimized Fixed Priority Scheduling (FPS) approach and a pure on-line FIFO scheduler; the results are very promising, as the PCP schedules exhibit good stability and improved average execution time (14% on average, up to 30% versus FPS and up to 40% versus the FIFO scheduler).

In High Performance Computing, heterogeneity is now the norm with specialized accelerators like GPUs providing efficient computational power. Resulting complexity led to the development of task-based runtime systems, where complex computations are described as task graphs, and scheduling decisions are made at runtime to perform load balancing between all resources of the platforms. Developing good scheduling strategies, even at the scale of a single node, and analyzing them both theoretically and in practice is expected to have a very high impact on the performance of current HPC systems. The special case of two kinds of resources, typically CPUs and GPUs is already of great practical interest. The scheduling policy Hetero-Prio has been proposed in the context of fast multipole computations (FMM), and has been extended to general task graphs with very promising results. In this paper, we provide a theoretical study of the performance of HeteroPrio, by proving approximation bounds compared to the optimal schedule, both in the case of independent tasks and in the case of general task graphs. Interestingly, our results establish that spoliation (a technique that enables resources to restart uncompleted tasks on another resource) is enough to prove bounded approximation ratios for a list scheduling algorithm on two unrelated resources, which is known to be impossible otherwise. This result holds true both for independent and dependent tasks graphs. Additionally, we provide an experimental evaluation of HeteroPrio on real task graphs from dense linear algebra computation, that establishes its strong performance in practice.

Hardware Software partitioning of a task graph refers to the mapping of task nodes to physical components such as processors, Application Specific Integrated Circuits, memory with an optimization of parameters involving execution time, physical area, cost of memory and other factors. This works evaluates the performance of iterative min-cut heuristic Fiduccia-Mattheyses for HW and SW partitioning. The results shows the algorithm can be very effective in giving the bi-partite partition.

The Network of Tasks (NOT) model allows adaptive node programs written in a variety of parallel languages to be connected together in an almost acyclic task graph. The main difference between NOT and other task graphs is that it is designed to make the performance of the graph predictable from knowledge of the performance of the component node programs and the visible structure of the graph. It can therefore be regarded as a coordination language that is transparent about performance. For largescale computations that are distributed to geographically-distributed compute servers, the NOT model helps programmers to plan, assemble, schedule, and distribute their problems.

Current multimedia and signal processing applications become more complex. This paper proposes a new parallelism management scheme that can explicitly deal with complex and general parallelism patterns. The parallelism description is based on a task ow graph representation interlaced with control commands. A graph management algorithm is proposed to extract eligible tasks and implement synchronization operations. We show that this management outperforms classical parallelism extraction in case of complex applications. Moreover, the parallelism description can be directly inserted in sequential programs without deep code modi cations.

Association rules discovered from transaction databases can be large in number. Reduction of association rules is an issue in recent times. Conventionally by varying support and confidence number of rules can be increased and decreased. By combining additional constraint with support number of frequent itemsets can be reduced and it leads to generation of less number of rules. Average inter itemset distance(IID) or Spread, which is the intervening separation of itemsets in the transactions has been used as a measure of interestingness for association rules with a view to reduce the number of association rules. In this paper by using average Inter Itemset Distance a complete algorithm based on the apriori is designed and implemented with a view to reduce the number of frequent itemsets and the association rules and also to find the distribution pattern of the association rules in terms of the number of transactions of non occurrences of the frequent itemsets. Further the apriori algorithm is also implemented and results are compared. The theoretical concepts related to inter itemset distance are also put forward.

One of the important problems in multiprocessor systems is Task Graph Scheduling. Task Graph Scheduling is an NP-Hard problem. Both learning automata and genetic algorithms are search tools which are used for solving many NP-Hard problems. In this paper a new hybrid method based on Genetic Algorithm and Learning Automata is proposed. The proposed algorithm begins with an initial population of randomly generated chromosomes and after some stages, each chromosome maps to an automaton. Experimental results show that superiority of the proposed algorithm over the current approaches.

Big data quickly comes under the spotlight in recent years. As big data is supposed to handle extremely huge amount of data, it is quite natural that the demand for the computational environment to accelerates, and scales out big data applications increases. The important thing is, however, the behavior of big data applications is not clearly defined yet. Among big data applications, this paper specifically focuses on stream mining applications. The behavior of stream mining applications varies according to the characteristics of the input data. The parameters for data characterization are, however, not clearly defined yet, and there is no study investigating explicit relationships between the input data, and stream mining applications, either. Therefore, this paper picks up frequent pattern mining as one of the representative stream mining applications, and interprets the relationships between the characteristics of the input data, and behaviors of signature algorithms for frequent pattern mining.