Software Implementation

Matrix computations are both fundamental and ubiquitous in computational science and its vast application areas. Along with the development of more advanced computer systems with complex memory hierarchies, there is a continuing demand for new algorithms and library software that efficiently utilize and adapt to new architecture features. This article reviews and details some of the recent advances made by applying the paradigm of recursion to dense matrix computations on today's memory-tiered computer systems. Recursion allows for efficient utilization of a memory hierarchy and generalizes existing fixed blocking by introducing automatic variable blocking that has the potential of matching every level of a deep memory hierarchy. Novel recursive blocked algorithms offer new ways to compute factorizations such as Cholesky and QR and to solve matrix equations. In fact, the whole gamut of existing dense linear algebra factorization is beginning to be reexamined in view of the recursive paradigm. Use of recursion has led to using new hybrid data structures and optimized superscalar kernels. The results we survey include new algorithms and library software implementations for level 3 kernels, matrix factorizations, and the solution of general systems of linear equations and several common matrix equations. The software implementations we survey are robust and show impressive performance on today's high performance computing systems.

De ces Maîtres, je garderai le dynamisme et la disponibilité. Ils m'ont encouragé et donné des conseils sur le plan scientifique et sur le plan humain. Leur sympathie, leur compréhension et leur aide permanente m'ont permis de mener à bien ce travail tout en exerçant une activité professionnelle prenante. Je remercie Monsieur Dieter Weichert Directeur de l'INSA de Rouen, qui me fait l'honneur de présider ce jury. Il est à l'origine du projet de collaboration MOM ✭✭ Modeling and Optimization in Mechanics✮✮ (entre the Institut of General Mechanics(IAM), RWTH d'Aixla-Chapelle et notre Équipe Modélisation Optimisation et Recherche Opérationnelle). Il a suivi régulièrement et avec beaucoup d'intérêt l'évolution des traveaux menés en commun. J'adresse mes vifs remerciements à Messieurs les Professeurs Le Dung Muu (Directeur de

Hard mathematical problems are at the core of security arguments in cryptography. In this paper, we study mathematical generalizations of the famous Rubik's cube puzzle, namely the factorization, representation and balance problems in non-Abelian groups. These problems arise naturally when describing the security of Cayley hash functions, a class of cryptographic hash functions with very interesting properties. The factorization problem is also strongly related to a famous long-standing conjecture of Babai, at the intersection of group theory and graph theory. A constructive proof of Babai's conjecture would make all Cayley hash functions insecure, but on the other hand it would have many positive applications in graph theory and computer science. In this paper, we classify existing attacks against Cayley hash functions and we review known results on Babai's conjecture. Despite recent cryptanalytic progress on particular instances, we show that the factorization, representation and balance problems presumably remain good sources of cryptographic hard problems. Our study demonstrates that Cayley hash functions deserve further interest by the cryptography community. Disclaimer. This paper contains essentially no new result but it rather collects and organizes all the results that were independently found by two distinct scientific communities on the same problems. Between September 2009 and May 2010, the first author gave a sequence of talks to a cryptographic audience, entitled "Hash functions and Cayley graphs: the end of the story?". Surprisingly, many cryptographers seemed to either ignore the beautiful Cayley hash construction, or believe that it had been definitively broken. The very positive feedback received after these talks motivated us to write this survey and to complete it with known results on Babai's conjecture.

In this paper we present a hardware architecture with software implementation able to track free swimming single 2µm in diameter MC-1 bacterium. The computer vision system operates at up to 77 fps at full speed and up to 24 fps when recording full 512×512 pixels frame from a coupled-charge device (CCD) array. Closed-loop control with lock-in tracking is achieved using the Otsu Segmentation Method (OSM) with a cubic spline model-based predictive algorithm. Using the system, speed distribution of MC-1 cells has been recorded showing a mean speed of 200µm/s. Tracking is demonstrated over a range of a few millimeters during 30 sec.

As software systems are maintained, their architecture modularity often degrades through architectural erosion and drift. More directly, however, the modularity of software implementations degrades through the introduction of code anomalies, informally known as code smells. A number of strategies have been developed for supporting the automatic identification of implementation anomalies when only the source code is available. However, it is still unknown how reliable these strategies are when revealing code anomalies related to erosion and drift processes. In this paper, we present an exploratory analysis that investigates to what extent the automatically-detected code anomalies are related to problems that occur with an evolving system's architecture. We analyzed code anomaly occurrences in 38 versions of 5 applications using existing detection strategies. The outcome of our evaluation suggests that many of the code anomalies detected by the employed strategies were not related to architectural problems. Even worse, over 50% of the anomalies not observed by the employed techniques (false negatives) were found to be correlated with architectural problems.

In this paper we present compiler extensions for the Molen programming paradigm, which is a sequential consistency paradigm for programming custom computing machines (CCM). The compiler supports instruction set extensions and register file extensions. Based on pragma annotations in the application code, it identifies the code fragments implemented on the reconfigurable hardware and automatically maps the application on the target reconfigurable architecture. We also define and implement a mechanism that allows multiple operations to be executed in parallel on the reconfigurable hardware. In a case study, the Molen processor has been evaluated. We considered two popular multimedia benchmarks: mpeg2enc and ijpeg and some well-known timeconsuming operations implemented in the reconfigurable hardware. The total number of executed instructions has been reduced with 72% for mpeg2enc and 35% for ijpeg encoder, compared to their pure software implementations on a general purpose processor (GPP).

This paper presents an automated flexible pipeline design algorithm for our unique acceleration technique called Recursive Variable Expansion. The preliminary experimental results on a kernel of real life application shows comparable performance to hand optimized implementation in reduced design time. This make it a good choice for generating high performance code for kernels, for which hand optimized codes are not available.

Mestrado em Engenharia Electrónica e TelecomunicaçõesO presente trabalho apresenta técnicas de processamento digital de sinal, nomeadamente em processamento de vídeo, recorrendo a tecnologia FPGA. Consiste numa introdução teórica sobre tópicos tais como o papel da visão artificial nos dias de hoje, reconhecimento de imagem, e técnicas matemáticas de processamento e análise morfol ógica de imagem. Aborda o tema do papel das FPGAs na tecnologia actual, e as suas vantagens quando utilizadas no processamento digital de sinal. Finalmente e demonstrado e explicado o algoritmo implementado na FPGA para deteção de contornos no processamento de vídeo, concluindo com uma análise a nível da sua eficiência, e discussão de melhorias a fazer num possível trabalho futuro em termos de otimização de recursos utilizados e velocidade de processamento.The present work presents techniques of digital signal processing, namely in video processing, using FPGA technology. It consists of a theoretical introd...

An electrocardiogram (ECG) is a signal that describes the heart's electrical activity. Signal processing techniques are necessary to extract meaningful information from ECG signals. Researchers often use large databases like the PhysioNet database to evaluate the performance of algorithms. However, these databases have limitations concerning the lack of temporal or morphological variations. This study addresses this limitation by introducing a synthetic ECG capable of producing both normal 12-lead ECG signals and abnormal ECG signals and implementing it into the microcontroller. The primary contribution involves developing a synthetic ECG model using McSharry's dynamic equation model and implementing it using Mikromedia 5 for STM32F4 Capacitive as a microcontroller. This model enables users to set the desired heart rate and accurately replicates ECG waveforms using parameters 𝑎 𝑖 , 𝑏 𝑖 , and 𝜃 𝑖 , each determines the peak's magnitude, the peak's time duration, and the angular velocity of the trajectory. The synthetic ECG was evaluated qualitatively and quantitatively, demonstrating waveform similarity to the ECG signals. This study implies that the synthetic ECG model serves as a valuable tool for researchers and practitioners in electrocardiography. It enables the generation of normal and abnormal ECG signals, aiding in algorithm development and potentially enhancing the understanding and diagnosis of heart conditions.

The central problem in the implementation of a Reed-Solomon code is finding the roots of the error locator polynomial. In 1967, Berlekamp et al. found an algorithm for finding the roots of an affine polynomial in GF(2 m ) that can be used to solve this problem. In this paper, it is shown that this Berlekamp-Rumsey-Solomon algorithm, together with the Chien-search method, makes possible a fast decoding algorithm in the standard-basis representation that is naturally suitable in a software implementation. Finally, simulation results for this fast algorithm are given.

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Business process analysis and modeling is a crucial step in formulating information systems user requirements. The practice of information technology (IT) development does not indicate a lack of problems in spite of the growing number of modeling techniques. This article gives an action research account of formulating and applying a new business process modeling framework to manufacturing processes to guide software development. It is based on a combination of soft systems methodology (SSM) and the Unified Modeling Language (UML) business process modeling extensions suggested by Eriksson and Penker. SSM has been linked to information systems provision in the past. The examination of prior research shows that there is no underlying reasoning about the justification from a methodological point of view of the combination of SSM and UML. This article justifies the mixing of SSM and Eriksson and Penker’s UML extensions using the ideas of Mingers’ Multimethodology. The latter helps to ove...

We develop reconfigurable designs to support radiosity, a computer graphics algorithm for producing highly realistic images of artificial scenes, but which is computationally expensive. We implement radiosity using stochastic raytracing, which affords both instruction-level and data parallelism. Our designs are parameterisable by bitwidth, allowing trade-offs between image quality and computation speed. We measure the speed of our designs for a Xilinx XC2V6000 device in the Celoxica RC2000 platform: at 53MHz it can run up to five times faster than a software implementation on an Athlon MP 2600+ processor at 2.1GHz. We estimate that retargeting our design for a Virtex-4 XCVSX55 device can result in over 160 times software speed, while a Spartan-3 XC3S5000 device can run more than 40 times faster than the software implementation.

A virtual pointer (VP) alignment task at designated probe points on a cylinder real object surface was carried out in a stereoscopic augmented reality environment. The object was to evaluate subjects' sensitivity to surface texture, target position on the curved surface, VP orientation relative to the surface, and binocular disparity. The main findings were: a) surface texture had a significant effect, with highly textured surfaces facilitating less error than low textured surfaces; b) target position had a significant influence, with the central position relative to the observer being better for locating surface positions than the off-centre position. Results are discussed in terms of hypothesised visual perceptual interactions.

The novel frequency-multiplexed modulator architecture of the MIT Mark III holo-video display poses a significant challenge in generation of appropriate video signals. Unlike in our previous work, here it is necessary to generate a group of adjacent single-sideband RF signals; as this display is intended to be manufacturable at consumer-electronics prices we face the added requirement of compact and inexpensive electronics that are compatible with standard PC graphics processors. In this paper we review the goals and architecture of Mark III and then describe our experiments and results in the use of a hardware/software implementation of Weaver's single-sideband modulation method to upconvert six 200MHz baseband analog video signals to a set of RF signals covering a nearly contiguous 1GHz range. We show that our method allows efficient generation of non-overlapping signals without aggressive filtering.

Visualizing hierarchical structures is of great importance in many economic and scientific applications. Many different approaches have been developed and enhanced in the last decades. Each of them claims specific advantages over competing methods, usually referring to visual or structural properties. Although several user studies investigated the usefulness of specific approaches, for practitioners it often remains unclear what the practical advantages of the approaches are and in which contexts they are useful. In our user study, we systematically investigated the value of three frequently used visualization types for the intuitive understanding of hierarchical data: treemap, icicle plot, and nodelink. We measured user performance in terms of correctness and time and tracked eye movements for each participant. The results regarding the user performance revealed that nodelink and icicle plot yield expected and comparable results, whereas treemap is only exceeding chance level for o...

Background: Whole genome shotgun sequencing produces increasingly higher coverage of a genome with random sequence reads. Progressive whole genome assembly and eventual finishing sequencing is a process that typically takes several years for large eukaryotic genomes. In the interim, all sequence reads of public sequencing projects are made available in repositories such as the NCBI Trace Archive. For a particular locus, sequencing coverage may be high enough early on to produce a reliable local genome assembly. We have developed software, Tracembler, that facilitates in silico chromosome walking by recursively assembling reads of a selected species from the NCBI Trace Archive starting with reads that significantly match sequence seeds supplied by the user. Results: Tracembler takes one or multiple DNA or protein sequence(s) as input to the NCBI Trace Archive BLAST engine to identify matching sequence reads from a species of interest. The BLAST searches are carried out recursively such that BLAST matching sequences identified in previous rounds of searches are used as new queries in subsequent rounds of BLAST searches. The recursive BLAST search stops when either no more new matching sequences are found, a given maximal number of queries is exhausted, or a specified maximum number of rounds of recursion is reached. All the BLAST matching sequences are then assembled into contigs based on significant sequence overlaps using the CAP3 program. We demonstrate the validity of the concept and software implementation with an example of successfully recovering a full-length Chrm2 gene as well as its upstream and downstream genomic regions from Rattus norvegicus reads. In a second example, a query with two adjacent Medicago truncatula genes as seeds resulted in a contig that likely identifies the microsyntenic homologous soybean locus. Tracembler streamlines the process of recursive database searches, sequence assembly, and gene identification in resulting contigs in attempts to identify homologous loci of genes of interest in species with emerging whole genome shotgun reads. A web server hosting Tracembler is provided at , and the software is also freely available from the authors for local installations.

The choice of a communication paradigm, or protocol, is central to the design of a largescale multiprocessor system. Unlike traditional multiprocessors, the FLASH machine uses a programmable node controller, called MAGIC, to implement all protocol processing. The architecture of the MAGIC chip allows FLASH to support multiple communication paradigms -in particular, cache-coherent shared memory and high-performance message passing -while minimizing both hardware and software overhead. Each node in FLASH contains a microprocessor, a portion of the machine's global memory, a port to the interconnection network, an I/O interface, and MAGIC, the custom node controller. The MAGIC chip handles all communication both within the node and among nodes, using hardwired data paths for efficient data movement and a programmable processor optimized for executing protocol operations. The result is a system that is flexible and scalable, yet competitive in performance with a traditional multiprocessor that implements a single communication paradigm completely in hardware. The application results are used to evaluate the performance costs of flexibility by comparing the performance of FLASH to that of a hardwired machine on representative parallel applications and multiprogramming workloads. These results show that poor application memory reference or load balancing characteristics cause the performance of the FLASH system to degrade more rapidly than the performance of the hardwired system; that is, FLASH's performance is less robust. For applications that incur a large number of remote misses or exhibit substantial hot-spotting, the increased remote access latencies or the occupancy of MAGIC lead to lower performance for the flexible design. Overall, however, the performance of FLASH can be competitive with the performance of the hardwired machine. Specifically, for a range of optimized parallel applications, the performance differences between the hardwired machine and FLASH are small, typically less than 10% at 32 processors and less than 15% at 64 processors. For these programs, either the processor cache miss rates are small or the latency of the programmable protocol processing can be hidden behind the memory access time.

Statistical agencies have longstanding concern over confidentiality of their data [14, 15]. But agencies must also report information to the public. This tension between confidentiality and dis-semination of statistical information is heightened by the emergence of the World ...

To predict the radon concentration in a house environment and to understand the role of all factors affecting its behavior, it is necessary to recognize time variation in both air exchange rate and radon entry rate into a house. This paper describes a new approach to the separation of their effects, which effectively allows continuous estimation of both radon entry rate and air exchange rate from simultaneous tracer gas (carbon monoxide) and radon gas measurement data. It is based on a state-space statistical model which permits quick and efficient calculations. Underlying computations are based on (extended) Kalman filtering, whose practical software implementation is easy. Key property is the model's flexibility, so that it can be easily adjusted to handle various artificial regimens of both radon gas and CO gas level manipulation. After introducing the statistical model formally, its performance will be demonstrated on real data from measurements conducted in our experimental, naturally ventilated and unoccupied room. To verify our method, radon entry rate calculated via proposed statistical model was compared with its known reference value. The results from several days of measurement indicated fairly good agreement (up to 5% between reference value radon entry rate and its value calculated continuously via proposed method, in average). Measured radon concentration moved around the level approximately 600 Bq m À3 , whereas the range of air exchange rate was 0.3e0.8 (h À1 ).

The compilation of Esterel into software has mainly targeted uniprocessor execution. The inherent parallelism of the original description would typically have to be compiled away in order for it to be executed sequentially on a processor. This paper proposes a new compilation scheme that would be able to compile Esterel for distributed execution. This method enables the parallelism of the original description to be realised through actual concurrent execution on multiple processors, or through sequentialized concurrency within a single processor. Both these forms of concurrency can be mixed together for a given implementation. Experimental results indicate significant speed-ups in the performance of concurrently executed distributed programs compared to software implementations on a uniprocessor. When the prototype compiler is used to compile for just a single processor, results show that its performance is comparable to other simulation-based compilers, and significantly faster compared to gate-based compilers, especially for large programs.

This paper investigates performance and energy characteristics of software algorithms for long integer arithmetic. We analyze and compare the number of RISC-like processor instructions (e.g. singleprecision multiplication, addition, load, and store instructions) required for the execution of different algorithms such as Schoolbook multiplication, Karatsuba and Comba multiplication, as well as Montgomery reduction. Our analysis shows that a combination of Karatsuba-Comba multiplication and Montgomery reduction (the so-called KCM method) allows to achieve better performance than other algorithms for modular multiplication. Furthermore, we present a simple model to compare the energy-efficiency of arithmetic algorithms. This model considers the clock cycles and average current consumption of the base instructions to estimate the overall amount of energy consumed during the execution of an algorithm. Our experiments, conducted on a StrongARM SA-1100 processor, indicate that a 1024-bit KCM multiplication consumes about 22% less energy than other modular multiplication techniques.

We present an implementation of elliptic curves and of hyperelliptic curves of genus 2 and 3 over prime fields. To achieve a fair comparison between the different types of groups, we developed an ad-hoc arithmetic library, designed to remove most of the overheads that penalize implementations of curve-based cryptography over prime fields. These overheads get worse for smaller fields, and thus for larger genera for a fixed group size. We also use techniques for delaying modular reductions to reduce the amount of modular reductions in the formulae for the group operations. The result is that the performance of hyperelliptic curves of genus 2 over prime fields is much closer to the performance of elliptic curves than previously thought. For groups of 192 and 256 bits the difference is about 14% and 15% respectively.

As emerging video coding standards, e.g. H.264, aim at high-quality video contents at low bit-rates, the encoding and decoding processes require much more computation than most existing standards do. This paper analyzes software implementation of a real-time H.264 decoder on general-purpose processors with media instructions. Specifically, we discuss how to optimize the speed of H.264 decoders on Intel Pentium 4 processors. This paper first analyzes the reference implementation to identify the time-consuming modules. Our study shows that a number of components, e.g., motion compensation and inverse integer transform, are the most time-consuming modules in the H.264 decoder. Second, we present a list of performance optimization methods using media instructions to improve the efficiency of these modules. After appropriate optimizations, the decoder speed improved by more than 3x-it can decode a 720x480 resolution video sequence at 48 frames per second on 2.4GHz Intel Pentium 4 processors compared to reference software's 12 frames per second. The optimization techniques demonstrated in this paper can also be applied to other video/image processing applications. Additionally, after presenting detailed application behavior on general-purpose processors, this paper discusses a few recommendations on how to design future efficient/powerful video/image applications/standards with given hardware implications.

A novel approach for the time-resolved analysis of high -speed sequences of particle images is presented. The proposed method aims at the minimization of PIV errors in the lower velocity range by adjusting locally and dynamically the interframe time interval of the PIV pairs in a recorded high-speed sequence. The algorithm performs the operation on a local basis, thus providing the same level of accuracy across the full velocity dynamic range of the flow. The present results indicate a greater performance than state-of-the-art PIV analysis based on multi-grid offset PIV and is successfully applied to synthetic and real flow cases. Figure 1 shows the application of the adaptive multi-frame PIV (AMF-PIV) algorithm to a cross-flow jet.

Wireless network is one of most important modes of communication. So providing security to the information being communicated through wireless networks is very important issue. Classical cryptography provides conditional security which has many loop holes whereas quantum cryptography promises to be unconditionally secure for wireless networks. In the present paper, we have implemented quantum cryptography in wireless communication systems using a quantum key distribution (QKD) protocol which is named as SARG04.

The workloads in a modern CPU are becoming more diversified but a common aspect is beginning to form around the need for cryptographic algorithms.There are a number of different cryptographic algorithms for hashing, block ciphers and stream ciphers.Block ciphers have recently been linked to the DES and AES standards and are the most widely used algorithms.Stream ciphers have not been dominated by a single standard.The EU ECRYPT network has developed a set of stream cipher as part of their eSTREAM portfolio. This paper examines the eSTREAM portfolio and analysis the mi- croarchitecture performance on the Intel Core2 Duo.Using hardware performance counters analysis is done in the areas of CPI, cache, branch prediction, and instruction-level parallelism (ILP).Our results show that the Salsa20 algorithm has the best CPI, sosemanuk is able to achieve more ILP, and branch prediction is highly accurate for HC-120, Rabbit and Salsa20. The results show the correlation between CPI with L1 cac...

Compression of floating-point data will play an important role in high-performance computing as data bandwidth and storage become dominant costs. Lossy compression of floating-point data is powerful, but theoretical results are needed to bound its errors when used to store look-up tables, simulation results, or even the solution state during the computation. In this paper, we analyze the round-off error introduced by ZFP, a lossy compression algorithm. The stopping criteria for ZFP depends on the compression mode specified by the user; either fixed rate, fixed accuracy, or fixed precision . While most of our discussion is focused on the fixed precision mode of ZFP, we establish a bound on the error introduced by all three compression modes. In order to tightly capture the error, we first introduce a vector space that allows us to work with binary representations of components. Under this vector space, we define operators that implement each step of the ZFP compression and decompression to establish a bound on the error caused by ZFP. To conclude, numerical tests are provided to demonstrate the accuracy of the established bounds.

A novel portable hardware architecture for the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proof-of-concept design by Pelzl, Šimka, et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the area-time product. The ECM architecture has been ported across three different families of FPGA devices in order to select the family with the best performance to cost ratio. A timing comparison with a highly optimized software implementation, GMP-ECM, has been performed. Our results indicate that low-cost families of FPGAs, such as Xilinx Spartan 3, offer at least an order of magnitude improvement over the same generation of microprocessors in terms of the performance to cost ratio.

notations et conventions 122 13 Bibliographie 125 choisi un mode de présentation un peu particulier. Plutôt que de donner directement la définition la plus générale possible des fonctions critiques, nous montrons comment, au fur et à mesure de l'obtention de nos résultats, nous avons fait évoluer la définition initialement donnée par E. Hebey et M. Vaugon pour l'étude des meilleures constantes dans les inégalités de Sobolev, vers celle de "triplet critique" pour mettre en valeur la puissance de ce concept dans l'étude des EDP qui nous intéressent. La présentation de ce chapitre est donc plus chronologique que synthétique. Chapitre 2 : Trois outils fondamentaux : le point de concentration, le changement d'echelle, le processus d'itération. Principe des démonstrations. Ces trois outils sont à la base des méthodes utilisées pour l'étude des phénomènes de concentration (comme le nom du premier l'indique). Leur présentation, dans les articles sur le sujet, est malheureusement souvent noyée au milieu des démonstrations. Nous avons voulu isoler la définition de ces outils maintenant classiques pour les mettre en valeur et pour rendre les démonstrations plus lisibles. Nous présentons également à la fin de ce chapitre le principe des principales démonstrations. Chapitre 3 : Existence de Fonctions Extrémales, Seconde Inégalité Fondamentale. C'est le coeur de notre travail. Dans une première partie, nous exposons les résultats sur les phénomènes de concentration valables pour une famille générale d'EDP. Ils sont issus du travail de plusieurs auteurs, et présentés selon le principe que nous avons exposé en préambule. Vient ensuite une méthode que nous développons pour obtenir la "seconde inégalité fondamentale" et qui permet d'aboutir au principal théorème. Chapitre 4 : Triplet Critique 1 : Existence de Fonctions Critiques. Notre travail portant sur les fonctions critiques, il est utile de montrer qu'il en existe ! Chapitre 5 : Triplet Critique 2 : Suivant la définition donnée d'un triplet critique, nous regardons ce que l'on peut dire lorsque la métrique varie dans une classe conforme. Chapitre 6 : Triplet Critique 3 : Le dernier problème lié à l'existence des triplets critiques est abordé. C'est une partie trés importante de notre travail, et bien que plus courte, les résultats n'y sont obtenus que grâce à la méthode développée dans le chapitre 3. Chapitre 7 : La dimension 3. Les précédents chapitres portent sur l'étude d'EDP sur des variétés de dimension au moins 4. La dimension 3 est à part, elle est étudiée dans ce chapitre. Chapitre 8 : Remarques sur le cas limite et le cas dégénéré. Quelques remarques (et regrets ?) sont proposées sur le possible affaiblissement des hypothèses faites dans les chapitres précédents. Quelques questions liées à ce travail auxquelles nous aimerions répondre dans l'avenir sont exposées. Appendice A : Démonstration des propriétés élémentaires des fonctions critiques citées au chapitre 1. Reportées ici pour une plus grande lisibilité du premier chapitre. Appendice B : Construction d'une fonction de Green. Nous nous servons de cette notion, mais bien que souvent citée, n'ayant pas pu trouver de références précises, nous en donnons une construction rapide. Appendice C : Limite de C t / u 2 t . Il s'agit d'une limite apparaissant au chapitre 3. Son calcul est issu d'un article de Z. Djadli et O. Druet. Conformément à notre principe nous avons voulu l'inclure car, dans l'article de Djadli et Druet, elle n'est pas calculée avec exactement nos hypothèses. Néanmoins le calcul étant

notations et conventions 122 13 Bibliographie 125 choisi un mode de présentation un peu particulier. Plutôt que de donner directement la définition la plus générale possible des fonctions critiques, nous montrons comment, au fur et à mesure de l'obtention de nos résultats, nous avons fait évoluer la définition initialement donnée par E. Hebey et M. Vaugon pour l'étude des meilleures constantes dans les inégalités de Sobolev, vers celle de "triplet critique" pour mettre en valeur la puissance de ce concept dans l'étude des EDP qui nous intéressent. La présentation de ce chapitre est donc plus chronologique que synthétique. Chapitre 2 : Trois outils fondamentaux : le point de concentration, le changement d'echelle, le processus d'itération. Principe des démonstrations. Ces trois outils sont à la base des méthodes utilisées pour l'étude des phénomènes de concentration (comme le nom du premier l'indique). Leur présentation, dans les articles sur le sujet, est malheureusement souvent noyée au milieu des démonstrations. Nous avons voulu isoler la définition de ces outils maintenant classiques pour les mettre en valeur et pour rendre les démonstrations plus lisibles. Nous présentons également à la fin de ce chapitre le principe des principales démonstrations. Chapitre 3 : Existence de Fonctions Extrémales, Seconde Inégalité Fondamentale. C'est le coeur de notre travail. Dans une première partie, nous exposons les résultats sur les phénomènes de concentration valables pour une famille générale d'EDP. Ils sont issus du travail de plusieurs auteurs, et présentés selon le principe que nous avons exposé en préambule. Vient ensuite une méthode que nous développons pour obtenir la "seconde inégalité fondamentale" et qui permet d'aboutir au principal théorème. Chapitre 4 : Triplet Critique 1 : Existence de Fonctions Critiques. Notre travail portant sur les fonctions critiques, il est utile de montrer qu'il en existe ! Chapitre 5 : Triplet Critique 2 : Suivant la définition donnée d'un triplet critique, nous regardons ce que l'on peut dire lorsque la métrique varie dans une classe conforme. Chapitre 6 : Triplet Critique 3 : Le dernier problème lié à l'existence des triplets critiques est abordé. C'est une partie trés importante de notre travail, et bien que plus courte, les résultats n'y sont obtenus que grâce à la méthode développée dans le chapitre 3. Chapitre 7 : La dimension 3. Les précédents chapitres portent sur l'étude d'EDP sur des variétés de dimension au moins 4. La dimension 3 est à part, elle est étudiée dans ce chapitre. Chapitre 8 : Remarques sur le cas limite et le cas dégénéré. Quelques remarques (et regrets ?) sont proposées sur le possible affaiblissement des hypothèses faites dans les chapitres précédents. Quelques questions liées à ce travail auxquelles nous aimerions répondre dans l'avenir sont exposées. Appendice A : Démonstration des propriétés élémentaires des fonctions critiques citées au chapitre 1. Reportées ici pour une plus grande lisibilité du premier chapitre. Appendice B : Construction d'une fonction de Green. Nous nous servons de cette notion, mais bien que souvent citée, n'ayant pas pu trouver de références précises, nous en donnons une construction rapide. Appendice C : Limite de C t / u 2 t . Il s'agit d'une limite apparaissant au chapitre 3. Son calcul est issu d'un article de Z. Djadli et O. Druet. Conformément à notre principe nous avons voulu l'inclure car, dans l'article de Djadli et Druet, elle n'est pas calculée avec exactement nos hypothèses. Néanmoins le calcul étant

Authors have proposed the approach to increase performance of software implementation of finite field multiplication algorithm, for 32-bit and 64-bit platforms. The approach is based on delayed carry mechanism of significant bit in sum accumulating. This allows to avoid the requirement of taking into account the significant bit carry at the each iteration of the sum accumulation loop. The delayed carry mechanism reduces the total number of additions and gives the opportunity to apply the modern parallelization technologies.

This paper describes the system parameters and software implementation of a HECDSA cryptosystem based on genus-2 hyperelliptic curves over prime fields. We show how to reduce the computational complexity for special cases and compare the given cryptosystem with the well-known ECDSA cryptosystem based on elliptic curves.

Embedded digital signal processing (DSP) systems are usually associated with real time constraints and/or high data rates such that fully software implementations are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. This paper presents the design of a HW/SW G.729 voice decoder dedicated to embedded systems. The decoder has been built around, on the one hand a reconfigurable digital circuit (FPGA) to achieve the so called IP hardware part-the autocorrelation computation-using a linear systolic array, and on the other hand a digital signal processor (DSP) for the remainder of the algorithm. Apart such an implementation is typically driven by the use of reusable component (IP) it is of great interest for new G729-based applications such as Voice over IP (VoIP) for example. It results in an overall reduction of the execution time per frame. Another interesting point is the design of a parameterizable autocorrelation block which can be useful for a wide range of applications such as GSM 13 Kbit/s, APC 9.6 Kbit/s and G723 6.3 Kbit/s and 5.3 Kbit/s. In the G729 context and using a V50 Virtex FPGA, the execution time of this function is 10 times faster than a TMS320C6201 DSP implementation.

This paper presents the concept of software boundaries and their automated detection. It describes an objective, high-level assessment technology to support process control of software development. The technique is largely independent of underlying design and development methods. A worked example illustrates an automated system partitioning application, The paper concludes with a discussion of the technique's potential for increasing confidence in the fault-tolerating properties of a system.

With demographic changes of the aging population and the increasing number of people living alone, pervasive home monitoring is set to play an important role in maintaining the independence and improving the quality of life for the elderly. The UbiSense † project aims to establish smart sensing networks based on low cost embedded video platforms for movement tracking and gait, posture analysis. To ensure privacy, the captured images in UbiSense are immediately filtered at the device level into blobs, which only encapsulate the shape and motion vectors of the subject so that no visual appearance of the subject is ever used. This demonstration will outline the concept of "from blob to personal metrics to behaviour profiling", and illustrate the latest hardware platform and software implementation of the UbiSense design.

Abstract—Computer vision techniques applied to systems used on road maintenance, which are related either to traffic signs or to the road itself, are playing a major role in many countries because of the higher investment on public works of this kind. These systems are able to collect a wide range of information au-tomatically and quickly, with the aim of improving road safety. In this context, the correct visibility of traffic signs and panels is vital for the safety of drivers. This paper describes an approach to the VISUAL Inspection of Signs and panEls (“VISUALISE”), which is an automatic inspection system, mounted onboard a vehicle, which performs inspection tasks at conventional driving speeds. VISUALISE allows for an improvement in the awareness of the road signaling state, supporting planning and decision making on the administration’s and infrastructure operators ’ side. A description of the main computer vision techniques and some experimental results obtained from thousan...

Abstract:-Designing an architecture to handle large conceptual data blocks is very much needed. This paper implements a model for the shape and dimension invariant programming of arrays based on the notation of the Mathematics of Arrays (MOA) algebra. It focuses on ...

This paper presents an approach to cryptanalysis of RSA cryptosystem based on the application of genetic algorithm. The search utilizes the idea of timing attack as computation time information may leak due to different modular operations throughout the RSA encoding. This approach suggests a speed up process, aiming at reducing the required number of plaintext-ciphertext samples needed for a successful timing attack. The proposed notion of timing attack outlined in this work with its preliminary implementation, have given encouraging results on RSA cryptosystem samples. Further work carried on to implement the idea of genetic algorithm technique to practical RSA system has demonstrated encouraging results.

A new metric distortion over latency (DOL) is proposed in this paper to overcome the deficiency of the traditional metric interaction latency in measuring the interactive performance of the modern remote rendering systems, which are enhanced with different latency reduction techniques. The proposed metric is novel in combining both latency and rendering quality into one score for measurement. Our experiments validate that in many scenarios, our new metric can effectively distinguish the performance difference between systems while interaction latency can not. The paper also introduces how DOL can be efficiently calculated at runtime.

In this paper, we present the ongoing research clone in the field of robots playing "football". Several development aspects are discussed such as the hardware system, followed by the software implementation. We will highlight three softwares : the central decision system and the embedded software (used for the real robots small RoboCup league), and the simulation software (used for the simulation RoboCup league). So, we will show and discuss, for each kind of competition, the implemented behaviors.

GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Programming thousands of massively parallel threads is a big challenge for software engineers, but understanding the performance bottlenecks of those parallel programs on GPU architectures to improve application performance is even more difficult. Current approaches rely on programmers to tune their applications by exploiting the design space exhaustively without fully understanding the performance characteristics of their applications. To provide insights into the performance bottlenecks of parallel applications on GPU architectures, we propose a simple analytical model that estimates the execution time of massively parallel programs. The key component of our model is estimating the number of parallel memory requests (we call this the memory warp parallelism) by considering the number of running threads and memory bandwidth. Based on the degree of memory warp parallelism, the model estimates the cost of memory requests, thereby estimating the overall execution time of a program. Comparisons between the outcome of the model and the actual execution time in several GPUs show that the geometric mean of absolute error of our model on micro-benchmarks is 5.4% and on GPU computing applications is 13.3%. All the applications are written in the CUDA programming language.

The Galois Sub-hierarchy (GSH) is a polynomial-size representation of a concept lattice which has been applied to several fields, such as software engineering and linguistics. In this paper, we analyze the performances, in terms of computation time, of three GSH-building algorithms with very different algorithmic strategies: Ares, Ceres and Pluton. We use Java and C++ as implementation languages and Galicia as our development platform. Our results show that implementations in C++ are significantly faster, and that in most cases Pluton is the best algorithm.

Manufacturing flexibility is a difficult to quantify concept that defies universal definition. This paper presents a novel fuzzy-logic approach for measuring manufacturing flexibility that exploits linguistic variables for quantifying pertinent factors affecting commonly utilized flexibility types. Towards this end, we identify and measure the contribution of specified state variables towards the assumed flexibility types in order to compute an overall flexibility index for a generic manufacturing system. The suggested framework provides a convenient end user approach amenable to software implementation that is exemplified through the development of a prototypical software tool called "Flexibility Evaluator".

We describe two classes of software systems that release tabular summaries of an underlying database. Table servers respond to user queries for (marginal) sub-tables of the "full" table summarizing the entire database, and are characterized by dynamic assessment of disclosure risk, in light of previously answered queries. Optimal tabular releases are static releases of sets of sub-tables that are characterized by maximizing the amount of information released, as given by a measure of data utility, subject to a constraint on disclosure risk. Underlying abstractions — primarily associated with the query space, as well as released and unreleasable sub-tables and frontiers, computational algorithms and issues, especially scalability, and prototype software implementations are discussed.

Battery Management System (BMS) is an essential component for lithium-ion battery-based devices. It provides a variety of functionalities that help improve the overall lifespan of the battery, including states estimation algorithms. An accurate estimation of the battery State Of Health (SOH) and State Of Charge (SOC) is a crucial task that an advanced battery management system should perform. This paper aims to outline the most relevant battery model types that were used in literature for Electric Vehicle (EV) applications. An overview of the estimation algorithms that estimate the battery state of charge and state of health are presented and simulations of some methods are also illustrated in order to test their accuracy.

Battery Management System (BMS) is an essential component for lithium-ion battery-based devices. It provides a variety of functionalities that help improve the overall lifespan of the battery, including states estimation algorithms. An accurate estimation of the battery State Of Health (SOH) and State Of Charge (SOC) is a crucial task that an advanced battery management system should perform. This paper aims to outline the most relevant battery model types that were used in literature for Electric Vehicle (EV) applications. An overview of the estimation algorithms that estimate the battery state of charge and state of health are presented and simulations of some methods are also illustrated in order to test their accuracy.

This paper describes a fault tolerant mechanical architecture with four levels devised and implemented in concert with NASA (Tesar, D. & Sreevijayan, D., Four-level fault tolerance in manipulator design for space operations. In First Int. Symp. Measurement and Control in Robotics (ISMCR '90), Houston, Texas, 20-22 June 1990.) Subsequent work has clarified and revised the architecture. The four levels proceed from fault tolerance at the actuator level, to fault tolerance via in-parallel chains, to fault tolerance using serial kinematic redundancy, and finally to the fault tolerance multiple arm systems provide. This is a subsumptive architecture because each successive layer can incorporate the fault tolerance provided by all layers beneath. For instance a serially-redundant robot can incorporate dual fault-tolerant actuators. Redundant systems provide the fault tolerance, but the guiding principle of this architecture is that functional redundancies actively increase the performance of the system. Redundancies do not simply remain dormant until needed. This paper includes specific examples of hardware and/or software implementation at all four levels.