Signal Integrity

Background: Cells interact with their environment and they have to react adequately to internal and external changes such changes in nutrient composition, physical properties like temperature or osmolarity and other stresses. More specifically, they must be able to evaluate whether the external change is significant or just in the range of noise. Based on multiple external parameters they have to compute an optimal response. Cellular signaling pathways are considered as the major means of information perception and transmission in cells. Scope of Review: Here, we review different attempts to quantify information processing on the level of individual cells. We refer to Shannon entropy, mutual information, and informal measures of signaling pathway cross-talk and specificity. Major Conclusions: Information theory in systems biology has been successfully applied to identification of optimal pathway structures, mutual information and entropy as system response in sensitivity analysis, and quantification of input and output information. General Significance: While the study of information transmission within the framework of information theory in technical systems is an advanced field with high impact in engineering and telecommunication, its application to biological objects and processes is still restricted to specific fields such as neuroscience, structural and molecular biology. However, in systems biology dealing with a holistic understanding of biochemical systems and cellular signaling only recently a number of examples for the application of information theory have emerged. This article is part of a Special Issue entitled Systems Biology of Microorganisms.

For many audiovisual applications, the integration and synchronization of audio and video signals is essential. The objective of this paper is to develop a system that displays the active objects in the captured video signal, integrated with their respective audio signals in the form of text. The video and audio signals are captured and processed separately. The signals are buffered and integrated and synchronized using a time-stamping technique. Time-stamps provide the timing information for each of the audio and video processes, the speech recognition and the object detection, respectively. This information is necessary to correlate the audio packets to the video frames. Hence, integration is achieved without the use of video information, such as lip movements. The results obtained are based on a specific implementation of the speech recognition module, which is determined to be the bottleneck process in the proposed system.

Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.

We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ (Quad Small Form Pluggable +) module. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical cable assemblies for an aggregated bandwidth of up to 40 Gbps. We implemented a complete testbench based on a commercial development card mounting an Altera Stratix IV FPGA with 24 serial transceivers at 8.5 Gbps, together with a custom mezzanine hosting three QSFP+ modules. We present test results and signal integrity measurements up to an aggregated bandwidth of 12 Gbps.

Processor, memory, and I/O are three important segments in today's high-speed server platforms. Doubling of processor speed almost every two years and recent advancements in processor performance by developments such as multi-core processing and ...

Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements bring in several challenges into the design of present day VLSI chips. In this paper we present the challenges faced and the approaches successfully adopted in the design of a complex 2.5 million gate high bandwidth data acquisition and processing VLSI chip (a trace-receiver chip, code-named Drishti) in a deep sub-micron technology at Texas Instruments India. The very high design complexity arises due to the rich architecture of the trace-receiver chip, the aggressive timing and performance requirements and its large size. The trace-receiver chip is highly configurable and scalable, thereby catering to both low-end systems, which are cost sensitive, and high-end applications, which demand performance. We present the innovative approaches that were applied to address the challenges encountered in meeting the aggressive design goals (which include functionality, timing, testability, manufacturability, reliability, system issues etc) and to bring the product early to market. Efficient logical and physical partitioning, design reuse and DFT strategies are a few of the techniques that were applied in this design. We present these along with details on the various analyses carried out as part of the design, including signal-integrity, reliability and system-level analyses, which were very critical in ensuring design-closure.

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single / multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling noise on the victim's far end signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling noise introduces the delay in the victim's far end signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to manufacturing defect such as under-etching or even, length of the victim interconnect is increased due to improper layouts of / routings between cores and devices on chips. Influences of other interconnect parasitics on the victim´s far end signal can also be analyzed using the same model. Simulation results obtained with the proposed reduced order model is found to be quite comparable to the accuracy of the PSPICE simulation.

A cascaded S-parameter method is proposed in this paper for signal/power integrity analysis of multiple vias in a multilayer printed circuit board (PCB). The proposed method enables efficient and accurate construction and simulation of physics-based via model for complex multilayer PCB structures involving vias. The physics-based via model describes the parasitic effects near each via region as well as mutual coupling among different vias. In this model, each via portion between two parallel plates is regarded as a three-port network with two coaxial ports and one radial port between the two plates. A procedure is first developed to obtain the S-parameters of a single plate pair, which combine the three-port via networks with the impedance matrix of the parallelplate pair. Once the S-parameters of each plate pair are obtained, an assembling technique for cascading microwave networks is further developed. The method proposed in this paper has been validated by both simulations with a commercial circuit simulator and measurements.

The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O's in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximumflow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.

Noise coupled from switched-mode power supply to signal nets can cause severe signal integrity problems because of the existence of fast switching voltages and currents in the circuit. In this paper, noise coupling mechanism from a synchronous buck converter to a nearby signal trace is studied using a hybrid non-linear model, which combines the synchronous buck converter circuit model and the passive electromagnetic model of the PCB coupling. General design guidelines to mitigate the noise coupling in practical printed circuit board (PCB) designs are provided based on the modeling results.

Ultra-wide-band (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB system-on-chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging method.

HDT (High Design Technology) has been a high-tech startup founded at the end of '80s for the development of state-of-the art predictive CAE tools in the field of wideband Signal/Power Integrity and EMC. Here the collection of posted content related to HDT on the CSELTMUSEUM Facebook public group.

—The paper deals with the methods of simulation of signal propagation on transmission lines when skin effect is taken into account. Such simulations are useful when solving signal integrity issues in todays high-speed electronic circuits where interconnects play an important role. On conditions of continuing increase of the frequency of signals to be transferred, the real interconnects are modelled as transmission lines. Then, in case of sufficiently high frequency band, additional losses caused mostly by a skin effect exist. Two basic approaches can be considered for the simulation, based on either the Laplace-domain or time-domain formulations of fractional telegraph equations, and both accompained by proper numerical techniques. The methods are intended to be utilized for both research and education, while respective Matlab language programs can be utilized for PC exercises. The educational aspects of this research are important, as signal integrity issues and related methods fit into a doctoral course Modern Electronic Circuits Design at our university.

This paper describes about signal integrity. This paper is base on the Eric Bogatin slides and presentations. The writings here refered to Eric Bogatin's Signal Integrity academy. This paper will explain about the right way to think about signals on interconnects. The essential principles for solving Signal integrity problems will be discussed. The main enemy of signal integrity are reflection noise, cross talk, EMI and PDN. Ground bounce phenomena and signal transition noise will also be described. Lastly, this paper will talk about analysis tools and explore design trade offs.

This paper gives an outline useful for introducing EMC (electromagnetic compatibility) design to first time students. It is based on the universal interference model and the concept of zoning. It structures the introduction to circuit design, filters, connections and shielding. The contributions of grounding and management are also incorporated into the outline

A novel method for practical prediction of interconnect conductor surface roughness effect on multi-gigabit digital signals is proposed. A differential impedance operator of a conductor is constructed with Trefftz finite elements and locally adjusted with a correction coefficient to account for the roughness effect. Any correction coefficient derived for the additional power loss due to roughness can be used with the proposed method. Modified Hammerstad's correction coefficient is proposed and used here as an example. A test board is manufactured and investigated up to 50 GHz. Parameters of the conductor roughness model are identified with generalized modal S-parameters. An increase of effective dielectric constant due to conductor surface roughness is observed and explained by capacitive effect of spikes on the surface of conductor. It is shown that the constructed interconnect models are consistent with the measured data.

In this paper, a unique technical approach is presented to accurately analyze and optimize the address bus of an onboard DDR4 memory module by taking power plane induced noise and thermal effect simultaneously in the analysis. For high-speed digital designers, designing data channel in DDR4 memory is always challenging due to high data rates of 3.2GB/s per data signal at a low-voltage of 1.2V. The design is simulated at 1.6 Gbps that is the highest DDR4 switching rate in a configuration containing four memory devices. It is important to catch SI and PI problems at an early stage in design that requires fast and accurate signal integrity analysis for address bus. To maximize eye opening, address bus interconnects impedance optimization is carried out. DDR4 power plane and address signals are analyzed using PI-SI solver that is based on full-wave electromagnetic simulation, then the transient simulation is performed on combined PI data of power plane and address bus. The coupling of simultaneous switching noise (SSN), power plane jitter and thermal effects on DDR4 address bus signals are accounted in power and thermal-aware signal integrity analysis using PIPro signal integrity solution.

A comprehensive overview is given of the strengths, limitations, and applicability of the short-pulse propagation technique (SPP). SPP is shown to be able to extract the broadband characteristics of a wide range of interconnect technologies found in digital computer applications and generate causal predictive models. Examples are given of such applications from on-chip wiring, ceramic and organic chip carrier, cards, boards, to cables, and structures with large inhomogeneities, such as found in differential and microstrip cases, irregularities (such as introduced by roughening of metallization), and various operating conditions, such as variable temperature and humidity. The use of SPP as a virtual test bench is explained and showcased through the analysis of the impact of manufacturing tolerances and via stub length on the electrical characteristics. The diverse versatility of the SPP method is discussed through many examples on practical interconnect structures with special emphasis on printed circuit board wiring.

This paper investigates the synergies between a GNSS Avionics Based Integrity Augmentation System (ABIA) and a novel Unmanned Aerial System (UAS) Sense-and-Avoid (SAA) architecture for cooperative and non-cooperative scenarios. The integration of ABIA with SAA has the potential to provide an integrity-augmented SAA solution that will allow the safe and unrestricted access of UAS to commercial airspace. The candidate SAA system uses Forward-Looking Sensors (FLS) for the non-cooperative case and Automatic Dependent Surveillance-Broadcast (ADS-B) for the cooperative case. In the non-cooperative scenario, the system employs Navigation-Based Image stabilization with image morphology operations and a multi-branch Viterbi filter for obstacle detection, which allows heading estimation. It utilizes a Track-to-Track (T3) algorithm for data fusion that allows combining data from different tracks obtained with FLS and/or ADS-B depending on the scenario. Successively, it utilizes an Interacting Multiple Model (IMM) algorithm to estimate the state vector allowing a prediction of the intruder trajectory over a specified time horizon. Both in the cooperative and non-cooperative cases, the risk of collision is evaluated by setting a threshold on the Probability Density Function (PDF) of a Near Mid-Air Collision (NMAC) event over the separation area. So, if the specified threshold is exceeded, an avoidance manoeuvre is performed based on a heading-based Differential Geometry (DG) algorithm and optimized utilizing a cost function with minimum time constraints and fuel penalty. In addition, the optimised avoidance trajectory considers the constraints imposed by the ABIA in terms of GNSS constellation satellite elevation angles, preventing degradation or losses of navigation data during the whole SAA loop. This integration scheme allows real-time trajectory corrections to re-establish the Required Navigation Performance (RNP) when actual GNSS accuracy degradations and/or data losses take place (e.g., due to aircraft-satellite relative geometry, GNSS receiver tracking, interference/jamming or other external factors). Various simulation case studies were accomplished to evaluate the performance of the Integrity-Augmented SAA (IAS) architecture. The selected host platform is the AEROSONDE UAV and the simulation cases address a variety of cooperative and non-cooperative scenarios in a representative cross-section of the AEROSONDE operational flight envelope. The analysis shows that the IAS architecture is an excellent candidate for high-integrity cooperative and non-cooperative SAA tasks utilizing GNSS as the primary source of navigation data, providing solid foundation for future research and developments in this domain.

This paper presents a novel Global Navigation Satellite System (GNSS) Avionics Based Integrity Augmentation (ABIA) system architecture suitable for civil and military air platforms, including Unmanned Aircraft Systems (UAS). Taking the
move from previous research on high-accuracy Differential GNSS (DGNSS) systems design, integration and experimental flight test activities conducted at the Italian Air Force Flight Test Centre (CSVRSV), our research focused on the development of a novel approach to the problem of GNSS ABIA for mission- and safety-critical air
vehicle applications and for multi-sensor avionics architectures based on GNSS. Detailed mathematical models were developed to describe the main causes of GNSS signal outages and degradation in flight, namely: antenna obscuration, multipath, fading due to adverse
geometry and Doppler shift. Adopting these models in association with suitable integrity thresholds and guidance algorithms, the ABIA system is able to generate integrity cautions (predictive flags) and warnings (reactive flags), as well as providing steering information to the pilot and electronic commands to the aircraft/UAS flight control systems. These features allow real-time avoidance of safety-critical flight conditions and fast recovery of the required navigation performance in case of GNSS data losses. In other words, this novel ABIA system addresses all three cornerstones of GNSS integrity augmentation in mission- and safety-critical  applications: prediction (caution flags), reaction (warning flags) and correction (alternate flight path computation).

The number of gates on a chip is quickly growing toward and beyond the one billion mark. Keeping all the gates running at the beat of a single or a few rationally related clocks is becoming impossible. In static timing analysis process variations and signal integrity issues stretch the timing margins to the point where they become too conservative and result in significant overdesign. Importance and difficulty of such problems push some developers to once again turn to asynchronous alternatives.

For the 56G and the forthcoming 112G PAM4 systems, it is no longer feasible to rely on SerDes alone to transmit data through channels up to 30dB in insertion loss to achieve the desired BER. FEC becomes mandatory to work jointly with the SerDes to achieve the post-FEC BER better than a designed target, e.g., 1e-15.
This paper starts with the less-adequate approaches adopted in the industry and with some standard bodies today for FEC capability assessment. First, a large number of data based on the 28G generation KR4 FEC performance analysis and the lab test is presented to show that simply specifying a pre-FEC BER is not enough for the FEC to help achieve the desired BER. Then a novel FEC post-processing method based on voltage bathtub curves is discussed. Recursive models for both PAM4 DFE burst error probability and KP4-FEC BER estimation are derived and applied to some system link simulation examples. The methodology should help the industry to gain better insight into the system BER requirement when FEC is applied.

— The paper deals with a simulation of nonlinear networks based on a classical approach of Volterra series expansion. It is known that a multidimensional Laplace transform (MLT) of a time-domain nonlinear impulse response results in the respective Laplace-domain transfer function which helps in finding Volterra kernels, for example via a harmonic input method. After solving the system in the Laplace domain, a final step is to transfer the solution back into the time domain. For this purpose proper multidimensional numerical inverse Laplace transforms (MNILT) are applied with advantages avoiding the usage of rather impractical associate variables method required to receive a single-variable Laplace image. To ensure good convergence and stability of the method the networks are limited to be rather weakly nonlinear when usually the kernels into the third order already yield reasonable results. That is why, methods for up to the third-dimensional NILT (3D NILT) are discussed in the paper, both the FFT-based one with a quotient-difference algorithm and a hyperbolic one with the Euler transformation. All the discussed methods are programmed and tested in Matlab language while considering a proper model of a nonlinear electrical network.

This paper presents a general strategy for the electrical performance and Signal Integrity assessment of electrically long multi-chip links. A black-box time-domain macromodel is first derived from tabulated frequency responses in scattering form. This model is structured as a combination of ideal delay terms with frequency-dependent rational coefficients. A new identification scheme is presented, based on an initial blind delay estimation process, followed by a refinement loop based on an iterative Delayed Vector Fitting (DVF) process. Two alternative passivity enforcement schemes based on local perturbations are then presented. The result is an accurate and guaranteed passive delay-based macromodel, which is synthesized as a SPICEcompatible netlist for channel analysis. The proposed procedure enables safe and reliable circuit-based transient simulations of complex multi-chip links, including nonlinear drivers and receivers. The performance of the proposed flow is demonstrated on a large number of channel benchmarks.

In this paper, parasitic modes, such as slotline, parallel plane, and surface wave (SW) modes, commonly found on printed circuit boards (PCBs) will be analyzed and their effects on electromagnetic compatibility (EMC) and signal integrity will be discussed. The analysis is based on numerical simulations using the finite difference time domain (FDTD) method which will be shown to be very well suited for rigorous modeling of parasitic mode effects. EMC and signal integrity problems discussed include power loss, crosstalk, ground bounce, and free space radiation. Design guidelines for improved EMC and signal integrity are derived from the results obtained. Comprehensive simulation and characterization of SWs using FDTD is presented for the first time.

We present a multichip structure assembled with a medical-grade stainless-steel microelectrode array intended for neural recordings from multiple channels. The design features a mixed-signal integrated circuit (IC) that handles conditioning, digitization, and time-division multiplexing of neural signals, and a digital IC that provides control, bandwidth reduction, and data communications for telemetry toward a remote host. Bandwidth reduction is achieved through action potential detection and complete capture of waveforms by means of onchip data buffering. The adopted architecture uses high parallelism and low-power building blocks for safety and long-term implantability. Both ICs are fabricated in a CMOS 0.18-m process and are subsequently mounted on the base of the microelectrode array. The chips are stacked according to a vertical integration approach for better compactness. The presented device integrates 16 channels, and is scalable to hundreds of recording channels. Its performance was validated on a testbench with synthetic neural signals. The proposed interface presents a power consumption of 138 W per channel, a size of 2.30 mm 2 , and achieves a bandwidth reduction factor of up to 48 with typical recordings.

We present a new multilevel fast Fourier transform (MLFFT) method, and its application for the three dimensional (3D) structures capacitance extraction. The multilevel octree structure, multilevel interpolation/projection, and subdomain FFTs techniques are employed in the MLFFT. The distinctions between the MLFFT and the conventional FFT-based methods are discussed carefully. Numerical results demonstrate that the MLFFT is more efficient than the conventional FFT based methods especially when analyzing inhomogeneous problems.

With increased operating frequencies and circuit component density, signal and power integrity problems caused by voltage bounces have become more important for high-speed digital systems. This paper presents a systematic macromodeling of power-bus structures based on the cavity model: first, more accurate models are used to describe conductor and dielectric losses, thus improving accuracy at low frequencies; second, a rational model of the overall power/ground structure in the Laplace domain is presented, and third, the rational macromodel is used to identify the dominant poles, and a simplified Spice-compatible equivalent circuit is synthesized by using only the selected poles. The numerical results confirm the correctness and effectiveness of the method.

This paper provides a SPICE-compatible circuit model for characterizing electrostatic discharge (ESD) clamping performance of protection devices mounted on printed circuit boards (PCBs). An equivalent circuit model for a commercial ESD generator is introduced and a simulation methodology of an ESD protection device with non-linear resistance characteristic using voltage controlled current source is described. These models combined to create a full circuit model with a PCB model in a SPICE-like circuit simulator. Comparison results between the simulated and measured are presented to verify the accuracy of the proposed circuit model. A trade-off analysis between the ESD clamping performance and signal integrity with the ESD protection device in high-speed applications is also presented as a case study.

This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency. A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice. The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison.

This paper presents a selective survey of¯nite di®erence time domain (FDTD)-based interconnects modeling for signal integrity analysis problems. In spite of 47 years of its existence, researchers have focused on FDTD method with further modi¯cations and enhancements for the signal integrity analysis of interconnects over the past two decades only. Because of the remarkable amount of interconnect-based FDTD-related research activity, tracking the FDTD literature can be a tedious and challenging task. This survey presents some of the signi¯cant methods and approaches employed to analyze the developments achieved up to the present-day signal integrity related research. These methods are based on solving telegrapher's equations which represent the transmission line behavior of interconnects. Recent research concentrates on developing novel methods for accurate interconnect modeling, extraction of interconnect parameters and incorporation of more lumped elements into FDTD. In this paper an attempt has been made to compare and summarize some of the well-known FDTD-based methods, which were used in interconnect related research.

Abstract—As the data rate is significantly increased, the effect of via discontinuity on the signal integrity of printed circuit boards has become more prominent and nonnegligible. In this paper, the artificial neural network approach to efficient design of reflection-less via ...

Placing shields around a victim signal line is a common way to enhance signal integrity while minimizing delay uncertainty. An analytic model of the peak noise is developed for shielded interconnects based on a ¢ ¡ ¤ £ ¤ ¥ § ¦ © -model. A design methodology for inserting shields between coupled interconnects to reduce crosstalk noise is presented.

This article presents the design of a novel and compact coplanar antenna using Metamaterials (MTM) and Micro Electro Mechanical Systems (MEMS). The antenna is based on coplanar waveguide (CPW) technology; therefore, the signal and ground are on the same plane, presenting lower dielectric losses and high signal integrity. The designed antenna can be tuned in the frequency range from 5.3 to 5.8 GHz by MEMS capacitors, and it is useful for wireless communications applications, especially beam steering systems. Finally, the design, 3D full-wave simulations and MEMS simulations are presented. Index Terms -Metamaterial (MTM), Transmission Line (TL), Coplanar (CPW), Composite Right/Left Handed (CRLH), Micro-Electro-Mechanical Systems (MEMS).

An in detail design of digital window comparators is presented. This comparator can be used for the on-chip (and potentially on-line) response evaluation of analogue circuits. The analysis shows that if the design parameter β is in the order of 1. .. 0,36 for the NOR and 1. .. 2,8 for the NAND good results for the comparator can be achieved and the variation of the window position is limited to 5%. Parameter and temperature drifts are discussed along with results from characterisation. The results can be extended to deep-submicron technologies if the respective equations are used to derive the logical threshold and beta values. A simplified comparator is described that also allows the localisation of the evaluated signal. The conditions for the implementation of the window comparators into Design-for-Testability schemes are outlined. It is demonstrated that the digital window comparator can be implemented in the digital part of the mixed-signal integrated circuit.

For critical high speed applications, system designers budget electrical performance for each individual component within the integration. During the budgeting process, each component is treated as a black box, and are assigned target performance levels. Crosstalk and switching noise levels are specified and closely watched, since they can cause episodes of false switching. SPICE simulations are performed at the IC, package, and system level to track down any signal integrity problems or issues. Obtaining accurate package models, in particular for power and ground, are key to overall simulation accuracy. Package power and ground inductance plays a major roll in determining switching noise performance. Ball Grid Array (BGA) packages are constructed with laminate substrates that provide an efficient means for achieving minimal power and ground inductance implementation. [2] A BGA that is strategically designed will yield m e r enhancements in crosstalk and switching noise performance[l]. This is accomplished by optimal implementation and location of power, ground, and signal networks. By doing so, loop inductance created at critical locations in the BGA are reduced by mutual inductance. BGA packages use power and ground rings to provide low inductance access from Integrated Circuit (IC) bond pads to package planes[3]. These connections are typically done using many bond wires equally distributed around the perimeter of the die. Rings are used in combination with via holes, planes, and solder balls to complete the power and ground network structures. Careful attention to how the currents flow in these structures in conjunction with signal traces will yield minimal effective inductance[4]. This paper presents a characterization methodology for creating BGA electrical models. It addresses a class of BGAs that contain power and ground planes, and the Plastic BGA package is used as a vehicle. The measurements are performed in frequency domain using a vector network analyzer. Using these models, electrical performance of BGA packages will be evaluated.

—The paper describes a method of modelling lossy transmission lines with frequency dependent parameters in the fractional-order domain. It is shown that in high frequency systems the frequency dependence of the transmission line (TL) and other related losses are essential to be considered in the model. In this paper fractional-order domain is used to model the lossy transmission line, which compensates for losses and provides higher flexibility and more reality for the TL analysis and simulation. As for the frequency dependence of the TL skin effect is included in the model, due to its high impact in high frequency applications. Analysis of a TL is processed in the Laplace-domain which effectively simplifies the solution. Though, the difficult or even impossible part is to obtain the required original time-domain from the results by analytic means. In order to overcome this difficulty a numerical inverse Laplace transform (NILT) method is introduced in this paper. The NILT method is implemented successfully, and the voltage/current waveform distributions along the lossy fractional-order TL are simulated and the results are displayed. The model is effectively tested and realized in the Matlab language.

This paper presents a method for fast and comprehensive simulation of signal propagation, power/ground noise, and radiated emissions by combining the merits of the physics-based via model, the modal decomposition technique, the contour integral method (CIM), and the equivalence principle. The physics-based via model combined with the modal decomposition technique is an efficient technique for signal integrity analysis of multilayer PCBs and packages. The CIM can be used to calculate the voltage distribution between arbitrarily shaped power planes. Far-field radiation can be obtained by applying the field equivalence principle. In this paper, we integrate the four techniques to analyze all the three effects in a fast, concurrent, and holistic manner. To the best knowledge of the authors, the four techniques are integrated here for the first time. Various structures are simulated and validated with full-wave simulations up to 20 GHz. It is shown that a reduction in simulation time of more than two orders of magnitude is achieved in comparison to a standard full-wave electromagnetic solver.