Programmable logic array

This paper proposes GAPLA: a globally asynchronous locally synchronous programmable logic array architecture. The whole FPGA area is divided into locally synchronous blocks wrapped with asynchronous I/O interfaces. Data communications between synchronous blocks are controlled by 2-phase handshaking signals under bundled-data delay assumption. The size and shape of each locally synchronous block are programmable so that different modules in a design can be effectively implemented. By dividing the FPGA area into smaller blocks, the delays of long interconnect wires, which could easily dominate other delays in conventional FPGAs, only come into picture when there are communications between blocks. Therefore, each block could run at higher speed. The area overhead of adopting the GALS style in GAPLA architecture is estimated to be very small (about 7%). Experimental results show an up to 55% performance improvement compared to the conventional FPGAs.

The development and implementation of an agent-based distributed control system in a wastewater treatment plant (WWTP) are shown. The hardware architecture contains different supervision levels, including two autonomous process computers, a programmable logic controller (PLC) and a knowledge-based system (KBS), acting at the top supervisory level. The knowledge is organized in several distributed agents, representing the available knowledge for every subprocess of the WWTP. In addition to these independent agents, a supervisor agent acts as its master. The distributed multi-agent architecture improves previous developments with monolithic KBS, allowing the development of independent and reusable agents. Different strategies have been included, adapted, and modified without a great programming effort. The developed system has involved the transformation of a classical control system into a system that enables a WWTP to respond to different usual problems. Finally, the system has been satisfactorily validated supervising a pilot WWTP for more than 3 years.

We have developed a wearable, battery-free tag that monitors heart sounds. The tag powers up by harvesting ambient RF energy, and contains a low-power integrated circuit, an antenna and up to four microphones. The chip, which consumes only 1.0µW of power, generates digital events when the outputs of any of the microphones exceeds a programmable threshold voltage, combines such events together by using a programmable logic array, and transmits them to a base station by using backscatter modulation. The chip can also be programmed to trade-off microphone sensitivity for power consumption. In this paper, we demonstrate that the tag, when attached to the chest, can reliably measure heart rate at distances up to 7m from an FCC-compliant RF power source. We also suggest how delays between signals measured by microphones at the wrist and neck can be used to provide information about relative blood-pressure variations.

The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle any number of variables. This paper describes a new model for the estimation of circuit complexity, based on Quine-McCluskey simplification method. The proposed method utilizes data derived from Monte-Carlo simulations for any Boolean function with different count of variables and product term complexities. The model allows design feasibility and performance analysis prior to the circuit realization.

The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on decomposing an initial PLA description of the FSM into a three interacting portions. The proposed solution provides ...

This paper deals with PLA folding strategies: in particular, the accurate evaluation of the area used by folded PLA's is presented. Criteria are proposed to choose the best folding strategy among those considered, without performing all the possible foldings.

We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all faces of minimum length. Increasing dimensions of the Boolean space are explored; for a given dimension constraints are satisfied one at a time. The following features help to reduce the nodes of the solution space that must be explored: candidate cubes instead of candidate codes are generated, cubes yielding symmetric solutions are not generated, a smaller sufficient set of solutions (producing basic sections) is explored, necessary conditions help discard unsuitable candidate cubes, early detection that a partial solution cannot be extended to be a global solution prunes infeasible portions of the search tree. We have implemented a prototype package minimum input satisfaction kernel (MINSK) based on the previous ideas and run experiments to evaluate it. The experiments show that MINSK is faster and solves more problems than any available algorithm. Moreover, MINSK is a robust algorithm, while most of the proposed alternatives are not.

AbstractÐAn FPD switch module w with w terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of w is at most w) is simultaneously routable through w [8]. Chang et al. have identified a class of universal switch blocks in . In this paper, we consider the design and routing problems for another popular model of switch modules called switch matrices. Unlike switch blocks, we prove that there exist no universal switch matrices. Nevertheless, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size and show that their routing capacities converge to those of universal switch blocks. Each of the quasi-universal switch matrices of size w has a total of only IRw À PH (IRw À PI) switches if w is even (odd), w b I, compared to a fully populated one which has Qw P À Pw switches. We prove that no switch matrix with less than IRw À PH (IRw À PI) switches can be quasi-universal. Experimental results demonstrate that the quasi-universal switch matrices improve routabilty at the chip level.

The pseudoexhaustive testing (PET) scheme is a economic approach to test a large embedded programmable logic array (PLA). In this paper, we propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying our algorithm, both the area overhead and test length are reduced significantly.

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5-10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurements are presented.

This paper revises and introduces to the field of reconfigurable computer systems, some traditional techniques used in the fields of fault-tolerance and testing of digital circuits. The target area is that of on-board spacecraft electronics, as this class of application is a good candidate for the use of reconfigurable computing technology. Fault tolerant strategies are used in order for the system to adapt itself to the severe conditions found in space. In addition, the paper describes some problems and possible solutions for the use of reconfigurable components, based on programmable logic, in space applications.

The paper deals with the fault tolerance of finite state machines (FSMs) implemented by nanoelectronic programmable logic arrays (PLAs). The paper studies a fault tolerant nano-PLA structure, which is based on implementing an initial FSM in a form of three interacting dense PLAs. The paper provides experimental benchmarks results for estimation of fault tolerance properties of the proposed solution. The results indicate a high efficiency of the proposed decomposition approach.

In this paper, a scalable architecture of the multicarrier CDMA system using Multiple-Input-Multiple-Output (MIMO) technology is designed in the programmable logic array. The system-level partitioning with different architecture design entries is described. The overall computing architecture for complex signal processing blocks, e.g., channel estimation, frequency domain equalization, demodulation etc is described. The MIMO architecture is easily extended from a SISO system with single antenna. This scalable architecture demonstrates resource utilization efficiency and easy extension to MIMO configurations.

When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software a nd the performance of hardware, while at the same time allowing for post -fabrication modification of circuits. To automate the layout of reconfigurable subsystems for systems-ona-chip, we present template reduction. Template reduction enables a designer to eliminate resources from a template that are unnecessary to support the specified applic ation domain. To facilitate this, we have created a feature rich template, from which we automatically generate application specific reconfigurable circuits. Compared to the full template, we achieve designs that are 53.4% smaller and 13.9% faster, while continuing to support the algorithms in a particular application domain.

Ecient parallel schemes for carry-propagation-free addition of modi®ed signed-digit trinary numbers are presented. The necessary minterms for implementation using an optical programmable logic array area are derived. The proposed schemes require only a truth table of 25 entries compared with an earlier scheme of 625 entries. The proposed schemes are amenable to optical implementation. Experimental results using an optical programmable logic array are demonstrated. The experiments show the problems of noise and crosstalk. This suggests some dc bias is necessary to increase the signal-to-noise ratio of the optical circuit. #

This paper deals with PLA folding strategies: in particular, the accurate evaluation of the area used by folded PLA's is presented. Criteria are proposed to choose the best folding strategy among those considered, without performing all the possible foldings.

Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits the size of the system that may be evolved. In this paper a new genetic algorithm, particularly designed for evolving logic circuits, is presented and tested for its scalability. The proposed algorithm designs and optimizes logic circuits based on a Programmable Logic Array (PLA) structure. Furthermore it allows the evolution of large logic circuits, without the use of any decomposition techniques. The experimental results, based on the evolution of several logic circuits taken from three different benchmarks, prove that the proposed algorithm is very fast, as only a few generations are required to fully evolve the logic circuits. In addition it optimizes the evolved circuits better than the optimization offered by other evolutionary algorithms based on a PLA and FPGA structures.

In this paper a new scheme is proposed for progressive image transmission over coded Orthogonal Frequency Division Multiplexing (OFDM) system with Low Density Parity Check Coding (LDPC). Trigonometric transforms are used in this scheme for improving the performance of the OFDM systems and reducing the Peak to-Average Power Ratio (PAPR) of OFDM signal. It improves the error resilience ability and transmission efficiency for progressive image transmission over Additive White Gaussian Noise (A WGN) channel. The Set Partitioning In Hierarchical Trees (SPIHT) algorithm is used for source coding of the images to be transmitted. In the proposed scheme the transmit data sequence of the OFDM signal after Inverse Fast Fourier Transform (lFFT) is grouped into in-phase and in-quadrature components, then each component is transformed using either the Discrete Cosine Transform (DCT) or the Discrete Sine Transform (DST). The simulation results show that adding the DST to the system improves the visual quality of reconstructed images and reduces the PAPR of OFDM signal more than the DCT.

The evolutionary design of electronic circuits, or evolvable hardware, is a discipline that allows the user to automatically obtain the desired circuit design. The circuit configuration is under the control of evolutionary algorithms. Several researchers have used evolvable hardware to design electrical circuits. Every time that one particular algorithm is selected to carry out the evolution, it is necessary that all its parameters, such as mutation rate, population size, selection mechanisms etc. are tuned in order to achieve the best results during the evolution process. This paper investigates the abilities of evolution strategy to evolve digital logic circuits based on programmable logic array structures when different mutation rates are used. Several mutation rates (fixed and variable) are analyzed and compared with each other to outline the most appropriate choice to be used during the evolution of combinational logic circuits. The experimental results outlined in this paper are important as they could be used by every researcher who might need to use the evolutionary algorithm to design digital logic circuits.

PHIPLA, a new algorithm for logic minimization, is presented. The algorithm sets out to find optimal sum-of-products representations for a set of Boolean functions, thus contributing to area minimization of the Programmable Logic Array corresponding to the set of functions. The results of a comparative study of PHIPLA and two other algorithms, SPAM and PRESTOL-II, are presented. From these results it is concluded that PHIPLA generates representations which are competitive with those generated by SPAM and PRESTOL-II, whilst the algorithm is extremely fast for small problems (up to 12 variables).

The past twenty years have seen a flurry of activity in the arena of parallel and distributed computing. In recent years, novel parallel and distributed computational models have been proposed in the literature, reflecting advances in new computational devices and environments such as optical interconnects, programmable logic arrays, networks of workstations, radio communications, mobile computing, DNA computing, quantum computing, sensor networks etc. It is very encouraging to note that the advent of these new models has lead to significant advances in the resolution of various difficult problems of practical interest. The main goal of this workshop is to provide a timely forum for the exchange and dissemination of new ideas, techniques and research in the field of the parallel and distributed computational models. The workshop is meant to bring together researchers and practitioners interested in all aspects of parallel and distributed computing taken in an inclusive, rather than exclusive, sense. We are convinced that the workshop atmosphere will be conducive to open and mutually beneficial exchanges of ideas between the participants.

Spintronics devices are based on the up or down spin of the electrons rather than on electrons or holes as in the traditional semiconductor electronics devices. Magnetic processors using spintronics devices in principle are much faster and with the potential features of nonvolatile, lower power consumption and higher integration density compared with transistor-based microprocessor. Full adder is one of the most important basic units of the arithmetic/logic unit for any processors. The design of the full adder determines the speed and chip-density of a processor. In this paper, a novel spintronics full adder is proposed based on novel programmable spintronics logic devices. Only seven magnetic tunnel junction elements are needed for this full adder design.

As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.

In this paper a new scheme is proposed for progressive image transmission over coded Orthogonal Frequency Division Multiplexing (OFDM) system with Low Density Parity Check Coding (LDPC). Trigonometric transforms are used in this scheme for improving the performance of the OFDM systems and reducing the Peak-to-Average Power Ratio (PAPR) of OFDM signal. It improves the error resilience ability and transmission efficiency for progressive image transmission over Additive White Gaussian Noise (AWGN) channel. The Set Partitioning In Hierarchical Trees (SPIHT) algorithm is used for source coding of the images to be transmitted. In the proposed scheme the transmit data sequence of the OFDM signal after Inverse Fast Fourier Transform (IFFT) is grouped into in-phase and in-quadrature components, then each component is transformed using either the Discrete Cosine Transform (DCT) or the Discrete Sine Transform (DST). The simulation results show that adding the DST to the system improves the visual quality of reconstructed images and reduces the PAPR of OFDM signal more than the DCT.

Several alternative building blocks have been proposed to replace planar transistors, among which a prominent spot belongs to nanometric filaments such as Silicon Nano Wires (SiNWs) and Carbon Nano Tubes (CNTs). However, chips leveraging these nanoscale structures are expected to be affected by a large amount of manufacturing faults, way beyond what chip architects have learned to counter. In this

The organization and circuit design of a 1.0-GHz integer processor built in 0.25-m CMOS technology are presented. A microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.

This paper examines the relationship between the functionality of a field-programmable gate array (FPGA) logic block and the area required to implement digital circuits using that logic block. This investigation is done experimentally by implementing a set of industrial circuits as FPGA's using CAD tools for technology mapping, placement, and routing. Using a simple model of the interconnection and logic block area, a range of programming technologies (the method of FPGA customization) is explored. The experiments are based on logic blocks that use lookup tables for implementing combinational logic. Results indicate that the best number of inputs to use (a measure of the block's functionality) is between three and four, and that a D flip-flop should be included in the logic block. These results are largely independent of the programming technology. More generally, it was observed that the area efficiency of a logic block depends not only on its functionality but on the average number of pins connected per logic block. It is shown that as the number of connected pins per block increases, the number of wiring tracks required to route those blocks also increases. Since adding functionality to a block will lead to an increase in the number of connected pins, it follows that an increase in functionality of the block is only beneficial if the total number of blocks is reduced to more than compensate for the increased wiring area. This notion leads to the conclusion that the most area-efficient logic blocks are those with a high amount of functionality per pin.

Many video compression systems such as high-definition televisions (HDTV) require a high-speed implementation of the variable-length code (VLC). The recursive iteration of the decoding process limits the achievable decoding throughput with a given IC technology. Two classes of architectures-the treebased and the PLA-based architectures-have been discussed in the literature for the VLC decoder. In Part I of this paper, we propose pipelined or parallel architectures in these two classes for high-speed implementation. In Part II, we propose some algorithm-level methods to create concurrency to further increase the decoder throughput. The pipelined tree-based architectures have the advantages of fully pipelined design, short clock cycle, and partial programmability. It is suitable for concurrent decoding of multiple independent bit streams. The PLA-based architectures have greater flexibility and can take advantages of some high-level optimization techniques. The input/output rate can be fixed or variable to meet the real application requirements. As an experiment, we have constructed a variable-length-code based on a popular video compression system and compared the architectures. A layout of the major parts and a simulation of the critical path of the pipelined constant-input-rate PLA-based architecture using a high-level synthesis approach estimates that a decoding throughput of 200 Mb/s with a single chip is achievable with CMOS 2.0 pm technology.

Commutation schemes for most common types of switched reluctance (SR) motors are presented. Commutation can be achieved using two- or three-positions sensors and a simple commutation logic in a similar fashion to brushless electronically commutated motors. The commutation logic can be easily housed on a programmable logic array (PLA) or similar device. Two-quadrant operation, usually with two position sensors with

ABSTRACT We developed a novel configurable logic array test structure using a highly scalable 3rd generation split-gate flash memory cell that features low power and fast configuration time. This split-gate SuperFlash® configuration element (SCE) has been demonstrated with a 90nm embedded Flash technology. The resulting SCE eliminates the need for esoteric fabrication process, and sensing, and SRAM circuits and reduces configuration time for programmable arrays (PA) such as FPGAs and CPLDs. Additionally, SCE inherently ports the advantages of SST's split-gate Flash memory technology with compact area, low-voltage read operation, low-power poly-to-poly erase and source-side channel hot electron (SSCHE) injection programming mechanisms, along with superior reliability.

This paper deals with PLA folding strategies: in particular, the accurate evaluation of the area used by folded PLA's is presented. Criteria are proposed to choose the best folding strategy among those considered, without performing all the possible foldings.

It has been shown that fundamental electronic structures such as Diodes, and FET's can be constructed using selectively doped semiconducting carbon nanotubes or silicon nanowires (CNT's, SiNW's) at nanometer scale. Memory and Logic cores using these technologies have been proposed, that use the configurable junctions in two-dimensional crossbars of CNT's. These memories and logic arrays at this scale exhibit significant amount of defects that account for poor yield. Configuration of these devices in presence of defects demands for an overhead in terms of area and programming time. In this work, we introduce a PLA (programmable logic array) configuration that makes use of design-specific redundancy in terms of number of nanowires, in order to simplify the process of programming the PLA, increase the yield and reduce the time complexity and in turn, the cost of the system.

Various implementations of the Quantum-dot Cellular Automata (QCA) device architecture may help many performance scaling trends continue as we approach the nano-scale. Experimental success has led to the evolution of a research track that looks at QCAbased design. The work presented in this paper follows that track and looks at implementation friendly, programmable QCA circuits. Specifically, we analyze a novel, QCA-based, Programmable Logic Array (PLA) structure, develop an implementation independent fault model, discuss how expected defects and faults might affect yield, and look at the design in the context of a magnetic implementation of QCA.

In many courses of digital system design, a large amount of time is spent introducing the students to architectural and circuit design. A typical laboratory application is the design of arithmetic digital circuits. In the past, as a hardware platform for educational digital design, programmable logic arrays (PLA's) have been widely used. Today, the field programmable gate arrays (FPGA's), seem to be the most suitable technology for this purpose. In this paper, among the many possible design examples, the authors have chosen the implementation of the radix-4 SRT algorithm for division. As convenient tradeoff between area cost and performance, SRT division implementation is being used in many recent general-purpose processors. The circuit offers a sufficient complexity to give practice to the students and to stimulate useful classroom discussions. Moreover, a system for rapid circuit prototyping and testing has been carried out. The prototyping-board allows the transfer of student designs into an SRAM-based FPGA chip and the performance of functional tests of the circuit. The prototyping system is directly controlled by a personal computer via ISA-Bus, and it allows students concentrate their attention on elaborating the digital design rather than striving with board assembly and PC-to-board communication. Gregorio Cappuccino was born in 1967. In 1992 he received the Laurea degree summa cum laude in Computer Science Engineering from the University of Calabria, Italy. In 1993 he joined Institute for Electromagnetics and Electronic Components of National Council of Research. In 1994 he joined the Department of Electronics, Computer Sciences and Systems of the University of Calabria, where he received the Ph.D. degree in systems engineering and computer science in 1998. Since 1999 he has been an Assistant Professor at the University of Calabria. His current research interests include digital systems for high-speed computing and high-speed low-power interconnect systems for ULSI.